Module gd32vf103_pac::dma1::intc
source · Expand description
Interrupt flag clear register
Structs
- Interrupt flag clear register
- Register
INTC
writer
Type Definitions
- Field
ERRIFC0
writer - Clear bit for error flag of channel 0 - Field
ERRIFC1
writer - Clear bit for error flag of channel 1 - Field
ERRIFC2
writer - Clear bit for error flag of channel 2 - Field
ERRIFC3
writer - Clear bit for error flag of channel 3 - Field
ERRIFC4
writer - Clear bit for error flag of channel 4 - Field
FTFIFC0
writer - Clear bit for full transfer finish flag of channel 0 - Field
FTFIFC1
writer - Clear bit for full transfer finish flag of channel 1 - Field
FTFIFC2
writer - Clear bit for full transfer finish flag of channel 2 - Field
FTFIFC3
writer - Clear bit for full transfer finish flag of channel 3 - Field
FTFIFC4
writer - Clear bit for full transfer finish flag of channel 4 - Field
GIFC0
writer - Clear global interrupt flag of channel 0 - Field
GIFC1
writer - Clear global interrupt flag of channel 1 - Field
GIFC2
writer - Clear global interrupt flag of channel 2 - Field
GIFC3
writer - Clear global interrupt flag of channel 3 - Field
GIFC4
writer - Clear global interrupt flag of channel 4 - Field
HTFIFC0
writer - Clear bit for half transfer finish flag of channel 0 - Field
HTFIFC1
writer - Clear bit for half transfer finish flag of channel 1 - Field
HTFIFC2
writer - Clear bit for half transfer finish flag of channel 2 - Field
HTFIFC3
writer - Clear bit for half transfer finish flag of channel 3 - Field
HTFIFC4
writer - Clear bit for half transfer finish flag of channel 4