Module gd32vf103_pac::dma0::ch6ctl
source · Expand description
Channel 6 control register
Structs
- Channel 6 control register
- Register
CH6CTL
reader - Register
CH6CTL
writer
Type Definitions
- Field
CHEN
reader - Channel enable - Field
CHEN
writer - Channel enable - Field
CMEN
reader - Circular mode enable - Field
CMEN
writer - Circular mode enable - Field
DIR
reader - Transfer direction - Field
DIR
writer - Transfer direction - Field
ERRIE
reader - Enable bit for channel error interrupt - Field
ERRIE
writer - Enable bit for channel error interrupt - Field
FTFIE
reader - Enable bit for channel full transfer finish interrupt - Field
FTFIE
writer - Enable bit for channel full transfer finish interrupt - Field
HTFIE
reader - Enable bit for channel half transfer finish interrupt - Field
HTFIE
writer - Enable bit for channel half transfer finish interrupt - Field
M2M
reader - Memory to Memory Mode - Field
M2M
writer - Memory to Memory Mode - Field
MNAGA
reader - Next address generation algorithm of memory - Field
MNAGA
writer - Next address generation algorithm of memory - Field
MWIDTH
reader - Transfer data size of memory - Field
MWIDTH
writer - Transfer data size of memory - Field
PNAGA
reader - Next address generation algorithm of peripheral - Field
PNAGA
writer - Next address generation algorithm of peripheral - Field
PRIO
reader - Priority level - Field
PRIO
writer - Priority level - Field
PWIDTH
reader - Transfer data size of peripheral - Field
PWIDTH
writer - Transfer data size of peripheral