Module gd32vf103_pac::dma0::ch2ctl

Channel 2 control register

Structs

• CH2CTL_SPEC
  Channel 2 control register
• R
  Register CH2CTL reader
• W
  Register CH2CTL writer

Type Definitions

• CHEN_R
  Field CHEN reader - Channel enable
• CHEN_W
  Field CHEN writer - Channel enable
• CMEN_R
  Field CMEN reader - Circular mode enable
• CMEN_W
  Field CMEN writer - Circular mode enable
• DIR_R
  Field DIR reader - Transfer direction
• DIR_W
  Field DIR writer - Transfer direction
• ERRIE_R
  Field ERRIE reader - Enable bit for channel error interrupt
• ERRIE_W
  Field ERRIE writer - Enable bit for channel error interrupt
• FTFIE_R
  Field FTFIE reader - Enable bit for channel full transfer finish interrupt
• FTFIE_W
  Field FTFIE writer - Enable bit for channel full transfer finish interrupt
• HTFIE_R
  Field HTFIE reader - Enable bit for channel half transfer finish interrupt
• HTFIE_W
  Field HTFIE writer - Enable bit for channel half transfer finish interrupt
• M2M_R
  Field M2M reader - Memory to Memory Mode
• M2M_W
  Field M2M writer - Memory to Memory Mode
• MNAGA_R
  Field MNAGA reader - Next address generation algorithm of memory
• MNAGA_W
  Field MNAGA writer - Next address generation algorithm of memory
• MWIDTH_R
  Field MWIDTH reader - Transfer data size of memory
• MWIDTH_W
  Field MWIDTH writer - Transfer data size of memory
• PNAGA_R
  Field PNAGA reader - Next address generation algorithm of peripheral
• PNAGA_W
  Field PNAGA writer - Next address generation algorithm of peripheral
• PRIO_R
  Field PRIO reader - Priority level
• PRIO_W
  Field PRIO writer - Priority level
• PWIDTH_R
  Field PWIDTH reader - Transfer data size of peripheral
• PWIDTH_W
  Field PWIDTH writer - Transfer data size of peripheral