[−][src]Module gd32vf103_pac::rcu
Reset and clock unit
Modules
| ahben | AHB enable register |
| ahbrst | AHB reset register |
| apb1en | APB1 clock enable register (RCU_APB1EN) |
| apb1rst | APB1 reset register (RCU_APB1RST) |
| apb2en | APB2 clock enable register (RCU_APB2EN) |
| apb2rst | APB2 reset register (RCU_APB2RST) |
| bdctl | Backup domain control register (RCU_BDCTL) |
| cfg0 | Clock configuration register 0 (RCU_CFG0) |
| cfg1 | Clock Configuration register 1 |
| ctl | Control register |
| dsv | Deep sleep mode Voltage register |
| int | Clock interrupt register (RCU_INT) |
| rstsck | Reset source /clock register (RCU_RSTSCK) |
Structs
| RegisterBlock | Register block |
Type Definitions
| AHBEN | AHB enable register |
| AHBRST | AHB reset register |
| APB1EN | APB1 clock enable register (RCU_APB1EN) |
| APB1RST | APB1 reset register (RCU_APB1RST) |
| APB2EN | APB2 clock enable register (RCU_APB2EN) |
| APB2RST | APB2 reset register (RCU_APB2RST) |
| BDCTL | Backup domain control register (RCU_BDCTL) |
| CFG0 | Clock configuration register 0 (RCU_CFG0) |
| CFG1 | Clock Configuration register 1 |
| CTL | Control register |
| DSV | Deep sleep mode Voltage register |
| INT | Clock interrupt register (RCU_INT) |
| RSTSCK | Reset source /clock register (RCU_RSTSCK) |