[−][src]Module gd32vf103_pac::dma0
DMA controller
Modules
ch0ctl | Channel 0 control register |
ch0cnt | Channel 0 counter register |
ch0paddr | Channel 0 peripheral base address register |
ch0maddr | Channel 0 memory base address register |
ch1ctl | Channel 1 control register |
ch1cnt | Channel 1 counter register |
ch1paddr | Channel 1 peripheral base address register |
ch1maddr | Channel 1 memory base address register |
ch2ctl | Channel 2 control register |
ch2cnt | Channel 2 counter register |
ch2paddr | Channel 2 peripheral base address register |
ch2maddr | Channel 2 memory base address register |
ch3ctl | Channel 3 control register |
ch3cnt | Channel 3 counter register |
ch3paddr | Channel 3 peripheral base address register |
ch3maddr | Channel 3 memory base address register |
ch4ctl | Channel 4 control register |
ch4cnt | Channel 4 counter register |
ch4paddr | Channel 4 peripheral base address register |
ch4maddr | Channel 4 memory base address register |
ch5ctl | Channel 5 control register |
ch5cnt | Channel 5 counter register |
ch5paddr | Channel 5 peripheral base address register |
ch5maddr | Channel 5 memory base address register |
ch6ctl | Channel 6 control register |
ch6cnt | Channel 6 counter register |
ch6paddr | Channel 6 peripheral base address register |
ch6maddr | Channel 6 memory base address register |
intc | Interrupt flag clear register |
intf | Interrupt flag register |
Structs
CH0CTL | Channel 0 control register |
CH0CNT | Channel 0 counter register |
CH0PADDR | Channel 0 peripheral base address register |
CH0MADDR | Channel 0 memory base address register |
CH1CTL | Channel 1 control register |
CH1CNT | Channel 1 counter register |
CH1PADDR | Channel 1 peripheral base address register |
CH1MADDR | Channel 1 memory base address register |
CH2CTL | Channel 2 control register |
CH2CNT | Channel 2 counter register |
CH2PADDR | Channel 2 peripheral base address register |
CH2MADDR | Channel 2 memory base address register |
CH3CTL | Channel 3 control register |
CH3CNT | Channel 3 counter register |
CH3PADDR | Channel 3 peripheral base address register |
CH3MADDR | Channel 3 memory base address register |
CH4CTL | Channel 4 control register |
CH4CNT | Channel 4 counter register |
CH4PADDR | Channel 4 peripheral base address register |
CH4MADDR | Channel 4 memory base address register |
CH5CTL | Channel 5 control register |
CH5CNT | Channel 5 counter register |
CH5PADDR | Channel 5 peripheral base address register |
CH5MADDR | Channel 5 memory base address register |
CH6CTL | Channel 6 control register |
CH6CNT | Channel 6 counter register |
CH6PADDR | Channel 6 peripheral base address register |
CH6MADDR | Channel 6 memory base address register |
INTC | Interrupt flag clear register |
INTF | Interrupt flag register |
RegisterBlock | Register block |