[−][src]Module gd32vf103_pac::dac
Digital-to-analog converter
Modules
| ctl | control register |
| dac0_do | DAC0 data output register |
| dac1_do | DAC1 data output register |
| dac0_l12dh | DAC0 12-bit left-aligned data holding register |
| dac0_r8dh | DAC0 8-bit right aligned data holding register |
| dac0_r12dh | DAC0 12-bit right-aligned data holding register |
| dac1_l12dh | DAC1 12-bit left aligned data holding register |
| dac1_r8dh | DAC1 8-bit right aligned data holding register |
| dac1_r12dh | DAC1 12-bit right-aligned data holding register |
| dacc_l12dh | DAC concurrent mode 12-bit left aligned data holding register |
| dacc_r8dh | DAC concurrent mode 8-bit right aligned data holding register |
| dacc_r12dh | DAC concurrent mode 12-bit right-aligned data holding register |
| swt | software trigger register |
Structs
| CTL | control register |
| DAC0_DO | DAC0 data output register |
| DAC1_DO | DAC1 data output register |
| DAC0_L12DH | DAC0 12-bit left-aligned data holding register |
| DAC0_R8DH | DAC0 8-bit right aligned data holding register |
| DAC0_R12DH | DAC0 12-bit right-aligned data holding register |
| DAC1_L12DH | DAC1 12-bit left aligned data holding register |
| DAC1_R8DH | DAC1 8-bit right aligned data holding register |
| DAC1_R12DH | DAC1 12-bit right-aligned data holding register |
| DACC_L12DH | DAC concurrent mode 12-bit left aligned data holding register |
| DACC_R8DH | DAC concurrent mode 8-bit right aligned data holding register |
| DACC_R12DH | DAC concurrent mode 12-bit right-aligned data holding register |
| RegisterBlock | Register block |
| SWT | software trigger register |