Module gd32f1x0_hal::pac::usart0::ctl1 [−][src]
Expand description
Control register 1
Structs
| ABDEN_R | Field |
| ABDEN_W | Field |
| ABDM_R | Field |
| ABDM_W | Field |
| ADDM_R | Field |
| ADDM_W | Field |
| ADDR_R | Field |
| ADDR_W | Field |
| CKEN_R | Field |
| CKEN_W | Field |
| CLEN_R | Field |
| CLEN_W | Field |
| CPH_R | Field |
| CPH_W | Field |
| CPL_R | Field |
| CPL_W | Field |
| CTL1_SPEC | Control register 1 |
| DINV_R | Field |
| DINV_W | Field |
| LBDIE_R | Field |
| LBDIE_W | Field |
| LBLEN_R | Field |
| LBLEN_W | Field |
| LMEN_R | Field |
| LMEN_W | Field |
| MSBF_R | Field |
| MSBF_W | Field |
| R | Register |
| RINV_R | Field |
| RINV_W | Field |
| RTEN_R | Field |
| RTEN_W | Field |
| STB_R | Field |
| STB_W | Field |
| STRP_R | Field |
| STRP_W | Field |
| TINV_R | Field |
| TINV_W | Field |
| W | Register |
Enums
| ABDEN_A | Auto baud rate enable |
| ABDM_A | Auto baud rate mode |
| ADDM_A | Address detection mode |
| CKEN_A | CK pin enable |
| CLEN_A | CK length |
| CPH_A | Clock phase |
| CPL_A | Clock polarity |
| DINV_A | Data bit level inversion |
| LBDIE_A | LIN break detection interrupt enable |
| LBLEN_A | LIN break frame length |
| LMEN_A | LIN mode enable |
| MSBF_A | Most significant bit first |
| RINV_A | RX pin level inversion |
| RTEN_A | Receiver timeout enable |
| STB_A | STOP bits length |
| STRP_A | Swap TX/RX pins |
| TINV_A | TX pin level inversion |