Module gd32f1x0_hal::pac::timer14::chctl0_output [−][src]
Expand description
Channel control register 0 (output mode)
Structs
| CH0COMCEN_W | Field |
| CH0COMCTL_W | Field |
| CH0COMFEN_W | Field |
| CH0COMSEN_W | Field |
| CH0MS_W | Field |
| CH1COMCEN_R | Field |
| CH1COMCEN_W | Field |
| CH1COMCTL_R | Field |
| CH1COMCTL_W | Field |
| CH1COMFEN_R | Field |
| CH1COMFEN_W | Field |
| CH1COMSEN_R | Field |
| CH1COMSEN_W | Field |
| CH1MS_R | Field |
| CH1MS_W | Field |
| CHCTL0_OUTPUT_SPEC | Channel control register 0 (output mode) |
| R | Register |
| W | Register |
Enums
| CH1COMCEN_A | Channel 1 output compare clear enable |
| CH1COMCTL_A | Channel 1 output compare mode |
| CH1COMFEN_A | Channel 1 output compare fast enable |
| CH1COMSEN_A | Channel 1 output compare shadow enable |
| CH1MS_A | Channel 1 mode selection |
Type Definitions
| CH0COMCEN_A | Channel 0 output compare clear enable |
| CH0COMCEN_R | Field |
| CH0COMCTL_A | Channel 0 compare output control |
| CH0COMCTL_R | Field |
| CH0COMFEN_A | Channel 0 output compare fast enable |
| CH0COMFEN_R | Field |
| CH0COMSEN_A | Channel 0 output compare shadow enable |
| CH0COMSEN_R | Field |
| CH0MS_A | Channel 0 mode selection |
| CH0MS_R | Field |