Module gd32f1x0_hal::pac::timer1::ctl1

control register 1

Structs

CTL1_SPEC	control register 1
DMAS_R	Field DMAS reader - DMA request source selection
DMAS_W	Field DMAS writer - DMA request source selection
MMC_R	Field MMC reader - Master mode control
MMC_W	Field MMC writer - Master mode control
R	Register CTL1 reader
TI0S_R	Field TI0S reader - Channel 0 trigger input selection
TI0S_W	Field TI0S writer - Channel 0 trigger input selection
W	Register CTL1 writer

Enums

DMAS_A	DMA request source selection
MMC_A	Master mode control
TI0S_A	Channel 0 trigger input selection