Module gd32f1x0_hal::pac::timer1::ctl0 [−][src]
Expand description
control register 0
Structs
ARSE_R | Field |
ARSE_W | Field |
CAM_R | Field |
CAM_W | Field |
CEN_R | Field |
CEN_W | Field |
CKDIV_R | Field |
CKDIV_W | Field |
CTL0_SPEC | control register 0 |
DIR_R | Field |
DIR_W | Field |
R | Register |
SPM_R | Field |
SPM_W | Field |
UPDIS_R | Field |
UPDIS_W | Field |
UPS_R | Field |
UPS_W | Field |
W | Register |
Enums
ARSE_A | Auto-reload shadow enable |
CAM_A | Counter aligns mode selection |
CEN_A | Counter enable |
CKDIV_A | Clock division |
DIR_A | Direction |
SPM_A | Single pulse mode |
UPDIS_A | Update disable |
UPS_A | Update request source |