Module gd32f1x0_hal::pac::timer1::chctl0_input

Channel control register 0 (input mode)

Structs

CH0CAPFLT_W	Field CH0CAPFLT writer - Channel 0 input capture filter control
CH0CAPPSC_W	Field CH0CAPPSC writer - Channel 0 input capture prescaler
CH0MS_W	Field CH0MS writer - Channel 0 mode selection
CH1CAPFLT_R	Field CH1CAPFLT reader - Channel 1 input capture filter control
CH1CAPFLT_W	Field CH1CAPFLT writer - Channel 1 input capture filter control
CH1CAPPSC_R	Field CH1CAPPSC reader - Channel 1 input capture prescaler
CH1CAPPSC_W	Field CH1CAPPSC writer - Channel 1 input capture prescaler
CH1MS_R	Field CH1MS reader - Channel 1 mode selection
CH1MS_W	Field CH1MS writer - Channel 1 mode selection
CHCTL0_INPUT_SPEC	Channel control register 0 (input mode)
R	Register CHCTL0_Input reader
W	Register CHCTL0_Input writer

Enums

CH1CAPFLT_A	Channel 1 input capture filter control
CH1CAPPSC_A	Channel 1 input capture prescaler
CH1MS_A	Channel 1 mode selection

Type Definitions

CH0CAPFLT_A	Channel 0 input capture filter control
CH0CAPFLT_R	Field CH0CAPFLT reader - Channel 0 input capture filter control
CH0CAPPSC_A	Channel 0 input capture prescaler
CH0CAPPSC_R	Field CH0CAPPSC reader - Channel 0 input capture prescaler
CH0MS_A	Channel 0 mode selection
CH0MS_R	Field CH0MS reader - Channel 0 mode selection