Module gd32f1x0_hal::pac::timer0::chctl1_input [−][src]
Expand description
Channel control register 1 (input mode)
Structs
CH2CAPFLT_W | Field |
CH2CAPPSC_W | Field |
CH2MS_W | Field |
CH3CAPFLT_R | Field |
CH3CAPFLT_W | Field |
CH3CAPPSC_R | Field |
CH3CAPPSC_W | Field |
CH3MS_R | Field |
CH3MS_W | Field |
CHCTL1_INPUT_SPEC | Channel control register 1 (input mode) |
R | Register |
W | Register |
Enums
CH3CAPFLT_A | Channel 3 input capture filter control |
CH3CAPPSC_A | Channel 3 input capture prescaler |
CH3MS_A | Channel 3 mode selection |
Type Definitions
CH2CAPFLT_A | Channel 2 input capture filter control |
CH2CAPFLT_R | Field |
CH2CAPPSC_A | Channel 2 input capture prescaler |
CH2CAPPSC_R | Field |
CH2MS_A | Channel 2 mode selection |
CH2MS_R | Field |