Module gd32f1x0_hal::pac::rcu::cfg0 [−][src]
Expand description
Clock configuration register 0 (RCU_CFG0)
Structs
ADCPSC_R | Field |
ADCPSC_W | Field |
AHBPSC_R | Field |
AHBPSC_W | Field |
APB1PSC_R | Field |
APB1PSC_W | Field |
APB2PSC_W | Field |
CFG0_SPEC | Clock configuration register 0 (RCU_CFG0) |
CKOUTDIV_R | Field |
CKOUTDIV_W | Field |
CKOUTSEL_R | Field |
CKOUTSEL_W | Field |
PLLDV_R | Field |
PLLDV_W | Field |
PLLMF_MSB_R | Field |
PLLMF_MSB_W | Field |
PLLMF_R | Field |
PLLMF_W | Field |
PLLPREDV_R | Field |
PLLPREDV_W | Field |
PLLSEL_R | Field |
PLLSEL_W | Field |
R | Register |
SCSS_R | Field |
SCS_R | Field |
SCS_W | Field |
USBDPSC_R | Field |
USBDPSC_W | Field |
W | Register |
Enums
ADCPSC_A | ADC clock prescaler selection |
AHBPSC_A | AHB prescaler selection |
APB1PSC_A | APB1 prescaler selection |
CKOUTDIV_A | The CK_OUT divider which the CK_OUT frequency can be reduced |
CKOUTSEL_A | CK_OUT Clock Source Selection |
PLLDV_A | The CK_PLL divide by 1 or 2 for CK_OUT |
PLLMF_A | PLL multiply factor |
PLLMF_MSB_A | Bit 4 of PLLMF register |
PLLPREDV_A | HXTAL divider for PLL source clock selection. |
PLLSEL_A | PLL Clock Source Selection |
SCSS_A | System clock switch status |
SCS_A | System clock switch |
USBDPSC_A | USBD clock prescaler selection |
Type Definitions
APB2PSC_A | APB2 prescaler selection |
APB2PSC_R | Field |