Module gd32f1x0_hal::pac::rcu::cfg0[][src]

Expand description

Clock configuration register 0 (RCU_CFG0)

Structs

ADCPSC_R

Field ADCPSC reader - ADC clock prescaler selection

ADCPSC_W

Field ADCPSC writer - ADC clock prescaler selection

AHBPSC_R

Field AHBPSC reader - AHB prescaler selection

AHBPSC_W

Field AHBPSC writer - AHB prescaler selection

APB1PSC_R

Field APB1PSC reader - APB1 prescaler selection

APB1PSC_W

Field APB1PSC writer - APB1 prescaler selection

APB2PSC_W

Field APB2PSC writer - APB2 prescaler selection

CFG0_SPEC

Clock configuration register 0 (RCU_CFG0)

CKOUTDIV_R

Field CKOUTDIV reader - The CK_OUT divider which the CK_OUT frequency can be reduced

CKOUTDIV_W

Field CKOUTDIV writer - The CK_OUT divider which the CK_OUT frequency can be reduced

CKOUTSEL_R

Field CKOUTSEL reader - CK_OUT Clock Source Selection

CKOUTSEL_W

Field CKOUTSEL writer - CK_OUT Clock Source Selection

PLLDV_R

Field PLLDV reader - The CK_PLL divide by 1 or 2 for CK_OUT

PLLDV_W

Field PLLDV writer - The CK_PLL divide by 1 or 2 for CK_OUT

PLLMF_MSB_R

Field PLLMF_MSB reader - Bit 4 of PLLMF register

PLLMF_MSB_W

Field PLLMF_MSB writer - Bit 4 of PLLMF register

PLLMF_R

Field PLLMF reader - PLL multiply factor

PLLMF_W

Field PLLMF writer - PLL multiply factor

PLLPREDV_R

Field PLLPREDV reader - HXTAL divider for PLL source clock selection.

PLLPREDV_W

Field PLLPREDV writer - HXTAL divider for PLL source clock selection.

PLLSEL_R

Field PLLSEL reader - PLL Clock Source Selection

PLLSEL_W

Field PLLSEL writer - PLL Clock Source Selection

R

Register CFG0 reader

SCSS_R

Field SCSS reader - System clock switch status

SCS_R

Field SCS reader - System clock switch

SCS_W

Field SCS writer - System clock switch

USBDPSC_R

Field USBDPSC reader - USBD clock prescaler selection

USBDPSC_W

Field USBDPSC writer - USBD clock prescaler selection

W

Register CFG0 writer

Enums

ADCPSC_A

ADC clock prescaler selection

AHBPSC_A

AHB prescaler selection

APB1PSC_A

APB1 prescaler selection

CKOUTDIV_A

The CK_OUT divider which the CK_OUT frequency can be reduced

CKOUTSEL_A

CK_OUT Clock Source Selection

PLLDV_A

The CK_PLL divide by 1 or 2 for CK_OUT

PLLMF_A

PLL multiply factor

PLLMF_MSB_A

Bit 4 of PLLMF register

PLLPREDV_A

HXTAL divider for PLL source clock selection.

PLLSEL_A

PLL Clock Source Selection

SCSS_A

System clock switch status

SCS_A

System clock switch

USBDPSC_A

USBD clock prescaler selection

Type Definitions

APB2PSC_A

APB2 prescaler selection

APB2PSC_R

Field APB2PSC reader - APB2 prescaler selection