Module gd32f1x0_hal::pac::gpiod::ctl [−][src]
Expand description
GPIO port control register
Structs
CTL0_W | Field |
CTL1_W | Field |
CTL2_W | Field |
CTL3_W | Field |
CTL4_W | Field |
CTL5_W | Field |
CTL6_W | Field |
CTL7_W | Field |
CTL8_W | Field |
CTL9_W | Field |
CTL10_W | Field |
CTL11_W | Field |
CTL12_W | Field |
CTL13_W | Field |
CTL14_W | Field |
CTL15_R | Field |
CTL15_W | Field |
CTL_SPEC | GPIO port control register |
R | Register |
W | Register |
Enums
CTL15_A | Port x configuration bits (y = 0..15) |
Type Definitions
CTL0_A | Port x configuration bits (y = 0..15) |
CTL0_R | Field |
CTL1_A | Port x configuration bits (y = 0..15) |
CTL1_R | Field |
CTL2_A | Port x configuration bits (y = 0..15) |
CTL2_R | Field |
CTL3_A | Port x configuration bits (y = 0..15) |
CTL3_R | Field |
CTL4_A | Port x configuration bits (y = 0..15) |
CTL4_R | Field |
CTL5_A | Port x configuration bits (y = 0..15) |
CTL5_R | Field |
CTL6_A | Port x configuration bits (y = 0..15) |
CTL6_R | Field |
CTL7_A | Port x configuration bits (y = 0..15) |
CTL7_R | Field |
CTL8_A | Port x configuration bits (y = 0..15) |
CTL8_R | Field |
CTL9_A | Port x configuration bits (y = 0..15) |
CTL9_R | Field |
CTL10_A | Port x configuration bits (y = 0..15) |
CTL10_R | Field |
CTL11_A | Port x configuration bits (y = 0..15) |
CTL11_R | Field |
CTL12_A | Port x configuration bits (y = 0..15) |
CTL12_R | Field |
CTL13_A | Port x configuration bits (y = 0..15) |
CTL13_R | Field |
CTL14_A | Port x configuration bits (y = 0..15) |
CTL14_R | Field |