Module gd32f1x0_hal::pac::adc::ctl1 [−][src]
Expand description
control register 1
Structs
| ADCON_R | Field |
| ADCON_W | Field |
| CLB_R | Field |
| CLB_W | Field |
| CTL1_SPEC | control register 1 |
| CTN_R | Field |
| CTN_W | Field |
| DAL_R | Field |
| DAL_W | Field |
| DMA_R | Field |
| DMA_W | Field |
| ETEIC_R | Field |
| ETEIC_W | Field |
| ETERC_R | Field |
| ETERC_W | Field |
| ETSIC_R | Field |
| ETSIC_W | Field |
| ETSRC_R | Field |
| ETSRC_W | Field |
| R | Register |
| RSTCLB_R | Field |
| RSTCLB_W | Field |
| SWICST_R | Field |
| SWICST_W | Field |
| SWRCST_R | Field |
| SWRCST_W | Field |
| TSVREN_R | Field |
| TSVREN_W | Field |
| VBATEN_R | Field |
| VBATEN_W | Field |
| W | Register |
Enums
| ADCON_A | ADC ON |
| CLB_A | ADC calibration |
| CLB_AW | ADC calibration |
| CTN_A | Continuous mode |
| DAL_A | Data alignment |
| DMA_A | DMA request enable |
| ETEIC_A | External trigger enable for inserted channel |
| ETERC_A | External trigger enable for regular channel |
| ETSIC_A | External trigger select for inserted channel |
| ETSRC_A | External trigger select for regular channel |
| RSTCLB_A | Reset calibration |
| RSTCLB_AW | Reset calibration |
| SWICST_A | Start on inserted channel |
| SWICST_AW | Start on inserted channel |
| SWRCST_A | Start on regular channel |
| SWRCST_AW | Start on regular channel |
| TSVREN_A | Channel 16 and 17 enable of ADC |
| VBATEN_A | enable/disable the VBAT channel |