#[doc = "Register `CTL1` reader"]
pub type R = crate::R<Ctl1Spec>;
#[doc = "Register `CTL1` writer"]
pub type W = crate::W<Ctl1Spec>;
#[doc = "Master mode control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mmc {
#[doc = "0: Use UPG bit from SWEVG register"]
Reset = 0,
#[doc = "1: Use CEN bit from CTL0 register"]
Enable = 1,
#[doc = "2: Use the update event"]
Update = 2,
}
impl From<Mmc> for u8 {
#[inline(always)]
fn from(variant: Mmc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mmc {
type Ux = u8;
}
#[doc = "Field `MMC` reader - Master mode control"]
pub type MmcR = crate::FieldReader<Mmc>;
impl MmcR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Mmc> {
match self.bits {
0 => Some(Mmc::Reset),
1 => Some(Mmc::Enable),
2 => Some(Mmc::Update),
_ => None,
}
}
#[doc = "Use UPG bit from SWEVG register"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == Mmc::Reset
}
#[doc = "Use CEN bit from CTL0 register"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == Mmc::Enable
}
#[doc = "Use the update event"]
#[inline(always)]
pub fn is_update(&self) -> bool {
*self == Mmc::Update
}
}
#[doc = "Field `MMC` writer - Master mode control"]
pub type MmcW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mmc>;
impl<'a, REG> MmcW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Use UPG bit from SWEVG register"]
#[inline(always)]
pub fn reset(self) -> &'a mut crate::W<REG> {
self.variant(Mmc::Reset)
}
#[doc = "Use CEN bit from CTL0 register"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(Mmc::Enable)
}
#[doc = "Use the update event"]
#[inline(always)]
pub fn update(self) -> &'a mut crate::W<REG> {
self.variant(Mmc::Update)
}
}
impl R {
#[doc = "Bits 4:6 - Master mode control"]
#[inline(always)]
pub fn mmc(&self) -> MmcR {
MmcR::new(((self.bits >> 4) & 7) as u8)
}
}
impl W {
#[doc = "Bits 4:6 - Master mode control"]
#[inline(always)]
#[must_use]
pub fn mmc(&mut self) -> MmcW<Ctl1Spec> {
MmcW::new(self, 4)
}
}
#[doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctl1Spec;
impl crate::RegisterSpec for Ctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
impl crate::Readable for Ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
impl crate::Writable for Ctl1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
}
#[doc = "`reset()` method sets CTL1 to value 0"]
impl crate::Resettable for Ctl1Spec {
const RESET_VALUE: u16 = 0;
}