Module gd32f1::gd32f190::timer1::chctl0_input

Channel control register 0 (input mode)

Re-exports

• pub use crate::gd32f190::timer0::chctl0_input::Ch0capflt;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0capfltR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0capfltR as Ch1capfltR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0capfltW;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0capfltW as Ch1capfltW;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0cappsc;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0cappscR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0cappscR as Ch1cappscR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0cappscW;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0cappscW as Ch1cappscW;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0ms;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0msR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0msR as Ch1msR;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0msW;
• pub use crate::gd32f190::timer0::chctl0_input::Ch0msW as Ch1msW;

Structs

• Chctl0InputSpec
  Channel control register 0 (input mode)

Type Aliases

• R
  Register CHCTL0_Input reader
• W
  Register CHCTL0_Input writer