Expand description
Analog to digital converter
Modules§
- control register 0
- control register 1
- injected data register 0
- injected data register 1
- injected data register 2
- injected data register 3
- Inserted channel data offset register 0
- Inserted channel data offset register 1
- Inserted channel data offset register 2
- Inserted channel data offset register 3
- Inserted sequence register
- oversample control register
- regular data register
- regular sequence register 0
- regular sequence register 1
- regular sequence register 2
- Sampling time register 1
- Sampling time register 2
- status register
- watchdog higher threshold register
- watchdog lower threshold register
Structs§
- Register block
Type Aliases§
- CTL0 (rw) register accessor: control register 0
- CTL1 (rw) register accessor: control register 1
- IDATA0 (r) register accessor: injected data register 0
- IDATA1 (r) register accessor: injected data register 1
- IDATA2 (r) register accessor: injected data register 2
- IDATA3 (r) register accessor: injected data register 3
- IOFF0 (rw) register accessor: Inserted channel data offset register 0
- IOFF1 (rw) register accessor: Inserted channel data offset register 1
- IOFF2 (rw) register accessor: Inserted channel data offset register 2
- IOFF3 (rw) register accessor: Inserted channel data offset register 3
- ISQ (rw) register accessor: Inserted sequence register
- OVSAMPCTL (rw) register accessor: oversample control register
- RDATA (r) register accessor: regular data register
- RSQ0 (rw) register accessor: regular sequence register 0
- RSQ1 (rw) register accessor: regular sequence register 1
- RSQ2 (rw) register accessor: regular sequence register 2
- SAMPT0 (rw) register accessor: Sampling time register 1
- SAMPT1 (rw) register accessor: Sampling time register 2
- STAT (rw) register accessor: status register
- WDHT (rw) register accessor: watchdog higher threshold register
- WDLT (rw) register accessor: watchdog lower threshold register