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#[doc = "Register `SWEVG` writer"]
pub struct W(crate::W<SWEVG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SWEVG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SWEVG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SWEVG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Channel 0 capture or compare event generation"]
pub type CH0G_AW = crate::gd32f190::timer0::swevg::CH0G_AW;
#[doc = "Field `CH0G` writer - Channel 0 capture or compare event generation"]
pub struct CH0G_W<'a> {
w: &'a mut W,
}
impl<'a> CH0G_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CH0G_AW) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Generate a capture or compare event"]
#[inline(always)]
pub fn capture_compare(self) -> &'a mut W {
self.variant(CH0G_AW::CAPTURECOMPARE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1);
self.w
}
}
#[doc = "Update generation"]
pub type UPG_AW = crate::gd32f190::timer0::swevg::UPG_AW;
#[doc = "Field `UPG` writer - Update generation"]
pub struct UPG_W<'a> {
w: &'a mut W,
}
impl<'a> UPG_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UPG_AW) -> &'a mut W {
self.bit(variant.into())
}
#[doc = "Re-initializes the timer counter and generates an update of the registers."]
#[inline(always)]
pub fn update(self) -> &'a mut W {
self.variant(UPG_AW::UPDATE)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01);
self.w
}
}
impl W {
#[doc = "Bit 1 - Channel 0 capture or compare event generation"]
#[inline(always)]
pub fn ch0g(&mut self) -> CH0G_W {
CH0G_W { w: self }
}
#[doc = "Bit 0 - Update generation"]
#[inline(always)]
pub fn upg(&mut self) -> UPG_W {
UPG_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Software event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevg](index.html) module"]
pub struct SWEVG_SPEC;
impl crate::RegisterSpec for SWEVG_SPEC {
type Ux = u16;
}
#[doc = "`write(|w| ..)` method takes [swevg::W](W) writer structure"]
impl crate::Writable for SWEVG_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets SWEVG to value 0"]
impl crate::Resettable for SWEVG_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}