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#[doc = "Register `DMACFG` reader"] pub struct R(crate::R<DMACFG_SPEC>); impl core::ops::Deref for R { type Target = crate::R<DMACFG_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::convert::From<crate::R<DMACFG_SPEC>> for R { fn from(reader: crate::R<DMACFG_SPEC>) -> Self { R(reader) } } #[doc = "Register `DMACFG` writer"] pub struct W(crate::W<DMACFG_SPEC>); impl core::ops::Deref for W { type Target = crate::W<DMACFG_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl core::convert::From<crate::W<DMACFG_SPEC>> for W { fn from(writer: crate::W<DMACFG_SPEC>) -> Self { W(writer) } } #[doc = "Field `DMATC` reader - DMA transfer count"] pub struct DMATC_R(crate::FieldReader<u8, u8>); impl DMATC_R { pub(crate) fn new(bits: u8) -> Self { DMATC_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for DMATC_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `DMATC` writer - DMA transfer count"] pub struct DMATC_W<'a> { w: &'a mut W, } impl<'a> DMATC_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u16 & 0x1f) << 8); self.w } } #[doc = "Field `DMATA` reader - DMA transfer access start address"] pub struct DMATA_R(crate::FieldReader<u8, u8>); impl DMATA_R { pub(crate) fn new(bits: u8) -> Self { DMATA_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for DMATA_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `DMATA` writer - DMA transfer access start address"] pub struct DMATA_W<'a> { w: &'a mut W, } impl<'a> DMATA_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x1f) | (value as u16 & 0x1f); self.w } } impl R { #[doc = "Bits 8:12 - DMA transfer count"] #[inline(always)] pub fn dmatc(&self) -> DMATC_R { DMATC_R::new(((self.bits >> 8) & 0x1f) as u8) } #[doc = "Bits 0:4 - DMA transfer access start address"] #[inline(always)] pub fn dmata(&self) -> DMATA_R { DMATA_R::new((self.bits & 0x1f) as u8) } } impl W { #[doc = "Bits 8:12 - DMA transfer count"] #[inline(always)] pub fn dmatc(&mut self) -> DMATC_W { DMATC_W { w: self } } #[doc = "Bits 0:4 - DMA transfer access start address"] #[inline(always)] pub fn dmata(&mut self) -> DMATA_W { DMATA_W { w: self } } #[doc = "Writes raw bits to the register."] pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { self.0.bits(bits); self } } #[doc = "DMA configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacfg](index.html) module"] pub struct DMACFG_SPEC; impl crate::RegisterSpec for DMACFG_SPEC { type Ux = u16; } #[doc = "`read()` method returns [dmacfg::R](R) reader structure"] impl crate::Readable for DMACFG_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dmacfg::W](W) writer structure"] impl crate::Writable for DMACFG_SPEC { type Writer = W; } #[doc = "`reset()` method sets DMACFG to value 0"] impl crate::Resettable for DMACFG_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }