Module gd32f1::gd32f190::timer15::ctl0 [−][src]
control register 0
Structs
ARSE_R | Field |
ARSE_W | Field |
CEN_R | Field |
CEN_W | Field |
CKDIV_R | Field |
CKDIV_W | Field |
CTL0_SPEC | control register 0 |
R | Register |
SPM_R | Field |
SPM_W | Field |
UPDIS_R | Field |
UPDIS_W | Field |
UPS_R | Field |
UPS_W | Field |
W | Register |
Enums
ARSE_A | Auto-reload shadow enable |
CEN_A | Counter enable |
CKDIV_A | Clock division |
SPM_A | Single pulse mode |
UPDIS_A | Update disable |
UPS_A | Update source |