Module gd32f1::gd32f190::timer14::dmainten [−][src]
DMA and interrupt enable register
Structs
| BRKIE_R | Field |
| BRKIE_W | Field |
| CH0DEN_W | Field |
| CH0IE_W | Field |
| CH1DEN_R | Field |
| CH1DEN_W | Field |
| CH1IE_R | Field |
| CH1IE_W | Field |
| CMTIE_R | Field |
| CMTIE_W | Field |
| DMAINTEN_SPEC | DMA and interrupt enable register |
| R | Register |
| TRGDEN_R | Field |
| TRGDEN_W | Field |
| TRGIE_R | Field |
| TRGIE_W | Field |
| UPDEN_R | Field |
| UPDEN_W | Field |
| UPIE_R | Field |
| UPIE_W | Field |
| W | Register |
Enums
| BRKIE_A | Break interrupt enable |
| CH1DEN_A | Channel 1 Capture/Compare DMA request enable |
| CH1IE_A | Channel 1 Capture/Compare interrupt enable |
| CMTIE_A | CMT interrupt enable |
| TRGDEN_A | DMA and interrupt enable register |
| TRGIE_A | Trigger interrupt enable |
| UPDEN_A | Update DMA request enable |
| UPIE_A | Update interrupt enable |
Type Definitions
| CH0DEN_A | Channel 0 Capture/Compare DMA request enable |
| CH0DEN_R | Field |
| CH0IE_A | Channel 0 Capture/Compare interrupt enable |
| CH0IE_R | Field |