Module gd32f1::gd32f130::timer0::ctl1 [−][src]
control register 1
Structs
CCSE_R | Field |
CCSE_W | Field |
CCUC_R | Field |
CCUC_W | Field |
CTL1_SPEC | control register 1 |
DMAS_R | Field |
DMAS_W | Field |
ISO0N_R | Field |
ISO0N_W | Field |
ISO0_R | Field |
ISO0_W | Field |
ISO1N_R | Field |
ISO1N_W | Field |
ISO1_R | Field |
ISO1_W | Field |
ISO2N_R | Field |
ISO2N_W | Field |
ISO2_R | Field |
ISO2_W | Field |
ISO3_R | Field |
ISO3_W | Field |
MMC_R | Field |
MMC_W | Field |
R | Register |
TI0S_R | Field |
TI0S_W | Field |
W | Register |
Enums
CCSE_A | Commutation control shadow register enable |
CCUC_A | Commutation control shadow register update control |
DMAS_A | DMA request source selection |
ISO0N_A | Idle state of channel 0 complementary output |
ISO0_A | Idle state of channel 0 output |
ISO1N_A | Idle state of channel 1 complementary output |
ISO1_A | Idle state of channel 1 output |
ISO2N_A | Idle state of channel 2 complementary output |
ISO2_A | Idle state of channel 2 output |
ISO3_A | Idle state of channel 3 output |
MMC_A | Master mode control |
TI0S_A | Channel 0 trigger input selection |