1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
#[doc = "Reader of register CFG3"]
pub type R = crate::R<u32, super::CFG3>;
#[doc = "Writer for register CFG3"]
pub type W = crate::W<u32, super::CFG3>;
#[doc = "Register CFG3 `reset()`'s with value 0"]
impl crate::ResetValue for super::CFG3 {
    type Type = u32;
    #[inline(always)]
    fn reset_value() -> Self::Type {
        0
    }
}
#[doc = "CKOUT1 Clock Source Selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum CKOUT1SEL_A {
    #[doc = "0: No clock selected"]
    NONE = 0,
    #[doc = "1: Internal 28 MHz RC oscillator clock selected"]
    IRC28M = 1,
    #[doc = "2: Internal 40 kHz RC oscillator clock selected"]
    LSI40K = 2,
    #[doc = "3: External low speed oscillator clock selected"]
    LXTAL = 3,
    #[doc = "4: System clock selected"]
    SYSCLK = 4,
    #[doc = "5: Internal RC 8 MHz (HSI) oscillator clock selected"]
    IRC8M = 5,
    #[doc = "6: External 4-32 MHz (HSE) oscillator clock selected"]
    HXTAL = 6,
    #[doc = "7: PLL clock selected (divided by 1 or 2, depending on PLLDV)"]
    PLL = 7,
}
impl From<CKOUT1SEL_A> for u8 {
    #[inline(always)]
    fn from(variant: CKOUT1SEL_A) -> Self {
        variant as _
    }
}
#[doc = "Reader of field `CKOUT1SEL`"]
pub type CKOUT1SEL_R = crate::R<u8, CKOUT1SEL_A>;
impl CKOUT1SEL_R {
    #[doc = r"Get enumerated values variant"]
    #[inline(always)]
    pub fn variant(&self) -> CKOUT1SEL_A {
        match self.bits {
            0 => CKOUT1SEL_A::NONE,
            1 => CKOUT1SEL_A::IRC28M,
            2 => CKOUT1SEL_A::LSI40K,
            3 => CKOUT1SEL_A::LXTAL,
            4 => CKOUT1SEL_A::SYSCLK,
            5 => CKOUT1SEL_A::IRC8M,
            6 => CKOUT1SEL_A::HXTAL,
            7 => CKOUT1SEL_A::PLL,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `NONE`"]
    #[inline(always)]
    pub fn is_none(&self) -> bool {
        *self == CKOUT1SEL_A::NONE
    }
    #[doc = "Checks if the value of the field is `IRC28M`"]
    #[inline(always)]
    pub fn is_irc28m(&self) -> bool {
        *self == CKOUT1SEL_A::IRC28M
    }
    #[doc = "Checks if the value of the field is `LSI40K`"]
    #[inline(always)]
    pub fn is_lsi40k(&self) -> bool {
        *self == CKOUT1SEL_A::LSI40K
    }
    #[doc = "Checks if the value of the field is `LXTAL`"]
    #[inline(always)]
    pub fn is_lxtal(&self) -> bool {
        *self == CKOUT1SEL_A::LXTAL
    }
    #[doc = "Checks if the value of the field is `SYSCLK`"]
    #[inline(always)]
    pub fn is_sysclk(&self) -> bool {
        *self == CKOUT1SEL_A::SYSCLK
    }
    #[doc = "Checks if the value of the field is `IRC8M`"]
    #[inline(always)]
    pub fn is_irc8m(&self) -> bool {
        *self == CKOUT1SEL_A::IRC8M
    }
    #[doc = "Checks if the value of the field is `HXTAL`"]
    #[inline(always)]
    pub fn is_hxtal(&self) -> bool {
        *self == CKOUT1SEL_A::HXTAL
    }
    #[doc = "Checks if the value of the field is `PLL`"]
    #[inline(always)]
    pub fn is_pll(&self) -> bool {
        *self == CKOUT1SEL_A::PLL
    }
}
#[doc = "Write proxy for field `CKOUT1SEL`"]
pub struct CKOUT1SEL_W<'a> {
    w: &'a mut W,
}
impl<'a> CKOUT1SEL_W<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: CKOUT1SEL_A) -> &'a mut W {
        {
            self.bits(variant.into())
        }
    }
    #[doc = "No clock selected"]
    #[inline(always)]
    pub fn none(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::NONE)
    }
    #[doc = "Internal 28 MHz RC oscillator clock selected"]
    #[inline(always)]
    pub fn irc28m(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::IRC28M)
    }
    #[doc = "Internal 40 kHz RC oscillator clock selected"]
    #[inline(always)]
    pub fn lsi40k(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::LSI40K)
    }
    #[doc = "External low speed oscillator clock selected"]
    #[inline(always)]
    pub fn lxtal(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::LXTAL)
    }
    #[doc = "System clock selected"]
    #[inline(always)]
    pub fn sysclk(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::SYSCLK)
    }
    #[doc = "Internal RC 8 MHz (HSI) oscillator clock selected"]
    #[inline(always)]
    pub fn irc8m(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::IRC8M)
    }
    #[doc = "External 4-32 MHz (HSE) oscillator clock selected"]
    #[inline(always)]
    pub fn hxtal(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::HXTAL)
    }
    #[doc = "PLL clock selected (divided by 1 or 2, depending on PLLDV)"]
    #[inline(always)]
    pub fn pll(self) -> &'a mut W {
        self.variant(CKOUT1SEL_A::PLL)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
        self.w
    }
}
#[doc = "Reader of field `CKOUT1DIV`"]
pub type CKOUT1DIV_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `CKOUT1DIV`"]
pub struct CKOUT1DIV_W<'a> {
    w: &'a mut W,
}
impl<'a> CKOUT1DIV_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
        self.w
    }
}
impl R {
    #[doc = "Bits 0:2 - CKOUT1 Clock Source Selection"]
    #[inline(always)]
    pub fn ckout1sel(&self) -> CKOUT1SEL_R {
        CKOUT1SEL_R::new((self.bits & 0x07) as u8)
    }
    #[doc = "Bits 8:13 - The CK_OUT1 divider which the CK_OUT1 frequency can be reduced see bits 2:0 of RCU_CFG3 for CK_OUT1"]
    #[inline(always)]
    pub fn ckout1div(&self) -> CKOUT1DIV_R {
        CKOUT1DIV_R::new(((self.bits >> 8) & 0x3f) as u8)
    }
}
impl W {
    #[doc = "Bits 0:2 - CKOUT1 Clock Source Selection"]
    #[inline(always)]
    pub fn ckout1sel(&mut self) -> CKOUT1SEL_W {
        CKOUT1SEL_W { w: self }
    }
    #[doc = "Bits 8:13 - The CK_OUT1 divider which the CK_OUT1 frequency can be reduced see bits 2:0 of RCU_CFG3 for CK_OUT1"]
    #[inline(always)]
    pub fn ckout1div(&mut self) -> CKOUT1DIV_W {
        CKOUT1DIV_W { w: self }
    }
}