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#[doc = "Reader of register CTL"] pub type R = crate::R<u32, super::CTL>; #[doc = "Writer for register CTL"] pub type W = crate::W<u32, super::CTL>; #[doc = "Register CTL `reset()`'s with value 0"] impl crate::ResetValue for super::CTL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `CDT`"] pub type CDT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CDT`"] pub struct CDT_W<'a> { w: &'a mut W, } impl<'a> CDT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28); self.w } } #[doc = "Reader of field `CTDT`"] pub type CTDT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CTDT`"] pub struct CTDT_W<'a> { w: &'a mut W, } impl<'a> CTDT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24); self.w } } #[doc = "Reader of field `ECDT`"] pub type ECDT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `ECDT`"] pub struct ECDT_W<'a> { w: &'a mut W, } impl<'a> ECDT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 17)) | (((value as u32) & 0x7f) << 17); self.w } } #[doc = "Reader of field `ECEN`"] pub type ECEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ECEN`"] pub struct ECEN_W<'a> { w: &'a mut W, } impl<'a> ECEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `ECDIV`"] pub type ECDIV_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ECDIV`"] pub struct ECDIV_W<'a> { w: &'a mut W, } impl<'a> ECDIV_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `CTCDIV`"] pub type CTCDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CTCDIV`"] pub struct CTCDIV_W<'a> { w: &'a mut W, } impl<'a> CTCDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12); self.w } } #[doc = "Reader of field `MCN`"] pub type MCN_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MCN`"] pub struct MCN_W<'a> { w: &'a mut W, } impl<'a> MCN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5); self.w } } #[doc = "Reader of field `PINMOD`"] pub type PINMOD_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PINMOD`"] pub struct PINMOD_W<'a> { w: &'a mut W, } impl<'a> PINMOD_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4); self.w } } #[doc = "Reader of field `EGSEL`"] pub type EGSEL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EGSEL`"] pub struct EGSEL_W<'a> { w: &'a mut W, } impl<'a> EGSEL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `TRGMOD`"] pub type TRGMOD_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TRGMOD`"] pub struct TRGMOD_W<'a> { w: &'a mut W, } impl<'a> TRGMOD_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `TSIS`"] pub type TSIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSIS`"] pub struct TSIS_W<'a> { w: &'a mut W, } impl<'a> TSIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `TSIEN`"] pub type TSIEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `TSIEN`"] pub struct TSIEN_W<'a> { w: &'a mut W, } impl<'a> TSIEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bits 28:31 - Charge State Duration Time"] #[inline(always)] pub fn cdt(&self) -> CDT_R { CDT_R::new(((self.bits >> 28) & 0x0f) as u8) } #[doc = "Bits 24:27 - Charge Transfer State Duration Time"] #[inline(always)] pub fn ctdt(&self) -> CTDT_R { CTDT_R::new(((self.bits >> 24) & 0x0f) as u8) } #[doc = "Bits 17:23 - Extend Charge State Maximum Duration Time"] #[inline(always)] pub fn ecdt(&self) -> ECDT_R { ECDT_R::new(((self.bits >> 17) & 0x7f) as u8) } #[doc = "Bit 16 - Extend Charge State Enable"] #[inline(always)] pub fn ecen(&self) -> ECEN_R { ECEN_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 15 - ECCLK clock division factor"] #[inline(always)] pub fn ecdiv(&self) -> ECDIV_R { ECDIV_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bits 12:14 - CTCLK clock division factor"] #[inline(always)] pub fn ctcdiv(&self) -> CTCDIV_R { CTCDIV_R::new(((self.bits >> 12) & 0x07) as u8) } #[doc = "Bits 5:7 - Max cycle number of a sequence"] #[inline(always)] pub fn mcn(&self) -> MCN_R { MCN_R::new(((self.bits >> 5) & 0x07) as u8) } #[doc = "Bit 4 - Pin mode"] #[inline(always)] pub fn pinmod(&self) -> PINMOD_R { PINMOD_R::new(((self.bits >> 4) & 0x01) != 0) } #[doc = "Bit 3 - Edge selection"] #[inline(always)] pub fn egsel(&self) -> EGSEL_R { EGSEL_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 2 - Trigger mode selection"] #[inline(always)] pub fn trgmod(&self) -> TRGMOD_R { TRGMOD_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 1 - TSI start"] #[inline(always)] pub fn tsis(&self) -> TSIS_R { TSIS_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 0 - TSI enable"] #[inline(always)] pub fn tsien(&self) -> TSIEN_R { TSIEN_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bits 28:31 - Charge State Duration Time"] #[inline(always)] pub fn cdt(&mut self) -> CDT_W { CDT_W { w: self } } #[doc = "Bits 24:27 - Charge Transfer State Duration Time"] #[inline(always)] pub fn ctdt(&mut self) -> CTDT_W { CTDT_W { w: self } } #[doc = "Bits 17:23 - Extend Charge State Maximum Duration Time"] #[inline(always)] pub fn ecdt(&mut self) -> ECDT_W { ECDT_W { w: self } } #[doc = "Bit 16 - Extend Charge State Enable"] #[inline(always)] pub fn ecen(&mut self) -> ECEN_W { ECEN_W { w: self } } #[doc = "Bit 15 - ECCLK clock division factor"] #[inline(always)] pub fn ecdiv(&mut self) -> ECDIV_W { ECDIV_W { w: self } } #[doc = "Bits 12:14 - CTCLK clock division factor"] #[inline(always)] pub fn ctcdiv(&mut self) -> CTCDIV_W { CTCDIV_W { w: self } } #[doc = "Bits 5:7 - Max cycle number of a sequence"] #[inline(always)] pub fn mcn(&mut self) -> MCN_W { MCN_W { w: self } } #[doc = "Bit 4 - Pin mode"] #[inline(always)] pub fn pinmod(&mut self) -> PINMOD_W { PINMOD_W { w: self } } #[doc = "Bit 3 - Edge selection"] #[inline(always)] pub fn egsel(&mut self) -> EGSEL_W { EGSEL_W { w: self } } #[doc = "Bit 2 - Trigger mode selection"] #[inline(always)] pub fn trgmod(&mut self) -> TRGMOD_W { TRGMOD_W { w: self } } #[doc = "Bit 1 - TSI start"] #[inline(always)] pub fn tsis(&mut self) -> TSIS_W { TSIS_W { w: self } } #[doc = "Bit 0 - TSI enable"] #[inline(always)] pub fn tsien(&mut self) -> TSIEN_W { TSIEN_W { w: self } } }