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#[doc = "Reader of register CHCTL0_Output"] pub type R = crate::R<u16, super::CHCTL0_OUTPUT>; #[doc = "Writer for register CHCTL0_Output"] pub type W = crate::W<u16, super::CHCTL0_OUTPUT>; #[doc = "Register CHCTL0_Output `reset()`'s with value 0"] impl crate::ResetValue for super::CHCTL0_OUTPUT { type Type = u16; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Channel 0 mode selection\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum CH0MS_A { #[doc = "0: Channel is configured as output"] OUTPUT = 0, #[doc = "1: Channel is configured as input, ISx is connected to CI0FE0"] CI1 = 1, #[doc = "2: Channel is configured as input, ISx is connected to CI1FE0"] CI2 = 2, #[doc = "3: Channel is configured as input, ISx is connected to ITS"] ITS = 3, } impl From<CH0MS_A> for u8 { #[inline(always)] fn from(variant: CH0MS_A) -> Self { variant as _ } } #[doc = "Reader of field `CH0MS`"] pub type CH0MS_R = crate::R<u8, CH0MS_A>; impl CH0MS_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CH0MS_A { match self.bits { 0 => CH0MS_A::OUTPUT, 1 => CH0MS_A::CI1, 2 => CH0MS_A::CI2, 3 => CH0MS_A::ITS, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `OUTPUT`"] #[inline(always)] pub fn is_output(&self) -> bool { *self == CH0MS_A::OUTPUT } #[doc = "Checks if the value of the field is `CI1`"] #[inline(always)] pub fn is_ci1(&self) -> bool { *self == CH0MS_A::CI1 } #[doc = "Checks if the value of the field is `CI2`"] #[inline(always)] pub fn is_ci2(&self) -> bool { *self == CH0MS_A::CI2 } #[doc = "Checks if the value of the field is `ITS`"] #[inline(always)] pub fn is_its(&self) -> bool { *self == CH0MS_A::ITS } } #[doc = "Write proxy for field `CH0MS`"] pub struct CH0MS_W<'a> { w: &'a mut W, } impl<'a> CH0MS_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CH0MS_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "Channel is configured as output"] #[inline(always)] pub fn output(self) -> &'a mut W { self.variant(CH0MS_A::OUTPUT) } #[doc = "Channel is configured as input, ISx is connected to CI0FE0"] #[inline(always)] pub fn ci1(self) -> &'a mut W { self.variant(CH0MS_A::CI1) } #[doc = "Channel is configured as input, ISx is connected to CI1FE0"] #[inline(always)] pub fn ci2(self) -> &'a mut W { self.variant(CH0MS_A::CI2) } #[doc = "Channel is configured as input, ISx is connected to ITS"] #[inline(always)] pub fn its(self) -> &'a mut W { self.variant(CH0MS_A::ITS) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u16) & 0x03); self.w } } #[doc = "Channel 0 output compare fast enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0COMFEN_A { #[doc = "0: The minimum delay from an edge is 5 clock cycles"] SLOW = 0, #[doc = "1: The minimum delay from an edge is 3 clock cycles"] FAST = 1, } impl From<CH0COMFEN_A> for bool { #[inline(always)] fn from(variant: CH0COMFEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `CH0COMFEN`"] pub type CH0COMFEN_R = crate::R<bool, CH0COMFEN_A>; impl CH0COMFEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CH0COMFEN_A { match self.bits { false => CH0COMFEN_A::SLOW, true => CH0COMFEN_A::FAST, } } #[doc = "Checks if the value of the field is `SLOW`"] #[inline(always)] pub fn is_slow(&self) -> bool { *self == CH0COMFEN_A::SLOW } #[doc = "Checks if the value of the field is `FAST`"] #[inline(always)] pub fn is_fast(&self) -> bool { *self == CH0COMFEN_A::FAST } } #[doc = "Write proxy for field `CH0COMFEN`"] pub struct CH0COMFEN_W<'a> { w: &'a mut W, } impl<'a> CH0COMFEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CH0COMFEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "The minimum delay from an edge is 5 clock cycles"] #[inline(always)] pub fn slow(self) -> &'a mut W { self.variant(CH0COMFEN_A::SLOW) } #[doc = "The minimum delay from an edge is 3 clock cycles"] #[inline(always)] pub fn fast(self) -> &'a mut W { self.variant(CH0COMFEN_A::FAST) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2); self.w } } #[doc = "Channel 0 output compare shadow enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0COMSEN_A { #[doc = "0: Preload register on CHyCV disabled. New values written to CHyCV are taken into account immediately"] DISABLED = 0, #[doc = "1: Preload register on CHyCV enabled. Preload value is loaded into active register on each update event"] ENABLED = 1, } impl From<CH0COMSEN_A> for bool { #[inline(always)] fn from(variant: CH0COMSEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `CH0COMSEN`"] pub type CH0COMSEN_R = crate::R<bool, CH0COMSEN_A>; impl CH0COMSEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CH0COMSEN_A { match self.bits { false => CH0COMSEN_A::DISABLED, true => CH0COMSEN_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == CH0COMSEN_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == CH0COMSEN_A::ENABLED } } #[doc = "Write proxy for field `CH0COMSEN`"] pub struct CH0COMSEN_W<'a> { w: &'a mut W, } impl<'a> CH0COMSEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CH0COMSEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Preload register on CHyCV disabled. New values written to CHyCV are taken into account immediately"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(CH0COMSEN_A::DISABLED) } #[doc = "Preload register on CHyCV enabled. Preload value is loaded into active register on each update event"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(CH0COMSEN_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3); self.w } } #[doc = "Channel 0 compare output control\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum CH0COMCTL_A { #[doc = "0: The comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs"] FROZEN = 0, #[doc = "1: Set channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV"] ACTIVEONMATCH = 1, #[doc = "2: Set channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV"] INACTIVEONMATCH = 2, #[doc = "3: OxCPRE toggles when CNT=CHyCV"] TOGGLE = 3, #[doc = "4: OxCPRE is forced low"] FORCEINACTIVE = 4, #[doc = "5: OxCPRE is forced high"] FORCEACTIVE = 5, #[doc = "6: In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active"] PWMMODE1 = 6, #[doc = "7: Inversely to PwmMode1"] PWMMODE2 = 7, } impl From<CH0COMCTL_A> for u8 { #[inline(always)] fn from(variant: CH0COMCTL_A) -> Self { variant as _ } } #[doc = "Reader of field `CH0COMCTL`"] pub type CH0COMCTL_R = crate::R<u8, CH0COMCTL_A>; impl CH0COMCTL_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CH0COMCTL_A { match self.bits { 0 => CH0COMCTL_A::FROZEN, 1 => CH0COMCTL_A::ACTIVEONMATCH, 2 => CH0COMCTL_A::INACTIVEONMATCH, 3 => CH0COMCTL_A::TOGGLE, 4 => CH0COMCTL_A::FORCEINACTIVE, 5 => CH0COMCTL_A::FORCEACTIVE, 6 => CH0COMCTL_A::PWMMODE1, 7 => CH0COMCTL_A::PWMMODE2, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `FROZEN`"] #[inline(always)] pub fn is_frozen(&self) -> bool { *self == CH0COMCTL_A::FROZEN } #[doc = "Checks if the value of the field is `ACTIVEONMATCH`"] #[inline(always)] pub fn is_active_on_match(&self) -> bool { *self == CH0COMCTL_A::ACTIVEONMATCH } #[doc = "Checks if the value of the field is `INACTIVEONMATCH`"] #[inline(always)] pub fn is_inactive_on_match(&self) -> bool { *self == CH0COMCTL_A::INACTIVEONMATCH } #[doc = "Checks if the value of the field is `TOGGLE`"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == CH0COMCTL_A::TOGGLE } #[doc = "Checks if the value of the field is `FORCEINACTIVE`"] #[inline(always)] pub fn is_force_inactive(&self) -> bool { *self == CH0COMCTL_A::FORCEINACTIVE } #[doc = "Checks if the value of the field is `FORCEACTIVE`"] #[inline(always)] pub fn is_force_active(&self) -> bool { *self == CH0COMCTL_A::FORCEACTIVE } #[doc = "Checks if the value of the field is `PWMMODE1`"] #[inline(always)] pub fn is_pwm_mode1(&self) -> bool { *self == CH0COMCTL_A::PWMMODE1 } #[doc = "Checks if the value of the field is `PWMMODE2`"] #[inline(always)] pub fn is_pwm_mode2(&self) -> bool { *self == CH0COMCTL_A::PWMMODE2 } } #[doc = "Write proxy for field `CH0COMCTL`"] pub struct CH0COMCTL_W<'a> { w: &'a mut W, } impl<'a> CH0COMCTL_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CH0COMCTL_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "The comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs"] #[inline(always)] pub fn frozen(self) -> &'a mut W { self.variant(CH0COMCTL_A::FROZEN) } #[doc = "Set channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV"] #[inline(always)] pub fn active_on_match(self) -> &'a mut W { self.variant(CH0COMCTL_A::ACTIVEONMATCH) } #[doc = "Set channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV"] #[inline(always)] pub fn inactive_on_match(self) -> &'a mut W { self.variant(CH0COMCTL_A::INACTIVEONMATCH) } #[doc = "OxCPRE toggles when CNT=CHyCV"] #[inline(always)] pub fn toggle(self) -> &'a mut W { self.variant(CH0COMCTL_A::TOGGLE) } #[doc = "OxCPRE is forced low"] #[inline(always)] pub fn force_inactive(self) -> &'a mut W { self.variant(CH0COMCTL_A::FORCEINACTIVE) } #[doc = "OxCPRE is forced high"] #[inline(always)] pub fn force_active(self) -> &'a mut W { self.variant(CH0COMCTL_A::FORCEACTIVE) } #[doc = "In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active"] #[inline(always)] pub fn pwm_mode1(self) -> &'a mut W { self.variant(CH0COMCTL_A::PWMMODE1) } #[doc = "Inversely to PwmMode1"] #[inline(always)] pub fn pwm_mode2(self) -> &'a mut W { self.variant(CH0COMCTL_A::PWMMODE2) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u16) & 0x07) << 4); self.w } } #[doc = "Channel 0 output compare clear enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum CH0COMCEN_A { #[doc = "0: Output compare clear disabled"] DISABLED = 0, #[doc = "1: Output compare clear enabled"] ENABLED = 1, } impl From<CH0COMCEN_A> for bool { #[inline(always)] fn from(variant: CH0COMCEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `CH0COMCEN`"] pub type CH0COMCEN_R = crate::R<bool, CH0COMCEN_A>; impl CH0COMCEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> CH0COMCEN_A { match self.bits { false => CH0COMCEN_A::DISABLED, true => CH0COMCEN_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == CH0COMCEN_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == CH0COMCEN_A::ENABLED } } #[doc = "Write proxy for field `CH0COMCEN`"] pub struct CH0COMCEN_W<'a> { w: &'a mut W, } impl<'a> CH0COMCEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: CH0COMCEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "Output compare clear disabled"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(CH0COMCEN_A::DISABLED) } #[doc = "Output compare clear enabled"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(CH0COMCEN_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7); self.w } } impl R { #[doc = "Bits 0:1 - Channel 0 mode selection"] #[inline(always)] pub fn ch0ms(&self) -> CH0MS_R { CH0MS_R::new((self.bits & 0x03) as u8) } #[doc = "Bit 2 - Channel 0 output compare fast enable"] #[inline(always)] pub fn ch0comfen(&self) -> CH0COMFEN_R { CH0COMFEN_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - Channel 0 output compare shadow enable"] #[inline(always)] pub fn ch0comsen(&self) -> CH0COMSEN_R { CH0COMSEN_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bits 4:6 - Channel 0 compare output control"] #[inline(always)] pub fn ch0comctl(&self) -> CH0COMCTL_R { CH0COMCTL_R::new(((self.bits >> 4) & 0x07) as u8) } #[doc = "Bit 7 - Channel 0 output compare clear enable"] #[inline(always)] pub fn ch0comcen(&self) -> CH0COMCEN_R { CH0COMCEN_R::new(((self.bits >> 7) & 0x01) != 0) } } impl W { #[doc = "Bits 0:1 - Channel 0 mode selection"] #[inline(always)] pub fn ch0ms(&mut self) -> CH0MS_W { CH0MS_W { w: self } } #[doc = "Bit 2 - Channel 0 output compare fast enable"] #[inline(always)] pub fn ch0comfen(&mut self) -> CH0COMFEN_W { CH0COMFEN_W { w: self } } #[doc = "Bit 3 - Channel 0 output compare shadow enable"] #[inline(always)] pub fn ch0comsen(&mut self) -> CH0COMSEN_W { CH0COMSEN_W { w: self } } #[doc = "Bits 4:6 - Channel 0 compare output control"] #[inline(always)] pub fn ch0comctl(&mut self) -> CH0COMCTL_W { CH0COMCTL_W { w: self } } #[doc = "Bit 7 - Channel 0 output compare clear enable"] #[inline(always)] pub fn ch0comcen(&mut self) -> CH0COMCEN_W { CH0COMCEN_W { w: self } } }