[−][src]Module gba_addresses::io
IO Control Registers.
This region of memory allows you to control the various parts of the GBA.
Each register has its own unique purpose.
- They are often 16-bits, but not always.
- They are often write-only, though some are read/write, and some are read-only.
- A the timer addresses do different things between reading and writing.
Most names here are the same as in GBATEK with _ADDR on the end. Note
that some documents do sometimes use alternate names for some of the IO
registers (particularly the sound registers).
- Wait states: 0
- Bus Size: 32-bit
- Read/Write: 8/16/32
Constants
| BG0CNT_ADDR | BG0 Control (video modes 0 or 1) |
| BG0HOFS_ADDR | BG0 Horizontal Offset (video modes 0 or 1) |
| BG0VOFS_ADDR | BG0 Vertical Offset (video modes 0 or 1) |
| BG1CNT_ADDR | BG1 Control (video modes 0 or 1) |
| BG1HOFS_ADDR | BG1 Horizontal Offset (video modes 0 or 1) |
| BG1VOFS_ADDR | BG1 Vertical Offset (video modes 0 or 1) |
| BG2CNT_ADDR | BG2 Control (video modes 0, 1, or 2) |
| BG2HOFS_ADDR | BG2 Horizontal Offset (video mode 0) |
| BG2PA_ADDR | BG2 Affine Param A (video mode 1 and 2) |
| BG2PB_ADDR | BG2 Affine Param B (video mode 1 and 2) |
| BG2PC_ADDR | BG2 Affine Param C (video mode 1 and 2) |
| BG2PD_ADDR | BG2 Affine Param D (video mode 1 and 2) |
| BG2VOFS_ADDR | BG1 Vertical Offset (video mode 0) |
| BG2X_ADDR | BG2 X reference point (video mode 1, 2, 3, 4, and 5) |
| BG2Y_ADDR | BG2 Y reference point (video mode 1, 2, 3, 4, and 5) |
| BG3CNT_ADDR | BG3 Control (video modes 0 or 2) |
| BG3HOFS_ADDR | BG3 Horizontal Offset (video mode 0) |
| BG3PA_ADDR | BG3 Affine Param A (video mode 2) |
| BG3PB_ADDR | BG3 Affine Param B (video mode 2) |
| BG3PC_ADDR | BG3 Affine Param C (video mode 2) |
| BG3PD_ADDR | BG3 Affine Param D (video mode 2) |
| BG3VOFS_ADDR | BG3 Vertical Offset (video mode 0) |
| BG3X_ADDR | BG3 X reference point (video mode 2) |
| BG3Y_ADDR | BG3 Y reference point (video mode 2) |
| BLDALPHA_A_ADDR | Alpha blend |
| BLDALPHA_B_ADDR | Alpha blend |
| BLDCNT_ADDR | Color blend special effect. |
| BLDY_ADDR | Brightness blend |
| CHANNEL1_DUTY_LEN_ENV | Channel 1 duty / len / envelope |
| CHANNEL1_FREQ_CTRL | Channel 1 frequency / control |
| CHANNEL1_SWEEP | Channel 1 Sweep register. |
| CHANNEL2_DUTY_LEN_ENV | Channel 2 duty / len / envelope |
| CHANNEL2_FREQ_CTRL | Channel 2 frequency / control |
| CHANNEL3_FREQ_CTRL | Channel 3 frequency / control |
| CHANNEL3_LEN | Channel 3 len |
| CHANNEL3_SELECT | Channel 3 stop / wave RAM select |
| CHANNEL3_VOLUME | Channel 3 volume |
| CHANNEL4_FREQ_CTRL | Channel 4 frequency / control |
| CHANNEL4_LEN_ENV | Channel 4 len / envelope |
| CHANNELS_LEFT_RIGHT_ENABLED | Sound Control left/right volume/enable |
| CHANNELS_LEFT_RIGHT_VOLUME | Sound Control left/right volume/enable |
| DISPCNT_ADDR | Display Control |
| DISPSTAT_ADDR | Display Status |
| DMA0CNT_H_ADDR | DMA 0 control bits |
| DMA0CNT_L_ADDR | DMA 0 transfer count |
| DMA0DAD_ADDR | DMA 0 Destination Address |
| DMA0SAD_ADDR | DMA 0 Source Address |
| DMA1CNT_H_ADDR | DMA 1 control bits |
| DMA1CNT_L_ADDR | DMA 1 transfer count |
| DMA1DAD_ADDR | DMA 1 Destination Address |
| DMA1SAD_ADDR | DMA 1 Source Address |
| DMA2CNT_H_ADDR | DMA 2 control bits |
| DMA2CNT_L_ADDR | DMA 2 transfer count |
| DMA2DAD_ADDR | DMA 2 Destination Address |
| DMA2SAD_ADDR | DMA 2 Source Address |
| DMA3CNT_H_ADDR | DMA 3 control bits |
| DMA3CNT_L_ADDR | DMA 3 transfer count |
| DMA3DAD_ADDR | DMA 3 Destination Address |
| DMA3SAD_ADDR | DMA 3 Source Address |
| DMA_MIXING_CTRL | DMA Sound Control / Mixing |
| FIFO_A_ADDR | FIFO sound target for sound using DMA 1. |
| FIFO_B_ADDR | FIFO sound target for sound using DMA 2. |
| IE_ADDR | Interrupt Enable |
| IF_ADDR | Interrupt Flags |
| IME_ADDR | Interrupt Master Enable |
| JOYCNT_ADDR | ? |
| JOYSTAT_ADDR | ? |
| JOY_RECV_ADDR | ? |
| JOY_TRANS_ADDR | ? |
| KEYCNT_ADDR | Keypad interrupt control |
| KEYINPUT_ADDR | Keys pressed |
| MOSAIC_ADDR | Mosaic effect size. |
| OBJ_WIN_ADDR | Object window display. |
| RCNT_ADDR | ? |
| SIOCNT_ADDR | ? |
| SIODATA8_ADDR | ? |
| SIODATA32_ADDR | ? |
| SIOMLT_SEND_ADDR | ? |
| SIOMULTI0_ADDR | ? |
| SIOMULTI1_ADDR | ? |
| SIOMULTI2_ADDR | ? |
| SIOMULTI3_ADDR | ? |
| SOUNDBIAS | Final sound output bias. |
| SOUND_ENABLED_CTRL | Sound on/off |
| TM0CNT_H_ADDR | Timer 0 control bits |
| TM0CNT_L_ADDR | Timer 0 counter / reload |
| TM1CNT_H_ADDR | Timer 1 control bits |
| TM1CNT_L_ADDR | Timer 1 counter / reload |
| TM2CNT_H_ADDR | Timer 2 control bits |
| TM2CNT_L_ADDR | Timer 2 counter / reload |
| TM3CNT_H_ADDR | Timer 3 control bits |
| TM3CNT_L_ADDR | Timer 3 counter / reload |
| VCOUNT_ADDR | Vertical Counter |
| WAITCNT_ADDR | Waitstate Control |
| WAVE_RAM_BASE_ADDR | Wave RAM data. |
| WIN0H_ADDR | Window 0 horizontal. |
| WIN0V_ADDR | Window 0 vertical. |
| WIN0_IN_ADDR | Window 0 inside display. |
| WIN1H_ADDR | Window 1 horizontal. |
| WIN1V_ADDR | Window 0 vertical. |
| WIN1_IN_ADDR | Window 1 inside display. |
| WIN_OUT_ADDR | Outside window display. |