Enum HwReg

#[non_exhaustive]
pub enum HwReg {
    Ramg = 0,
    Romb0 = 8_192,
    Romb1 = 12_288,
    Ramb = 16_384,
    Rtclatch = 24_576,
    P1 = 65_280,
    Sb = 65_281,
    Sc = 65_282,
    Div = 65_284,
    Tima = 65_285,
    Tma = 65_286,
    Tac = 65_287,
    If = 65_295,
    Nr10 = 65_296,
    Nr11 = 65_297,
    Nr12 = 65_298,
    Nr13 = 65_299,
    Nr14 = 65_300,
    Nr21 = 65_302,
    Nr22 = 65_303,
    Nr23 = 65_304,
    Nr24 = 65_305,
    Nr30 = 65_306,
    Nr31 = 65_307,
    Nr32 = 65_308,
    Nr33 = 65_309,
    Nr34 = 65_310,
    Nr41 = 65_312,
    Nr42 = 65_313,
    Nr43 = 65_314,
    Nr44 = 65_315,
    Nr50 = 65_316,
    Nr51 = 65_317,
    Nr52 = 65_318,
    Wave0 = 65_328,
    Wave1 = 65_329,
    Wave2 = 65_330,
    Wave3 = 65_331,
    Wave4 = 65_332,
    Wave5 = 65_333,
    Wave6 = 65_334,
    Wave7 = 65_335,
    Wave8 = 65_336,
    Wave9 = 65_337,
    WaveA = 65_338,
    WaveB = 65_339,
    WaveC = 65_340,
    WaveD = 65_341,
    WaveE = 65_342,
    WaveF = 65_343,
    Lcdc = 65_344,
    Stat = 65_345,
    Scy = 65_346,
    Scx = 65_347,
    Ly = 65_348,
    Lyc = 65_349,
    Dma = 65_350,
    Bgp = 65_351,
    Obp0 = 65_352,
    Obp1 = 65_353,
    Wy = 65_354,
    Wx = 65_355,
    Key1 = 65_357,
    Vbk = 65_359,
    Hdma1 = 65_361,
    Hdma2 = 65_362,
    Hdma3 = 65_363,
    Hdma4 = 65_364,
    Hdma5 = 65_365,
    Rp = 65_366,
    Bcps = 65_384,
    Bcpd = 65_385,
    Ocps = 65_386,
    Ocpd = 65_387,
    Svbk = 65_392,
    Pcm12 = 65_398,
    Pcm34 = 65_399,
    Ie = 65_535,
}

A collection of hardware registers’ addresses, extracted from hardware.inc.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Ramg = 0

MBC SRAM enable.

Romb0 = 8_192

MBC ROM bank switch, low 8 bits.

Romb1 = 12_288

MBC ROM bank switch, upper 8 bits.

Ramb = 16_384

MBC SRAM bank switch.

Rtclatch = 24_576

MBC RTC latch toggle.

P1 = 65_280

Joypad.

Sb = 65_281

Serial data.

Sc = 65_282

Serial control.

Div = 65_284

Divided clock counter.

Tima = 65_285

Timer counter.

Tma = 65_286

Timer modulo.

Tac = 65_287

Timer control.

If = 65_295

Pending interrupts.

Nr10 = 65_296

CH1 frequency sweep.

Nr11 = 65_297

CH1 duty control & sound length.

Nr12 = 65_298

CH1 volume control.

Nr13 = 65_299

CH1 wave_length, low 8 bits.

Nr14 = 65_300

CH1 wave_length, upper 3 bits & control.

Nr21 = 65_302

CH2 duty control & sound length.

Nr22 = 65_303

CH2 volume control.

Nr23 = 65_304

CH2 wave_length, low 8 bits.

Nr24 = 65_305

CH2 wave_length, upper 3 bits & control.

Nr30 = 65_306

CH3 enable.

Nr31 = 65_307

CH3 sound length.

Nr32 = 65_308

CH3 volume control.

Nr33 = 65_309

CH3 wave_length, low 8 bits.

Nr34 = 65_310

CH3 wave_length, upper 3 bits.

Nr41 = 65_312

CH4 sound length.

Nr42 = 65_313

CH4 volume control.

Nr43 = 65_314

CH4 LFSR control.

Nr44 = 65_315

CH4 control.

Nr50 = 65_316

Master volume & VIN panning.

Nr51 = 65_317

Sound panning.

Nr52 = 65_318

Audio control.

Wave0 = 65_328

Wave1 = 65_329

Wave2 = 65_330

Wave3 = 65_331

Wave4 = 65_332

Wave5 = 65_333

Wave6 = 65_334

Wave7 = 65_335

Wave8 = 65_336

Wave9 = 65_337

WaveA = 65_338

WaveB = 65_339

WaveC = 65_340

WaveD = 65_341

WaveE = 65_342

WaveF = 65_343

Lcdc = 65_344

LCD control.

Stat = 65_345

LCD status.

Scy = 65_346

Viewport vertical offset.

Scx = 65_347

Viewport horizontal offset.

Ly = 65_348

Current scanline.

Lyc = 65_349

LY comparison.

Dma = 65_350

OAM DMA source & start.

Bgp = 65_351

DMG background palette.

Obp0 = 65_352

DMG OBJ palette 0.

Obp1 = 65_353

DMG OBJ palette 1.

Wy = 65_354

Window Y coordinate.

Wx = 65_355

Window X coordinate.

Key1 = 65_357

CGB speed switch.

Vbk = 65_359

CGB VRAM bank switch.

Hdma1 = 65_361

CGB DMA source, upper 8 bits.

Hdma2 = 65_362

CGB DMA source, lower 8 bits.

Hdma3 = 65_363

CGB DMA destination, upper 8 bits.

Hdma4 = 65_364

CGB DMA destination, lower 8 bits.

Hdma5 = 65_365

CGB DMA length & mode & start.

Rp = 65_366

CGB IR.

Bcps = 65_384

CGB BG palette address.

Bcpd = 65_385

CGB BG palette data.

Ocps = 65_386

CGB OBJ palette address.

Ocpd = 65_387

CGB OBJ palette data.

Svbk = 65_392

CGB WRAM bank switch.

Pcm12 = 65_398

CH1 & CH2 digital output.

Pcm34 = 65_399

CH3 & CH4 digital output.

Ie = 65_535

Enabled interrupts.

Trait Implementations

impl Clone for HwReg

fn clone(&self) -> HwReg

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for HwReg

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<HwReg> for u16

fn from(reg: HwReg) -> Self

Converts to this type from the input type.

impl TryFrom<u16> for HwReg

This tries to convert from a raw value into a HwReg. On failure, the original value is returned.

type Error = u16

The type returned in the event of a conversion error.

fn try_from(raw: u16) -> Result<Self, Self::Error>

Performs the conversion.

impl Copy for HwReg