[−][src]Module feather_m4::sercom
Working with the SERCOM peripherals.
The atsamd51 hardware has several SERCOM instances that can be configured to perform a variety of serial communication tasks. This configuration is expressed through the use of type states to make it difficult to misuse. Each sercom instance is associated with a group of IO pins referred to as a Pad. When the pins are set to the appropriate peripheral function mode they are routed to the sercom pad.
Structs
| I2CMaster0 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| I2CMaster1 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| I2CMaster2 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| I2CMaster3 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| I2CMaster4 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| I2CMaster5 | Represents the Sercom instance configured to act as an I2C Master. The embedded_hal blocking I2C traits are implemented by this instance. |
| SPIMaster0 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| SPIMaster1 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| SPIMaster2 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| SPIMaster3 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| SPIMaster4 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| SPIMaster5 | SPIMasterX represents the corresponding SERCOMX instance configured to
act in the role of an SPI Master.
Objects of this type implement the HAL |
| UART0 | |
| UART1 | |
| UART2 | |
| UART3 | |
| UART4 | |
| UART5 |
Enums
| Error | |
| I2CError | |
| SPI0Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| SPI1Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| SPI2Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| SPI3Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| SPI4Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| SPI5Pinout | When configured for SPI, in addition to the normal Sercom pad mapping, the SPI peripheral allows those pads to be assigned to different combinations of DI (data-in), DO (data-out), SCK (clock) and SS (slave select) functions. The SPIXPinOut types represent concrete pad mappings for a given SPI Instance. For slaves, DI is the MOSI function and DO is the MISO function. For masters, DI is the MISO function and DO is the MOSI function. The slave configurations all require an SS pin and are constructed using the enum variants ending with SS. The master confiugrations do not require an SS pin and are constructed using the other variants. The SPI master hardware has support for automatically managing the SS line to enable a slave, but this interface does not expose that functionality. The variant names refer to the Data-in-Data-out configuration that is used to configure the SPI peripheral. |
| Sercom0Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom0Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom0Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom0Pad3 | Represents a numbered pad for the associated sercom instance |
| Sercom1Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom1Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom1Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom1Pad3 | Represents a numbered pad for the associated sercom instance |
| Sercom2Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom2Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom2Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom2Pad3 | Represents a numbered pad for the associated sercom instance |
| Sercom3Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom3Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom3Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom3Pad3 | Represents a numbered pad for the associated sercom instance |
| Sercom4Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom4Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom4Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom4Pad3 | Represents a numbered pad for the associated sercom instance |
| Sercom5Pad0 | Represents a numbered pad for the associated sercom instance |
| Sercom5Pad1 | Represents a numbered pad for the associated sercom instance |
| Sercom5Pad2 | Represents a numbered pad for the associated sercom instance |
| Sercom5Pad3 | Represents a numbered pad for the associated sercom instance |
| UART0Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
| UART1Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
| UART2Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
| UART3Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
| UART4Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
| UART5Pinout | Similar to SPI Pinout the UART allows selecting any pad for RX and either pad 0 or 2 for TX |
Traits
| PadPin | The PadPin trait makes it more ergonomic to convert a pin into a Sercom pad. You should not implement this trait for yourself; only the implementations in the sercom module make sense. |