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#[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - UART FIFO,length 128"] pub uart_fifo: UART_FIFO, #[doc = "0x04 - UART INTERRUPT RAW STATE"] pub uart_int_raw: UART_INT_RAW, #[doc = "0x08 - UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] pub uart_int_st: UART_INT_ST, #[doc = "0x0c - UART INTERRUPT ENABLE REGISTER"] pub uart_int_ena: UART_INT_ENA, #[doc = "0x10 - UART INTERRUPT CLEAR REGISTER"] pub uart_int_clr: UART_INT_CLR, #[doc = "0x14 - UART CLK DIV REGISTER"] pub uart_clkdiv: UART_CLKDIV, #[doc = "0x18 - UART BAUDRATE DETECT REGISTER"] pub uart_autobaud: UART_AUTOBAUD, #[doc = "0x1c - UART STATUS REGISTER"] pub uart_status: UART_STATUS, #[doc = "0x20 - UART CONFIG0(UART0 and UART1)"] pub uart_conf0: UART_CONF0, #[doc = "0x24 - Set this bit to enable rx time-out function"] pub uart_conf1: UART_CONF1, #[doc = "0x28 - UART_LOWPULSE"] pub uart_lowpulse: UART_LOWPULSE, #[doc = "0x2c - UART_HIGHPULSE"] pub uart_highpulse: UART_HIGHPULSE, #[doc = "0x30 - UART_RXD_CNT"] pub uart_rxd_cnt: UART_RXD_CNT, _reserved13: [u8; 68usize], #[doc = "0x78 - UART HW INFO"] pub uart_date: UART_DATE, } #[doc = "UART FIFO,length 128\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_fifo](uart_fifo) module"] pub type UART_FIFO = crate::Reg<u32, _UART_FIFO>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_FIFO; #[doc = "`read()` method returns [uart_fifo::R](uart_fifo::R) reader structure"] impl crate::Readable for UART_FIFO {} #[doc = "`write(|w| ..)` method takes [uart_fifo::W](uart_fifo::W) writer structure"] impl crate::Writable for UART_FIFO {} #[doc = "UART FIFO,length 128"] pub mod uart_fifo; #[doc = "UART INTERRUPT RAW STATE\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_raw](uart_int_raw) module"] pub type UART_INT_RAW = crate::Reg<u32, _UART_INT_RAW>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_INT_RAW; #[doc = "`read()` method returns [uart_int_raw::R](uart_int_raw::R) reader structure"] impl crate::Readable for UART_INT_RAW {} #[doc = "`write(|w| ..)` method takes [uart_int_raw::W](uart_int_raw::W) writer structure"] impl crate::Writable for UART_INT_RAW {} #[doc = "UART INTERRUPT RAW STATE"] pub mod uart_int_raw; #[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_st](uart_int_st) module"] pub type UART_INT_ST = crate::Reg<u32, _UART_INT_ST>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_INT_ST; #[doc = "`read()` method returns [uart_int_st::R](uart_int_st::R) reader structure"] impl crate::Readable for UART_INT_ST {} #[doc = "`write(|w| ..)` method takes [uart_int_st::W](uart_int_st::W) writer structure"] impl crate::Writable for UART_INT_ST {} #[doc = "UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA"] pub mod uart_int_st; #[doc = "UART INTERRUPT ENABLE REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_ena](uart_int_ena) module"] pub type UART_INT_ENA = crate::Reg<u32, _UART_INT_ENA>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_INT_ENA; #[doc = "`read()` method returns [uart_int_ena::R](uart_int_ena::R) reader structure"] impl crate::Readable for UART_INT_ENA {} #[doc = "`write(|w| ..)` method takes [uart_int_ena::W](uart_int_ena::W) writer structure"] impl crate::Writable for UART_INT_ENA {} #[doc = "UART INTERRUPT ENABLE REGISTER"] pub mod uart_int_ena; #[doc = "UART INTERRUPT CLEAR REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_clr](uart_int_clr) module"] pub type UART_INT_CLR = crate::Reg<u32, _UART_INT_CLR>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_INT_CLR; #[doc = "`read()` method returns [uart_int_clr::R](uart_int_clr::R) reader structure"] impl crate::Readable for UART_INT_CLR {} #[doc = "`write(|w| ..)` method takes [uart_int_clr::W](uart_int_clr::W) writer structure"] impl crate::Writable for UART_INT_CLR {} #[doc = "UART INTERRUPT CLEAR REGISTER"] pub mod uart_int_clr; #[doc = "UART CLK DIV REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_clkdiv](uart_clkdiv) module"] pub type UART_CLKDIV = crate::Reg<u32, _UART_CLKDIV>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_CLKDIV; #[doc = "`read()` method returns [uart_clkdiv::R](uart_clkdiv::R) reader structure"] impl crate::Readable for UART_CLKDIV {} #[doc = "`write(|w| ..)` method takes [uart_clkdiv::W](uart_clkdiv::W) writer structure"] impl crate::Writable for UART_CLKDIV {} #[doc = "UART CLK DIV REGISTER"] pub mod uart_clkdiv; #[doc = "UART BAUDRATE DETECT REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_autobaud](uart_autobaud) module"] pub type UART_AUTOBAUD = crate::Reg<u32, _UART_AUTOBAUD>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_AUTOBAUD; #[doc = "`read()` method returns [uart_autobaud::R](uart_autobaud::R) reader structure"] impl crate::Readable for UART_AUTOBAUD {} #[doc = "`write(|w| ..)` method takes [uart_autobaud::W](uart_autobaud::W) writer structure"] impl crate::Writable for UART_AUTOBAUD {} #[doc = "UART BAUDRATE DETECT REGISTER"] pub mod uart_autobaud; #[doc = "UART STATUS REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_status](uart_status) module"] pub type UART_STATUS = crate::Reg<u32, _UART_STATUS>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_STATUS; #[doc = "`read()` method returns [uart_status::R](uart_status::R) reader structure"] impl crate::Readable for UART_STATUS {} #[doc = "`write(|w| ..)` method takes [uart_status::W](uart_status::W) writer structure"] impl crate::Writable for UART_STATUS {} #[doc = "UART STATUS REGISTER"] pub mod uart_status; #[doc = "UART CONFIG0(UART0 and UART1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_conf0](uart_conf0) module"] pub type UART_CONF0 = crate::Reg<u32, _UART_CONF0>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_CONF0; #[doc = "`read()` method returns [uart_conf0::R](uart_conf0::R) reader structure"] impl crate::Readable for UART_CONF0 {} #[doc = "`write(|w| ..)` method takes [uart_conf0::W](uart_conf0::W) writer structure"] impl crate::Writable for UART_CONF0 {} #[doc = "UART CONFIG0(UART0 and UART1)"] pub mod uart_conf0; #[doc = "Set this bit to enable rx time-out function\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_conf1](uart_conf1) module"] pub type UART_CONF1 = crate::Reg<u32, _UART_CONF1>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_CONF1; #[doc = "`read()` method returns [uart_conf1::R](uart_conf1::R) reader structure"] impl crate::Readable for UART_CONF1 {} #[doc = "`write(|w| ..)` method takes [uart_conf1::W](uart_conf1::W) writer structure"] impl crate::Writable for UART_CONF1 {} #[doc = "Set this bit to enable rx time-out function"] pub mod uart_conf1; #[doc = "UART_LOWPULSE\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_lowpulse](uart_lowpulse) module"] pub type UART_LOWPULSE = crate::Reg<u32, _UART_LOWPULSE>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_LOWPULSE; #[doc = "`read()` method returns [uart_lowpulse::R](uart_lowpulse::R) reader structure"] impl crate::Readable for UART_LOWPULSE {} #[doc = "`write(|w| ..)` method takes [uart_lowpulse::W](uart_lowpulse::W) writer structure"] impl crate::Writable for UART_LOWPULSE {} #[doc = "UART_LOWPULSE"] pub mod uart_lowpulse; #[doc = "UART_HIGHPULSE\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_highpulse](uart_highpulse) module"] pub type UART_HIGHPULSE = crate::Reg<u32, _UART_HIGHPULSE>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_HIGHPULSE; #[doc = "`read()` method returns [uart_highpulse::R](uart_highpulse::R) reader structure"] impl crate::Readable for UART_HIGHPULSE {} #[doc = "`write(|w| ..)` method takes [uart_highpulse::W](uart_highpulse::W) writer structure"] impl crate::Writable for UART_HIGHPULSE {} #[doc = "UART_HIGHPULSE"] pub mod uart_highpulse; #[doc = "UART_RXD_CNT\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_rxd_cnt](uart_rxd_cnt) module"] pub type UART_RXD_CNT = crate::Reg<u32, _UART_RXD_CNT>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_RXD_CNT; #[doc = "`read()` method returns [uart_rxd_cnt::R](uart_rxd_cnt::R) reader structure"] impl crate::Readable for UART_RXD_CNT {} #[doc = "`write(|w| ..)` method takes [uart_rxd_cnt::W](uart_rxd_cnt::W) writer structure"] impl crate::Writable for UART_RXD_CNT {} #[doc = "UART_RXD_CNT"] pub mod uart_rxd_cnt; #[doc = "UART HW INFO\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_date](uart_date) module"] pub type UART_DATE = crate::Reg<u32, _UART_DATE>; #[allow(missing_docs)] #[doc(hidden)] pub struct _UART_DATE; #[doc = "`read()` method returns [uart_date::R](uart_date::R) reader structure"] impl crate::Readable for UART_DATE {} #[doc = "`write(|w| ..)` method takes [uart_date::W](uart_date::W) writer structure"] impl crate::Writable for UART_DATE {} #[doc = "UART HW INFO"] pub mod uart_date;