Module esp32s3::lcd_cam::lcd_clock

LCD clock configuration register

Structs

• LCD_CLOCK_SPEC
  LCD clock configuration register

Type Aliases

• CLK_EN_R
  Field CLK_EN reader - Set this bit to force enable the clock for all configuration registers. Clock gate is not used.
• CLK_EN_W
  Field CLK_EN writer - Set this bit to force enable the clock for all configuration registers. Clock gate is not used.
• LCD_CK_IDLE_EDGE_R
  Field LCD_CK_IDLE_EDGE reader - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle.
• LCD_CK_IDLE_EDGE_W
  Field LCD_CK_IDLE_EDGE writer - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle.
• LCD_CK_OUT_EDGE_R
  Field LCD_CK_OUT_EDGE reader - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle.
• LCD_CK_OUT_EDGE_W
  Field LCD_CK_OUT_EDGE writer - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle.
• LCD_CLKCNT_N_R
  Field LCD_CLKCNT_N reader - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0.
• LCD_CLKCNT_N_W
  Field LCD_CLKCNT_N writer - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0.
• LCD_CLKM_DIV_A_R
  Field LCD_CLKM_DIV_A reader - Fractional clock divider denominator value.
• LCD_CLKM_DIV_A_W
  Field LCD_CLKM_DIV_A writer - Fractional clock divider denominator value.
• LCD_CLKM_DIV_B_R
  Field LCD_CLKM_DIV_B reader - Fractional clock divider numerator value.
• LCD_CLKM_DIV_B_W
  Field LCD_CLKM_DIV_B writer - Fractional clock divider numerator value.
• LCD_CLKM_DIV_NUM_R
  Field LCD_CLKM_DIV_NUM reader - Integral LCD clock divider value.
• LCD_CLKM_DIV_NUM_W
  Field LCD_CLKM_DIV_NUM writer - Integral LCD clock divider value.
• LCD_CLK_EQU_SYSCLK_R
  Field LCD_CLK_EQU_SYSCLK reader - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1).
• LCD_CLK_EQU_SYSCLK_W
  Field LCD_CLK_EQU_SYSCLK writer - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1).
• LCD_CLK_SEL_R
  Field LCD_CLK_SEL reader - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.
• LCD_CLK_SEL_W
  Field LCD_CLK_SEL writer - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.
• R
  Register LCD_CLOCK reader
• W
  Register LCD_CLOCK writer