Expand description
Universal Host Controller Interface 0
Modules
- UHCI ACK number configuration
- Software interrupt trigger source
- UHCI configuration register
- UHCI configuration register
- UHCI version control register
- Escape sequence configuration register 0
- Escape sequence configuration register 1
- Escape sequence configuration register 2
- Escape sequence configuration register 3
- Escape character configuration
- Timeout configuration
- Interrupt clear bits
- Interrupt enable bits
- Raw interrupt status
- Masked interrupt status
- Configure register for packet length
- UHCI quick send configuration register
- Q0_WORD0 quick_sent register
- Q0_WORD1 quick_sent register
- Q1_WORD0 quick_sent register
- Q1_WORD1 quick_sent register
- Q2_WORD0 quick_sent register
- Q2_WORD1 quick_sent register
- Q3_WORD0 quick_sent register
- Q3_WORD1 quick_sent register
- Q4_WORD0 quick_sent register
- Q4_WORD1 quick_sent register
- Q5_WORD0 quick_sent register
- Q5_WORD1 quick_sent register
- Q6_WORD0 quick_sent register
- Q6_WORD1 quick_sent register
- UHCI packet header register
- UHCI receive status
- UHCI transmit status
Structs
- Register block
Type Aliases
- ACK_NUM (rw) register accessor: UHCI ACK number configuration
- APP_INT_SET (w) register accessor: Software interrupt trigger source
- CONF0 (rw) register accessor: UHCI configuration register
- CONF1 (rw) register accessor: UHCI configuration register
- DATE (rw) register accessor: UHCI version control register
- ESCAPE_CONF (rw) register accessor: Escape character configuration
- ESC_CONF0 (rw) register accessor: Escape sequence configuration register 0
- ESC_CONF1 (rw) register accessor: Escape sequence configuration register 1
- ESC_CONF2 (rw) register accessor: Escape sequence configuration register 2
- ESC_CONF3 (rw) register accessor: Escape sequence configuration register 3
- HUNG_CONF (rw) register accessor: Timeout configuration
- INT_CLR (w) register accessor: Interrupt clear bits
- INT_ENA (rw) register accessor: Interrupt enable bits
- INT_RAW (rw) register accessor: Raw interrupt status
- INT_ST (r) register accessor: Masked interrupt status
- PKT_THRES (rw) register accessor: Configure register for packet length
- QUICK_SENT (rw) register accessor: UHCI quick send configuration register
- REG_Q0_WORD0 (rw) register accessor: Q0_WORD0 quick_sent register
- REG_Q0_WORD1 (rw) register accessor: Q0_WORD1 quick_sent register
- REG_Q1_WORD0 (rw) register accessor: Q1_WORD0 quick_sent register
- REG_Q1_WORD1 (rw) register accessor: Q1_WORD1 quick_sent register
- REG_Q2_WORD0 (rw) register accessor: Q2_WORD0 quick_sent register
- REG_Q2_WORD1 (rw) register accessor: Q2_WORD1 quick_sent register
- REG_Q3_WORD0 (rw) register accessor: Q3_WORD0 quick_sent register
- REG_Q3_WORD1 (rw) register accessor: Q3_WORD1 quick_sent register
- REG_Q4_WORD0 (rw) register accessor: Q4_WORD0 quick_sent register
- REG_Q4_WORD1 (rw) register accessor: Q4_WORD1 quick_sent register
- REG_Q5_WORD0 (rw) register accessor: Q5_WORD0 quick_sent register
- REG_Q5_WORD1 (rw) register accessor: Q5_WORD1 quick_sent register
- REG_Q6_WORD0 (rw) register accessor: Q6_WORD0 quick_sent register
- REG_Q6_WORD1 (rw) register accessor: Q6_WORD1 quick_sent register
- RX_HEAD (r) register accessor: UHCI packet header register
- STATE0 (r) register accessor: UHCI receive status
- STATE1 (r) register accessor: UHCI transmit status