Struct esp32s3::rtc_cntl::wdtconfig0::R

pub struct R(_);

Register WDTCONFIG0 reader

Implementations

impl R

pub fn wdt_chip_reset_width(&self) -> WDT_CHIP_RESET_WIDTH_R

Bits 0:7 - chip reset siginal pulse width

pub fn wdt_chip_reset_en(&self) -> WDT_CHIP_RESET_EN_R

Bit 8 - wdt reset whole chip enable

pub fn wdt_pause_in_slp(&self) -> WDT_PAUSE_IN_SLP_R

Bit 9 - pause WDT in sleep

pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R

Bit 10 - enable WDT reset APP CPU

pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R

Bit 11 - enable WDT reset PRO CPU

pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R

Bit 12 - enable WDT in flash boot

pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R

Bits 13:15 - system reset counter length

pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R

Bits 16:18 - CPU reset counter length

pub fn wdt_stg3(&self) -> WDT_STG3_R

Bits 19:21 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en

pub fn wdt_stg2(&self) -> WDT_STG2_R

Bits 22:24 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en

pub fn wdt_stg1(&self) -> WDT_STG1_R

Bits 25:27 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en

pub fn wdt_stg0(&self) -> WDT_STG0_R

Bits 28:30 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en

pub fn wdt_en(&self) -> WDT_EN_R

Bit 31 - enable rtc watch dog

Methods from Deref<Target = R<WDTCONFIG0_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<WDTCONFIG0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<WDTCONFIG0_SPEC>> for R

fn from(reader: R<WDTCONFIG0_SPEC>) -> Self

Converts to this type from the input type.