Module esp32s3::sensitive::core_1_pif_pms_constrain_9

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Expand description

Core1 access peripherals permission configuration register 9.

Structs

CORE_1_PIF_PMS_CONSTRAIN_9_SPEC
Core1 access peripherals permission configuration register 9.
R
Register CORE_1_PIF_PMS_CONSTRAIN_9 reader
W
Register CORE_1_PIF_PMS_CONSTRAIN_9 writer

Type Definitions

CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R
Field CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 reader - RTCFast memory split address in world 0 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W
Field CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 writer - RTCFast memory split address in world 0 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R
Field CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 reader - RTCFast memory split address in world 1 for core1.
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W
Field CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 writer - RTCFast memory split address in world 1 for core1.