Type Alias W

pub type W = W<LCD_D_MODE_SPEC>;

Register LCD_D_MODE writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn d_dqs_mode(&mut self) -> D_DQS_MODE_W<'_, LCD_D_MODE_SPEC>

Bits 0:2 - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

pub fn d_cd_mode(&mut self) -> D_CD_MODE_W<'_, LCD_D_MODE_SPEC>

Bits 3:5 - the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

pub fn d_de_mode(&mut self) -> D_DE_MODE_W<'_, LCD_D_MODE_SPEC>

Bits 6:8 - the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

pub fn d_hsync_mode(&mut self) -> D_HSYNC_MODE_W<'_, LCD_D_MODE_SPEC>

Bits 9:11 - the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

pub fn d_vsync_mode(&mut self) -> D_VSYNC_MODE_W<'_, LCD_D_MODE_SPEC>

Bits 12:14 - the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.

pub fn de_idle_pol(&mut self) -> DE_IDLE_POL_W<'_, LCD_D_MODE_SPEC>

Bit 15 - It is the idle value of spi_de.

pub fn hs_blank_en(&mut self) -> HS_BLANK_EN_W<'_, LCD_D_MODE_SPEC>

Bit 16 - 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.