Module esp32s2::uhci0::conf1

UHCI configuration register

Structs

• CONF1_SPEC
  UHCI configuration register
• R
  Register CONF1 reader
• W
  Register CONF1 writer

Type Definitions

• CHECK_OWNER_R
  Field CHECK_OWNER reader - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor.
• CHECK_OWNER_W
  Field CHECK_OWNER writer - 1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor.
• CHECK_SEQ_EN_R
  Field CHECK_SEQ_EN reader - This is the enable bit to check sequence number when UHCI receives a data packet.
• CHECK_SEQ_EN_W
  Field CHECK_SEQ_EN writer - This is the enable bit to check sequence number when UHCI receives a data packet.
• CHECK_SUM_EN_R
  Field CHECK_SUM_EN reader - This is the enable bit to check header checksum when UHCI receives a data packet.
• CHECK_SUM_EN_W
  Field CHECK_SUM_EN writer - This is the enable bit to check header checksum when UHCI receives a data packet.
• CRC_DISABLE_R
  Field CRC_DISABLE reader - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1.
• CRC_DISABLE_W
  Field CRC_DISABLE writer - Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1.
• DMA_INFIFO_FULL_THRS_R
  Field DMA_INFIFO_FULL_THRS reader - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register.
• DMA_INFIFO_FULL_THRS_W
  Field DMA_INFIFO_FULL_THRS writer - This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register.
• SAVE_HEAD_R
  Field SAVE_HEAD reader - Set this bit to save the packet header when UHCI receives a data packet.
• SAVE_HEAD_W
  Field SAVE_HEAD writer - Set this bit to save the packet header when UHCI receives a data packet.
• SW_START_R
  Field SW_START reader - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.
• SW_START_W
  Field SW_START writer - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.
• TX_ACK_NUM_RE_R
  Field TX_ACK_NUM_RE reader - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit.
• TX_ACK_NUM_RE_W
  Field TX_ACK_NUM_RE writer - Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit.
• TX_CHECK_SUM_RE_R
  Field TX_CHECK_SUM_RE reader - Set this bit to encode the data packet with a checksum.
• TX_CHECK_SUM_RE_W
  Field TX_CHECK_SUM_RE writer - Set this bit to encode the data packet with a checksum.
• WAIT_SW_START_R
  Field WAIT_SW_START reader - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1.
• WAIT_SW_START_W
  Field WAIT_SW_START writer - The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1.