esp32p4/spi1/
ctrl1.rs

1#[doc = "Register `CTRL1` reader"]
2pub type R = crate::R<CTRL1_SPEC>;
3#[doc = "Register `CTRL1` writer"]
4pub type W = crate::W<CTRL1_SPEC>;
5#[doc = "Field `CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
6pub type CLK_MODE_R = crate::FieldReader;
7#[doc = "Field `CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
8pub type CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CS_HOLD_DLY_RES` reader - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."]
10pub type CS_HOLD_DLY_RES_R = crate::FieldReader<u16>;
11#[doc = "Field `CS_HOLD_DLY_RES` writer - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."]
12pub type CS_HOLD_DLY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
13impl R {
14    #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
15    #[inline(always)]
16    pub fn clk_mode(&self) -> CLK_MODE_R {
17        CLK_MODE_R::new((self.bits & 3) as u8)
18    }
19    #[doc = "Bits 2:11 - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."]
20    #[inline(always)]
21    pub fn cs_hold_dly_res(&self) -> CS_HOLD_DLY_RES_R {
22        CS_HOLD_DLY_RES_R::new(((self.bits >> 2) & 0x03ff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CTRL1")
29            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
30            .field(
31                "cs_hold_dly_res",
32                &format_args!("{}", self.cs_hold_dly_res().bits()),
33            )
34            .finish()
35    }
36}
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
39    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
40        core::fmt::Debug::fmt(&self.read(), f)
41    }
42}
43impl W {
44    #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
45    #[inline(always)]
46    #[must_use]
47    pub fn clk_mode(&mut self) -> CLK_MODE_W<CTRL1_SPEC> {
48        CLK_MODE_W::new(self, 0)
49    }
50    #[doc = "Bits 2:11 - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."]
51    #[inline(always)]
52    #[must_use]
53    pub fn cs_hold_dly_res(&mut self) -> CS_HOLD_DLY_RES_W<CTRL1_SPEC> {
54        CS_HOLD_DLY_RES_W::new(self, 2)
55    }
56}
57#[doc = "SPI1 control1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
58pub struct CTRL1_SPEC;
59impl crate::RegisterSpec for CTRL1_SPEC {
60    type Ux = u32;
61}
62#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
63impl crate::Readable for CTRL1_SPEC {}
64#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
65impl crate::Writable for CTRL1_SPEC {
66    type Safety = crate::Unsafe;
67    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69}
70#[doc = "`reset()` method sets CTRL1 to value 0x0ffc"]
71impl crate::Resettable for CTRL1_SPEC {
72    const RESET_VALUE: u32 = 0x0ffc;
73}
esp32p4/spi1/ctrl1.rs

esp32p4/spi1/
ctrl1.rs
