1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_WM` writer - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."]
4pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_WM` writer - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."]
6pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RXFIFO_OVF` writer - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."]
8pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `END_DETECT` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."]
10pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `BYTE_TRANS_DONE` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."]
12pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ARBITRATION_LOST` writer - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."]
14pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `MST_TXFIFO_UDF` writer - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."]
16pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` writer - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."]
18pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TIME_OUT` writer - Write 1 to clear the I2C_TIME_OUT_INT interrupt."]
20pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TRANS_START` writer - Write 1 to clear the I2C_TRANS_START_INT interrupt."]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `NACK` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."]
24pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `TXFIFO_OVF` writer - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."]
26pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `RXFIFO_UDF` writer - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."]
28pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `SCL_ST_TO` writer - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."]
30pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SCL_MAIN_ST_TO` writer - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
32pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `DET_START` writer - Write 1 to clear I2C_DET_START_INT interrupt."]
34pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `SLAVE_STRETCH` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."]
36pub type SLAVE_STRETCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `GENERAL_CALL` writer - Write 1 to clear I2C_GENARAL_CALL_INT interrupt."]
38pub type GENERAL_CALL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `SLAVE_ADDR_UNMATCH` writer - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."]
40pub type SLAVE_ADDR_UNMATCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
43 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
44 write!(f, "(not readable)")
45 }
46}
47impl W {
48 #[doc = "Bit 0 - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."]
49 #[inline(always)]
50 #[must_use]
51 pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
52 RXFIFO_WM_W::new(self, 0)
53 }
54 #[doc = "Bit 1 - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."]
55 #[inline(always)]
56 #[must_use]
57 pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
58 TXFIFO_WM_W::new(self, 1)
59 }
60 #[doc = "Bit 2 - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."]
61 #[inline(always)]
62 #[must_use]
63 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
64 RXFIFO_OVF_W::new(self, 2)
65 }
66 #[doc = "Bit 3 - Write 1 to clear the I2C_END_DETECT_INT interrupt."]
67 #[inline(always)]
68 #[must_use]
69 pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
70 END_DETECT_W::new(self, 3)
71 }
72 #[doc = "Bit 4 - Write 1 to clear the I2C_END_DETECT_INT interrupt."]
73 #[inline(always)]
74 #[must_use]
75 pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
76 BYTE_TRANS_DONE_W::new(self, 4)
77 }
78 #[doc = "Bit 5 - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."]
79 #[inline(always)]
80 #[must_use]
81 pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
82 ARBITRATION_LOST_W::new(self, 5)
83 }
84 #[doc = "Bit 6 - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."]
85 #[inline(always)]
86 #[must_use]
87 pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
88 MST_TXFIFO_UDF_W::new(self, 6)
89 }
90 #[doc = "Bit 7 - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."]
91 #[inline(always)]
92 #[must_use]
93 pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
94 TRANS_COMPLETE_W::new(self, 7)
95 }
96 #[doc = "Bit 8 - Write 1 to clear the I2C_TIME_OUT_INT interrupt."]
97 #[inline(always)]
98 #[must_use]
99 pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
100 TIME_OUT_W::new(self, 8)
101 }
102 #[doc = "Bit 9 - Write 1 to clear the I2C_TRANS_START_INT interrupt."]
103 #[inline(always)]
104 #[must_use]
105 pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
106 TRANS_START_W::new(self, 9)
107 }
108 #[doc = "Bit 10 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."]
109 #[inline(always)]
110 #[must_use]
111 pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
112 NACK_W::new(self, 10)
113 }
114 #[doc = "Bit 11 - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."]
115 #[inline(always)]
116 #[must_use]
117 pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
118 TXFIFO_OVF_W::new(self, 11)
119 }
120 #[doc = "Bit 12 - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."]
121 #[inline(always)]
122 #[must_use]
123 pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
124 RXFIFO_UDF_W::new(self, 12)
125 }
126 #[doc = "Bit 13 - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."]
127 #[inline(always)]
128 #[must_use]
129 pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
130 SCL_ST_TO_W::new(self, 13)
131 }
132 #[doc = "Bit 14 - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
133 #[inline(always)]
134 #[must_use]
135 pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
136 SCL_MAIN_ST_TO_W::new(self, 14)
137 }
138 #[doc = "Bit 15 - Write 1 to clear I2C_DET_START_INT interrupt."]
139 #[inline(always)]
140 #[must_use]
141 pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
142 DET_START_W::new(self, 15)
143 }
144 #[doc = "Bit 16 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."]
145 #[inline(always)]
146 #[must_use]
147 pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_CLR_SPEC> {
148 SLAVE_STRETCH_W::new(self, 16)
149 }
150 #[doc = "Bit 17 - Write 1 to clear I2C_GENARAL_CALL_INT interrupt."]
151 #[inline(always)]
152 #[must_use]
153 pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_CLR_SPEC> {
154 GENERAL_CALL_W::new(self, 17)
155 }
156 #[doc = "Bit 18 - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."]
157 #[inline(always)]
158 #[must_use]
159 pub fn slave_addr_unmatch(&mut self) -> SLAVE_ADDR_UNMATCH_W<INT_CLR_SPEC> {
160 SLAVE_ADDR_UNMATCH_W::new(self, 18)
161 }
162}
163#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
164pub struct INT_CLR_SPEC;
165impl crate::RegisterSpec for INT_CLR_SPEC {
166 type Ux = u32;
167}
168#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
169impl crate::Writable for INT_CLR_SPEC {
170 type Safety = crate::Unsafe;
171 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
172 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ffff;
173}
174#[doc = "`reset()` method sets INT_CLR to value 0"]
175impl crate::Resettable for INT_CLR_SPEC {
176 const RESET_VALUE: u32 = 0;
177}