Module esp32c6::extmem

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Expand description

External Memory

Modules§

Structs§

Type Aliases§

  • CACHE_LOCK_ADDR
    CACHE_LOCK_ADDR (rw) register accessor: Lock (manual lock) address configure register
  • CACHE_LOCK_CTRL
    CACHE_LOCK_CTRL (rw) register accessor: Lock-class (manual lock) operation control register
  • CACHE_LOCK_MAP
    CACHE_LOCK_MAP (rw) register accessor: Lock (manual lock) map configure register
  • CACHE_LOCK_SIZE
    CACHE_LOCK_SIZE (rw) register accessor: Lock (manual lock) size configure register
  • CACHE_SYNC_ADDR
    CACHE_SYNC_ADDR (rw) register accessor: Sync address configure register
  • CACHE_SYNC_CTRL
    CACHE_SYNC_CTRL (rw) register accessor: Sync-class operation control register
  • CACHE_SYNC_MAP
    CACHE_SYNC_MAP (rw) register accessor: Sync map configure register
  • CACHE_SYNC_SIZE
    CACHE_SYNC_SIZE (rw) register accessor: Sync size configure register
  • CLOCK_GATE
    CLOCK_GATE (rw) register accessor: Clock gate control register
  • DATE
    DATE (rw) register accessor: Version control register
  • L1_BUS0_ACS_CONFLICT_CNT
    L1_BUS0_ACS_CONFLICT_CNT (r) register accessor: L1-Cache bus0 Conflict-Access Counter register
  • L1_BUS0_ACS_HIT_CNT
    L1_BUS0_ACS_HIT_CNT (r) register accessor: L1-Cache bus0 Hit-Access Counter register
  • L1_BUS0_ACS_MISS_CNT
    L1_BUS0_ACS_MISS_CNT (r) register accessor: L1-Cache bus0 Miss-Access Counter register
  • L1_BUS0_ACS_NXTLVL_CNT
    L1_BUS0_ACS_NXTLVL_CNT (r) register accessor: L1-Cache bus0 Next-Level-Access Counter register
  • L1_BUS1_ACS_CONFLICT_CNT
    L1_BUS1_ACS_CONFLICT_CNT (r) register accessor: L1-Cache bus1 Conflict-Access Counter register
  • L1_BUS1_ACS_HIT_CNT
    L1_BUS1_ACS_HIT_CNT (r) register accessor: L1-Cache bus1 Hit-Access Counter register
  • L1_BUS1_ACS_MISS_CNT
    L1_BUS1_ACS_MISS_CNT (r) register accessor: L1-Cache bus1 Miss-Access Counter register
  • L1_BUS1_ACS_NXTLVL_CNT
    L1_BUS1_ACS_NXTLVL_CNT (r) register accessor: L1-Cache bus1 Next-Level-Access Counter register
  • L1_BYPASS_CACHE_CONF
    L1_BYPASS_CACHE_CONF (r) register accessor: Bypass Cache configure register
  • L1_CACHE_ACS_CNT_CTRL
    L1_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register
  • L1_CACHE_ACS_CNT_INT_CLR
    L1_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register
  • L1_CACHE_ACS_CNT_INT_ENA
    L1_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register
  • L1_CACHE_ACS_CNT_INT_RAW
    L1_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register
  • L1_CACHE_ACS_CNT_INT_ST
    L1_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register
  • L1_CACHE_ACS_FAIL_ID_ATTR
    L1_CACHE_ACS_FAIL_ID_ATTR (r) register accessor: L1-Cache Access Fail ID/attribution information register
  • L1_CACHE_ACS_FAIL_INT_CLR
    L1_CACHE_ACS_FAIL_INT_CLR (rw) register accessor: L1-Cache Access Fail Interrupt clear register
  • L1_CACHE_ACS_FAIL_INT_ENA
    L1_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register
  • L1_CACHE_ACS_FAIL_INT_RAW
    L1_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register
  • L1_CACHE_ACS_FAIL_INT_ST
    L1_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register
  • L1_CACHE_ATOMIC_CONF
    L1_CACHE_ATOMIC_CONF (r) register accessor: L1 Cache atomic feature configure register
  • L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
    L1_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register
  • L1_CACHE_AUTOLOAD_CTRL
    L1_CACHE_AUTOLOAD_CTRL (rw) register accessor: L1 Cache autoload-operation control register
  • L1_CACHE_AUTOLOAD_SCT0_ADDR
    L1_CACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 Cache autoload section 0 address configure register
  • L1_CACHE_AUTOLOAD_SCT0_SIZE
    L1_CACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 Cache autoload section 0 size configure register
  • L1_CACHE_AUTOLOAD_SCT1_ADDR
    L1_CACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 Cache autoload section 1 address configure register
  • L1_CACHE_AUTOLOAD_SCT1_SIZE
    L1_CACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 Cache autoload section 1 size configure register
  • L1_CACHE_AUTOLOAD_SCT2_ADDR
    L1_CACHE_AUTOLOAD_SCT2_ADDR (r) register accessor: L1 Cache autoload section 2 address configure register
  • L1_CACHE_AUTOLOAD_SCT2_SIZE
    L1_CACHE_AUTOLOAD_SCT2_SIZE (r) register accessor: L1 Cache autoload section 2 size configure register
  • L1_CACHE_AUTOLOAD_SCT3_ADDR
    L1_CACHE_AUTOLOAD_SCT3_ADDR (r) register accessor: L1 Cache autoload section 1 address configure register
  • L1_CACHE_AUTOLOAD_SCT3_SIZE
    L1_CACHE_AUTOLOAD_SCT3_SIZE (r) register accessor: L1 Cache autoload section 1 size configure register
  • L1_CACHE_BLOCKSIZE_CONF
    L1_CACHE_BLOCKSIZE_CONF (r) register accessor: L1 data Cache BlockSize mode configure register
  • L1_CACHE_CACHESIZE_CONF
    L1_CACHE_CACHESIZE_CONF (r) register accessor: L1 data Cache CacheSize mode configure register
  • L1_CACHE_CTRL
    L1_CACHE_CTRL (rw) register accessor: L1 data Cache(L1-Cache) control register
  • L1_CACHE_DATA_MEM_ACS_CONF
    L1_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register
  • L1_CACHE_DATA_MEM_POWER_CTRL
    L1_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register
  • L1_CACHE_DEBUG_BUS
    L1_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register
  • L1_CACHE_FREEZE_CTRL
    L1_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register
  • L1_CACHE_OBJECT_CTRL
    L1_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register
  • L1_CACHE_PRELOAD_CTRL
    L1_CACHE_PRELOAD_CTRL (rw) register accessor: L1 Cache preload-operation control register
  • L1_CACHE_PRELOAD_RST_CTRL
    L1_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register
  • L1_CACHE_PRELOCK_CONF
    L1_CACHE_PRELOCK_CONF (rw) register accessor: L1 Cache prelock configure register
  • L1_CACHE_PRELOCK_SCT0_ADDR
    L1_CACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L1 Cache prelock section0 address configure register
  • L1_CACHE_SYNC_PRELOAD_EXCEPTION
    L1_CACHE_SYNC_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register
  • L1_CACHE_SYNC_PRELOAD_INT_CLR
    L1_CACHE_SYNC_PRELOAD_INT_CLR (rw) register accessor: Sync Preload operation Interrupt clear register
  • L1_CACHE_SYNC_PRELOAD_INT_ENA
    L1_CACHE_SYNC_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register
  • L1_CACHE_SYNC_PRELOAD_INT_RAW
    L1_CACHE_SYNC_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register
  • L1_CACHE_SYNC_PRELOAD_INT_ST
    L1_CACHE_SYNC_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register
  • L1_CACHE_SYNC_RST_CTRL
    L1_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register
  • L1_CACHE_TAG_MEM_ACS_CONF
    L1_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register
  • L1_CACHE_TAG_MEM_POWER_CTRL
    L1_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register
  • L1_CACHE_VADDR
    L1_CACHE_VADDR (rw) register accessor: Cache Vaddr register
  • L1_CACHE_WAY_OBJECT
    L1_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register
  • L1_CACHE_WRAP_AROUND_CTRL
    L1_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register
  • L1_DBUS2_ACS_CONFLICT_CNT
    L1_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus2 Conflict-Access Counter register
  • L1_DBUS2_ACS_HIT_CNT
    L1_DBUS2_ACS_HIT_CNT (r) register accessor: L1-DCache bus2 Hit-Access Counter register
  • L1_DBUS2_ACS_MISS_CNT
    L1_DBUS2_ACS_MISS_CNT (r) register accessor: L1-DCache bus2 Miss-Access Counter register
  • L1_DBUS2_ACS_NXTLVL_CNT
    L1_DBUS2_ACS_NXTLVL_CNT (r) register accessor: L1-DCache bus2 Next-Level-Access Counter register
  • L1_DBUS3_ACS_CONFLICT_CNT
    L1_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus3 Conflict-Access Counter register
  • L1_DBUS3_ACS_HIT_CNT
    L1_DBUS3_ACS_HIT_CNT (r) register accessor: L1-DCache bus3 Hit-Access Counter register
  • L1_DBUS3_ACS_MISS_CNT
    L1_DBUS3_ACS_MISS_CNT (r) register accessor: L1-DCache bus3 Miss-Access Counter register
  • L1_DBUS3_ACS_NXTLVL_CNT
    L1_DBUS3_ACS_NXTLVL_CNT (r) register accessor: L1-DCache bus3 Next-Level-Access Counter register
  • L1_DCACHE_ACS_FAIL_ADDR
    L1_DCACHE_ACS_FAIL_ADDR (r) register accessor: L1-Cache Access Fail Address information register
  • L1_DCACHE_PRELOAD_ADDR
    L1_DCACHE_PRELOAD_ADDR (rw) register accessor: L1 Cache preload address configure register
  • L1_DCACHE_PRELOAD_SIZE
    L1_DCACHE_PRELOAD_SIZE (rw) register accessor: L1 Cache preload size configure register
  • L1_DCACHE_PRELOCK_SCT1_ADDR
    L1_DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L1 Cache prelock section1 address configure register
  • L1_DCACHE_PRELOCK_SCT_SIZE
    L1_DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: L1 Cache prelock section size configure register
  • L1_IBUS0_ACS_CONFLICT_CNT
    L1_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus0 Conflict-Access Counter register
  • L1_IBUS0_ACS_HIT_CNT
    L1_IBUS0_ACS_HIT_CNT (r) register accessor: L1-ICache bus0 Hit-Access Counter register
  • L1_IBUS0_ACS_MISS_CNT
    L1_IBUS0_ACS_MISS_CNT (r) register accessor: L1-ICache bus0 Miss-Access Counter register
  • L1_IBUS0_ACS_NXTLVL_CNT
    L1_IBUS0_ACS_NXTLVL_CNT (r) register accessor: L1-ICache bus0 Next-Level-Access Counter register
  • L1_IBUS1_ACS_CONFLICT_CNT
    L1_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus1 Conflict-Access Counter register
  • L1_IBUS1_ACS_HIT_CNT
    L1_IBUS1_ACS_HIT_CNT (r) register accessor: L1-ICache bus1 Hit-Access Counter register
  • L1_IBUS1_ACS_MISS_CNT
    L1_IBUS1_ACS_MISS_CNT (r) register accessor: L1-ICache bus1 Miss-Access Counter register
  • L1_IBUS1_ACS_NXTLVL_CNT
    L1_IBUS1_ACS_NXTLVL_CNT (r) register accessor: L1-ICache bus1 Next-Level-Access Counter register
  • L1_IBUS2_ACS_CONFLICT_CNT
    L1_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus2 Conflict-Access Counter register
  • L1_IBUS2_ACS_HIT_CNT
    L1_IBUS2_ACS_HIT_CNT (r) register accessor: L1-ICache bus2 Hit-Access Counter register
  • L1_IBUS2_ACS_MISS_CNT
    L1_IBUS2_ACS_MISS_CNT (r) register accessor: L1-ICache bus2 Miss-Access Counter register
  • L1_IBUS2_ACS_NXTLVL_CNT
    L1_IBUS2_ACS_NXTLVL_CNT (r) register accessor: L1-ICache bus2 Next-Level-Access Counter register
  • L1_IBUS3_ACS_CONFLICT_CNT
    L1_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus3 Conflict-Access Counter register
  • L1_IBUS3_ACS_HIT_CNT
    L1_IBUS3_ACS_HIT_CNT (r) register accessor: L1-ICache bus3 Hit-Access Counter register
  • L1_IBUS3_ACS_MISS_CNT
    L1_IBUS3_ACS_MISS_CNT (r) register accessor: L1-ICache bus3 Miss-Access Counter register
  • L1_IBUS3_ACS_NXTLVL_CNT
    L1_IBUS3_ACS_NXTLVL_CNT (r) register accessor: L1-ICache bus3 Next-Level-Access Counter register
  • L1_ICACHE0_ACS_FAIL_ADDR
    L1_ICACHE0_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
  • L1_ICACHE0_ACS_FAIL_ID_ATTR
    L1_ICACHE0_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
  • L1_ICACHE0_AUTOLOAD_CTRL
    L1_ICACHE0_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 0 autoload-operation control register
  • L1_ICACHE0_AUTOLOAD_SCT0_ADDR
    L1_ICACHE0_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 0 autoload section 0 address configure register
  • L1_ICACHE0_AUTOLOAD_SCT0_SIZE
    L1_ICACHE0_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 0 autoload section 0 size configure register
  • L1_ICACHE0_AUTOLOAD_SCT1_ADDR
    L1_ICACHE0_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 0 autoload section 1 address configure register
  • L1_ICACHE0_AUTOLOAD_SCT1_SIZE
    L1_ICACHE0_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 0 autoload section 1 size configure register
  • L1_ICACHE0_PRELOAD_ADDR
    L1_ICACHE0_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 0 preload address configure register
  • L1_ICACHE0_PRELOAD_CTRL
    L1_ICACHE0_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 0 preload-operation control register
  • L1_ICACHE0_PRELOAD_SIZE
    L1_ICACHE0_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 0 preload size configure register
  • L1_ICACHE0_PRELOCK_CONF
    L1_ICACHE0_PRELOCK_CONF (r) register accessor: L1 instruction Cache 0 prelock configure register
  • L1_ICACHE0_PRELOCK_SCT0_ADDR
    L1_ICACHE0_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 0 prelock section0 address configure register
  • L1_ICACHE0_PRELOCK_SCT1_ADDR
    L1_ICACHE0_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 0 prelock section1 address configure register
  • L1_ICACHE0_PRELOCK_SCT_SIZE
    L1_ICACHE0_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 0 prelock section size configure register
  • L1_ICACHE1_ACS_FAIL_ADDR
    L1_ICACHE1_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
  • L1_ICACHE1_ACS_FAIL_ID_ATTR
    L1_ICACHE1_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
  • L1_ICACHE1_AUTOLOAD_CTRL
    L1_ICACHE1_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 1 autoload-operation control register
  • L1_ICACHE1_AUTOLOAD_SCT0_ADDR
    L1_ICACHE1_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 1 autoload section 0 address configure register
  • L1_ICACHE1_AUTOLOAD_SCT0_SIZE
    L1_ICACHE1_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 1 autoload section 0 size configure register
  • L1_ICACHE1_AUTOLOAD_SCT1_ADDR
    L1_ICACHE1_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 1 autoload section 1 address configure register
  • L1_ICACHE1_AUTOLOAD_SCT1_SIZE
    L1_ICACHE1_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 1 autoload section 1 size configure register
  • L1_ICACHE1_PRELOAD_ADDR
    L1_ICACHE1_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 1 preload address configure register
  • L1_ICACHE1_PRELOAD_CTRL
    L1_ICACHE1_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 1 preload-operation control register
  • L1_ICACHE1_PRELOAD_SIZE
    L1_ICACHE1_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 1 preload size configure register
  • L1_ICACHE1_PRELOCK_CONF
    L1_ICACHE1_PRELOCK_CONF (r) register accessor: L1 instruction Cache 1 prelock configure register
  • L1_ICACHE1_PRELOCK_SCT0_ADDR
    L1_ICACHE1_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 1 prelock section0 address configure register
  • L1_ICACHE1_PRELOCK_SCT1_ADDR
    L1_ICACHE1_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 1 prelock section1 address configure register
  • L1_ICACHE1_PRELOCK_SCT_SIZE
    L1_ICACHE1_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 1 prelock section size configure register
  • L1_ICACHE2_ACS_FAIL_ADDR
    L1_ICACHE2_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
  • L1_ICACHE2_ACS_FAIL_ID_ATTR
    L1_ICACHE2_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
  • L1_ICACHE2_AUTOLOAD_CTRL
    L1_ICACHE2_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 2 autoload-operation control register
  • L1_ICACHE2_AUTOLOAD_SCT0_ADDR
    L1_ICACHE2_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 0 address configure register
  • L1_ICACHE2_AUTOLOAD_SCT0_SIZE
    L1_ICACHE2_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 0 size configure register
  • L1_ICACHE2_AUTOLOAD_SCT1_ADDR
    L1_ICACHE2_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 1 address configure register
  • L1_ICACHE2_AUTOLOAD_SCT1_SIZE
    L1_ICACHE2_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 1 size configure register
  • L1_ICACHE2_PRELOAD_ADDR
    L1_ICACHE2_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 2 preload address configure register
  • L1_ICACHE2_PRELOAD_CTRL
    L1_ICACHE2_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 2 preload-operation control register
  • L1_ICACHE2_PRELOAD_SIZE
    L1_ICACHE2_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 2 preload size configure register
  • L1_ICACHE2_PRELOCK_CONF
    L1_ICACHE2_PRELOCK_CONF (r) register accessor: L1 instruction Cache 2 prelock configure register
  • L1_ICACHE2_PRELOCK_SCT0_ADDR
    L1_ICACHE2_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 prelock section0 address configure register
  • L1_ICACHE2_PRELOCK_SCT1_ADDR
    L1_ICACHE2_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 prelock section1 address configure register
  • L1_ICACHE2_PRELOCK_SCT_SIZE
    L1_ICACHE2_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 2 prelock section size configure register
  • L1_ICACHE3_ACS_FAIL_ADDR
    L1_ICACHE3_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register
  • L1_ICACHE3_ACS_FAIL_ID_ATTR
    L1_ICACHE3_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register
  • L1_ICACHE3_AUTOLOAD_CTRL
    L1_ICACHE3_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 3 autoload-operation control register
  • L1_ICACHE3_AUTOLOAD_SCT0_ADDR
    L1_ICACHE3_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 0 address configure register
  • L1_ICACHE3_AUTOLOAD_SCT0_SIZE
    L1_ICACHE3_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 0 size configure register
  • L1_ICACHE3_AUTOLOAD_SCT1_ADDR
    L1_ICACHE3_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 1 address configure register
  • L1_ICACHE3_AUTOLOAD_SCT1_SIZE
    L1_ICACHE3_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 1 size configure register
  • L1_ICACHE3_PRELOAD_ADDR
    L1_ICACHE3_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 3 preload address configure register
  • L1_ICACHE3_PRELOAD_CTRL
    L1_ICACHE3_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 3 preload-operation control register
  • L1_ICACHE3_PRELOAD_SIZE
    L1_ICACHE3_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 3 preload size configure register
  • L1_ICACHE3_PRELOCK_CONF
    L1_ICACHE3_PRELOCK_CONF (r) register accessor: L1 instruction Cache 3 prelock configure register
  • L1_ICACHE3_PRELOCK_SCT0_ADDR
    L1_ICACHE3_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 prelock section0 address configure register
  • L1_ICACHE3_PRELOCK_SCT1_ADDR
    L1_ICACHE3_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 prelock section1 address configure register
  • L1_ICACHE3_PRELOCK_SCT_SIZE
    L1_ICACHE3_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 3 prelock section size configure register
  • L1_ICACHE_BLOCKSIZE_CONF
    L1_ICACHE_BLOCKSIZE_CONF (r) register accessor: L1 instruction Cache BlockSize mode configure register
  • L1_ICACHE_CACHESIZE_CONF
    L1_ICACHE_CACHESIZE_CONF (r) register accessor: L1 instruction Cache CacheSize mode configure register
  • L1_ICACHE_CTRL
    L1_ICACHE_CTRL (r) register accessor: L1 instruction Cache(L1-ICache) control register
  • L1_UNALLOCATE_BUFFER_CLEAR
    L1_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers
  • L2_BYPASS_CACHE_CONF
    L2_BYPASS_CACHE_CONF (r) register accessor: Bypass Cache configure register
  • L2_CACHE_ACCESS_ATTR_CTRL
    L2_CACHE_ACCESS_ATTR_CTRL (r) register accessor: L1 Cache access Attribute propagation control register
  • L2_CACHE_ACS_CNT_CTRL
    L2_CACHE_ACS_CNT_CTRL (r) register accessor: Cache Access Counter enable and clear register
  • L2_CACHE_ACS_CNT_INT_CLR
    L2_CACHE_ACS_CNT_INT_CLR (r) register accessor: Cache Access Counter Interrupt clear register
  • L2_CACHE_ACS_CNT_INT_ENA
    L2_CACHE_ACS_CNT_INT_ENA (r) register accessor: Cache Access Counter Interrupt enable register
  • L2_CACHE_ACS_CNT_INT_RAW
    L2_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register
  • L2_CACHE_ACS_CNT_INT_ST
    L2_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register
  • L2_CACHE_ACS_FAIL_ADDR
    L2_CACHE_ACS_FAIL_ADDR (r) register accessor: L2-Cache Access Fail Address information register
  • L2_CACHE_ACS_FAIL_ID_ATTR
    L2_CACHE_ACS_FAIL_ID_ATTR (r) register accessor: L2-Cache Access Fail ID/attribution information register
  • L2_CACHE_ACS_FAIL_INT_CLR
    L2_CACHE_ACS_FAIL_INT_CLR (r) register accessor: L1-Cache Access Fail Interrupt clear register
  • L2_CACHE_ACS_FAIL_INT_ENA
    L2_CACHE_ACS_FAIL_INT_ENA (r) register accessor: Cache Access Fail Interrupt enable register
  • L2_CACHE_ACS_FAIL_INT_RAW
    L2_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register
  • L2_CACHE_ACS_FAIL_INT_ST
    L2_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register
  • L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
    L2_CACHE_AUTOLOAD_BUF_CLR_CTRL (r) register accessor: Cache Autoload buffer clear control register
  • L2_CACHE_AUTOLOAD_CTRL
    L2_CACHE_AUTOLOAD_CTRL (r) register accessor: L2 Cache autoload-operation control register
  • L2_CACHE_AUTOLOAD_SCT0_ADDR
    L2_CACHE_AUTOLOAD_SCT0_ADDR (r) register accessor: L2 Cache autoload section 0 address configure register
  • L2_CACHE_AUTOLOAD_SCT0_SIZE
    L2_CACHE_AUTOLOAD_SCT0_SIZE (r) register accessor: L2 Cache autoload section 0 size configure register
  • L2_CACHE_AUTOLOAD_SCT1_ADDR
    L2_CACHE_AUTOLOAD_SCT1_ADDR (r) register accessor: L2 Cache autoload section 1 address configure register
  • L2_CACHE_AUTOLOAD_SCT1_SIZE
    L2_CACHE_AUTOLOAD_SCT1_SIZE (r) register accessor: L2 Cache autoload section 1 size configure register
  • L2_CACHE_AUTOLOAD_SCT2_ADDR
    L2_CACHE_AUTOLOAD_SCT2_ADDR (r) register accessor: L2 Cache autoload section 2 address configure register
  • L2_CACHE_AUTOLOAD_SCT2_SIZE
    L2_CACHE_AUTOLOAD_SCT2_SIZE (r) register accessor: L2 Cache autoload section 2 size configure register
  • L2_CACHE_AUTOLOAD_SCT3_ADDR
    L2_CACHE_AUTOLOAD_SCT3_ADDR (r) register accessor: L2 Cache autoload section 3 address configure register
  • L2_CACHE_AUTOLOAD_SCT3_SIZE
    L2_CACHE_AUTOLOAD_SCT3_SIZE (r) register accessor: L2 Cache autoload section 3 size configure register
  • L2_CACHE_BLOCKSIZE_CONF
    L2_CACHE_BLOCKSIZE_CONF (r) register accessor: L2 Cache BlockSize mode configure register
  • L2_CACHE_CACHESIZE_CONF
    L2_CACHE_CACHESIZE_CONF (r) register accessor: L2 Cache CacheSize mode configure register
  • L2_CACHE_CTRL
    L2_CACHE_CTRL (r) register accessor: L2 Cache(L2-Cache) control register
  • L2_CACHE_DATA_MEM_ACS_CONF
    L2_CACHE_DATA_MEM_ACS_CONF (r) register accessor: Cache data memory access configure register
  • L2_CACHE_DATA_MEM_POWER_CTRL
    L2_CACHE_DATA_MEM_POWER_CTRL (r) register accessor: Cache data memory power control register
  • L2_CACHE_DEBUG_BUS
    L2_CACHE_DEBUG_BUS (r) register accessor: Cache Tag/data memory content register
  • L2_CACHE_FREEZE_CTRL
    L2_CACHE_FREEZE_CTRL (r) register accessor: Cache Freeze control register
  • L2_CACHE_OBJECT_CTRL
    L2_CACHE_OBJECT_CTRL (r) register accessor: Cache Tag and Data memory Object control register
  • L2_CACHE_PRELOAD_ADDR
    L2_CACHE_PRELOAD_ADDR (r) register accessor: L2 Cache preload address configure register
  • L2_CACHE_PRELOAD_CTRL
    L2_CACHE_PRELOAD_CTRL (rw) register accessor: L2 Cache preload-operation control register
  • L2_CACHE_PRELOAD_RST_CTRL
    L2_CACHE_PRELOAD_RST_CTRL (r) register accessor: Cache Preload Reset control register
  • L2_CACHE_PRELOAD_SIZE
    L2_CACHE_PRELOAD_SIZE (r) register accessor: L2 Cache preload size configure register
  • L2_CACHE_PRELOCK_CONF
    L2_CACHE_PRELOCK_CONF (r) register accessor: L2 Cache prelock configure register
  • L2_CACHE_PRELOCK_SCT0_ADDR
    L2_CACHE_PRELOCK_SCT0_ADDR (r) register accessor: L2 Cache prelock section0 address configure register
  • L2_CACHE_PRELOCK_SCT1_ADDR
    L2_CACHE_PRELOCK_SCT1_ADDR (r) register accessor: L2 Cache prelock section1 address configure register
  • L2_CACHE_PRELOCK_SCT_SIZE
    L2_CACHE_PRELOCK_SCT_SIZE (r) register accessor: L2 Cache prelock section size configure register
  • L2_CACHE_SYNC_PRELOAD_EXCEPTION
    L2_CACHE_SYNC_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register
  • L2_CACHE_SYNC_PRELOAD_INT_CLR
    L2_CACHE_SYNC_PRELOAD_INT_CLR (r) register accessor: Sync Preload operation Interrupt clear register
  • L2_CACHE_SYNC_PRELOAD_INT_ENA
    L2_CACHE_SYNC_PRELOAD_INT_ENA (r) register accessor: L1-Cache Access Fail Interrupt enable register
  • L2_CACHE_SYNC_PRELOAD_INT_RAW
    L2_CACHE_SYNC_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register
  • L2_CACHE_SYNC_PRELOAD_INT_ST
    L2_CACHE_SYNC_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register
  • L2_CACHE_SYNC_RST_CTRL
    L2_CACHE_SYNC_RST_CTRL (r) register accessor: Cache Sync Reset control register
  • L2_CACHE_TAG_MEM_ACS_CONF
    L2_CACHE_TAG_MEM_ACS_CONF (r) register accessor: Cache tag memory access configure register
  • L2_CACHE_TAG_MEM_POWER_CTRL
    L2_CACHE_TAG_MEM_POWER_CTRL (r) register accessor: Cache tag memory power control register
  • L2_CACHE_VADDR
    L2_CACHE_VADDR (r) register accessor: Cache Vaddr register
  • L2_CACHE_WAY_OBJECT
    L2_CACHE_WAY_OBJECT (r) register accessor: Cache Tag and Data memory way register
  • L2_CACHE_WRAP_AROUND_CTRL
    L2_CACHE_WRAP_AROUND_CTRL (r) register accessor: Cache wrap around control register
  • L2_DBUS0_ACS_CONFLICT_CNT
    L2_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register
  • L2_DBUS0_ACS_HIT_CNT
    L2_DBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register
  • L2_DBUS0_ACS_MISS_CNT
    L2_DBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register
  • L2_DBUS0_ACS_NXTLVL_CNT
    L2_DBUS0_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register
  • L2_DBUS1_ACS_CONFLICT_CNT
    L2_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register
  • L2_DBUS1_ACS_HIT_CNT
    L2_DBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register
  • L2_DBUS1_ACS_MISS_CNT
    L2_DBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register
  • L2_DBUS1_ACS_NXTLVL_CNT
    L2_DBUS1_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register
  • L2_DBUS2_ACS_CONFLICT_CNT
    L2_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register
  • L2_DBUS2_ACS_HIT_CNT
    L2_DBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register
  • L2_DBUS2_ACS_MISS_CNT
    L2_DBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register
  • L2_DBUS2_ACS_NXTLVL_CNT
    L2_DBUS2_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register
  • L2_DBUS3_ACS_CONFLICT_CNT
    L2_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register
  • L2_DBUS3_ACS_HIT_CNT
    L2_DBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register
  • L2_DBUS3_ACS_MISS_CNT
    L2_DBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register
  • L2_DBUS3_ACS_NXTLVL_CNT
    L2_DBUS3_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register
  • L2_IBUS0_ACS_CONFLICT_CNT
    L2_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register
  • L2_IBUS0_ACS_HIT_CNT
    L2_IBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register
  • L2_IBUS0_ACS_MISS_CNT
    L2_IBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register
  • L2_IBUS0_ACS_NXTLVL_CNT
    L2_IBUS0_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register
  • L2_IBUS1_ACS_CONFLICT_CNT
    L2_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register
  • L2_IBUS1_ACS_HIT_CNT
    L2_IBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register
  • L2_IBUS1_ACS_MISS_CNT
    L2_IBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register
  • L2_IBUS1_ACS_NXTLVL_CNT
    L2_IBUS1_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register
  • L2_IBUS2_ACS_CONFLICT_CNT
    L2_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register
  • L2_IBUS2_ACS_HIT_CNT
    L2_IBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register
  • L2_IBUS2_ACS_MISS_CNT
    L2_IBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register
  • L2_IBUS2_ACS_NXTLVL_CNT
    L2_IBUS2_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register
  • L2_IBUS3_ACS_CONFLICT_CNT
    L2_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register
  • L2_IBUS3_ACS_HIT_CNT
    L2_IBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register
  • L2_IBUS3_ACS_MISS_CNT
    L2_IBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register
  • L2_IBUS3_ACS_NXTLVL_CNT
    L2_IBUS3_ACS_NXTLVL_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register
  • L2_UNALLOCATE_BUFFER_CLEAR
    L2_UNALLOCATE_BUFFER_CLEAR (r) register accessor: Unallocate request buffer clear registers
  • LEVEL_SPLIT0
    LEVEL_SPLIT0 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE
  • LEVEL_SPLIT1
    LEVEL_SPLIT1 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE
  • REDUNDANCY_SIG0
    REDUNDANCY_SIG0 (rw) register accessor: Cache redundancy signal 0 register
  • REDUNDANCY_SIG1
    REDUNDANCY_SIG1 (rw) register accessor: Cache redundancy signal 1 register
  • REDUNDANCY_SIG2
    REDUNDANCY_SIG2 (rw) register accessor: Cache redundancy signal 2 register
  • REDUNDANCY_SIG3
    REDUNDANCY_SIG3 (rw) register accessor: Cache redundancy signal 3 register
  • REDUNDANCY_SIG4
    REDUNDANCY_SIG4 (r) register accessor: Cache redundancy signal 0 register