Module esp32c3::i2s0::tx_clkm_conf
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I2S TX clock configure register
Structs§
- I2S TX clock configure register
Type Aliases§
- Field
CLK_EN
reader - Set this bit to enable clk gate - Field
CLK_EN
writer - Set this bit to enable clk gate - Register
TX_CLKM_CONF
reader - Field
TX_CLKM_DIV_NUM
reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. - Field
TX_CLKM_DIV_NUM
writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. - Field
TX_CLK_ACTIVE
reader - I2S Tx module clock enable signal. - Field
TX_CLK_ACTIVE
writer - I2S Tx module clock enable signal. - Field
TX_CLK_SEL
reader - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. - Field
TX_CLK_SEL
writer - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. - Register
TX_CLKM_CONF
writer