1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
#[doc = "Reader of register 0TX_LINK"] pub type R = crate::R<u32, super::_0TX_LINK>; #[doc = "Writer for register 0TX_LINK"] pub type W = crate::W<u32, super::_0TX_LINK>; #[doc = "Register 0TX_LINK `reset()`'s with value 0"] impl crate::ResetValue for super::_0TX_LINK { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SLC0_TXLINK_PARK`"] pub type SLC0_TXLINK_PARK_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SLC0_TXLINK_PARK`"] pub struct SLC0_TXLINK_PARK_W<'a> { w: &'a mut W, } impl<'a> SLC0_TXLINK_PARK_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } #[doc = "Reader of field `SLC0_TXLINK_RESTART`"] pub type SLC0_TXLINK_RESTART_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SLC0_TXLINK_RESTART`"] pub struct SLC0_TXLINK_RESTART_W<'a> { w: &'a mut W, } impl<'a> SLC0_TXLINK_RESTART_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `SLC0_TXLINK_START`"] pub type SLC0_TXLINK_START_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SLC0_TXLINK_START`"] pub struct SLC0_TXLINK_START_W<'a> { w: &'a mut W, } impl<'a> SLC0_TXLINK_START_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Reader of field `SLC0_TXLINK_STOP`"] pub type SLC0_TXLINK_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SLC0_TXLINK_STOP`"] pub struct SLC0_TXLINK_STOP_W<'a> { w: &'a mut W, } impl<'a> SLC0_TXLINK_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Reader of field `SLC0_TXLINK_ADDR`"] pub type SLC0_TXLINK_ADDR_R = crate::R<u32, u32>; #[doc = "Write proxy for field `SLC0_TXLINK_ADDR`"] pub struct SLC0_TXLINK_ADDR_W<'a> { w: &'a mut W, } impl<'a> SLC0_TXLINK_ADDR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !0x000f_ffff) | ((value as u32) & 0x000f_ffff); self.w } } impl R { #[doc = "Bit 31"] #[inline(always)] pub fn slc0_txlink_park(&self) -> SLC0_TXLINK_PARK_R { SLC0_TXLINK_PARK_R::new(((self.bits >> 31) & 0x01) != 0) } #[doc = "Bit 30"] #[inline(always)] pub fn slc0_txlink_restart(&self) -> SLC0_TXLINK_RESTART_R { SLC0_TXLINK_RESTART_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 29"] #[inline(always)] pub fn slc0_txlink_start(&self) -> SLC0_TXLINK_START_R { SLC0_TXLINK_START_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 28"] #[inline(always)] pub fn slc0_txlink_stop(&self) -> SLC0_TXLINK_STOP_R { SLC0_TXLINK_STOP_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bits 0:19"] #[inline(always)] pub fn slc0_txlink_addr(&self) -> SLC0_TXLINK_ADDR_R { SLC0_TXLINK_ADDR_R::new((self.bits & 0x000f_ffff) as u32) } } impl W { #[doc = "Bit 31"] #[inline(always)] pub fn slc0_txlink_park(&mut self) -> SLC0_TXLINK_PARK_W { SLC0_TXLINK_PARK_W { w: self } } #[doc = "Bit 30"] #[inline(always)] pub fn slc0_txlink_restart(&mut self) -> SLC0_TXLINK_RESTART_W { SLC0_TXLINK_RESTART_W { w: self } } #[doc = "Bit 29"] #[inline(always)] pub fn slc0_txlink_start(&mut self) -> SLC0_TXLINK_START_W { SLC0_TXLINK_START_W { w: self } } #[doc = "Bit 28"] #[inline(always)] pub fn slc0_txlink_stop(&mut self) -> SLC0_TXLINK_STOP_W { SLC0_TXLINK_STOP_W { w: self } } #[doc = "Bits 0:19"] #[inline(always)] pub fn slc0_txlink_addr(&mut self) -> SLC0_TXLINK_ADDR_W { SLC0_TXLINK_ADDR_W { w: self } } }