[−][src]Module esp32::dport
DPORT
Modules
| access_check | DPORT_ACCESS_CHECK |
| ahb_lite_mask | DPORT_AHB_LITE_MASK |
| ahb_mpu_table_0 | DPORT_AHB_MPU_TABLE_0 |
| ahb_mpu_table_1 | DPORT_AHB_MPU_TABLE_1 |
| ahblite_mpu_table_apb_ctrl | DPORT_AHBLITE_MPU_TABLE_APB_CTRL |
| ahblite_mpu_table_bb | DPORT_AHBLITE_MPU_TABLE_BB |
| ahblite_mpu_table_bt | DPORT_AHBLITE_MPU_TABLE_BT |
| ahblite_mpu_table_bt_buffer | DPORT_AHBLITE_MPU_TABLE_BT_BUFFER |
| ahblite_mpu_table_btmac | DPORT_AHBLITE_MPU_TABLE_BTMAC |
| ahblite_mpu_table_can | DPORT_AHBLITE_MPU_TABLE_CAN |
| ahblite_mpu_table_efuse | DPORT_AHBLITE_MPU_TABLE_EFUSE |
| ahblite_mpu_table_emac | DPORT_AHBLITE_MPU_TABLE_EMAC |
| ahblite_mpu_table_fe | DPORT_AHBLITE_MPU_TABLE_FE |
| ahblite_mpu_table_fe2 | DPORT_AHBLITE_MPU_TABLE_FE2 |
| ahblite_mpu_table_gpio | DPORT_AHBLITE_MPU_TABLE_GPIO |
| ahblite_mpu_table_hinf | DPORT_AHBLITE_MPU_TABLE_HINF |
| ahblite_mpu_table_i2c | DPORT_AHBLITE_MPU_TABLE_I2C |
| ahblite_mpu_table_i2c_ext0 | DPORT_AHBLITE_MPU_TABLE_I2C_EXT0 |
| ahblite_mpu_table_i2c_ext1 | DPORT_AHBLITE_MPU_TABLE_I2C_EXT1 |
| ahblite_mpu_table_i2s0 | DPORT_AHBLITE_MPU_TABLE_I2S0 |
| ahblite_mpu_table_i2s1 | DPORT_AHBLITE_MPU_TABLE_I2S1 |
| ahblite_mpu_table_io_mux | DPORT_AHBLITE_MPU_TABLE_IO_MUX |
| ahblite_mpu_table_ledc | DPORT_AHBLITE_MPU_TABLE_LEDC |
| ahblite_mpu_table_misc | DPORT_AHBLITE_MPU_TABLE_MISC |
| ahblite_mpu_table_pcnt | DPORT_AHBLITE_MPU_TABLE_PCNT |
| ahblite_mpu_table_pwm0 | DPORT_AHBLITE_MPU_TABLE_PWM0 |
| ahblite_mpu_table_pwm1 | DPORT_AHBLITE_MPU_TABLE_PWM1 |
| ahblite_mpu_table_pwm2 | DPORT_AHBLITE_MPU_TABLE_PWM2 |
| ahblite_mpu_table_pwm3 | DPORT_AHBLITE_MPU_TABLE_PWM3 |
| ahblite_mpu_table_pwr | DPORT_AHBLITE_MPU_TABLE_PWR |
| ahblite_mpu_table_rmt | DPORT_AHBLITE_MPU_TABLE_RMT |
| ahblite_mpu_table_rtc | DPORT_AHBLITE_MPU_TABLE_RTC |
| ahblite_mpu_table_rwbt | DPORT_AHBLITE_MPU_TABLE_RWBT |
| ahblite_mpu_table_sdio_host | DPORT_AHBLITE_MPU_TABLE_SDIO_HOST |
| ahblite_mpu_table_slc | DPORT_AHBLITE_MPU_TABLE_SLC |
| ahblite_mpu_table_slchost | DPORT_AHBLITE_MPU_TABLE_SLCHOST |
| ahblite_mpu_table_spi0 | DPORT_AHBLITE_MPU_TABLE_SPI0 |
| ahblite_mpu_table_spi1 | DPORT_AHBLITE_MPU_TABLE_SPI1 |
| ahblite_mpu_table_spi2 | DPORT_AHBLITE_MPU_TABLE_SPI2 |
| ahblite_mpu_table_spi3 | DPORT_AHBLITE_MPU_TABLE_SPI3 |
| ahblite_mpu_table_spi_encrypt | DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT |
| ahblite_mpu_table_timer | DPORT_AHBLITE_MPU_TABLE_TIMER |
| ahblite_mpu_table_timergroup | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP |
| ahblite_mpu_table_timergroup1 | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1 |
| ahblite_mpu_table_uart | DPORT_AHBLITE_MPU_TABLE_UART |
| ahblite_mpu_table_uart1 | DPORT_AHBLITE_MPU_TABLE_UART1 |
| ahblite_mpu_table_uart2 | DPORT_AHBLITE_MPU_TABLE_UART2 |
| ahblite_mpu_table_uhci0 | DPORT_AHBLITE_MPU_TABLE_UHCI0 |
| ahblite_mpu_table_uhci1 | DPORT_AHBLITE_MPU_TABLE_UHCI1 |
| ahblite_mpu_table_wdg | DPORT_AHBLITE_MPU_TABLE_WDG |
| ahblite_mpu_table_wifimac | DPORT_AHBLITE_MPU_TABLE_WIFIMAC |
| app_bb_int_map | DPORT_APP_BB_INT_MAP |
| app_boot_remap_ctrl | DPORT_APP_BOOT_REMAP_CTRL |
| app_bt_bb_int_map | DPORT_APP_BT_BB_INT_MAP |
| app_bt_bb_nmi_map | DPORT_APP_BT_BB_NMI_MAP |
| app_bt_mac_int_map | DPORT_APP_BT_MAC_INT_MAP |
| app_cache_ctrl | DPORT_APP_CACHE_CTRL |
| app_cache_ctrl1 | DPORT_APP_CACHE_CTRL1 |
| app_cache_ia_int_map | DPORT_APP_CACHE_IA_INT_MAP |
| app_cache_lock_0_addr | DPORT_APP_CACHE_LOCK_0_ADDR |
| app_cache_lock_1_addr | DPORT_APP_CACHE_LOCK_1_ADDR |
| app_cache_lock_2_addr | DPORT_APP_CACHE_LOCK_2_ADDR |
| app_cache_lock_3_addr | DPORT_APP_CACHE_LOCK_3_ADDR |
| app_can_int_map | DPORT_APP_CAN_INT_MAP |
| app_cpu_intr_from_cpu_0_map | DPORT_APP_CPU_INTR_FROM_CPU_0_MAP |
| app_cpu_intr_from_cpu_1_map | DPORT_APP_CPU_INTR_FROM_CPU_1_MAP |
| app_cpu_intr_from_cpu_2_map | DPORT_APP_CPU_INTR_FROM_CPU_2_MAP |
| app_cpu_intr_from_cpu_3_map | DPORT_APP_CPU_INTR_FROM_CPU_3_MAP |
| app_cpu_record_ctrl | DPORT_APP_CPU_RECORD_CTRL |
| app_cpu_record_pdebugdata | DPORT_APP_CPU_RECORD_PDEBUGDATA |
| app_cpu_record_pdebuginst | DPORT_APP_CPU_RECORD_PDEBUGINST |
| app_cpu_record_pdebugls0stat | DPORT_APP_CPU_RECORD_PDEBUGLS0STAT |
| app_cpu_record_pdebugls0addr | DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR |
| app_cpu_record_pdebugls0data | DPORT_APP_CPU_RECORD_PDEBUGLS0DATA |
| app_cpu_record_pdebugpc | DPORT_APP_CPU_RECORD_PDEBUGPC |
| app_cpu_record_pdebugstatus | DPORT_APP_CPU_RECORD_PDEBUGSTATUS |
| app_cpu_record_pid | DPORT_APP_CPU_RECORD_PID |
| app_cpu_record_status | DPORT_APP_CPU_RECORD_STATUS |
| app_dcache_dbug0 | DPORT_APP_DCACHE_DBUG0 |
| app_dcache_dbug1 | DPORT_APP_DCACHE_DBUG1 |
| app_dcache_dbug2 | DPORT_APP_DCACHE_DBUG2 |
| app_dcache_dbug3 | DPORT_APP_DCACHE_DBUG3 |
| app_dcache_dbug4 | DPORT_APP_DCACHE_DBUG4 |
| app_dcache_dbug5 | DPORT_APP_DCACHE_DBUG5 |
| app_dcache_dbug6 | DPORT_APP_DCACHE_DBUG6 |
| app_dcache_dbug7 | DPORT_APP_DCACHE_DBUG7 |
| app_dcache_dbug8 | DPORT_APP_DCACHE_DBUG8 |
| app_dcache_dbug9 | DPORT_APP_DCACHE_DBUG9 |
| app_dport_apb_mask0 | DPORT_APP_DPORT_APB_MASK0 |
| app_dport_apb_mask1 | DPORT_APP_DPORT_APB_MASK1 |
| app_efuse_int_map | DPORT_APP_EFUSE_INT_MAP |
| app_emac_int_map | DPORT_APP_EMAC_INT_MAP |
| app_gpio_interrupt_map | DPORT_APP_GPIO_INTERRUPT_MAP |
| app_gpio_interrupt_nmi_map | DPORT_APP_GPIO_INTERRUPT_NMI_MAP |
| app_i2c_ext0_intr_map | DPORT_APP_I2C_EXT0_INTR_MAP |
| app_i2c_ext1_intr_map | DPORT_APP_I2C_EXT1_INTR_MAP |
| app_i2s0_int_map | DPORT_APP_I2S0_INT_MAP |
| app_i2s1_int_map | DPORT_APP_I2S1_INT_MAP |
| app_intr_status_0 | DPORT_APP_INTR_STATUS_0 |
| app_intr_status_1 | DPORT_APP_INTR_STATUS_1 |
| app_intr_status_2 | DPORT_APP_INTR_STATUS_2 |
| app_intrusion_ctrl | DPORT_APP_INTRUSION_CTRL |
| app_intrusion_status | DPORT_APP_INTRUSION_STATUS |
| app_ledc_int_map | DPORT_APP_LEDC_INT_MAP |
| app_mac_intr_map | DPORT_APP_MAC_INTR_MAP |
| app_mac_nmi_map | DPORT_APP_MAC_NMI_MAP |
| app_mmu_ia_int_map | DPORT_APP_MMU_IA_INT_MAP |
| app_mpu_ia_int_map | DPORT_APP_MPU_IA_INT_MAP |
| app_pcnt_intr_map | DPORT_APP_PCNT_INTR_MAP |
| app_pwm0_intr_map | DPORT_APP_PWM0_INTR_MAP |
| app_pwm1_intr_map | DPORT_APP_PWM1_INTR_MAP |
| app_pwm2_intr_map | DPORT_APP_PWM2_INTR_MAP |
| app_pwm3_intr_map | DPORT_APP_PWM3_INTR_MAP |
| app_rmt_intr_map | DPORT_APP_RMT_INTR_MAP |
| app_rsa_intr_map | DPORT_APP_RSA_INTR_MAP |
| app_rtc_core_intr_map | DPORT_APP_RTC_CORE_INTR_MAP |
| app_rwble_irq_map | DPORT_APP_RWBLE_IRQ_MAP |
| app_rwble_nmi_map | DPORT_APP_RWBLE_NMI_MAP |
| app_rwbt_irq_map | DPORT_APP_RWBT_IRQ_MAP |
| app_rwbt_nmi_map | DPORT_APP_RWBT_NMI_MAP |
| app_sdio_host_interrupt_map | DPORT_APP_SDIO_HOST_INTERRUPT_MAP |
| app_slc0_intr_map | DPORT_APP_SLC0_INTR_MAP |
| app_slc1_intr_map | DPORT_APP_SLC1_INTR_MAP |
| app_spi1_dma_int_map | DPORT_APP_SPI1_DMA_INT_MAP |
| app_spi2_dma_int_map | DPORT_APP_SPI2_DMA_INT_MAP |
| app_spi3_dma_int_map | DPORT_APP_SPI3_DMA_INT_MAP |
| app_spi_intr_0_map | DPORT_APP_SPI_INTR_0_MAP |
| app_spi_intr_1_map | DPORT_APP_SPI_INTR_1_MAP |
| app_spi_intr_2_map | DPORT_APP_SPI_INTR_2_MAP |
| app_spi_intr_3_map | DPORT_APP_SPI_INTR_3_MAP |
| app_tg1_wdt_level_int_map | DPORT_APP_TG1_WDT_LEVEL_INT_MAP |
| app_tg1_lact_level_int_map | DPORT_APP_TG1_LACT_LEVEL_INT_MAP |
| app_tg1_wdt_edge_int_map | DPORT_APP_TG1_WDT_EDGE_INT_MAP |
| app_tg1_lact_edge_int_map | DPORT_APP_TG1_LACT_EDGE_INT_MAP |
| app_tg1_t0_edge_int_map | DPORT_APP_TG1_T0_EDGE_INT_MAP |
| app_tg1_t0_level_int_map | DPORT_APP_TG1_T0_LEVEL_INT_MAP |
| app_tg1_t1_level_int_map | DPORT_APP_TG1_T1_LEVEL_INT_MAP |
| app_tg1_t1_edge_int_map | DPORT_APP_TG1_T1_EDGE_INT_MAP |
| app_tg_lact_edge_int_map | DPORT_APP_TG_LACT_EDGE_INT_MAP |
| app_tg_lact_level_int_map | DPORT_APP_TG_LACT_LEVEL_INT_MAP |
| app_tg_t0_edge_int_map | DPORT_APP_TG_T0_EDGE_INT_MAP |
| app_tg_t0_level_int_map | DPORT_APP_TG_T0_LEVEL_INT_MAP |
| app_tg_t1_level_int_map | DPORT_APP_TG_T1_LEVEL_INT_MAP |
| app_tg_t1_edge_int_map | DPORT_APP_TG_T1_EDGE_INT_MAP |
| app_tg_wdt_edge_int_map | DPORT_APP_TG_WDT_EDGE_INT_MAP |
| app_tg_wdt_level_int_map | DPORT_APP_TG_WDT_LEVEL_INT_MAP |
| app_timer_int1_map | DPORT_APP_TIMER_INT1_MAP |
| app_timer_int2_map | DPORT_APP_TIMER_INT2_MAP |
| app_tracemem_ena | DPORT_APP_TRACEMEM_ENA |
| app_uart1_intr_map | DPORT_APP_UART1_INTR_MAP |
| app_uart2_intr_map | DPORT_APP_UART2_INTR_MAP |
| app_uart_intr_map | DPORT_APP_UART_INTR_MAP |
| app_uhci0_intr_map | DPORT_APP_UHCI0_INTR_MAP |
| app_uhci1_intr_map | DPORT_APP_UHCI1_INTR_MAP |
| app_vecbase_ctrl | DPORT_APP_VECBASE_CTRL |
| app_vecbase_set | DPORT_APP_VECBASE_SET |
| app_wdg_int_map | DPORT_APP_WDG_INT_MAP |
| appcpu_ctrl_a | DPORT_APPCPU_CTRL_A |
| appcpu_ctrl_b | DPORT_APPCPU_CTRL_B |
| appcpu_ctrl_c | DPORT_APPCPU_CTRL_C |
| appcpu_ctrl_d | DPORT_APPCPU_CTRL_D |
| bt_lpck_div_frac | DPORT_BT_LPCK_DIV_FRAC |
| bt_lpck_div_int | DPORT_BT_LPCK_DIV_INT |
| cache_ia_int_en | DPORT_CACHE_IA_INT_EN |
| cache_mux_mode | DPORT_CACHE_MUX_MODE |
| core_rst_en | DPORT_CORE_RST_EN |
| cpu_intr_from_cpu_0 | DPORT_CPU_INTR_FROM_CPU_0 |
| cpu_intr_from_cpu_1 | DPORT_CPU_INTR_FROM_CPU_1 |
| cpu_intr_from_cpu_2 | DPORT_CPU_INTR_FROM_CPU_2 |
| cpu_intr_from_cpu_3 | DPORT_CPU_INTR_FROM_CPU_3 |
| cpu_per_conf | DPORT_CPU_PER_CONF |
| date | DPORT_DATE |
| dmmu_page_mode | DPORT_DMMU_PAGE_MODE |
| dmmu_table0 | DPORT_DMMU_TABLE0 |
| dmmu_table1 | DPORT_DMMU_TABLE1 |
| dmmu_table2 | DPORT_DMMU_TABLE2 |
| dmmu_table3 | DPORT_DMMU_TABLE3 |
| dmmu_table4 | DPORT_DMMU_TABLE4 |
| dmmu_table5 | DPORT_DMMU_TABLE5 |
| dmmu_table6 | DPORT_DMMU_TABLE6 |
| dmmu_table7 | DPORT_DMMU_TABLE7 |
| dmmu_table8 | DPORT_DMMU_TABLE8 |
| dmmu_table9 | DPORT_DMMU_TABLE9 |
| dmmu_table10 | DPORT_DMMU_TABLE10 |
| dmmu_table11 | DPORT_DMMU_TABLE11 |
| dmmu_table12 | DPORT_DMMU_TABLE12 |
| dmmu_table13 | DPORT_DMMU_TABLE13 |
| dmmu_table14 | DPORT_DMMU_TABLE14 |
| dmmu_table15 | DPORT_DMMU_TABLE15 |
| front_end_mem_pd | DPORT_FRONT_END_MEM_PD |
| host_inf_sel | DPORT_HOST_INF_SEL |
| immu_page_mode | DPORT_IMMU_PAGE_MODE |
| immu_table0 | DPORT_IMMU_TABLE0 |
| immu_table1 | DPORT_IMMU_TABLE1 |
| immu_table2 | DPORT_IMMU_TABLE2 |
| immu_table3 | DPORT_IMMU_TABLE3 |
| immu_table4 | DPORT_IMMU_TABLE4 |
| immu_table5 | DPORT_IMMU_TABLE5 |
| immu_table6 | DPORT_IMMU_TABLE6 |
| immu_table7 | DPORT_IMMU_TABLE7 |
| immu_table8 | DPORT_IMMU_TABLE8 |
| immu_table9 | DPORT_IMMU_TABLE9 |
| immu_table10 | DPORT_IMMU_TABLE10 |
| immu_table11 | DPORT_IMMU_TABLE11 |
| immu_table12 | DPORT_IMMU_TABLE12 |
| immu_table13 | DPORT_IMMU_TABLE13 |
| immu_table14 | DPORT_IMMU_TABLE14 |
| immu_table15 | DPORT_IMMU_TABLE15 |
| iram_dram_ahb_sel | DPORT_IRAM_DRAM_AHB_SEL |
| mem_access_dbug0 | DPORT_MEM_ACCESS_DBUG0 |
| mem_access_dbug1 | DPORT_MEM_ACCESS_DBUG1 |
| mem_pd_mask | DPORT_MEM_PD_MASK |
| mmu_ia_int_en | DPORT_MMU_IA_INT_EN |
| mpu_ia_int_en | DPORT_MPU_IA_INT_EN |
| peri_clk_en | DPORT_PERI_CLK_EN |
| peri_rst_en | DPORT_PERI_RST_EN |
| perip_clk_en | DPORT_PERIP_CLK_EN |
| perip_rst_en | DPORT_PERIP_RST_EN |
| pro_bb_int_map | DPORT_PRO_BB_INT_MAP |
| pro_boot_remap_ctrl | DPORT_PRO_BOOT_REMAP_CTRL |
| pro_bt_bb_int_map | DPORT_PRO_BT_BB_INT_MAP |
| pro_bt_bb_nmi_map | DPORT_PRO_BT_BB_NMI_MAP |
| pro_bt_mac_int_map | DPORT_PRO_BT_MAC_INT_MAP |
| pro_cache_ctrl | DPORT_PRO_CACHE_CTRL |
| pro_cache_ctrl1 | DPORT_PRO_CACHE_CTRL1 |
| pro_cache_ia_int_map | DPORT_PRO_CACHE_IA_INT_MAP |
| pro_cache_lock_0_addr | DPORT_PRO_CACHE_LOCK_0_ADDR |
| pro_cache_lock_1_addr | DPORT_PRO_CACHE_LOCK_1_ADDR |
| pro_cache_lock_2_addr | DPORT_PRO_CACHE_LOCK_2_ADDR |
| pro_cache_lock_3_addr | DPORT_PRO_CACHE_LOCK_3_ADDR |
| pro_can_int_map | DPORT_PRO_CAN_INT_MAP |
| pro_cpu_intr_from_cpu_0_map | DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP |
| pro_cpu_intr_from_cpu_1_map | DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP |
| pro_cpu_intr_from_cpu_2_map | DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP |
| pro_cpu_intr_from_cpu_3_map | DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP |
| pro_cpu_record_ctrl | DPORT_PRO_CPU_RECORD_CTRL |
| pro_cpu_record_pdebugdata | DPORT_PRO_CPU_RECORD_PDEBUGDATA |
| pro_cpu_record_pdebuginst | DPORT_PRO_CPU_RECORD_PDEBUGINST |
| pro_cpu_record_pdebugls0stat | DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT |
| pro_cpu_record_pdebugls0addr | DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR |
| pro_cpu_record_pdebugls0data | DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA |
| pro_cpu_record_pdebugpc | DPORT_PRO_CPU_RECORD_PDEBUGPC |
| pro_cpu_record_pdebugstatus | DPORT_PRO_CPU_RECORD_PDEBUGSTATUS |
| pro_cpu_record_pid | DPORT_PRO_CPU_RECORD_PID |
| pro_cpu_record_status | DPORT_PRO_CPU_RECORD_STATUS |
| pro_dcache_dbug0 | DPORT_PRO_DCACHE_DBUG0 |
| pro_dcache_dbug1 | DPORT_PRO_DCACHE_DBUG1 |
| pro_dcache_dbug2 | DPORT_PRO_DCACHE_DBUG2 |
| pro_dcache_dbug3 | DPORT_PRO_DCACHE_DBUG3 |
| pro_dcache_dbug4 | DPORT_PRO_DCACHE_DBUG4 |
| pro_dcache_dbug5 | DPORT_PRO_DCACHE_DBUG5 |
| pro_dcache_dbug6 | DPORT_PRO_DCACHE_DBUG6 |
| pro_dcache_dbug7 | DPORT_PRO_DCACHE_DBUG7 |
| pro_dcache_dbug8 | DPORT_PRO_DCACHE_DBUG8 |
| pro_dcache_dbug9 | DPORT_PRO_DCACHE_DBUG9 |
| pro_dport_apb_mask0 | DPORT_PRO_DPORT_APB_MASK0 |
| pro_dport_apb_mask1 | DPORT_PRO_DPORT_APB_MASK1 |
| pro_efuse_int_map | DPORT_PRO_EFUSE_INT_MAP |
| pro_emac_int_map | DPORT_PRO_EMAC_INT_MAP |
| pro_gpio_interrupt_map | DPORT_PRO_GPIO_INTERRUPT_MAP |
| pro_gpio_interrupt_nmi_map | DPORT_PRO_GPIO_INTERRUPT_NMI_MAP |
| pro_i2c_ext0_intr_map | DPORT_PRO_I2C_EXT0_INTR_MAP |
| pro_i2c_ext1_intr_map | DPORT_PRO_I2C_EXT1_INTR_MAP |
| pro_i2s0_int_map | DPORT_PRO_I2S0_INT_MAP |
| pro_i2s1_int_map | DPORT_PRO_I2S1_INT_MAP |
| pro_intr_status_0 | DPORT_PRO_INTR_STATUS_0 |
| pro_intr_status_1 | DPORT_PRO_INTR_STATUS_1 |
| pro_intr_status_2 | DPORT_PRO_INTR_STATUS_2 |
| pro_intrusion_ctrl | DPORT_PRO_INTRUSION_CTRL |
| pro_intrusion_status | DPORT_PRO_INTRUSION_STATUS |
| pro_ledc_int_map | DPORT_PRO_LEDC_INT_MAP |
| pro_mac_intr_map | DPORT_PRO_MAC_INTR_MAP |
| pro_mac_nmi_map | DPORT_PRO_MAC_NMI_MAP |
| pro_mmu_ia_int_map | DPORT_PRO_MMU_IA_INT_MAP |
| pro_mpu_ia_int_map | DPORT_PRO_MPU_IA_INT_MAP |
| pro_pcnt_intr_map | DPORT_PRO_PCNT_INTR_MAP |
| pro_pwm0_intr_map | DPORT_PRO_PWM0_INTR_MAP |
| pro_pwm1_intr_map | DPORT_PRO_PWM1_INTR_MAP |
| pro_pwm2_intr_map | DPORT_PRO_PWM2_INTR_MAP |
| pro_pwm3_intr_map | DPORT_PRO_PWM3_INTR_MAP |
| pro_rmt_intr_map | DPORT_PRO_RMT_INTR_MAP |
| pro_rsa_intr_map | DPORT_PRO_RSA_INTR_MAP |
| pro_rtc_core_intr_map | DPORT_PRO_RTC_CORE_INTR_MAP |
| pro_rwble_irq_map | DPORT_PRO_RWBLE_IRQ_MAP |
| pro_rwble_nmi_map | DPORT_PRO_RWBLE_NMI_MAP |
| pro_rwbt_irq_map | DPORT_PRO_RWBT_IRQ_MAP |
| pro_rwbt_nmi_map | DPORT_PRO_RWBT_NMI_MAP |
| pro_sdio_host_interrupt_map | DPORT_PRO_SDIO_HOST_INTERRUPT_MAP |
| pro_slc0_intr_map | DPORT_PRO_SLC0_INTR_MAP |
| pro_slc1_intr_map | DPORT_PRO_SLC1_INTR_MAP |
| pro_spi1_dma_int_map | DPORT_PRO_SPI1_DMA_INT_MAP |
| pro_spi2_dma_int_map | DPORT_PRO_SPI2_DMA_INT_MAP |
| pro_spi3_dma_int_map | DPORT_PRO_SPI3_DMA_INT_MAP |
| pro_spi_intr_0_map | DPORT_PRO_SPI_INTR_0_MAP |
| pro_spi_intr_1_map | DPORT_PRO_SPI_INTR_1_MAP |
| pro_spi_intr_2_map | DPORT_PRO_SPI_INTR_2_MAP |
| pro_spi_intr_3_map | DPORT_PRO_SPI_INTR_3_MAP |
| pro_tg1_wdt_level_int_map | DPORT_PRO_TG1_WDT_LEVEL_INT_MAP |
| pro_tg1_lact_level_int_map | DPORT_PRO_TG1_LACT_LEVEL_INT_MAP |
| pro_tg1_wdt_edge_int_map | DPORT_PRO_TG1_WDT_EDGE_INT_MAP |
| pro_tg1_lact_edge_int_map | DPORT_PRO_TG1_LACT_EDGE_INT_MAP |
| pro_tg1_t0_edge_int_map | DPORT_PRO_TG1_T0_EDGE_INT_MAP |
| pro_tg1_t0_level_int_map | DPORT_PRO_TG1_T0_LEVEL_INT_MAP |
| pro_tg1_t1_level_int_map | DPORT_PRO_TG1_T1_LEVEL_INT_MAP |
| pro_tg1_t1_edge_int_map | DPORT_PRO_TG1_T1_EDGE_INT_MAP |
| pro_tg_lact_edge_int_map | DPORT_PRO_TG_LACT_EDGE_INT_MAP |
| pro_tg_lact_level_int_map | DPORT_PRO_TG_LACT_LEVEL_INT_MAP |
| pro_tg_t0_edge_int_map | DPORT_PRO_TG_T0_EDGE_INT_MAP |
| pro_tg_t0_level_int_map | DPORT_PRO_TG_T0_LEVEL_INT_MAP |
| pro_tg_t1_level_int_map | DPORT_PRO_TG_T1_LEVEL_INT_MAP |
| pro_tg_t1_edge_int_map | DPORT_PRO_TG_T1_EDGE_INT_MAP |
| pro_tg_wdt_edge_int_map | DPORT_PRO_TG_WDT_EDGE_INT_MAP |
| pro_tg_wdt_level_int_map | DPORT_PRO_TG_WDT_LEVEL_INT_MAP |
| pro_timer_int1_map | DPORT_PRO_TIMER_INT1_MAP |
| pro_timer_int2_map | DPORT_PRO_TIMER_INT2_MAP |
| pro_tracemem_ena | DPORT_PRO_TRACEMEM_ENA |
| pro_uart1_intr_map | DPORT_PRO_UART1_INTR_MAP |
| pro_uart2_intr_map | DPORT_PRO_UART2_INTR_MAP |
| pro_uart_intr_map | DPORT_PRO_UART_INTR_MAP |
| pro_uhci0_intr_map | DPORT_PRO_UHCI0_INTR_MAP |
| pro_uhci1_intr_map | DPORT_PRO_UHCI1_INTR_MAP |
| pro_vecbase_ctrl | DPORT_PRO_VECBASE_CTRL |
| pro_vecbase_set | DPORT_PRO_VECBASE_SET |
| pro_wdg_int_map | DPORT_PRO_WDG_INT_MAP |
| rom_fo_ctrl | DPORT_ROM_FO_CTRL |
| rom_mpu_ena | DPORT_ROM_MPU_ENA |
| rom_mpu_table0 | DPORT_ROM_MPU_TABLE0 |
| rom_mpu_table1 | DPORT_ROM_MPU_TABLE1 |
| rom_mpu_table2 | DPORT_ROM_MPU_TABLE2 |
| rom_mpu_table3 | DPORT_ROM_MPU_TABLE3 |
| rom_pd_ctrl | DPORT_ROM_PD_CTRL |
| rsa_pd_ctrl | DPORT_RSA_PD_CTRL |
| secure_boot_ctrl | DPORT_SECURE_BOOT_CTRL |
| shrom_mpu_table0 | DPORT_SHROM_MPU_TABLE0 |
| shrom_mpu_table1 | DPORT_SHROM_MPU_TABLE1 |
| shrom_mpu_table2 | DPORT_SHROM_MPU_TABLE2 |
| shrom_mpu_table3 | DPORT_SHROM_MPU_TABLE3 |
| shrom_mpu_table4 | DPORT_SHROM_MPU_TABLE4 |
| shrom_mpu_table5 | DPORT_SHROM_MPU_TABLE5 |
| shrom_mpu_table6 | DPORT_SHROM_MPU_TABLE6 |
| shrom_mpu_table7 | DPORT_SHROM_MPU_TABLE7 |
| shrom_mpu_table8 | DPORT_SHROM_MPU_TABLE8 |
| shrom_mpu_table9 | DPORT_SHROM_MPU_TABLE9 |
| shrom_mpu_table10 | DPORT_SHROM_MPU_TABLE10 |
| shrom_mpu_table11 | DPORT_SHROM_MPU_TABLE11 |
| shrom_mpu_table12 | DPORT_SHROM_MPU_TABLE12 |
| shrom_mpu_table13 | DPORT_SHROM_MPU_TABLE13 |
| shrom_mpu_table14 | DPORT_SHROM_MPU_TABLE14 |
| shrom_mpu_table15 | DPORT_SHROM_MPU_TABLE15 |
| shrom_mpu_table16 | DPORT_SHROM_MPU_TABLE16 |
| shrom_mpu_table17 | DPORT_SHROM_MPU_TABLE17 |
| shrom_mpu_table18 | DPORT_SHROM_MPU_TABLE18 |
| shrom_mpu_table19 | DPORT_SHROM_MPU_TABLE19 |
| shrom_mpu_table20 | DPORT_SHROM_MPU_TABLE20 |
| shrom_mpu_table21 | DPORT_SHROM_MPU_TABLE21 |
| shrom_mpu_table22 | DPORT_SHROM_MPU_TABLE22 |
| shrom_mpu_table23 | DPORT_SHROM_MPU_TABLE23 |
| spi_dma_chan_sel | DPORT_SPI_DMA_CHAN_SEL |
| sram_fo_ctrl_0 | DPORT_SRAM_FO_CTRL_0 |
| sram_fo_ctrl_1 | DPORT_SRAM_FO_CTRL_1 |
| sram_pd_ctrl_0 | DPORT_SRAM_PD_CTRL_0 |
| sram_pd_ctrl_1 | DPORT_SRAM_PD_CTRL_1 |
| tag_fo_ctrl | DPORT_TAG_FO_CTRL |
| tracemem_mux_mode | DPORT_TRACEMEM_MUX_MODE |
| wifi_bb_cfg | DPORT_WIFI_BB_CFG |
| wifi_bb_cfg_2 | DPORT_WIFI_BB_CFG_2 |
| wifi_clk_en | DPORT_WIFI_CLK_EN |
Structs
| RegisterBlock | Register block |
Type Definitions
| ACCESS_CHECK | DPORT_ACCESS_CHECK |
| AHBLITE_MPU_TABLE_APB_CTRL | DPORT_AHBLITE_MPU_TABLE_APB_CTRL |
| AHBLITE_MPU_TABLE_BB | DPORT_AHBLITE_MPU_TABLE_BB |
| AHBLITE_MPU_TABLE_BT | DPORT_AHBLITE_MPU_TABLE_BT |
| AHBLITE_MPU_TABLE_BTMAC | DPORT_AHBLITE_MPU_TABLE_BTMAC |
| AHBLITE_MPU_TABLE_BT_BUFFER | DPORT_AHBLITE_MPU_TABLE_BT_BUFFER |
| AHBLITE_MPU_TABLE_CAN | DPORT_AHBLITE_MPU_TABLE_CAN |
| AHBLITE_MPU_TABLE_EFUSE | DPORT_AHBLITE_MPU_TABLE_EFUSE |
| AHBLITE_MPU_TABLE_EMAC | DPORT_AHBLITE_MPU_TABLE_EMAC |
| AHBLITE_MPU_TABLE_FE | DPORT_AHBLITE_MPU_TABLE_FE |
| AHBLITE_MPU_TABLE_FE2 | DPORT_AHBLITE_MPU_TABLE_FE2 |
| AHBLITE_MPU_TABLE_GPIO | DPORT_AHBLITE_MPU_TABLE_GPIO |
| AHBLITE_MPU_TABLE_HINF | DPORT_AHBLITE_MPU_TABLE_HINF |
| AHBLITE_MPU_TABLE_I2C | DPORT_AHBLITE_MPU_TABLE_I2C |
| AHBLITE_MPU_TABLE_I2C_EXT0 | DPORT_AHBLITE_MPU_TABLE_I2C_EXT0 |
| AHBLITE_MPU_TABLE_I2C_EXT1 | DPORT_AHBLITE_MPU_TABLE_I2C_EXT1 |
| AHBLITE_MPU_TABLE_I2S0 | DPORT_AHBLITE_MPU_TABLE_I2S0 |
| AHBLITE_MPU_TABLE_I2S1 | DPORT_AHBLITE_MPU_TABLE_I2S1 |
| AHBLITE_MPU_TABLE_IO_MUX | DPORT_AHBLITE_MPU_TABLE_IO_MUX |
| AHBLITE_MPU_TABLE_LEDC | DPORT_AHBLITE_MPU_TABLE_LEDC |
| AHBLITE_MPU_TABLE_MISC | DPORT_AHBLITE_MPU_TABLE_MISC |
| AHBLITE_MPU_TABLE_PCNT | DPORT_AHBLITE_MPU_TABLE_PCNT |
| AHBLITE_MPU_TABLE_PWM0 | DPORT_AHBLITE_MPU_TABLE_PWM0 |
| AHBLITE_MPU_TABLE_PWM1 | DPORT_AHBLITE_MPU_TABLE_PWM1 |
| AHBLITE_MPU_TABLE_PWM2 | DPORT_AHBLITE_MPU_TABLE_PWM2 |
| AHBLITE_MPU_TABLE_PWM3 | DPORT_AHBLITE_MPU_TABLE_PWM3 |
| AHBLITE_MPU_TABLE_PWR | DPORT_AHBLITE_MPU_TABLE_PWR |
| AHBLITE_MPU_TABLE_RMT | DPORT_AHBLITE_MPU_TABLE_RMT |
| AHBLITE_MPU_TABLE_RTC | DPORT_AHBLITE_MPU_TABLE_RTC |
| AHBLITE_MPU_TABLE_RWBT | DPORT_AHBLITE_MPU_TABLE_RWBT |
| AHBLITE_MPU_TABLE_SDIO_HOST | DPORT_AHBLITE_MPU_TABLE_SDIO_HOST |
| AHBLITE_MPU_TABLE_SLC | DPORT_AHBLITE_MPU_TABLE_SLC |
| AHBLITE_MPU_TABLE_SLCHOST | DPORT_AHBLITE_MPU_TABLE_SLCHOST |
| AHBLITE_MPU_TABLE_SPI0 | DPORT_AHBLITE_MPU_TABLE_SPI0 |
| AHBLITE_MPU_TABLE_SPI1 | DPORT_AHBLITE_MPU_TABLE_SPI1 |
| AHBLITE_MPU_TABLE_SPI2 | DPORT_AHBLITE_MPU_TABLE_SPI2 |
| AHBLITE_MPU_TABLE_SPI3 | DPORT_AHBLITE_MPU_TABLE_SPI3 |
| AHBLITE_MPU_TABLE_SPI_ENCRYPT | DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT |
| AHBLITE_MPU_TABLE_TIMER | DPORT_AHBLITE_MPU_TABLE_TIMER |
| AHBLITE_MPU_TABLE_TIMERGROUP | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP |
| AHBLITE_MPU_TABLE_TIMERGROUP1 | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1 |
| AHBLITE_MPU_TABLE_UART | DPORT_AHBLITE_MPU_TABLE_UART |
| AHBLITE_MPU_TABLE_UART1 | DPORT_AHBLITE_MPU_TABLE_UART1 |
| AHBLITE_MPU_TABLE_UART2 | DPORT_AHBLITE_MPU_TABLE_UART2 |
| AHBLITE_MPU_TABLE_UHCI0 | DPORT_AHBLITE_MPU_TABLE_UHCI0 |
| AHBLITE_MPU_TABLE_UHCI1 | DPORT_AHBLITE_MPU_TABLE_UHCI1 |
| AHBLITE_MPU_TABLE_WDG | DPORT_AHBLITE_MPU_TABLE_WDG |
| AHBLITE_MPU_TABLE_WIFIMAC | DPORT_AHBLITE_MPU_TABLE_WIFIMAC |
| AHB_LITE_MASK | DPORT_AHB_LITE_MASK |
| AHB_MPU_TABLE_0 | DPORT_AHB_MPU_TABLE_0 |
| AHB_MPU_TABLE_1 | DPORT_AHB_MPU_TABLE_1 |
| APPCPU_CTRL_A | DPORT_APPCPU_CTRL_A |
| APPCPU_CTRL_B | DPORT_APPCPU_CTRL_B |
| APPCPU_CTRL_C | DPORT_APPCPU_CTRL_C |
| APPCPU_CTRL_D | DPORT_APPCPU_CTRL_D |
| APP_BB_INT_MAP | DPORT_APP_BB_INT_MAP |
| APP_BOOT_REMAP_CTRL | DPORT_APP_BOOT_REMAP_CTRL |
| APP_BT_BB_INT_MAP | DPORT_APP_BT_BB_INT_MAP |
| APP_BT_BB_NMI_MAP | DPORT_APP_BT_BB_NMI_MAP |
| APP_BT_MAC_INT_MAP | DPORT_APP_BT_MAC_INT_MAP |
| APP_CACHE_CTRL | DPORT_APP_CACHE_CTRL |
| APP_CACHE_CTRL1 | DPORT_APP_CACHE_CTRL1 |
| APP_CACHE_IA_INT_MAP | DPORT_APP_CACHE_IA_INT_MAP |
| APP_CACHE_LOCK_0_ADDR | DPORT_APP_CACHE_LOCK_0_ADDR |
| APP_CACHE_LOCK_1_ADDR | DPORT_APP_CACHE_LOCK_1_ADDR |
| APP_CACHE_LOCK_2_ADDR | DPORT_APP_CACHE_LOCK_2_ADDR |
| APP_CACHE_LOCK_3_ADDR | DPORT_APP_CACHE_LOCK_3_ADDR |
| APP_CAN_INT_MAP | DPORT_APP_CAN_INT_MAP |
| APP_CPU_INTR_FROM_CPU_0_MAP | DPORT_APP_CPU_INTR_FROM_CPU_0_MAP |
| APP_CPU_INTR_FROM_CPU_1_MAP | DPORT_APP_CPU_INTR_FROM_CPU_1_MAP |
| APP_CPU_INTR_FROM_CPU_2_MAP | DPORT_APP_CPU_INTR_FROM_CPU_2_MAP |
| APP_CPU_INTR_FROM_CPU_3_MAP | DPORT_APP_CPU_INTR_FROM_CPU_3_MAP |
| APP_CPU_RECORD_CTRL | DPORT_APP_CPU_RECORD_CTRL |
| APP_CPU_RECORD_PDEBUGDATA | DPORT_APP_CPU_RECORD_PDEBUGDATA |
| APP_CPU_RECORD_PDEBUGINST | DPORT_APP_CPU_RECORD_PDEBUGINST |
| APP_CPU_RECORD_PDEBUGLS0STAT | DPORT_APP_CPU_RECORD_PDEBUGLS0STAT |
| APP_CPU_RECORD_PDEBUGLS0ADDR | DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR |
| APP_CPU_RECORD_PDEBUGLS0DATA | DPORT_APP_CPU_RECORD_PDEBUGLS0DATA |
| APP_CPU_RECORD_PDEBUGPC | DPORT_APP_CPU_RECORD_PDEBUGPC |
| APP_CPU_RECORD_PDEBUGSTATUS | DPORT_APP_CPU_RECORD_PDEBUGSTATUS |
| APP_CPU_RECORD_PID | DPORT_APP_CPU_RECORD_PID |
| APP_CPU_RECORD_STATUS | DPORT_APP_CPU_RECORD_STATUS |
| APP_DCACHE_DBUG0 | DPORT_APP_DCACHE_DBUG0 |
| APP_DCACHE_DBUG1 | DPORT_APP_DCACHE_DBUG1 |
| APP_DCACHE_DBUG2 | DPORT_APP_DCACHE_DBUG2 |
| APP_DCACHE_DBUG3 | DPORT_APP_DCACHE_DBUG3 |
| APP_DCACHE_DBUG4 | DPORT_APP_DCACHE_DBUG4 |
| APP_DCACHE_DBUG5 | DPORT_APP_DCACHE_DBUG5 |
| APP_DCACHE_DBUG6 | DPORT_APP_DCACHE_DBUG6 |
| APP_DCACHE_DBUG7 | DPORT_APP_DCACHE_DBUG7 |
| APP_DCACHE_DBUG8 | DPORT_APP_DCACHE_DBUG8 |
| APP_DCACHE_DBUG9 | DPORT_APP_DCACHE_DBUG9 |
| APP_DPORT_APB_MASK0 | DPORT_APP_DPORT_APB_MASK0 |
| APP_DPORT_APB_MASK1 | DPORT_APP_DPORT_APB_MASK1 |
| APP_EFUSE_INT_MAP | DPORT_APP_EFUSE_INT_MAP |
| APP_EMAC_INT_MAP | DPORT_APP_EMAC_INT_MAP |
| APP_GPIO_INTERRUPT_MAP | DPORT_APP_GPIO_INTERRUPT_MAP |
| APP_GPIO_INTERRUPT_NMI_MAP | DPORT_APP_GPIO_INTERRUPT_NMI_MAP |
| APP_I2C_EXT0_INTR_MAP | DPORT_APP_I2C_EXT0_INTR_MAP |
| APP_I2C_EXT1_INTR_MAP | DPORT_APP_I2C_EXT1_INTR_MAP |
| APP_I2S0_INT_MAP | DPORT_APP_I2S0_INT_MAP |
| APP_I2S1_INT_MAP | DPORT_APP_I2S1_INT_MAP |
| APP_INTRUSION_CTRL | DPORT_APP_INTRUSION_CTRL |
| APP_INTRUSION_STATUS | DPORT_APP_INTRUSION_STATUS |
| APP_INTR_STATUS_0 | DPORT_APP_INTR_STATUS_0 |
| APP_INTR_STATUS_1 | DPORT_APP_INTR_STATUS_1 |
| APP_INTR_STATUS_2 | DPORT_APP_INTR_STATUS_2 |
| APP_LEDC_INT_MAP | DPORT_APP_LEDC_INT_MAP |
| APP_MAC_INTR_MAP | DPORT_APP_MAC_INTR_MAP |
| APP_MAC_NMI_MAP | DPORT_APP_MAC_NMI_MAP |
| APP_MMU_IA_INT_MAP | DPORT_APP_MMU_IA_INT_MAP |
| APP_MPU_IA_INT_MAP | DPORT_APP_MPU_IA_INT_MAP |
| APP_PCNT_INTR_MAP | DPORT_APP_PCNT_INTR_MAP |
| APP_PWM0_INTR_MAP | DPORT_APP_PWM0_INTR_MAP |
| APP_PWM1_INTR_MAP | DPORT_APP_PWM1_INTR_MAP |
| APP_PWM2_INTR_MAP | DPORT_APP_PWM2_INTR_MAP |
| APP_PWM3_INTR_MAP | DPORT_APP_PWM3_INTR_MAP |
| APP_RMT_INTR_MAP | DPORT_APP_RMT_INTR_MAP |
| APP_RSA_INTR_MAP | DPORT_APP_RSA_INTR_MAP |
| APP_RTC_CORE_INTR_MAP | DPORT_APP_RTC_CORE_INTR_MAP |
| APP_RWBLE_IRQ_MAP | DPORT_APP_RWBLE_IRQ_MAP |
| APP_RWBLE_NMI_MAP | DPORT_APP_RWBLE_NMI_MAP |
| APP_RWBT_IRQ_MAP | DPORT_APP_RWBT_IRQ_MAP |
| APP_RWBT_NMI_MAP | DPORT_APP_RWBT_NMI_MAP |
| APP_SDIO_HOST_INTERRUPT_MAP | DPORT_APP_SDIO_HOST_INTERRUPT_MAP |
| APP_SLC0_INTR_MAP | DPORT_APP_SLC0_INTR_MAP |
| APP_SLC1_INTR_MAP | DPORT_APP_SLC1_INTR_MAP |
| APP_SPI1_DMA_INT_MAP | DPORT_APP_SPI1_DMA_INT_MAP |
| APP_SPI2_DMA_INT_MAP | DPORT_APP_SPI2_DMA_INT_MAP |
| APP_SPI3_DMA_INT_MAP | DPORT_APP_SPI3_DMA_INT_MAP |
| APP_SPI_INTR_0_MAP | DPORT_APP_SPI_INTR_0_MAP |
| APP_SPI_INTR_1_MAP | DPORT_APP_SPI_INTR_1_MAP |
| APP_SPI_INTR_2_MAP | DPORT_APP_SPI_INTR_2_MAP |
| APP_SPI_INTR_3_MAP | DPORT_APP_SPI_INTR_3_MAP |
| APP_TG1_WDT_LEVEL_INT_MAP | DPORT_APP_TG1_WDT_LEVEL_INT_MAP |
| APP_TG1_LACT_LEVEL_INT_MAP | DPORT_APP_TG1_LACT_LEVEL_INT_MAP |
| APP_TG1_WDT_EDGE_INT_MAP | DPORT_APP_TG1_WDT_EDGE_INT_MAP |
| APP_TG1_LACT_EDGE_INT_MAP | DPORT_APP_TG1_LACT_EDGE_INT_MAP |
| APP_TG1_T0_EDGE_INT_MAP | DPORT_APP_TG1_T0_EDGE_INT_MAP |
| APP_TG1_T0_LEVEL_INT_MAP | DPORT_APP_TG1_T0_LEVEL_INT_MAP |
| APP_TG1_T1_LEVEL_INT_MAP | DPORT_APP_TG1_T1_LEVEL_INT_MAP |
| APP_TG1_T1_EDGE_INT_MAP | DPORT_APP_TG1_T1_EDGE_INT_MAP |
| APP_TG_LACT_EDGE_INT_MAP | DPORT_APP_TG_LACT_EDGE_INT_MAP |
| APP_TG_LACT_LEVEL_INT_MAP | DPORT_APP_TG_LACT_LEVEL_INT_MAP |
| APP_TG_T0_EDGE_INT_MAP | DPORT_APP_TG_T0_EDGE_INT_MAP |
| APP_TG_T0_LEVEL_INT_MAP | DPORT_APP_TG_T0_LEVEL_INT_MAP |
| APP_TG_T1_LEVEL_INT_MAP | DPORT_APP_TG_T1_LEVEL_INT_MAP |
| APP_TG_T1_EDGE_INT_MAP | DPORT_APP_TG_T1_EDGE_INT_MAP |
| APP_TG_WDT_EDGE_INT_MAP | DPORT_APP_TG_WDT_EDGE_INT_MAP |
| APP_TG_WDT_LEVEL_INT_MAP | DPORT_APP_TG_WDT_LEVEL_INT_MAP |
| APP_TIMER_INT1_MAP | DPORT_APP_TIMER_INT1_MAP |
| APP_TIMER_INT2_MAP | DPORT_APP_TIMER_INT2_MAP |
| APP_TRACEMEM_ENA | DPORT_APP_TRACEMEM_ENA |
| APP_UART1_INTR_MAP | DPORT_APP_UART1_INTR_MAP |
| APP_UART2_INTR_MAP | DPORT_APP_UART2_INTR_MAP |
| APP_UART_INTR_MAP | DPORT_APP_UART_INTR_MAP |
| APP_UHCI0_INTR_MAP | DPORT_APP_UHCI0_INTR_MAP |
| APP_UHCI1_INTR_MAP | DPORT_APP_UHCI1_INTR_MAP |
| APP_VECBASE_CTRL | DPORT_APP_VECBASE_CTRL |
| APP_VECBASE_SET | DPORT_APP_VECBASE_SET |
| APP_WDG_INT_MAP | DPORT_APP_WDG_INT_MAP |
| BT_LPCK_DIV_FRAC | DPORT_BT_LPCK_DIV_FRAC |
| BT_LPCK_DIV_INT | DPORT_BT_LPCK_DIV_INT |
| CACHE_IA_INT_EN | DPORT_CACHE_IA_INT_EN |
| CACHE_MUX_MODE | DPORT_CACHE_MUX_MODE |
| CORE_RST_EN | DPORT_CORE_RST_EN |
| CPU_INTR_FROM_CPU_0 | DPORT_CPU_INTR_FROM_CPU_0 |
| CPU_INTR_FROM_CPU_1 | DPORT_CPU_INTR_FROM_CPU_1 |
| CPU_INTR_FROM_CPU_2 | DPORT_CPU_INTR_FROM_CPU_2 |
| CPU_INTR_FROM_CPU_3 | DPORT_CPU_INTR_FROM_CPU_3 |
| CPU_PER_CONF | DPORT_CPU_PER_CONF |
| DATE | DPORT_DATE |
| DMMU_PAGE_MODE | DPORT_DMMU_PAGE_MODE |
| DMMU_TABLE0 | DPORT_DMMU_TABLE0 |
| DMMU_TABLE1 | DPORT_DMMU_TABLE1 |
| DMMU_TABLE2 | DPORT_DMMU_TABLE2 |
| DMMU_TABLE3 | DPORT_DMMU_TABLE3 |
| DMMU_TABLE4 | DPORT_DMMU_TABLE4 |
| DMMU_TABLE5 | DPORT_DMMU_TABLE5 |
| DMMU_TABLE6 | DPORT_DMMU_TABLE6 |
| DMMU_TABLE7 | DPORT_DMMU_TABLE7 |
| DMMU_TABLE8 | DPORT_DMMU_TABLE8 |
| DMMU_TABLE9 | DPORT_DMMU_TABLE9 |
| DMMU_TABLE10 | DPORT_DMMU_TABLE10 |
| DMMU_TABLE11 | DPORT_DMMU_TABLE11 |
| DMMU_TABLE12 | DPORT_DMMU_TABLE12 |
| DMMU_TABLE13 | DPORT_DMMU_TABLE13 |
| DMMU_TABLE14 | DPORT_DMMU_TABLE14 |
| DMMU_TABLE15 | DPORT_DMMU_TABLE15 |
| FRONT_END_MEM_PD | DPORT_FRONT_END_MEM_PD |
| HOST_INF_SEL | DPORT_HOST_INF_SEL |
| IMMU_PAGE_MODE | DPORT_IMMU_PAGE_MODE |
| IMMU_TABLE0 | DPORT_IMMU_TABLE0 |
| IMMU_TABLE1 | DPORT_IMMU_TABLE1 |
| IMMU_TABLE2 | DPORT_IMMU_TABLE2 |
| IMMU_TABLE3 | DPORT_IMMU_TABLE3 |
| IMMU_TABLE4 | DPORT_IMMU_TABLE4 |
| IMMU_TABLE5 | DPORT_IMMU_TABLE5 |
| IMMU_TABLE6 | DPORT_IMMU_TABLE6 |
| IMMU_TABLE7 | DPORT_IMMU_TABLE7 |
| IMMU_TABLE8 | DPORT_IMMU_TABLE8 |
| IMMU_TABLE9 | DPORT_IMMU_TABLE9 |
| IMMU_TABLE10 | DPORT_IMMU_TABLE10 |
| IMMU_TABLE11 | DPORT_IMMU_TABLE11 |
| IMMU_TABLE12 | DPORT_IMMU_TABLE12 |
| IMMU_TABLE13 | DPORT_IMMU_TABLE13 |
| IMMU_TABLE14 | DPORT_IMMU_TABLE14 |
| IMMU_TABLE15 | DPORT_IMMU_TABLE15 |
| IRAM_DRAM_AHB_SEL | DPORT_IRAM_DRAM_AHB_SEL |
| MEM_ACCESS_DBUG0 | DPORT_MEM_ACCESS_DBUG0 |
| MEM_ACCESS_DBUG1 | DPORT_MEM_ACCESS_DBUG1 |
| MEM_PD_MASK | DPORT_MEM_PD_MASK |
| MMU_IA_INT_EN | DPORT_MMU_IA_INT_EN |
| MPU_IA_INT_EN | DPORT_MPU_IA_INT_EN |
| PERIP_CLK_EN | DPORT_PERIP_CLK_EN |
| PERIP_RST_EN | DPORT_PERIP_RST_EN |
| PERI_CLK_EN | DPORT_PERI_CLK_EN |
| PERI_RST_EN | DPORT_PERI_RST_EN |
| PRO_BB_INT_MAP | DPORT_PRO_BB_INT_MAP |
| PRO_BOOT_REMAP_CTRL | DPORT_PRO_BOOT_REMAP_CTRL |
| PRO_BT_BB_INT_MAP | DPORT_PRO_BT_BB_INT_MAP |
| PRO_BT_BB_NMI_MAP | DPORT_PRO_BT_BB_NMI_MAP |
| PRO_BT_MAC_INT_MAP | DPORT_PRO_BT_MAC_INT_MAP |
| PRO_CACHE_CTRL | DPORT_PRO_CACHE_CTRL |
| PRO_CACHE_CTRL1 | DPORT_PRO_CACHE_CTRL1 |
| PRO_CACHE_IA_INT_MAP | DPORT_PRO_CACHE_IA_INT_MAP |
| PRO_CACHE_LOCK_0_ADDR | DPORT_PRO_CACHE_LOCK_0_ADDR |
| PRO_CACHE_LOCK_1_ADDR | DPORT_PRO_CACHE_LOCK_1_ADDR |
| PRO_CACHE_LOCK_2_ADDR | DPORT_PRO_CACHE_LOCK_2_ADDR |
| PRO_CACHE_LOCK_3_ADDR | DPORT_PRO_CACHE_LOCK_3_ADDR |
| PRO_CAN_INT_MAP | DPORT_PRO_CAN_INT_MAP |
| PRO_CPU_INTR_FROM_CPU_0_MAP | DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP |
| PRO_CPU_INTR_FROM_CPU_1_MAP | DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP |
| PRO_CPU_INTR_FROM_CPU_2_MAP | DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP |
| PRO_CPU_INTR_FROM_CPU_3_MAP | DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP |
| PRO_CPU_RECORD_CTRL | DPORT_PRO_CPU_RECORD_CTRL |
| PRO_CPU_RECORD_PDEBUGDATA | DPORT_PRO_CPU_RECORD_PDEBUGDATA |
| PRO_CPU_RECORD_PDEBUGINST | DPORT_PRO_CPU_RECORD_PDEBUGINST |
| PRO_CPU_RECORD_PDEBUGLS0STAT | DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT |
| PRO_CPU_RECORD_PDEBUGLS0ADDR | DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR |
| PRO_CPU_RECORD_PDEBUGLS0DATA | DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA |
| PRO_CPU_RECORD_PDEBUGPC | DPORT_PRO_CPU_RECORD_PDEBUGPC |
| PRO_CPU_RECORD_PDEBUGSTATUS | DPORT_PRO_CPU_RECORD_PDEBUGSTATUS |
| PRO_CPU_RECORD_PID | DPORT_PRO_CPU_RECORD_PID |
| PRO_CPU_RECORD_STATUS | DPORT_PRO_CPU_RECORD_STATUS |
| PRO_DCACHE_DBUG0 | DPORT_PRO_DCACHE_DBUG0 |
| PRO_DCACHE_DBUG1 | DPORT_PRO_DCACHE_DBUG1 |
| PRO_DCACHE_DBUG2 | DPORT_PRO_DCACHE_DBUG2 |
| PRO_DCACHE_DBUG3 | DPORT_PRO_DCACHE_DBUG3 |
| PRO_DCACHE_DBUG4 | DPORT_PRO_DCACHE_DBUG4 |
| PRO_DCACHE_DBUG5 | DPORT_PRO_DCACHE_DBUG5 |
| PRO_DCACHE_DBUG6 | DPORT_PRO_DCACHE_DBUG6 |
| PRO_DCACHE_DBUG7 | DPORT_PRO_DCACHE_DBUG7 |
| PRO_DCACHE_DBUG8 | DPORT_PRO_DCACHE_DBUG8 |
| PRO_DCACHE_DBUG9 | DPORT_PRO_DCACHE_DBUG9 |
| PRO_DPORT_APB_MASK0 | DPORT_PRO_DPORT_APB_MASK0 |
| PRO_DPORT_APB_MASK1 | DPORT_PRO_DPORT_APB_MASK1 |
| PRO_EFUSE_INT_MAP | DPORT_PRO_EFUSE_INT_MAP |
| PRO_EMAC_INT_MAP | DPORT_PRO_EMAC_INT_MAP |
| PRO_GPIO_INTERRUPT_MAP | DPORT_PRO_GPIO_INTERRUPT_MAP |
| PRO_GPIO_INTERRUPT_NMI_MAP | DPORT_PRO_GPIO_INTERRUPT_NMI_MAP |
| PRO_I2C_EXT0_INTR_MAP | DPORT_PRO_I2C_EXT0_INTR_MAP |
| PRO_I2C_EXT1_INTR_MAP | DPORT_PRO_I2C_EXT1_INTR_MAP |
| PRO_I2S0_INT_MAP | DPORT_PRO_I2S0_INT_MAP |
| PRO_I2S1_INT_MAP | DPORT_PRO_I2S1_INT_MAP |
| PRO_INTRUSION_CTRL | DPORT_PRO_INTRUSION_CTRL |
| PRO_INTRUSION_STATUS | DPORT_PRO_INTRUSION_STATUS |
| PRO_INTR_STATUS_0 | DPORT_PRO_INTR_STATUS_0 |
| PRO_INTR_STATUS_1 | DPORT_PRO_INTR_STATUS_1 |
| PRO_INTR_STATUS_2 | DPORT_PRO_INTR_STATUS_2 |
| PRO_LEDC_INT_MAP | DPORT_PRO_LEDC_INT_MAP |
| PRO_MAC_INTR_MAP | DPORT_PRO_MAC_INTR_MAP |
| PRO_MAC_NMI_MAP | DPORT_PRO_MAC_NMI_MAP |
| PRO_MMU_IA_INT_MAP | DPORT_PRO_MMU_IA_INT_MAP |
| PRO_MPU_IA_INT_MAP | DPORT_PRO_MPU_IA_INT_MAP |
| PRO_PCNT_INTR_MAP | DPORT_PRO_PCNT_INTR_MAP |
| PRO_PWM0_INTR_MAP | DPORT_PRO_PWM0_INTR_MAP |
| PRO_PWM1_INTR_MAP | DPORT_PRO_PWM1_INTR_MAP |
| PRO_PWM2_INTR_MAP | DPORT_PRO_PWM2_INTR_MAP |
| PRO_PWM3_INTR_MAP | DPORT_PRO_PWM3_INTR_MAP |
| PRO_RMT_INTR_MAP | DPORT_PRO_RMT_INTR_MAP |
| PRO_RSA_INTR_MAP | DPORT_PRO_RSA_INTR_MAP |
| PRO_RTC_CORE_INTR_MAP | DPORT_PRO_RTC_CORE_INTR_MAP |
| PRO_RWBLE_IRQ_MAP | DPORT_PRO_RWBLE_IRQ_MAP |
| PRO_RWBLE_NMI_MAP | DPORT_PRO_RWBLE_NMI_MAP |
| PRO_RWBT_IRQ_MAP | DPORT_PRO_RWBT_IRQ_MAP |
| PRO_RWBT_NMI_MAP | DPORT_PRO_RWBT_NMI_MAP |
| PRO_SDIO_HOST_INTERRUPT_MAP | DPORT_PRO_SDIO_HOST_INTERRUPT_MAP |
| PRO_SLC0_INTR_MAP | DPORT_PRO_SLC0_INTR_MAP |
| PRO_SLC1_INTR_MAP | DPORT_PRO_SLC1_INTR_MAP |
| PRO_SPI1_DMA_INT_MAP | DPORT_PRO_SPI1_DMA_INT_MAP |
| PRO_SPI2_DMA_INT_MAP | DPORT_PRO_SPI2_DMA_INT_MAP |
| PRO_SPI3_DMA_INT_MAP | DPORT_PRO_SPI3_DMA_INT_MAP |
| PRO_SPI_INTR_0_MAP | DPORT_PRO_SPI_INTR_0_MAP |
| PRO_SPI_INTR_1_MAP | DPORT_PRO_SPI_INTR_1_MAP |
| PRO_SPI_INTR_2_MAP | DPORT_PRO_SPI_INTR_2_MAP |
| PRO_SPI_INTR_3_MAP | DPORT_PRO_SPI_INTR_3_MAP |
| PRO_TG1_WDT_LEVEL_INT_MAP | DPORT_PRO_TG1_WDT_LEVEL_INT_MAP |
| PRO_TG1_LACT_LEVEL_INT_MAP | DPORT_PRO_TG1_LACT_LEVEL_INT_MAP |
| PRO_TG1_WDT_EDGE_INT_MAP | DPORT_PRO_TG1_WDT_EDGE_INT_MAP |
| PRO_TG1_LACT_EDGE_INT_MAP | DPORT_PRO_TG1_LACT_EDGE_INT_MAP |
| PRO_TG1_T0_EDGE_INT_MAP | DPORT_PRO_TG1_T0_EDGE_INT_MAP |
| PRO_TG1_T0_LEVEL_INT_MAP | DPORT_PRO_TG1_T0_LEVEL_INT_MAP |
| PRO_TG1_T1_LEVEL_INT_MAP | DPORT_PRO_TG1_T1_LEVEL_INT_MAP |
| PRO_TG1_T1_EDGE_INT_MAP | DPORT_PRO_TG1_T1_EDGE_INT_MAP |
| PRO_TG_LACT_EDGE_INT_MAP | DPORT_PRO_TG_LACT_EDGE_INT_MAP |
| PRO_TG_LACT_LEVEL_INT_MAP | DPORT_PRO_TG_LACT_LEVEL_INT_MAP |
| PRO_TG_T0_EDGE_INT_MAP | DPORT_PRO_TG_T0_EDGE_INT_MAP |
| PRO_TG_T0_LEVEL_INT_MAP | DPORT_PRO_TG_T0_LEVEL_INT_MAP |
| PRO_TG_T1_LEVEL_INT_MAP | DPORT_PRO_TG_T1_LEVEL_INT_MAP |
| PRO_TG_T1_EDGE_INT_MAP | DPORT_PRO_TG_T1_EDGE_INT_MAP |
| PRO_TG_WDT_EDGE_INT_MAP | DPORT_PRO_TG_WDT_EDGE_INT_MAP |
| PRO_TG_WDT_LEVEL_INT_MAP | DPORT_PRO_TG_WDT_LEVEL_INT_MAP |
| PRO_TIMER_INT1_MAP | DPORT_PRO_TIMER_INT1_MAP |
| PRO_TIMER_INT2_MAP | DPORT_PRO_TIMER_INT2_MAP |
| PRO_TRACEMEM_ENA | DPORT_PRO_TRACEMEM_ENA |
| PRO_UART1_INTR_MAP | DPORT_PRO_UART1_INTR_MAP |
| PRO_UART2_INTR_MAP | DPORT_PRO_UART2_INTR_MAP |
| PRO_UART_INTR_MAP | DPORT_PRO_UART_INTR_MAP |
| PRO_UHCI0_INTR_MAP | DPORT_PRO_UHCI0_INTR_MAP |
| PRO_UHCI1_INTR_MAP | DPORT_PRO_UHCI1_INTR_MAP |
| PRO_VECBASE_CTRL | DPORT_PRO_VECBASE_CTRL |
| PRO_VECBASE_SET | DPORT_PRO_VECBASE_SET |
| PRO_WDG_INT_MAP | DPORT_PRO_WDG_INT_MAP |
| ROM_FO_CTRL | DPORT_ROM_FO_CTRL |
| ROM_MPU_ENA | DPORT_ROM_MPU_ENA |
| ROM_MPU_TABLE0 | DPORT_ROM_MPU_TABLE0 |
| ROM_MPU_TABLE1 | DPORT_ROM_MPU_TABLE1 |
| ROM_MPU_TABLE2 | DPORT_ROM_MPU_TABLE2 |
| ROM_MPU_TABLE3 | DPORT_ROM_MPU_TABLE3 |
| ROM_PD_CTRL | DPORT_ROM_PD_CTRL |
| RSA_PD_CTRL | DPORT_RSA_PD_CTRL |
| SECURE_BOOT_CTRL | DPORT_SECURE_BOOT_CTRL |
| SHROM_MPU_TABLE0 | DPORT_SHROM_MPU_TABLE0 |
| SHROM_MPU_TABLE1 | DPORT_SHROM_MPU_TABLE1 |
| SHROM_MPU_TABLE2 | DPORT_SHROM_MPU_TABLE2 |
| SHROM_MPU_TABLE3 | DPORT_SHROM_MPU_TABLE3 |
| SHROM_MPU_TABLE4 | DPORT_SHROM_MPU_TABLE4 |
| SHROM_MPU_TABLE5 | DPORT_SHROM_MPU_TABLE5 |
| SHROM_MPU_TABLE6 | DPORT_SHROM_MPU_TABLE6 |
| SHROM_MPU_TABLE7 | DPORT_SHROM_MPU_TABLE7 |
| SHROM_MPU_TABLE8 | DPORT_SHROM_MPU_TABLE8 |
| SHROM_MPU_TABLE9 | DPORT_SHROM_MPU_TABLE9 |
| SHROM_MPU_TABLE10 | DPORT_SHROM_MPU_TABLE10 |
| SHROM_MPU_TABLE11 | DPORT_SHROM_MPU_TABLE11 |
| SHROM_MPU_TABLE12 | DPORT_SHROM_MPU_TABLE12 |
| SHROM_MPU_TABLE13 | DPORT_SHROM_MPU_TABLE13 |
| SHROM_MPU_TABLE14 | DPORT_SHROM_MPU_TABLE14 |
| SHROM_MPU_TABLE15 | DPORT_SHROM_MPU_TABLE15 |
| SHROM_MPU_TABLE16 | DPORT_SHROM_MPU_TABLE16 |
| SHROM_MPU_TABLE17 | DPORT_SHROM_MPU_TABLE17 |
| SHROM_MPU_TABLE18 | DPORT_SHROM_MPU_TABLE18 |
| SHROM_MPU_TABLE19 | DPORT_SHROM_MPU_TABLE19 |
| SHROM_MPU_TABLE20 | DPORT_SHROM_MPU_TABLE20 |
| SHROM_MPU_TABLE21 | DPORT_SHROM_MPU_TABLE21 |
| SHROM_MPU_TABLE22 | DPORT_SHROM_MPU_TABLE22 |
| SHROM_MPU_TABLE23 | DPORT_SHROM_MPU_TABLE23 |
| SPI_DMA_CHAN_SEL | DPORT_SPI_DMA_CHAN_SEL |
| SRAM_FO_CTRL_0 | DPORT_SRAM_FO_CTRL_0 |
| SRAM_FO_CTRL_1 | DPORT_SRAM_FO_CTRL_1 |
| SRAM_PD_CTRL_0 | DPORT_SRAM_PD_CTRL_0 |
| SRAM_PD_CTRL_1 | DPORT_SRAM_PD_CTRL_1 |
| TAG_FO_CTRL | DPORT_TAG_FO_CTRL |
| TRACEMEM_MUX_MODE | DPORT_TRACEMEM_MUX_MODE |
| WIFI_BB_CFG | DPORT_WIFI_BB_CFG |
| WIFI_BB_CFG_2 | DPORT_WIFI_BB_CFG_2 |
| WIFI_CLK_EN | DPORT_WIFI_CLK_EN |