Expand description
Structs
Field APB_MEM_RST_CH2 reader - Set this bit to reset W/R ram address for channel2 by apb fifo access
Field APB_MEM_RST_CH2 writer - Set this bit to reset W/R ram address for channel2 by apb fifo access
This register you can [read]
(crate::generic::Reg::read), [write_with_zero]
(crate::generic::Reg::write_with_zero), [reset]
(crate::generic::Reg::reset), write
(crate::generic::Reg::write), [modify]
(crate::generic::Reg::modify). See [API]
(https://docs.rs/svd2rust/#read–modify–write-api).
Field IDLE_OUT_EN_CH2 reader - This is the output enable control bit for channel2 in IDLE state.
Field IDLE_OUT_EN_CH2 writer - This is the output enable control bit for channel2 in IDLE state.
Field IDLE_OUT_LV_CH2 reader - This bit configures the output signal’s level for channel2 in IDLE state.
Field IDLE_OUT_LV_CH2 writer - This bit configures the output signal’s level for channel2 in IDLE state.
Field MEM_OWNER_CH2 reader - This is the mark of channel2’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram
Field MEM_OWNER_CH2 writer - This is the mark of channel2’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram
Field MEM_RD_RST_CH2 reader - Set this bit to reset read ram address for channel2 by transmitter access.
Field MEM_RD_RST_CH2 writer - Set this bit to reset read ram address for channel2 by transmitter access.
Field MEM_WR_RST_CH2 reader - Set this bit to reset write ram address for channel2 by receiver access.
Field MEM_WR_RST_CH2 writer - Set this bit to reset write ram address for channel2 by receiver access.
Register CH2CONF1 reader
Field REF_ALWAYS_ON_CH2 reader - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref
Field REF_ALWAYS_ON_CH2 writer - This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref
Field REF_CNT_RST_CH2 reader - This bit is used to reset divider in channel2.
Field REF_CNT_RST_CH2 writer - This bit is used to reset divider in channel2.
Field RX_EN_CH2 reader - Set this bit to enbale receving data for channel2.
Field RX_EN_CH2 writer - Set this bit to enbale receving data for channel2.
Field RX_FILTER_EN_CH2 reader - This is the receive filter enable bit for channel2.
Field RX_FILTER_EN_CH2 writer - This is the receive filter enable bit for channel2.
Field RX_FILTER_THRES_CH2 reader - in receive mode channel2 ignore input pulse when the pulse width is smaller then this value.
Field RX_FILTER_THRES_CH2 writer - in receive mode channel2 ignore input pulse when the pulse width is smaller then this value.
Field TX_CONTI_MODE_CH2 reader - Set this bit to continue sending from the first data to the last data in channel2.
Field TX_CONTI_MODE_CH2 writer - Set this bit to continue sending from the first data to the last data in channel2.
Field TX_START_CH2 reader - Set this bit to start sending data for channel2.
Field TX_START_CH2 writer - Set this bit to start sending data for channel2.
Register CH2CONF1 writer