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#[doc = "Register `PRO_CACHE_LOCK_0_ADDR` reader"] pub struct R(crate::R<PRO_CACHE_LOCK_0_ADDR_SPEC>); impl core::ops::Deref for R { type Target = crate::R<PRO_CACHE_LOCK_0_ADDR_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::convert::From<crate::R<PRO_CACHE_LOCK_0_ADDR_SPEC>> for R { fn from(reader: crate::R<PRO_CACHE_LOCK_0_ADDR_SPEC>) -> Self { R(reader) } } #[doc = "Register `PRO_CACHE_LOCK_0_ADDR` writer"] pub struct W(crate::W<PRO_CACHE_LOCK_0_ADDR_SPEC>); impl core::ops::Deref for W { type Target = crate::W<PRO_CACHE_LOCK_0_ADDR_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl core::convert::From<crate::W<PRO_CACHE_LOCK_0_ADDR_SPEC>> for W { fn from(writer: crate::W<PRO_CACHE_LOCK_0_ADDR_SPEC>) -> Self { W(writer) } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_MAX` reader - "] pub struct PRO_CACHE_LOCK_0_ADDR_MAX_R(crate::FieldReader<u8, u8>); impl PRO_CACHE_LOCK_0_ADDR_MAX_R { pub(crate) fn new(bits: u8) -> Self { PRO_CACHE_LOCK_0_ADDR_MAX_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for PRO_CACHE_LOCK_0_ADDR_MAX_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_MAX` writer - "] pub struct PRO_CACHE_LOCK_0_ADDR_MAX_W<'a> { w: &'a mut W, } impl<'a> PRO_CACHE_LOCK_0_ADDR_MAX_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 18)) | (((value as u32) & 0x0f) << 18); self.w } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_MIN` reader - "] pub struct PRO_CACHE_LOCK_0_ADDR_MIN_R(crate::FieldReader<u8, u8>); impl PRO_CACHE_LOCK_0_ADDR_MIN_R { pub(crate) fn new(bits: u8) -> Self { PRO_CACHE_LOCK_0_ADDR_MIN_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for PRO_CACHE_LOCK_0_ADDR_MIN_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_MIN` writer - "] pub struct PRO_CACHE_LOCK_0_ADDR_MIN_W<'a> { w: &'a mut W, } impl<'a> PRO_CACHE_LOCK_0_ADDR_MIN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 14)) | (((value as u32) & 0x0f) << 14); self.w } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_PRE` reader - "] pub struct PRO_CACHE_LOCK_0_ADDR_PRE_R(crate::FieldReader<u16, u16>); impl PRO_CACHE_LOCK_0_ADDR_PRE_R { pub(crate) fn new(bits: u16) -> Self { PRO_CACHE_LOCK_0_ADDR_PRE_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for PRO_CACHE_LOCK_0_ADDR_PRE_R { type Target = crate::FieldReader<u16, u16>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `PRO_CACHE_LOCK_0_ADDR_PRE` writer - "] pub struct PRO_CACHE_LOCK_0_ADDR_PRE_W<'a> { w: &'a mut W, } impl<'a> PRO_CACHE_LOCK_0_ADDR_PRE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x3fff) | ((value as u32) & 0x3fff); self.w } } impl R { #[doc = "Bits 18:21"] #[inline(always)] pub fn pro_cache_lock_0_addr_max(&self) -> PRO_CACHE_LOCK_0_ADDR_MAX_R { PRO_CACHE_LOCK_0_ADDR_MAX_R::new(((self.bits >> 18) & 0x0f) as u8) } #[doc = "Bits 14:17"] #[inline(always)] pub fn pro_cache_lock_0_addr_min(&self) -> PRO_CACHE_LOCK_0_ADDR_MIN_R { PRO_CACHE_LOCK_0_ADDR_MIN_R::new(((self.bits >> 14) & 0x0f) as u8) } #[doc = "Bits 0:13"] #[inline(always)] pub fn pro_cache_lock_0_addr_pre(&self) -> PRO_CACHE_LOCK_0_ADDR_PRE_R { PRO_CACHE_LOCK_0_ADDR_PRE_R::new((self.bits & 0x3fff) as u16) } } impl W { #[doc = "Bits 18:21"] #[inline(always)] pub fn pro_cache_lock_0_addr_max(&mut self) -> PRO_CACHE_LOCK_0_ADDR_MAX_W { PRO_CACHE_LOCK_0_ADDR_MAX_W { w: self } } #[doc = "Bits 14:17"] #[inline(always)] pub fn pro_cache_lock_0_addr_min(&mut self) -> PRO_CACHE_LOCK_0_ADDR_MIN_W { PRO_CACHE_LOCK_0_ADDR_MIN_W { w: self } } #[doc = "Bits 0:13"] #[inline(always)] pub fn pro_cache_lock_0_addr_pre(&mut self) -> PRO_CACHE_LOCK_0_ADDR_PRE_W { PRO_CACHE_LOCK_0_ADDR_PRE_W { w: self } } #[doc = "Writes raw bits to the register."] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "DPORT_PRO_CACHE_LOCK_0_ADDR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pro_cache_lock_0_addr](index.html) module"] pub struct PRO_CACHE_LOCK_0_ADDR_SPEC; impl crate::RegisterSpec for PRO_CACHE_LOCK_0_ADDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [pro_cache_lock_0_addr::R](R) reader structure"] impl crate::Readable for PRO_CACHE_LOCK_0_ADDR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [pro_cache_lock_0_addr::W](W) writer structure"] impl crate::Writable for PRO_CACHE_LOCK_0_ADDR_SPEC { type Writer = W; } #[doc = "`reset()` method sets PRO_CACHE_LOCK_0_ADDR to value 0"] impl crate::Resettable for PRO_CACHE_LOCK_0_ADDR_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }