[−][src]Module esp32::mcpwm
MCPWM
Modules
| mcmcpwm_int_clr_mcpwm_reg | MCMCPWM_INT_CLR_MCPWM_REG(i) |
| mcmcpwm_int_ena_mcpwm_reg | MCMCPWM_INT_ENA_MCPWM_REG(i) |
| mcmcpwm_int_raw_mcpwm_reg | MCMCPWM_INT_RAW_MCPWM_REG(i) |
| mcmcpwm_int_st_mcpwm_reg | MCMCPWM_INT_ST_MCPWM_REG(i) |
| mcpwm_cap_ch0_reg | MCPWM_CAP_CH0_REG(i) |
| mcpwm_cap_ch0_cfg_reg | MCPWM_CAP_CH0_CFG_REG(i) |
| mcpwm_cap_ch1_cfg_reg | MCPWM_CAP_CH1_CFG_REG(i) |
| mcpwm_cap_ch1_reg | MCPWM_CAP_CH1_REG(i) |
| mcpwm_cap_ch2_cfg_reg | MCPWM_CAP_CH2_CFG_REG(i) |
| mcpwm_cap_ch2_reg | MCPWM_CAP_CH2_REG(i) |
| mcpwm_cap_status_reg | MCPWM_CAP_STATUS_REG(i) |
| mcpwm_cap_timer_cfg_reg | MCPWM_CAP_TIMER_CFG_REG(i) |
| mcpwm_cap_timer_phase_reg | MCPWM_CAP_TIMER_PHASE_REG(i) |
| mcpwm_carrier0_cfg_reg | MCPWM_CARRIER0_CFG_REG(i) |
| mcpwm_carrier1_cfg_reg | MCPWM_CARRIER1_CFG_REG(i) |
| mcpwm_carrier2_cfg_reg | MCPWM_CARRIER2_CFG_REG(i) |
| mcpwm_clk_cfg_reg | MCPWM_CLK_CFG_REG(i) |
| mcpwm_clk_reg | MCPWM_CLK_REG(i) |
| mcpwm_dt0_cfg_reg | MCPWM_DT0_CFG_REG(i) |
| mcpwm_dt0_fed_cfg_reg | MCPWM_DT0_FED_CFG_REG(i) |
| mcpwm_dt0_red_cfg_reg | MCPWM_DT0_RED_CFG_REG(i) |
| mcpwm_dt1_cfg_reg | MCPWM_DT1_CFG_REG(i) |
| mcpwm_dt1_fed_cfg_reg | MCPWM_DT1_FED_CFG_REG(i) |
| mcpwm_dt1_red_cfg_reg | MCPWM_DT1_RED_CFG_REG(i) |
| mcpwm_dt2_cfg_reg | MCPWM_DT2_CFG_REG(i) |
| mcpwm_dt2_fed_cfg_reg | MCPWM_DT2_FED_CFG_REG(i) |
| mcpwm_dt2_red_cfg_reg | MCPWM_DT2_RED_CFG_REG(i) |
| mcpwm_fault_detect_reg | MCPWM_FAULT_DETECT_REG(i) |
| mcpwm_fh0_status_reg | MCPWM_FH0_STATUS_REG(i) |
| mcpwm_fh1_status_reg | MCPWM_FH1_STATUS_REG(i) |
| mcpwm_fh2_status_reg | MCPWM_FH2_STATUS_REG(i) |
| mcpwm_fh0_cfg0_reg | MCPWM_FH0_CFG0_REG(i) |
| mcpwm_fh0_cfg1_reg | MCPWM_FH0_CFG1_REG(i) |
| mcpwm_fh1_cfg0_reg | MCPWM_FH1_CFG0_REG(i) |
| mcpwm_fh1_cfg1_reg | MCPWM_FH1_CFG1_REG(i) |
| mcpwm_fh2_cfg0_reg | MCPWM_FH2_CFG0_REG(i) |
| mcpwm_fh2_cfg1_reg | MCPWM_FH2_CFG1_REG(i) |
| mcpwm_gen0_a_reg | MCPWM_GEN0_A_REG(i) |
| mcpwm_gen0_b_reg | MCPWM_GEN0_B_REG(i) |
| mcpwm_gen0_force_reg | MCPWM_GEN0_FORCE_REG(i) |
| mcpwm_gen0_tstmp_a_reg | MCPWM_GEN0_TSTMP_A_REG(i) |
| mcpwm_gen0_tstmp_b_reg | MCPWM_GEN0_TSTMP_B_REG(i) |
| mcpwm_gen0_stmp_cfg_reg | MCPWM_GEN0_STMP_CFG_REG(i) |
| mcpwm_gen1_stmp_cfg_reg | MCPWM_GEN1_STMP_CFG_REG(i) |
| mcpwm_gen1_tstmp_a_reg | MCPWM_GEN1_TSTMP_A_REG(i) |
| mcpwm_gen1_tstmp_b_reg | MCPWM_GEN1_TSTMP_B_REG(i) |
| mcpwm_gen1_force_reg | MCPWM_GEN1_FORCE_REG(i) |
| mcpwm_gen1_a_reg | MCPWM_GEN1_A_REG(i) |
| mcpwm_gen1_b_reg | MCPWM_GEN1_B_REG(i) |
| mcpwm_gen2_stmp_cfg_reg | MCPWM_GEN2_STMP_CFG_REG(i) |
| mcpwm_gen2_tstmp_a_reg | MCPWM_GEN2_TSTMP_A_REG(i) |
| mcpwm_gen2_tstmp_b_reg | MCPWM_GEN2_TSTMP_B_REG(i) |
| mcpwm_gen2_force_reg | MCPWM_GEN2_FORCE_REG(i) |
| mcpwm_gen2_a_reg | MCPWM_GEN2_A_REG(i) |
| mcpwm_gen2_b_reg | MCPWM_GEN2_B_REG(i) |
| mcpwm_gen0_cfg0_reg | MCPWM_GEN0_CFG0_REG(i) |
| mcpwm_gen1_cfg0_reg | MCPWM_GEN1_CFG0_REG(i) |
| mcpwm_gen2_cfg0_reg | MCPWM_GEN2_CFG0_REG(i) |
| mcpwm_operator_timersel_reg | MCPWM_OPERATOR_TIMERSEL_REG(i) |
| mcpwm_timer0_sync_reg | MCPWM_TIMER0_SYNC_REG(i) |
| mcpwm_timer0_status_reg | MCPWM_TIMER0_STATUS_REG(i) |
| mcpwm_timer1_sync_reg | MCPWM_TIMER1_SYNC_REG(i) |
| mcpwm_timer1_status_reg | MCPWM_TIMER1_STATUS_REG(i) |
| mcpwm_timer2_sync_reg | MCPWM_TIMER2_SYNC_REG(i) |
| mcpwm_timer2_status_reg | MCPWM_TIMER2_STATUS_REG(i) |
| mcpwm_timer0_cfg0_reg | MCPWM_TIMER0_CFG0_REG(i) |
| mcpwm_timer0_cfg1_reg | MCPWM_TIMER0_CFG1_REG(i) |
| mcpwm_timer1_cfg0_reg | MCPWM_TIMER1_CFG0_REG(i) |
| mcpwm_timer1_cfg1_reg | MCPWM_TIMER1_CFG1_REG(i) |
| mcpwm_timer2_cfg0_reg | MCPWM_TIMER2_CFG0_REG(i) |
| mcpwm_timer2_cfg1_reg | MCPWM_TIMER2_CFG1_REG(i) |
| mcpwm_timer_synci_cfg_reg | MCPWM_TIMER_SYNCI_CFG_REG(i) |
| mcpwm_update_cfg_reg | MCPWM_UPDATE_CFG_REG(i) |
| mcpwm_version_reg | MCPWM_VERSION_REG(i) |
Structs
| RegisterBlock | Register block |
Type Definitions
| MCMCPWM_INT_CLR_MCPWM_REG | MCMCPWM_INT_CLR_MCPWM_REG(i) |
| MCMCPWM_INT_ENA_MCPWM_REG | MCMCPWM_INT_ENA_MCPWM_REG(i) |
| MCMCPWM_INT_RAW_MCPWM_REG | MCMCPWM_INT_RAW_MCPWM_REG(i) |
| MCMCPWM_INT_ST_MCPWM_REG | MCMCPWM_INT_ST_MCPWM_REG(i) |
| MCPWM_CAP_CH0_REG | MCPWM_CAP_CH0_REG(i) |
| MCPWM_CAP_CH0_CFG_REG | MCPWM_CAP_CH0_CFG_REG(i) |
| MCPWM_CAP_CH1_CFG_REG | MCPWM_CAP_CH1_CFG_REG(i) |
| MCPWM_CAP_CH1_REG | MCPWM_CAP_CH1_REG(i) |
| MCPWM_CAP_CH2_CFG_REG | MCPWM_CAP_CH2_CFG_REG(i) |
| MCPWM_CAP_CH2_REG | MCPWM_CAP_CH2_REG(i) |
| MCPWM_CAP_STATUS_REG | MCPWM_CAP_STATUS_REG(i) |
| MCPWM_CAP_TIMER_CFG_REG | MCPWM_CAP_TIMER_CFG_REG(i) |
| MCPWM_CAP_TIMER_PHASE_REG | MCPWM_CAP_TIMER_PHASE_REG(i) |
| MCPWM_CARRIER0_CFG_REG | MCPWM_CARRIER0_CFG_REG(i) |
| MCPWM_CARRIER1_CFG_REG | MCPWM_CARRIER1_CFG_REG(i) |
| MCPWM_CARRIER2_CFG_REG | MCPWM_CARRIER2_CFG_REG(i) |
| MCPWM_CLK_CFG_REG | MCPWM_CLK_CFG_REG(i) |
| MCPWM_CLK_REG | MCPWM_CLK_REG(i) |
| MCPWM_DT0_CFG_REG | MCPWM_DT0_CFG_REG(i) |
| MCPWM_DT0_FED_CFG_REG | MCPWM_DT0_FED_CFG_REG(i) |
| MCPWM_DT0_RED_CFG_REG | MCPWM_DT0_RED_CFG_REG(i) |
| MCPWM_DT1_CFG_REG | MCPWM_DT1_CFG_REG(i) |
| MCPWM_DT1_FED_CFG_REG | MCPWM_DT1_FED_CFG_REG(i) |
| MCPWM_DT1_RED_CFG_REG | MCPWM_DT1_RED_CFG_REG(i) |
| MCPWM_DT2_CFG_REG | MCPWM_DT2_CFG_REG(i) |
| MCPWM_DT2_FED_CFG_REG | MCPWM_DT2_FED_CFG_REG(i) |
| MCPWM_DT2_RED_CFG_REG | MCPWM_DT2_RED_CFG_REG(i) |
| MCPWM_FAULT_DETECT_REG | MCPWM_FAULT_DETECT_REG(i) |
| MCPWM_FH0_STATUS_REG | MCPWM_FH0_STATUS_REG(i) |
| MCPWM_FH1_STATUS_REG | MCPWM_FH1_STATUS_REG(i) |
| MCPWM_FH2_STATUS_REG | MCPWM_FH2_STATUS_REG(i) |
| MCPWM_FH0_CFG0_REG | MCPWM_FH0_CFG0_REG(i) |
| MCPWM_FH0_CFG1_REG | MCPWM_FH0_CFG1_REG(i) |
| MCPWM_FH1_CFG0_REG | MCPWM_FH1_CFG0_REG(i) |
| MCPWM_FH1_CFG1_REG | MCPWM_FH1_CFG1_REG(i) |
| MCPWM_FH2_CFG0_REG | MCPWM_FH2_CFG0_REG(i) |
| MCPWM_FH2_CFG1_REG | MCPWM_FH2_CFG1_REG(i) |
| MCPWM_GEN0_A_REG | MCPWM_GEN0_A_REG(i) |
| MCPWM_GEN0_B_REG | MCPWM_GEN0_B_REG(i) |
| MCPWM_GEN0_FORCE_REG | MCPWM_GEN0_FORCE_REG(i) |
| MCPWM_GEN0_TSTMP_A_REG | MCPWM_GEN0_TSTMP_A_REG(i) |
| MCPWM_GEN0_TSTMP_B_REG | MCPWM_GEN0_TSTMP_B_REG(i) |
| MCPWM_GEN0_STMP_CFG_REG | MCPWM_GEN0_STMP_CFG_REG(i) |
| MCPWM_GEN1_STMP_CFG_REG | MCPWM_GEN1_STMP_CFG_REG(i) |
| MCPWM_GEN1_TSTMP_A_REG | MCPWM_GEN1_TSTMP_A_REG(i) |
| MCPWM_GEN1_TSTMP_B_REG | MCPWM_GEN1_TSTMP_B_REG(i) |
| MCPWM_GEN1_FORCE_REG | MCPWM_GEN1_FORCE_REG(i) |
| MCPWM_GEN1_A_REG | MCPWM_GEN1_A_REG(i) |
| MCPWM_GEN1_B_REG | MCPWM_GEN1_B_REG(i) |
| MCPWM_GEN2_STMP_CFG_REG | MCPWM_GEN2_STMP_CFG_REG(i) |
| MCPWM_GEN2_TSTMP_A_REG | MCPWM_GEN2_TSTMP_A_REG(i) |
| MCPWM_GEN2_TSTMP_B_REG | MCPWM_GEN2_TSTMP_B_REG(i) |
| MCPWM_GEN2_FORCE_REG | MCPWM_GEN2_FORCE_REG(i) |
| MCPWM_GEN2_A_REG | MCPWM_GEN2_A_REG(i) |
| MCPWM_GEN2_B_REG | MCPWM_GEN2_B_REG(i) |
| MCPWM_GEN0_CFG0_REG | MCPWM_GEN0_CFG0_REG(i) |
| MCPWM_GEN1_CFG0_REG | MCPWM_GEN1_CFG0_REG(i) |
| MCPWM_GEN2_CFG0_REG | MCPWM_GEN2_CFG0_REG(i) |
| MCPWM_OPERATOR_TIMERSEL_REG | MCPWM_OPERATOR_TIMERSEL_REG(i) |
| MCPWM_TIMER0_SYNC_REG | MCPWM_TIMER0_SYNC_REG(i) |
| MCPWM_TIMER0_STATUS_REG | MCPWM_TIMER0_STATUS_REG(i) |
| MCPWM_TIMER1_SYNC_REG | MCPWM_TIMER1_SYNC_REG(i) |
| MCPWM_TIMER1_STATUS_REG | MCPWM_TIMER1_STATUS_REG(i) |
| MCPWM_TIMER2_SYNC_REG | MCPWM_TIMER2_SYNC_REG(i) |
| MCPWM_TIMER2_STATUS_REG | MCPWM_TIMER2_STATUS_REG(i) |
| MCPWM_TIMER0_CFG0_REG | MCPWM_TIMER0_CFG0_REG(i) |
| MCPWM_TIMER0_CFG1_REG | MCPWM_TIMER0_CFG1_REG(i) |
| MCPWM_TIMER1_CFG0_REG | MCPWM_TIMER1_CFG0_REG(i) |
| MCPWM_TIMER1_CFG1_REG | MCPWM_TIMER1_CFG1_REG(i) |
| MCPWM_TIMER2_CFG0_REG | MCPWM_TIMER2_CFG0_REG(i) |
| MCPWM_TIMER2_CFG1_REG | MCPWM_TIMER2_CFG1_REG(i) |
| MCPWM_TIMER_SYNCI_CFG_REG | MCPWM_TIMER_SYNCI_CFG_REG(i) |
| MCPWM_UPDATE_CFG_REG | MCPWM_UPDATE_CFG_REG(i) |
| MCPWM_VERSION_REG | MCPWM_VERSION_REG(i) |