[−][src]Module esp32::dport
DPORT
Modules
| dport_access_check_reg | DPORT_ACCESS_CHECK_REG |
| dport_ahb_lite_mask_reg | DPORT_AHB_LITE_MASK_REG |
| dport_ahb_mpu_table_0_reg | DPORT_AHB_MPU_TABLE_0_REG |
| dport_ahb_mpu_table_1_reg | DPORT_AHB_MPU_TABLE_1_REG |
| dport_ahblite_mpu_table_apb_ctrl_reg | DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG |
| dport_ahblite_mpu_table_bb_reg | DPORT_AHBLITE_MPU_TABLE_BB_REG |
| dport_ahblite_mpu_table_bt_buffer_reg | DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG |
| dport_ahblite_mpu_table_bt_reg | DPORT_AHBLITE_MPU_TABLE_BT_REG |
| dport_ahblite_mpu_table_btmac_reg | DPORT_AHBLITE_MPU_TABLE_BTMAC_REG |
| dport_ahblite_mpu_table_can_reg | DPORT_AHBLITE_MPU_TABLE_CAN_REG |
| dport_ahblite_mpu_table_efuse_reg | DPORT_AHBLITE_MPU_TABLE_EFUSE_REG |
| dport_ahblite_mpu_table_emac_reg | DPORT_AHBLITE_MPU_TABLE_EMAC_REG |
| dport_ahblite_mpu_table_fe2_reg | DPORT_AHBLITE_MPU_TABLE_FE2_REG |
| dport_ahblite_mpu_table_fe_reg | DPORT_AHBLITE_MPU_TABLE_FE_REG |
| dport_ahblite_mpu_table_gpio_reg | DPORT_AHBLITE_MPU_TABLE_GPIO_REG |
| dport_ahblite_mpu_table_hinf_reg | DPORT_AHBLITE_MPU_TABLE_HINF_REG |
| dport_ahblite_mpu_table_i2c_reg | DPORT_AHBLITE_MPU_TABLE_I2C_REG |
| dport_ahblite_mpu_table_i2c_ext0_reg | DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG |
| dport_ahblite_mpu_table_i2c_ext1_reg | DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG |
| dport_ahblite_mpu_table_i2s0_reg | DPORT_AHBLITE_MPU_TABLE_I2S0_REG |
| dport_ahblite_mpu_table_i2s1_reg | DPORT_AHBLITE_MPU_TABLE_I2S1_REG |
| dport_ahblite_mpu_table_io_mux_reg | DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG |
| dport_ahblite_mpu_table_ledc_reg | DPORT_AHBLITE_MPU_TABLE_LEDC_REG |
| dport_ahblite_mpu_table_misc_reg | DPORT_AHBLITE_MPU_TABLE_MISC_REG |
| dport_ahblite_mpu_table_pcnt_reg | DPORT_AHBLITE_MPU_TABLE_PCNT_REG |
| dport_ahblite_mpu_table_pwm0_reg | DPORT_AHBLITE_MPU_TABLE_PWM0_REG |
| dport_ahblite_mpu_table_pwm1_reg | DPORT_AHBLITE_MPU_TABLE_PWM1_REG |
| dport_ahblite_mpu_table_pwm2_reg | DPORT_AHBLITE_MPU_TABLE_PWM2_REG |
| dport_ahblite_mpu_table_pwm3_reg | DPORT_AHBLITE_MPU_TABLE_PWM3_REG |
| dport_ahblite_mpu_table_pwr_reg | DPORT_AHBLITE_MPU_TABLE_PWR_REG |
| dport_ahblite_mpu_table_rmt_reg | DPORT_AHBLITE_MPU_TABLE_RMT_REG |
| dport_ahblite_mpu_table_rtc_reg | DPORT_AHBLITE_MPU_TABLE_RTC_REG |
| dport_ahblite_mpu_table_rwbt_reg | DPORT_AHBLITE_MPU_TABLE_RWBT_REG |
| dport_ahblite_mpu_table_sdio_host_reg | DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG |
| dport_ahblite_mpu_table_slc_reg | DPORT_AHBLITE_MPU_TABLE_SLC_REG |
| dport_ahblite_mpu_table_slchost_reg | DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG |
| dport_ahblite_mpu_table_spi0_reg | DPORT_AHBLITE_MPU_TABLE_SPI0_REG |
| dport_ahblite_mpu_table_spi1_reg | DPORT_AHBLITE_MPU_TABLE_SPI1_REG |
| dport_ahblite_mpu_table_spi2_reg | DPORT_AHBLITE_MPU_TABLE_SPI2_REG |
| dport_ahblite_mpu_table_spi3_reg | DPORT_AHBLITE_MPU_TABLE_SPI3_REG |
| dport_ahblite_mpu_table_spi_encrypt_reg | DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG |
| dport_ahblite_mpu_table_timer_reg | DPORT_AHBLITE_MPU_TABLE_TIMER_REG |
| dport_ahblite_mpu_table_timergroup1_reg | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG |
| dport_ahblite_mpu_table_timergroup_reg | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG |
| dport_ahblite_mpu_table_uart1_reg | DPORT_AHBLITE_MPU_TABLE_UART1_REG |
| dport_ahblite_mpu_table_uart2_reg | DPORT_AHBLITE_MPU_TABLE_UART2_REG |
| dport_ahblite_mpu_table_uart_reg | DPORT_AHBLITE_MPU_TABLE_UART_REG |
| dport_ahblite_mpu_table_uhci0_reg | DPORT_AHBLITE_MPU_TABLE_UHCI0_REG |
| dport_ahblite_mpu_table_uhci1_reg | DPORT_AHBLITE_MPU_TABLE_UHCI1_REG |
| dport_ahblite_mpu_table_wdg_reg | DPORT_AHBLITE_MPU_TABLE_WDG_REG |
| dport_ahblite_mpu_table_wifimac_reg | DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG |
| dport_app_bb_int_map_reg | DPORT_APP_BB_INT_MAP_REG |
| dport_app_boot_remap_ctrl_reg | DPORT_APP_BOOT_REMAP_CTRL_REG |
| dport_app_bt_bb_int_map_reg | DPORT_APP_BT_BB_INT_MAP_REG |
| dport_app_bt_bb_nmi_map_reg | DPORT_APP_BT_BB_NMI_MAP_REG |
| dport_app_bt_mac_int_map_reg | DPORT_APP_BT_MAC_INT_MAP_REG |
| dport_app_cache_ctrl1_reg | DPORT_APP_CACHE_CTRL1_REG |
| dport_app_cache_ctrl_reg | DPORT_APP_CACHE_CTRL_REG |
| dport_app_cache_ia_int_map_reg | DPORT_APP_CACHE_IA_INT_MAP_REG |
| dport_app_cache_lock_0_addr_reg | DPORT_APP_CACHE_LOCK_0_ADDR_REG |
| dport_app_cache_lock_1_addr_reg | DPORT_APP_CACHE_LOCK_1_ADDR_REG |
| dport_app_cache_lock_2_addr_reg | DPORT_APP_CACHE_LOCK_2_ADDR_REG |
| dport_app_cache_lock_3_addr_reg | DPORT_APP_CACHE_LOCK_3_ADDR_REG |
| dport_app_can_int_map_reg | DPORT_APP_CAN_INT_MAP_REG |
| dport_app_cpu_intr_from_cpu_0_map_reg | DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG |
| dport_app_cpu_intr_from_cpu_1_map_reg | DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG |
| dport_app_cpu_intr_from_cpu_2_map_reg | DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG |
| dport_app_cpu_intr_from_cpu_3_map_reg | DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG |
| dport_app_cpu_record_ctrl_reg | DPORT_APP_CPU_RECORD_CTRL_REG |
| dport_app_cpu_record_pdebugdata_reg | DPORT_APP_CPU_RECORD_PDEBUGDATA_REG |
| dport_app_cpu_record_pdebuginst_reg | DPORT_APP_CPU_RECORD_PDEBUGINST_REG |
| dport_app_cpu_record_pdebugls0stat_reg | DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG |
| dport_app_cpu_record_pdebugls0addr_reg | DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG |
| dport_app_cpu_record_pdebugls0data_reg | DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG |
| dport_app_cpu_record_pdebugpc_reg | DPORT_APP_CPU_RECORD_PDEBUGPC_REG |
| dport_app_cpu_record_pdebugstatus_reg | DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG |
| dport_app_cpu_record_pid_reg | DPORT_APP_CPU_RECORD_PID_REG |
| dport_app_cpu_record_status_reg | DPORT_APP_CPU_RECORD_STATUS_REG |
| dport_app_dcache_dbug0_reg | DPORT_APP_DCACHE_DBUG0_REG |
| dport_app_dcache_dbug1_reg | DPORT_APP_DCACHE_DBUG1_REG |
| dport_app_dcache_dbug2_reg | DPORT_APP_DCACHE_DBUG2_REG |
| dport_app_dcache_dbug3_reg | DPORT_APP_DCACHE_DBUG3_REG |
| dport_app_dcache_dbug4_reg | DPORT_APP_DCACHE_DBUG4_REG |
| dport_app_dcache_dbug5_reg | DPORT_APP_DCACHE_DBUG5_REG |
| dport_app_dcache_dbug6_reg | DPORT_APP_DCACHE_DBUG6_REG |
| dport_app_dcache_dbug7_reg | DPORT_APP_DCACHE_DBUG7_REG |
| dport_app_dcache_dbug8_reg | DPORT_APP_DCACHE_DBUG8_REG |
| dport_app_dcache_dbug9_reg | DPORT_APP_DCACHE_DBUG9_REG |
| dport_app_dport_apb_mask0_reg | DPORT_APP_DPORT_APB_MASK0_REG |
| dport_app_dport_apb_mask1_reg | DPORT_APP_DPORT_APB_MASK1_REG |
| dport_app_efuse_int_map_reg | DPORT_APP_EFUSE_INT_MAP_REG |
| dport_app_emac_int_map_reg | DPORT_APP_EMAC_INT_MAP_REG |
| dport_app_gpio_interrupt_map_reg | DPORT_APP_GPIO_INTERRUPT_MAP_REG |
| dport_app_gpio_interrupt_nmi_map_reg | DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG |
| dport_app_i2c_ext0_intr_map_reg | DPORT_APP_I2C_EXT0_INTR_MAP_REG |
| dport_app_i2c_ext1_intr_map_reg | DPORT_APP_I2C_EXT1_INTR_MAP_REG |
| dport_app_i2s0_int_map_reg | DPORT_APP_I2S0_INT_MAP_REG |
| dport_app_i2s1_int_map_reg | DPORT_APP_I2S1_INT_MAP_REG |
| dport_app_intr_status_0_reg | DPORT_APP_INTR_STATUS_0_REG |
| dport_app_intr_status_1_reg | DPORT_APP_INTR_STATUS_1_REG |
| dport_app_intr_status_2_reg | DPORT_APP_INTR_STATUS_2_REG |
| dport_app_intrusion_ctrl_reg | DPORT_APP_INTRUSION_CTRL_REG |
| dport_app_intrusion_status_reg | DPORT_APP_INTRUSION_STATUS_REG |
| dport_app_ledc_int_map_reg | DPORT_APP_LEDC_INT_MAP_REG |
| dport_app_mac_intr_map_reg | DPORT_APP_MAC_INTR_MAP_REG |
| dport_app_mac_nmi_map_reg | DPORT_APP_MAC_NMI_MAP_REG |
| dport_app_mmu_ia_int_map_reg | DPORT_APP_MMU_IA_INT_MAP_REG |
| dport_app_mpu_ia_int_map_reg | DPORT_APP_MPU_IA_INT_MAP_REG |
| dport_app_pcnt_intr_map_reg | DPORT_APP_PCNT_INTR_MAP_REG |
| dport_app_pwm0_intr_map_reg | DPORT_APP_PWM0_INTR_MAP_REG |
| dport_app_pwm1_intr_map_reg | DPORT_APP_PWM1_INTR_MAP_REG |
| dport_app_pwm2_intr_map_reg | DPORT_APP_PWM2_INTR_MAP_REG |
| dport_app_pwm3_intr_map_reg | DPORT_APP_PWM3_INTR_MAP_REG |
| dport_app_rmt_intr_map_reg | DPORT_APP_RMT_INTR_MAP_REG |
| dport_app_rsa_intr_map_reg | DPORT_APP_RSA_INTR_MAP_REG |
| dport_app_rtc_core_intr_map_reg | DPORT_APP_RTC_CORE_INTR_MAP_REG |
| dport_app_rwble_irq_map_reg | DPORT_APP_RWBLE_IRQ_MAP_REG |
| dport_app_rwble_nmi_map_reg | DPORT_APP_RWBLE_NMI_MAP_REG |
| dport_app_rwbt_irq_map_reg | DPORT_APP_RWBT_IRQ_MAP_REG |
| dport_app_rwbt_nmi_map_reg | DPORT_APP_RWBT_NMI_MAP_REG |
| dport_app_sdio_host_interrupt_map_reg | DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG |
| dport_app_slc0_intr_map_reg | DPORT_APP_SLC0_INTR_MAP_REG |
| dport_app_slc1_intr_map_reg | DPORT_APP_SLC1_INTR_MAP_REG |
| dport_app_spi1_dma_int_map_reg | DPORT_APP_SPI1_DMA_INT_MAP_REG |
| dport_app_spi2_dma_int_map_reg | DPORT_APP_SPI2_DMA_INT_MAP_REG |
| dport_app_spi3_dma_int_map_reg | DPORT_APP_SPI3_DMA_INT_MAP_REG |
| dport_app_spi_intr_0_map_reg | DPORT_APP_SPI_INTR_0_MAP_REG |
| dport_app_spi_intr_1_map_reg | DPORT_APP_SPI_INTR_1_MAP_REG |
| dport_app_spi_intr_2_map_reg | DPORT_APP_SPI_INTR_2_MAP_REG |
| dport_app_spi_intr_3_map_reg | DPORT_APP_SPI_INTR_3_MAP_REG |
| dport_app_tg1_wdt_level_int_map_reg | DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG |
| dport_app_tg1_lact_level_int_map_reg | DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG |
| dport_app_tg1_wdt_edge_int_map_reg | DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG |
| dport_app_tg1_lact_edge_int_map_reg | DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG |
| dport_app_tg1_t0_edge_int_map_reg | DPORT_APP_TG1_T0_EDGE_INT_MAP_REG |
| dport_app_tg1_t0_level_int_map_reg | DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG |
| dport_app_tg1_t1_level_int_map_reg | DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG |
| dport_app_tg1_t1_edge_int_map_reg | DPORT_APP_TG1_T1_EDGE_INT_MAP_REG |
| dport_app_tg_lact_edge_int_map_reg | DPORT_APP_TG_LACT_EDGE_INT_MAP_REG |
| dport_app_tg_lact_level_int_map_reg | DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG |
| dport_app_tg_t0_edge_int_map_reg | DPORT_APP_TG_T0_EDGE_INT_MAP_REG |
| dport_app_tg_t0_level_int_map_reg | DPORT_APP_TG_T0_LEVEL_INT_MAP_REG |
| dport_app_tg_t1_level_int_map_reg | DPORT_APP_TG_T1_LEVEL_INT_MAP_REG |
| dport_app_tg_t1_edge_int_map_reg | DPORT_APP_TG_T1_EDGE_INT_MAP_REG |
| dport_app_tg_wdt_edge_int_map_reg | DPORT_APP_TG_WDT_EDGE_INT_MAP_REG |
| dport_app_tg_wdt_level_int_map_reg | DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG |
| dport_app_timer_int1_map_reg | DPORT_APP_TIMER_INT1_MAP_REG |
| dport_app_timer_int2_map_reg | DPORT_APP_TIMER_INT2_MAP_REG |
| dport_app_tracemem_ena_reg | DPORT_APP_TRACEMEM_ENA_REG |
| dport_app_uart1_intr_map_reg | DPORT_APP_UART1_INTR_MAP_REG |
| dport_app_uart2_intr_map_reg | DPORT_APP_UART2_INTR_MAP_REG |
| dport_app_uart_intr_map_reg | DPORT_APP_UART_INTR_MAP_REG |
| dport_app_uhci0_intr_map_reg | DPORT_APP_UHCI0_INTR_MAP_REG |
| dport_app_uhci1_intr_map_reg | DPORT_APP_UHCI1_INTR_MAP_REG |
| dport_app_vecbase_ctrl_reg | DPORT_APP_VECBASE_CTRL_REG |
| dport_app_vecbase_set_reg | DPORT_APP_VECBASE_SET_REG |
| dport_app_wdg_int_map_reg | DPORT_APP_WDG_INT_MAP_REG |
| dport_appcpu_ctrl_a_reg | DPORT_APPCPU_CTRL_A_REG |
| dport_appcpu_ctrl_b_reg | DPORT_APPCPU_CTRL_B_REG |
| dport_appcpu_ctrl_c_reg | DPORT_APPCPU_CTRL_C_REG |
| dport_appcpu_ctrl_d_reg | DPORT_APPCPU_CTRL_D_REG |
| dport_bt_lpck_div_frac_reg | DPORT_BT_LPCK_DIV_FRAC_REG |
| dport_bt_lpck_div_int_reg | DPORT_BT_LPCK_DIV_INT_REG |
| dport_cache_ia_int_en_reg | DPORT_CACHE_IA_INT_EN_REG |
| dport_cache_mux_mode_reg | DPORT_CACHE_MUX_MODE_REG |
| dport_core_rst_en_reg | DPORT_CORE_RST_EN_REG |
| dport_cpu_intr_from_cpu_0_reg | DPORT_CPU_INTR_FROM_CPU_0_REG |
| dport_cpu_intr_from_cpu_1_reg | DPORT_CPU_INTR_FROM_CPU_1_REG |
| dport_cpu_intr_from_cpu_2_reg | DPORT_CPU_INTR_FROM_CPU_2_REG |
| dport_cpu_intr_from_cpu_3_reg | DPORT_CPU_INTR_FROM_CPU_3_REG |
| dport_cpu_per_conf_reg | DPORT_CPU_PER_CONF_REG |
| dport_date_reg | DPORT_DATE_REG |
| dport_dmmu_page_mode_reg | DPORT_DMMU_PAGE_MODE_REG |
| dport_dmmu_table0_reg | DPORT_DMMU_TABLE0_REG |
| dport_dmmu_table1_reg | DPORT_DMMU_TABLE1_REG |
| dport_dmmu_table2_reg | DPORT_DMMU_TABLE2_REG |
| dport_dmmu_table3_reg | DPORT_DMMU_TABLE3_REG |
| dport_dmmu_table4_reg | DPORT_DMMU_TABLE4_REG |
| dport_dmmu_table5_reg | DPORT_DMMU_TABLE5_REG |
| dport_dmmu_table6_reg | DPORT_DMMU_TABLE6_REG |
| dport_dmmu_table7_reg | DPORT_DMMU_TABLE7_REG |
| dport_dmmu_table8_reg | DPORT_DMMU_TABLE8_REG |
| dport_dmmu_table9_reg | DPORT_DMMU_TABLE9_REG |
| dport_dmmu_table10_reg | DPORT_DMMU_TABLE10_REG |
| dport_dmmu_table11_reg | DPORT_DMMU_TABLE11_REG |
| dport_dmmu_table12_reg | DPORT_DMMU_TABLE12_REG |
| dport_dmmu_table13_reg | DPORT_DMMU_TABLE13_REG |
| dport_dmmu_table14_reg | DPORT_DMMU_TABLE14_REG |
| dport_dmmu_table15_reg | DPORT_DMMU_TABLE15_REG |
| dport_front_end_mem_pd_reg | DPORT_FRONT_END_MEM_PD_REG |
| dport_host_inf_sel_reg | DPORT_HOST_INF_SEL_REG |
| dport_immu_page_mode_reg | DPORT_IMMU_PAGE_MODE_REG |
| dport_immu_table0_reg | DPORT_IMMU_TABLE0_REG |
| dport_immu_table1_reg | DPORT_IMMU_TABLE1_REG |
| dport_immu_table2_reg | DPORT_IMMU_TABLE2_REG |
| dport_immu_table3_reg | DPORT_IMMU_TABLE3_REG |
| dport_immu_table4_reg | DPORT_IMMU_TABLE4_REG |
| dport_immu_table5_reg | DPORT_IMMU_TABLE5_REG |
| dport_immu_table6_reg | DPORT_IMMU_TABLE6_REG |
| dport_immu_table7_reg | DPORT_IMMU_TABLE7_REG |
| dport_immu_table8_reg | DPORT_IMMU_TABLE8_REG |
| dport_immu_table9_reg | DPORT_IMMU_TABLE9_REG |
| dport_immu_table10_reg | DPORT_IMMU_TABLE10_REG |
| dport_immu_table11_reg | DPORT_IMMU_TABLE11_REG |
| dport_immu_table12_reg | DPORT_IMMU_TABLE12_REG |
| dport_immu_table13_reg | DPORT_IMMU_TABLE13_REG |
| dport_immu_table14_reg | DPORT_IMMU_TABLE14_REG |
| dport_immu_table15_reg | DPORT_IMMU_TABLE15_REG |
| dport_iram_dram_ahb_sel_reg | DPORT_IRAM_DRAM_AHB_SEL_REG |
| dport_mem_access_dbug0_reg | DPORT_MEM_ACCESS_DBUG0_REG |
| dport_mem_access_dbug1_reg | DPORT_MEM_ACCESS_DBUG1_REG |
| dport_mem_pd_mask_reg | DPORT_MEM_PD_MASK_REG |
| dport_mmu_ia_int_en_reg | DPORT_MMU_IA_INT_EN_REG |
| dport_mpu_ia_int_en_reg | DPORT_MPU_IA_INT_EN_REG |
| dport_peri_clk_en_reg | DPORT_PERI_CLK_EN_REG |
| dport_peri_rst_en_reg | DPORT_PERI_RST_EN_REG |
| dport_perip_clk_en_reg | DPORT_PERIP_CLK_EN_REG |
| dport_perip_rst_en_reg | DPORT_PERIP_RST_EN_REG |
| dport_pro_bb_int_map_reg | DPORT_PRO_BB_INT_MAP_REG |
| dport_pro_boot_remap_ctrl_reg | DPORT_PRO_BOOT_REMAP_CTRL_REG |
| dport_pro_bt_bb_int_map_reg | DPORT_PRO_BT_BB_INT_MAP_REG |
| dport_pro_bt_bb_nmi_map_reg | DPORT_PRO_BT_BB_NMI_MAP_REG |
| dport_pro_bt_mac_int_map_reg | DPORT_PRO_BT_MAC_INT_MAP_REG |
| dport_pro_cache_ctrl1_reg | DPORT_PRO_CACHE_CTRL1_REG |
| dport_pro_cache_ctrl_reg | DPORT_PRO_CACHE_CTRL_REG |
| dport_pro_cache_ia_int_map_reg | DPORT_PRO_CACHE_IA_INT_MAP_REG |
| dport_pro_cache_lock_0_addr_reg | DPORT_PRO_CACHE_LOCK_0_ADDR_REG |
| dport_pro_cache_lock_1_addr_reg | DPORT_PRO_CACHE_LOCK_1_ADDR_REG |
| dport_pro_cache_lock_2_addr_reg | DPORT_PRO_CACHE_LOCK_2_ADDR_REG |
| dport_pro_cache_lock_3_addr_reg | DPORT_PRO_CACHE_LOCK_3_ADDR_REG |
| dport_pro_can_int_map_reg | DPORT_PRO_CAN_INT_MAP_REG |
| dport_pro_cpu_intr_from_cpu_0_map_reg | DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG |
| dport_pro_cpu_intr_from_cpu_1_map_reg | DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG |
| dport_pro_cpu_intr_from_cpu_2_map_reg | DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG |
| dport_pro_cpu_intr_from_cpu_3_map_reg | DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG |
| dport_pro_cpu_record_ctrl_reg | DPORT_PRO_CPU_RECORD_CTRL_REG |
| dport_pro_cpu_record_pdebugdata_reg | DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG |
| dport_pro_cpu_record_pdebuginst_reg | DPORT_PRO_CPU_RECORD_PDEBUGINST_REG |
| dport_pro_cpu_record_pdebugls0stat_reg | DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG |
| dport_pro_cpu_record_pdebugls0addr_reg | DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG |
| dport_pro_cpu_record_pdebugls0data_reg | DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG |
| dport_pro_cpu_record_pdebugpc_reg | DPORT_PRO_CPU_RECORD_PDEBUGPC_REG |
| dport_pro_cpu_record_pdebugstatus_reg | DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG |
| dport_pro_cpu_record_pid_reg | DPORT_PRO_CPU_RECORD_PID_REG |
| dport_pro_cpu_record_status_reg | DPORT_PRO_CPU_RECORD_STATUS_REG |
| dport_pro_dcache_dbug0_reg | DPORT_PRO_DCACHE_DBUG0_REG |
| dport_pro_dcache_dbug1_reg | DPORT_PRO_DCACHE_DBUG1_REG |
| dport_pro_dcache_dbug2_reg | DPORT_PRO_DCACHE_DBUG2_REG |
| dport_pro_dcache_dbug3_reg | DPORT_PRO_DCACHE_DBUG3_REG |
| dport_pro_dcache_dbug4_reg | DPORT_PRO_DCACHE_DBUG4_REG |
| dport_pro_dcache_dbug5_reg | DPORT_PRO_DCACHE_DBUG5_REG |
| dport_pro_dcache_dbug6_reg | DPORT_PRO_DCACHE_DBUG6_REG |
| dport_pro_dcache_dbug7_reg | DPORT_PRO_DCACHE_DBUG7_REG |
| dport_pro_dcache_dbug8_reg | DPORT_PRO_DCACHE_DBUG8_REG |
| dport_pro_dcache_dbug9_reg | DPORT_PRO_DCACHE_DBUG9_REG |
| dport_pro_dport_apb_mask0_reg | DPORT_PRO_DPORT_APB_MASK0_REG |
| dport_pro_dport_apb_mask1_reg | DPORT_PRO_DPORT_APB_MASK1_REG |
| dport_pro_efuse_int_map_reg | DPORT_PRO_EFUSE_INT_MAP_REG |
| dport_pro_emac_int_map_reg | DPORT_PRO_EMAC_INT_MAP_REG |
| dport_pro_gpio_interrupt_map_reg | DPORT_PRO_GPIO_INTERRUPT_MAP_REG |
| dport_pro_gpio_interrupt_nmi_map_reg | DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG |
| dport_pro_i2c_ext0_intr_map_reg | DPORT_PRO_I2C_EXT0_INTR_MAP_REG |
| dport_pro_i2c_ext1_intr_map_reg | DPORT_PRO_I2C_EXT1_INTR_MAP_REG |
| dport_pro_i2s0_int_map_reg | DPORT_PRO_I2S0_INT_MAP_REG |
| dport_pro_i2s1_int_map_reg | DPORT_PRO_I2S1_INT_MAP_REG |
| dport_pro_intr_status_0_reg | DPORT_PRO_INTR_STATUS_0_REG |
| dport_pro_intr_status_1_reg | DPORT_PRO_INTR_STATUS_1_REG |
| dport_pro_intr_status_2_reg | DPORT_PRO_INTR_STATUS_2_REG |
| dport_pro_intrusion_ctrl_reg | DPORT_PRO_INTRUSION_CTRL_REG |
| dport_pro_intrusion_status_reg | DPORT_PRO_INTRUSION_STATUS_REG |
| dport_pro_ledc_int_map_reg | DPORT_PRO_LEDC_INT_MAP_REG |
| dport_pro_mac_intr_map_reg | DPORT_PRO_MAC_INTR_MAP_REG |
| dport_pro_mac_nmi_map_reg | DPORT_PRO_MAC_NMI_MAP_REG |
| dport_pro_mmu_ia_int_map_reg | DPORT_PRO_MMU_IA_INT_MAP_REG |
| dport_pro_mpu_ia_int_map_reg | DPORT_PRO_MPU_IA_INT_MAP_REG |
| dport_pro_pcnt_intr_map_reg | DPORT_PRO_PCNT_INTR_MAP_REG |
| dport_pro_pwm0_intr_map_reg | DPORT_PRO_PWM0_INTR_MAP_REG |
| dport_pro_pwm1_intr_map_reg | DPORT_PRO_PWM1_INTR_MAP_REG |
| dport_pro_pwm2_intr_map_reg | DPORT_PRO_PWM2_INTR_MAP_REG |
| dport_pro_pwm3_intr_map_reg | DPORT_PRO_PWM3_INTR_MAP_REG |
| dport_pro_rmt_intr_map_reg | DPORT_PRO_RMT_INTR_MAP_REG |
| dport_pro_rsa_intr_map_reg | DPORT_PRO_RSA_INTR_MAP_REG |
| dport_pro_rtc_core_intr_map_reg | DPORT_PRO_RTC_CORE_INTR_MAP_REG |
| dport_pro_rwble_irq_map_reg | DPORT_PRO_RWBLE_IRQ_MAP_REG |
| dport_pro_rwble_nmi_map_reg | DPORT_PRO_RWBLE_NMI_MAP_REG |
| dport_pro_rwbt_irq_map_reg | DPORT_PRO_RWBT_IRQ_MAP_REG |
| dport_pro_rwbt_nmi_map_reg | DPORT_PRO_RWBT_NMI_MAP_REG |
| dport_pro_sdio_host_interrupt_map_reg | DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG |
| dport_pro_slc0_intr_map_reg | DPORT_PRO_SLC0_INTR_MAP_REG |
| dport_pro_slc1_intr_map_reg | DPORT_PRO_SLC1_INTR_MAP_REG |
| dport_pro_spi1_dma_int_map_reg | DPORT_PRO_SPI1_DMA_INT_MAP_REG |
| dport_pro_spi2_dma_int_map_reg | DPORT_PRO_SPI2_DMA_INT_MAP_REG |
| dport_pro_spi3_dma_int_map_reg | DPORT_PRO_SPI3_DMA_INT_MAP_REG |
| dport_pro_spi_intr_0_map_reg | DPORT_PRO_SPI_INTR_0_MAP_REG |
| dport_pro_spi_intr_1_map_reg | DPORT_PRO_SPI_INTR_1_MAP_REG |
| dport_pro_spi_intr_2_map_reg | DPORT_PRO_SPI_INTR_2_MAP_REG |
| dport_pro_spi_intr_3_map_reg | DPORT_PRO_SPI_INTR_3_MAP_REG |
| dport_pro_tg1_wdt_level_int_map_reg | DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG |
| dport_pro_tg1_lact_level_int_map_reg | DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG |
| dport_pro_tg1_wdt_edge_int_map_reg | DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG |
| dport_pro_tg1_lact_edge_int_map_reg | DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG |
| dport_pro_tg1_t0_edge_int_map_reg | DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG |
| dport_pro_tg1_t0_level_int_map_reg | DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG |
| dport_pro_tg1_t1_level_int_map_reg | DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG |
| dport_pro_tg1_t1_edge_int_map_reg | DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG |
| dport_pro_tg_lact_edge_int_map_reg | DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG |
| dport_pro_tg_lact_level_int_map_reg | DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG |
| dport_pro_tg_t0_edge_int_map_reg | DPORT_PRO_TG_T0_EDGE_INT_MAP_REG |
| dport_pro_tg_t0_level_int_map_reg | DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG |
| dport_pro_tg_t1_level_int_map_reg | DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG |
| dport_pro_tg_t1_edge_int_map_reg | DPORT_PRO_TG_T1_EDGE_INT_MAP_REG |
| dport_pro_tg_wdt_edge_int_map_reg | DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG |
| dport_pro_tg_wdt_level_int_map_reg | DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG |
| dport_pro_timer_int1_map_reg | DPORT_PRO_TIMER_INT1_MAP_REG |
| dport_pro_timer_int2_map_reg | DPORT_PRO_TIMER_INT2_MAP_REG |
| dport_pro_tracemem_ena_reg | DPORT_PRO_TRACEMEM_ENA_REG |
| dport_pro_uart1_intr_map_reg | DPORT_PRO_UART1_INTR_MAP_REG |
| dport_pro_uart2_intr_map_reg | DPORT_PRO_UART2_INTR_MAP_REG |
| dport_pro_uart_intr_map_reg | DPORT_PRO_UART_INTR_MAP_REG |
| dport_pro_uhci0_intr_map_reg | DPORT_PRO_UHCI0_INTR_MAP_REG |
| dport_pro_uhci1_intr_map_reg | DPORT_PRO_UHCI1_INTR_MAP_REG |
| dport_pro_vecbase_ctrl_reg | DPORT_PRO_VECBASE_CTRL_REG |
| dport_pro_vecbase_set_reg | DPORT_PRO_VECBASE_SET_REG |
| dport_pro_wdg_int_map_reg | DPORT_PRO_WDG_INT_MAP_REG |
| dport_rom_fo_ctrl_reg | DPORT_ROM_FO_CTRL_REG |
| dport_rom_mpu_ena_reg | DPORT_ROM_MPU_ENA_REG |
| dport_rom_mpu_table0_reg | DPORT_ROM_MPU_TABLE0_REG |
| dport_rom_mpu_table1_reg | DPORT_ROM_MPU_TABLE1_REG |
| dport_rom_mpu_table2_reg | DPORT_ROM_MPU_TABLE2_REG |
| dport_rom_mpu_table3_reg | DPORT_ROM_MPU_TABLE3_REG |
| dport_rom_pd_ctrl_reg | DPORT_ROM_PD_CTRL_REG |
| dport_rsa_pd_ctrl_reg | DPORT_RSA_PD_CTRL_REG |
| dport_secure_boot_ctrl_reg | DPORT_SECURE_BOOT_CTRL_REG |
| dport_shrom_mpu_table0_reg | DPORT_SHROM_MPU_TABLE0_REG |
| dport_shrom_mpu_table1_reg | DPORT_SHROM_MPU_TABLE1_REG |
| dport_shrom_mpu_table2_reg | DPORT_SHROM_MPU_TABLE2_REG |
| dport_shrom_mpu_table3_reg | DPORT_SHROM_MPU_TABLE3_REG |
| dport_shrom_mpu_table4_reg | DPORT_SHROM_MPU_TABLE4_REG |
| dport_shrom_mpu_table5_reg | DPORT_SHROM_MPU_TABLE5_REG |
| dport_shrom_mpu_table6_reg | DPORT_SHROM_MPU_TABLE6_REG |
| dport_shrom_mpu_table7_reg | DPORT_SHROM_MPU_TABLE7_REG |
| dport_shrom_mpu_table8_reg | DPORT_SHROM_MPU_TABLE8_REG |
| dport_shrom_mpu_table9_reg | DPORT_SHROM_MPU_TABLE9_REG |
| dport_shrom_mpu_table10_reg | DPORT_SHROM_MPU_TABLE10_REG |
| dport_shrom_mpu_table11_reg | DPORT_SHROM_MPU_TABLE11_REG |
| dport_shrom_mpu_table12_reg | DPORT_SHROM_MPU_TABLE12_REG |
| dport_shrom_mpu_table13_reg | DPORT_SHROM_MPU_TABLE13_REG |
| dport_shrom_mpu_table14_reg | DPORT_SHROM_MPU_TABLE14_REG |
| dport_shrom_mpu_table15_reg | DPORT_SHROM_MPU_TABLE15_REG |
| dport_shrom_mpu_table16_reg | DPORT_SHROM_MPU_TABLE16_REG |
| dport_shrom_mpu_table17_reg | DPORT_SHROM_MPU_TABLE17_REG |
| dport_shrom_mpu_table18_reg | DPORT_SHROM_MPU_TABLE18_REG |
| dport_shrom_mpu_table19_reg | DPORT_SHROM_MPU_TABLE19_REG |
| dport_shrom_mpu_table20_reg | DPORT_SHROM_MPU_TABLE20_REG |
| dport_shrom_mpu_table21_reg | DPORT_SHROM_MPU_TABLE21_REG |
| dport_shrom_mpu_table22_reg | DPORT_SHROM_MPU_TABLE22_REG |
| dport_shrom_mpu_table23_reg | DPORT_SHROM_MPU_TABLE23_REG |
| dport_spi_dma_chan_sel_reg | DPORT_SPI_DMA_CHAN_SEL_REG |
| dport_sram_fo_ctrl_0_reg | DPORT_SRAM_FO_CTRL_0_REG |
| dport_sram_fo_ctrl_1_reg | DPORT_SRAM_FO_CTRL_1_REG |
| dport_sram_pd_ctrl_0_reg | DPORT_SRAM_PD_CTRL_0_REG |
| dport_sram_pd_ctrl_1_reg | DPORT_SRAM_PD_CTRL_1_REG |
| dport_tag_fo_ctrl_reg | DPORT_TAG_FO_CTRL_REG |
| dport_tracemem_mux_mode_reg | DPORT_TRACEMEM_MUX_MODE_REG |
| dport_wifi_bb_cfg_2_reg | DPORT_WIFI_BB_CFG_2_REG |
| dport_wifi_bb_cfg_reg | DPORT_WIFI_BB_CFG_REG |
| dport_wifi_clk_en_reg | DPORT_WIFI_CLK_EN_REG |
Structs
| RegisterBlock | Register block |
Type Definitions
| DPORT_ACCESS_CHECK_REG | DPORT_ACCESS_CHECK_REG |
| DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG | DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG |
| DPORT_AHBLITE_MPU_TABLE_BB_REG | DPORT_AHBLITE_MPU_TABLE_BB_REG |
| DPORT_AHBLITE_MPU_TABLE_BTMAC_REG | DPORT_AHBLITE_MPU_TABLE_BTMAC_REG |
| DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG | DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG |
| DPORT_AHBLITE_MPU_TABLE_BT_REG | DPORT_AHBLITE_MPU_TABLE_BT_REG |
| DPORT_AHBLITE_MPU_TABLE_CAN_REG | DPORT_AHBLITE_MPU_TABLE_CAN_REG |
| DPORT_AHBLITE_MPU_TABLE_EFUSE_REG | DPORT_AHBLITE_MPU_TABLE_EFUSE_REG |
| DPORT_AHBLITE_MPU_TABLE_EMAC_REG | DPORT_AHBLITE_MPU_TABLE_EMAC_REG |
| DPORT_AHBLITE_MPU_TABLE_FE2_REG | DPORT_AHBLITE_MPU_TABLE_FE2_REG |
| DPORT_AHBLITE_MPU_TABLE_FE_REG | DPORT_AHBLITE_MPU_TABLE_FE_REG |
| DPORT_AHBLITE_MPU_TABLE_GPIO_REG | DPORT_AHBLITE_MPU_TABLE_GPIO_REG |
| DPORT_AHBLITE_MPU_TABLE_HINF_REG | DPORT_AHBLITE_MPU_TABLE_HINF_REG |
| DPORT_AHBLITE_MPU_TABLE_I2C_REG | DPORT_AHBLITE_MPU_TABLE_I2C_REG |
| DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG | DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG |
| DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG | DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG |
| DPORT_AHBLITE_MPU_TABLE_I2S0_REG | DPORT_AHBLITE_MPU_TABLE_I2S0_REG |
| DPORT_AHBLITE_MPU_TABLE_I2S1_REG | DPORT_AHBLITE_MPU_TABLE_I2S1_REG |
| DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG | DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG |
| DPORT_AHBLITE_MPU_TABLE_LEDC_REG | DPORT_AHBLITE_MPU_TABLE_LEDC_REG |
| DPORT_AHBLITE_MPU_TABLE_MISC_REG | DPORT_AHBLITE_MPU_TABLE_MISC_REG |
| DPORT_AHBLITE_MPU_TABLE_PCNT_REG | DPORT_AHBLITE_MPU_TABLE_PCNT_REG |
| DPORT_AHBLITE_MPU_TABLE_PWM0_REG | DPORT_AHBLITE_MPU_TABLE_PWM0_REG |
| DPORT_AHBLITE_MPU_TABLE_PWM1_REG | DPORT_AHBLITE_MPU_TABLE_PWM1_REG |
| DPORT_AHBLITE_MPU_TABLE_PWM2_REG | DPORT_AHBLITE_MPU_TABLE_PWM2_REG |
| DPORT_AHBLITE_MPU_TABLE_PWM3_REG | DPORT_AHBLITE_MPU_TABLE_PWM3_REG |
| DPORT_AHBLITE_MPU_TABLE_PWR_REG | DPORT_AHBLITE_MPU_TABLE_PWR_REG |
| DPORT_AHBLITE_MPU_TABLE_RMT_REG | DPORT_AHBLITE_MPU_TABLE_RMT_REG |
| DPORT_AHBLITE_MPU_TABLE_RTC_REG | DPORT_AHBLITE_MPU_TABLE_RTC_REG |
| DPORT_AHBLITE_MPU_TABLE_RWBT_REG | DPORT_AHBLITE_MPU_TABLE_RWBT_REG |
| DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG | DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG |
| DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG | DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG |
| DPORT_AHBLITE_MPU_TABLE_SLC_REG | DPORT_AHBLITE_MPU_TABLE_SLC_REG |
| DPORT_AHBLITE_MPU_TABLE_SPI0_REG | DPORT_AHBLITE_MPU_TABLE_SPI0_REG |
| DPORT_AHBLITE_MPU_TABLE_SPI1_REG | DPORT_AHBLITE_MPU_TABLE_SPI1_REG |
| DPORT_AHBLITE_MPU_TABLE_SPI2_REG | DPORT_AHBLITE_MPU_TABLE_SPI2_REG |
| DPORT_AHBLITE_MPU_TABLE_SPI3_REG | DPORT_AHBLITE_MPU_TABLE_SPI3_REG |
| DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG | DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG |
| DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG |
| DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG | DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG |
| DPORT_AHBLITE_MPU_TABLE_TIMER_REG | DPORT_AHBLITE_MPU_TABLE_TIMER_REG |
| DPORT_AHBLITE_MPU_TABLE_UART1_REG | DPORT_AHBLITE_MPU_TABLE_UART1_REG |
| DPORT_AHBLITE_MPU_TABLE_UART2_REG | DPORT_AHBLITE_MPU_TABLE_UART2_REG |
| DPORT_AHBLITE_MPU_TABLE_UART_REG | DPORT_AHBLITE_MPU_TABLE_UART_REG |
| DPORT_AHBLITE_MPU_TABLE_UHCI0_REG | DPORT_AHBLITE_MPU_TABLE_UHCI0_REG |
| DPORT_AHBLITE_MPU_TABLE_UHCI1_REG | DPORT_AHBLITE_MPU_TABLE_UHCI1_REG |
| DPORT_AHBLITE_MPU_TABLE_WDG_REG | DPORT_AHBLITE_MPU_TABLE_WDG_REG |
| DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG | DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG |
| DPORT_AHB_LITE_MASK_REG | DPORT_AHB_LITE_MASK_REG |
| DPORT_AHB_MPU_TABLE_0_REG | DPORT_AHB_MPU_TABLE_0_REG |
| DPORT_AHB_MPU_TABLE_1_REG | DPORT_AHB_MPU_TABLE_1_REG |
| DPORT_APPCPU_CTRL_A_REG | DPORT_APPCPU_CTRL_A_REG |
| DPORT_APPCPU_CTRL_B_REG | DPORT_APPCPU_CTRL_B_REG |
| DPORT_APPCPU_CTRL_C_REG | DPORT_APPCPU_CTRL_C_REG |
| DPORT_APPCPU_CTRL_D_REG | DPORT_APPCPU_CTRL_D_REG |
| DPORT_APP_BB_INT_MAP_REG | DPORT_APP_BB_INT_MAP_REG |
| DPORT_APP_BOOT_REMAP_CTRL_REG | DPORT_APP_BOOT_REMAP_CTRL_REG |
| DPORT_APP_BT_BB_INT_MAP_REG | DPORT_APP_BT_BB_INT_MAP_REG |
| DPORT_APP_BT_BB_NMI_MAP_REG | DPORT_APP_BT_BB_NMI_MAP_REG |
| DPORT_APP_BT_MAC_INT_MAP_REG | DPORT_APP_BT_MAC_INT_MAP_REG |
| DPORT_APP_CACHE_CTRL1_REG | DPORT_APP_CACHE_CTRL1_REG |
| DPORT_APP_CACHE_CTRL_REG | DPORT_APP_CACHE_CTRL_REG |
| DPORT_APP_CACHE_IA_INT_MAP_REG | DPORT_APP_CACHE_IA_INT_MAP_REG |
| DPORT_APP_CACHE_LOCK_0_ADDR_REG | DPORT_APP_CACHE_LOCK_0_ADDR_REG |
| DPORT_APP_CACHE_LOCK_1_ADDR_REG | DPORT_APP_CACHE_LOCK_1_ADDR_REG |
| DPORT_APP_CACHE_LOCK_2_ADDR_REG | DPORT_APP_CACHE_LOCK_2_ADDR_REG |
| DPORT_APP_CACHE_LOCK_3_ADDR_REG | DPORT_APP_CACHE_LOCK_3_ADDR_REG |
| DPORT_APP_CAN_INT_MAP_REG | DPORT_APP_CAN_INT_MAP_REG |
| DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG | DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG |
| DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG | DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG |
| DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG | DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG |
| DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG | DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG |
| DPORT_APP_CPU_RECORD_CTRL_REG | DPORT_APP_CPU_RECORD_CTRL_REG |
| DPORT_APP_CPU_RECORD_PDEBUGDATA_REG | DPORT_APP_CPU_RECORD_PDEBUGDATA_REG |
| DPORT_APP_CPU_RECORD_PDEBUGINST_REG | DPORT_APP_CPU_RECORD_PDEBUGINST_REG |
| DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG | DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG |
| DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG | DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG |
| DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG | DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG |
| DPORT_APP_CPU_RECORD_PDEBUGPC_REG | DPORT_APP_CPU_RECORD_PDEBUGPC_REG |
| DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG | DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG |
| DPORT_APP_CPU_RECORD_PID_REG | DPORT_APP_CPU_RECORD_PID_REG |
| DPORT_APP_CPU_RECORD_STATUS_REG | DPORT_APP_CPU_RECORD_STATUS_REG |
| DPORT_APP_DCACHE_DBUG0_REG | DPORT_APP_DCACHE_DBUG0_REG |
| DPORT_APP_DCACHE_DBUG1_REG | DPORT_APP_DCACHE_DBUG1_REG |
| DPORT_APP_DCACHE_DBUG2_REG | DPORT_APP_DCACHE_DBUG2_REG |
| DPORT_APP_DCACHE_DBUG3_REG | DPORT_APP_DCACHE_DBUG3_REG |
| DPORT_APP_DCACHE_DBUG4_REG | DPORT_APP_DCACHE_DBUG4_REG |
| DPORT_APP_DCACHE_DBUG5_REG | DPORT_APP_DCACHE_DBUG5_REG |
| DPORT_APP_DCACHE_DBUG6_REG | DPORT_APP_DCACHE_DBUG6_REG |
| DPORT_APP_DCACHE_DBUG7_REG | DPORT_APP_DCACHE_DBUG7_REG |
| DPORT_APP_DCACHE_DBUG8_REG | DPORT_APP_DCACHE_DBUG8_REG |
| DPORT_APP_DCACHE_DBUG9_REG | DPORT_APP_DCACHE_DBUG9_REG |
| DPORT_APP_DPORT_APB_MASK0_REG | DPORT_APP_DPORT_APB_MASK0_REG |
| DPORT_APP_DPORT_APB_MASK1_REG | DPORT_APP_DPORT_APB_MASK1_REG |
| DPORT_APP_EFUSE_INT_MAP_REG | DPORT_APP_EFUSE_INT_MAP_REG |
| DPORT_APP_EMAC_INT_MAP_REG | DPORT_APP_EMAC_INT_MAP_REG |
| DPORT_APP_GPIO_INTERRUPT_MAP_REG | DPORT_APP_GPIO_INTERRUPT_MAP_REG |
| DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG | DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG |
| DPORT_APP_I2C_EXT0_INTR_MAP_REG | DPORT_APP_I2C_EXT0_INTR_MAP_REG |
| DPORT_APP_I2C_EXT1_INTR_MAP_REG | DPORT_APP_I2C_EXT1_INTR_MAP_REG |
| DPORT_APP_I2S0_INT_MAP_REG | DPORT_APP_I2S0_INT_MAP_REG |
| DPORT_APP_I2S1_INT_MAP_REG | DPORT_APP_I2S1_INT_MAP_REG |
| DPORT_APP_INTRUSION_CTRL_REG | DPORT_APP_INTRUSION_CTRL_REG |
| DPORT_APP_INTRUSION_STATUS_REG | DPORT_APP_INTRUSION_STATUS_REG |
| DPORT_APP_INTR_STATUS_0_REG | DPORT_APP_INTR_STATUS_0_REG |
| DPORT_APP_INTR_STATUS_1_REG | DPORT_APP_INTR_STATUS_1_REG |
| DPORT_APP_INTR_STATUS_2_REG | DPORT_APP_INTR_STATUS_2_REG |
| DPORT_APP_LEDC_INT_MAP_REG | DPORT_APP_LEDC_INT_MAP_REG |
| DPORT_APP_MAC_INTR_MAP_REG | DPORT_APP_MAC_INTR_MAP_REG |
| DPORT_APP_MAC_NMI_MAP_REG | DPORT_APP_MAC_NMI_MAP_REG |
| DPORT_APP_MMU_IA_INT_MAP_REG | DPORT_APP_MMU_IA_INT_MAP_REG |
| DPORT_APP_MPU_IA_INT_MAP_REG | DPORT_APP_MPU_IA_INT_MAP_REG |
| DPORT_APP_PCNT_INTR_MAP_REG | DPORT_APP_PCNT_INTR_MAP_REG |
| DPORT_APP_PWM0_INTR_MAP_REG | DPORT_APP_PWM0_INTR_MAP_REG |
| DPORT_APP_PWM1_INTR_MAP_REG | DPORT_APP_PWM1_INTR_MAP_REG |
| DPORT_APP_PWM2_INTR_MAP_REG | DPORT_APP_PWM2_INTR_MAP_REG |
| DPORT_APP_PWM3_INTR_MAP_REG | DPORT_APP_PWM3_INTR_MAP_REG |
| DPORT_APP_RMT_INTR_MAP_REG | DPORT_APP_RMT_INTR_MAP_REG |
| DPORT_APP_RSA_INTR_MAP_REG | DPORT_APP_RSA_INTR_MAP_REG |
| DPORT_APP_RTC_CORE_INTR_MAP_REG | DPORT_APP_RTC_CORE_INTR_MAP_REG |
| DPORT_APP_RWBLE_IRQ_MAP_REG | DPORT_APP_RWBLE_IRQ_MAP_REG |
| DPORT_APP_RWBLE_NMI_MAP_REG | DPORT_APP_RWBLE_NMI_MAP_REG |
| DPORT_APP_RWBT_IRQ_MAP_REG | DPORT_APP_RWBT_IRQ_MAP_REG |
| DPORT_APP_RWBT_NMI_MAP_REG | DPORT_APP_RWBT_NMI_MAP_REG |
| DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG | DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG |
| DPORT_APP_SLC0_INTR_MAP_REG | DPORT_APP_SLC0_INTR_MAP_REG |
| DPORT_APP_SLC1_INTR_MAP_REG | DPORT_APP_SLC1_INTR_MAP_REG |
| DPORT_APP_SPI1_DMA_INT_MAP_REG | DPORT_APP_SPI1_DMA_INT_MAP_REG |
| DPORT_APP_SPI2_DMA_INT_MAP_REG | DPORT_APP_SPI2_DMA_INT_MAP_REG |
| DPORT_APP_SPI3_DMA_INT_MAP_REG | DPORT_APP_SPI3_DMA_INT_MAP_REG |
| DPORT_APP_SPI_INTR_0_MAP_REG | DPORT_APP_SPI_INTR_0_MAP_REG |
| DPORT_APP_SPI_INTR_1_MAP_REG | DPORT_APP_SPI_INTR_1_MAP_REG |
| DPORT_APP_SPI_INTR_2_MAP_REG | DPORT_APP_SPI_INTR_2_MAP_REG |
| DPORT_APP_SPI_INTR_3_MAP_REG | DPORT_APP_SPI_INTR_3_MAP_REG |
| DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG | DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG |
| DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG | DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG |
| DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG | DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG |
| DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG | DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG |
| DPORT_APP_TG1_T0_EDGE_INT_MAP_REG | DPORT_APP_TG1_T0_EDGE_INT_MAP_REG |
| DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG | DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG |
| DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG | DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG |
| DPORT_APP_TG1_T1_EDGE_INT_MAP_REG | DPORT_APP_TG1_T1_EDGE_INT_MAP_REG |
| DPORT_APP_TG_LACT_EDGE_INT_MAP_REG | DPORT_APP_TG_LACT_EDGE_INT_MAP_REG |
| DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG | DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG |
| DPORT_APP_TG_T0_EDGE_INT_MAP_REG | DPORT_APP_TG_T0_EDGE_INT_MAP_REG |
| DPORT_APP_TG_T0_LEVEL_INT_MAP_REG | DPORT_APP_TG_T0_LEVEL_INT_MAP_REG |
| DPORT_APP_TG_T1_LEVEL_INT_MAP_REG | DPORT_APP_TG_T1_LEVEL_INT_MAP_REG |
| DPORT_APP_TG_T1_EDGE_INT_MAP_REG | DPORT_APP_TG_T1_EDGE_INT_MAP_REG |
| DPORT_APP_TG_WDT_EDGE_INT_MAP_REG | DPORT_APP_TG_WDT_EDGE_INT_MAP_REG |
| DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG | DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG |
| DPORT_APP_TIMER_INT1_MAP_REG | DPORT_APP_TIMER_INT1_MAP_REG |
| DPORT_APP_TIMER_INT2_MAP_REG | DPORT_APP_TIMER_INT2_MAP_REG |
| DPORT_APP_TRACEMEM_ENA_REG | DPORT_APP_TRACEMEM_ENA_REG |
| DPORT_APP_UART1_INTR_MAP_REG | DPORT_APP_UART1_INTR_MAP_REG |
| DPORT_APP_UART2_INTR_MAP_REG | DPORT_APP_UART2_INTR_MAP_REG |
| DPORT_APP_UART_INTR_MAP_REG | DPORT_APP_UART_INTR_MAP_REG |
| DPORT_APP_UHCI0_INTR_MAP_REG | DPORT_APP_UHCI0_INTR_MAP_REG |
| DPORT_APP_UHCI1_INTR_MAP_REG | DPORT_APP_UHCI1_INTR_MAP_REG |
| DPORT_APP_VECBASE_CTRL_REG | DPORT_APP_VECBASE_CTRL_REG |
| DPORT_APP_VECBASE_SET_REG | DPORT_APP_VECBASE_SET_REG |
| DPORT_APP_WDG_INT_MAP_REG | DPORT_APP_WDG_INT_MAP_REG |
| DPORT_BT_LPCK_DIV_FRAC_REG | DPORT_BT_LPCK_DIV_FRAC_REG |
| DPORT_BT_LPCK_DIV_INT_REG | DPORT_BT_LPCK_DIV_INT_REG |
| DPORT_CACHE_IA_INT_EN_REG | DPORT_CACHE_IA_INT_EN_REG |
| DPORT_CACHE_MUX_MODE_REG | DPORT_CACHE_MUX_MODE_REG |
| DPORT_CORE_RST_EN_REG | DPORT_CORE_RST_EN_REG |
| DPORT_CPU_INTR_FROM_CPU_0_REG | DPORT_CPU_INTR_FROM_CPU_0_REG |
| DPORT_CPU_INTR_FROM_CPU_1_REG | DPORT_CPU_INTR_FROM_CPU_1_REG |
| DPORT_CPU_INTR_FROM_CPU_2_REG | DPORT_CPU_INTR_FROM_CPU_2_REG |
| DPORT_CPU_INTR_FROM_CPU_3_REG | DPORT_CPU_INTR_FROM_CPU_3_REG |
| DPORT_CPU_PER_CONF_REG | DPORT_CPU_PER_CONF_REG |
| DPORT_DATE_REG | DPORT_DATE_REG |
| DPORT_DMMU_PAGE_MODE_REG | DPORT_DMMU_PAGE_MODE_REG |
| DPORT_DMMU_TABLE0_REG | DPORT_DMMU_TABLE0_REG |
| DPORT_DMMU_TABLE1_REG | DPORT_DMMU_TABLE1_REG |
| DPORT_DMMU_TABLE2_REG | DPORT_DMMU_TABLE2_REG |
| DPORT_DMMU_TABLE3_REG | DPORT_DMMU_TABLE3_REG |
| DPORT_DMMU_TABLE4_REG | DPORT_DMMU_TABLE4_REG |
| DPORT_DMMU_TABLE5_REG | DPORT_DMMU_TABLE5_REG |
| DPORT_DMMU_TABLE6_REG | DPORT_DMMU_TABLE6_REG |
| DPORT_DMMU_TABLE7_REG | DPORT_DMMU_TABLE7_REG |
| DPORT_DMMU_TABLE8_REG | DPORT_DMMU_TABLE8_REG |
| DPORT_DMMU_TABLE9_REG | DPORT_DMMU_TABLE9_REG |
| DPORT_DMMU_TABLE10_REG | DPORT_DMMU_TABLE10_REG |
| DPORT_DMMU_TABLE11_REG | DPORT_DMMU_TABLE11_REG |
| DPORT_DMMU_TABLE12_REG | DPORT_DMMU_TABLE12_REG |
| DPORT_DMMU_TABLE13_REG | DPORT_DMMU_TABLE13_REG |
| DPORT_DMMU_TABLE14_REG | DPORT_DMMU_TABLE14_REG |
| DPORT_DMMU_TABLE15_REG | DPORT_DMMU_TABLE15_REG |
| DPORT_FRONT_END_MEM_PD_REG | DPORT_FRONT_END_MEM_PD_REG |
| DPORT_HOST_INF_SEL_REG | DPORT_HOST_INF_SEL_REG |
| DPORT_IMMU_PAGE_MODE_REG | DPORT_IMMU_PAGE_MODE_REG |
| DPORT_IMMU_TABLE0_REG | DPORT_IMMU_TABLE0_REG |
| DPORT_IMMU_TABLE1_REG | DPORT_IMMU_TABLE1_REG |
| DPORT_IMMU_TABLE2_REG | DPORT_IMMU_TABLE2_REG |
| DPORT_IMMU_TABLE3_REG | DPORT_IMMU_TABLE3_REG |
| DPORT_IMMU_TABLE4_REG | DPORT_IMMU_TABLE4_REG |
| DPORT_IMMU_TABLE5_REG | DPORT_IMMU_TABLE5_REG |
| DPORT_IMMU_TABLE6_REG | DPORT_IMMU_TABLE6_REG |
| DPORT_IMMU_TABLE7_REG | DPORT_IMMU_TABLE7_REG |
| DPORT_IMMU_TABLE8_REG | DPORT_IMMU_TABLE8_REG |
| DPORT_IMMU_TABLE9_REG | DPORT_IMMU_TABLE9_REG |
| DPORT_IMMU_TABLE10_REG | DPORT_IMMU_TABLE10_REG |
| DPORT_IMMU_TABLE11_REG | DPORT_IMMU_TABLE11_REG |
| DPORT_IMMU_TABLE12_REG | DPORT_IMMU_TABLE12_REG |
| DPORT_IMMU_TABLE13_REG | DPORT_IMMU_TABLE13_REG |
| DPORT_IMMU_TABLE14_REG | DPORT_IMMU_TABLE14_REG |
| DPORT_IMMU_TABLE15_REG | DPORT_IMMU_TABLE15_REG |
| DPORT_IRAM_DRAM_AHB_SEL_REG | DPORT_IRAM_DRAM_AHB_SEL_REG |
| DPORT_MEM_ACCESS_DBUG0_REG | DPORT_MEM_ACCESS_DBUG0_REG |
| DPORT_MEM_ACCESS_DBUG1_REG | DPORT_MEM_ACCESS_DBUG1_REG |
| DPORT_MEM_PD_MASK_REG | DPORT_MEM_PD_MASK_REG |
| DPORT_MMU_IA_INT_EN_REG | DPORT_MMU_IA_INT_EN_REG |
| DPORT_MPU_IA_INT_EN_REG | DPORT_MPU_IA_INT_EN_REG |
| DPORT_PERIP_CLK_EN_REG | DPORT_PERIP_CLK_EN_REG |
| DPORT_PERIP_RST_EN_REG | DPORT_PERIP_RST_EN_REG |
| DPORT_PERI_CLK_EN_REG | DPORT_PERI_CLK_EN_REG |
| DPORT_PERI_RST_EN_REG | DPORT_PERI_RST_EN_REG |
| DPORT_PRO_BB_INT_MAP_REG | DPORT_PRO_BB_INT_MAP_REG |
| DPORT_PRO_BOOT_REMAP_CTRL_REG | DPORT_PRO_BOOT_REMAP_CTRL_REG |
| DPORT_PRO_BT_BB_INT_MAP_REG | DPORT_PRO_BT_BB_INT_MAP_REG |
| DPORT_PRO_BT_BB_NMI_MAP_REG | DPORT_PRO_BT_BB_NMI_MAP_REG |
| DPORT_PRO_BT_MAC_INT_MAP_REG | DPORT_PRO_BT_MAC_INT_MAP_REG |
| DPORT_PRO_CACHE_CTRL1_REG | DPORT_PRO_CACHE_CTRL1_REG |
| DPORT_PRO_CACHE_CTRL_REG | DPORT_PRO_CACHE_CTRL_REG |
| DPORT_PRO_CACHE_IA_INT_MAP_REG | DPORT_PRO_CACHE_IA_INT_MAP_REG |
| DPORT_PRO_CACHE_LOCK_0_ADDR_REG | DPORT_PRO_CACHE_LOCK_0_ADDR_REG |
| DPORT_PRO_CACHE_LOCK_1_ADDR_REG | DPORT_PRO_CACHE_LOCK_1_ADDR_REG |
| DPORT_PRO_CACHE_LOCK_2_ADDR_REG | DPORT_PRO_CACHE_LOCK_2_ADDR_REG |
| DPORT_PRO_CACHE_LOCK_3_ADDR_REG | DPORT_PRO_CACHE_LOCK_3_ADDR_REG |
| DPORT_PRO_CAN_INT_MAP_REG | DPORT_PRO_CAN_INT_MAP_REG |
| DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG | DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG |
| DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG | DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG |
| DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG | DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG |
| DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG | DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG |
| DPORT_PRO_CPU_RECORD_CTRL_REG | DPORT_PRO_CPU_RECORD_CTRL_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG | DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGINST_REG | DPORT_PRO_CPU_RECORD_PDEBUGINST_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG | DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG | DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG | DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGPC_REG | DPORT_PRO_CPU_RECORD_PDEBUGPC_REG |
| DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG | DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG |
| DPORT_PRO_CPU_RECORD_PID_REG | DPORT_PRO_CPU_RECORD_PID_REG |
| DPORT_PRO_CPU_RECORD_STATUS_REG | DPORT_PRO_CPU_RECORD_STATUS_REG |
| DPORT_PRO_DCACHE_DBUG0_REG | DPORT_PRO_DCACHE_DBUG0_REG |
| DPORT_PRO_DCACHE_DBUG1_REG | DPORT_PRO_DCACHE_DBUG1_REG |
| DPORT_PRO_DCACHE_DBUG2_REG | DPORT_PRO_DCACHE_DBUG2_REG |
| DPORT_PRO_DCACHE_DBUG3_REG | DPORT_PRO_DCACHE_DBUG3_REG |
| DPORT_PRO_DCACHE_DBUG4_REG | DPORT_PRO_DCACHE_DBUG4_REG |
| DPORT_PRO_DCACHE_DBUG5_REG | DPORT_PRO_DCACHE_DBUG5_REG |
| DPORT_PRO_DCACHE_DBUG6_REG | DPORT_PRO_DCACHE_DBUG6_REG |
| DPORT_PRO_DCACHE_DBUG7_REG | DPORT_PRO_DCACHE_DBUG7_REG |
| DPORT_PRO_DCACHE_DBUG8_REG | DPORT_PRO_DCACHE_DBUG8_REG |
| DPORT_PRO_DCACHE_DBUG9_REG | DPORT_PRO_DCACHE_DBUG9_REG |
| DPORT_PRO_DPORT_APB_MASK0_REG | DPORT_PRO_DPORT_APB_MASK0_REG |
| DPORT_PRO_DPORT_APB_MASK1_REG | DPORT_PRO_DPORT_APB_MASK1_REG |
| DPORT_PRO_EFUSE_INT_MAP_REG | DPORT_PRO_EFUSE_INT_MAP_REG |
| DPORT_PRO_EMAC_INT_MAP_REG | DPORT_PRO_EMAC_INT_MAP_REG |
| DPORT_PRO_GPIO_INTERRUPT_MAP_REG | DPORT_PRO_GPIO_INTERRUPT_MAP_REG |
| DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG | DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG |
| DPORT_PRO_I2C_EXT0_INTR_MAP_REG | DPORT_PRO_I2C_EXT0_INTR_MAP_REG |
| DPORT_PRO_I2C_EXT1_INTR_MAP_REG | DPORT_PRO_I2C_EXT1_INTR_MAP_REG |
| DPORT_PRO_I2S0_INT_MAP_REG | DPORT_PRO_I2S0_INT_MAP_REG |
| DPORT_PRO_I2S1_INT_MAP_REG | DPORT_PRO_I2S1_INT_MAP_REG |
| DPORT_PRO_INTRUSION_CTRL_REG | DPORT_PRO_INTRUSION_CTRL_REG |
| DPORT_PRO_INTRUSION_STATUS_REG | DPORT_PRO_INTRUSION_STATUS_REG |
| DPORT_PRO_INTR_STATUS_0_REG | DPORT_PRO_INTR_STATUS_0_REG |
| DPORT_PRO_INTR_STATUS_1_REG | DPORT_PRO_INTR_STATUS_1_REG |
| DPORT_PRO_INTR_STATUS_2_REG | DPORT_PRO_INTR_STATUS_2_REG |
| DPORT_PRO_LEDC_INT_MAP_REG | DPORT_PRO_LEDC_INT_MAP_REG |
| DPORT_PRO_MAC_INTR_MAP_REG | DPORT_PRO_MAC_INTR_MAP_REG |
| DPORT_PRO_MAC_NMI_MAP_REG | DPORT_PRO_MAC_NMI_MAP_REG |
| DPORT_PRO_MMU_IA_INT_MAP_REG | DPORT_PRO_MMU_IA_INT_MAP_REG |
| DPORT_PRO_MPU_IA_INT_MAP_REG | DPORT_PRO_MPU_IA_INT_MAP_REG |
| DPORT_PRO_PCNT_INTR_MAP_REG | DPORT_PRO_PCNT_INTR_MAP_REG |
| DPORT_PRO_PWM0_INTR_MAP_REG | DPORT_PRO_PWM0_INTR_MAP_REG |
| DPORT_PRO_PWM1_INTR_MAP_REG | DPORT_PRO_PWM1_INTR_MAP_REG |
| DPORT_PRO_PWM2_INTR_MAP_REG | DPORT_PRO_PWM2_INTR_MAP_REG |
| DPORT_PRO_PWM3_INTR_MAP_REG | DPORT_PRO_PWM3_INTR_MAP_REG |
| DPORT_PRO_RMT_INTR_MAP_REG | DPORT_PRO_RMT_INTR_MAP_REG |
| DPORT_PRO_RSA_INTR_MAP_REG | DPORT_PRO_RSA_INTR_MAP_REG |
| DPORT_PRO_RTC_CORE_INTR_MAP_REG | DPORT_PRO_RTC_CORE_INTR_MAP_REG |
| DPORT_PRO_RWBLE_IRQ_MAP_REG | DPORT_PRO_RWBLE_IRQ_MAP_REG |
| DPORT_PRO_RWBLE_NMI_MAP_REG | DPORT_PRO_RWBLE_NMI_MAP_REG |
| DPORT_PRO_RWBT_IRQ_MAP_REG | DPORT_PRO_RWBT_IRQ_MAP_REG |
| DPORT_PRO_RWBT_NMI_MAP_REG | DPORT_PRO_RWBT_NMI_MAP_REG |
| DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG | DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG |
| DPORT_PRO_SLC0_INTR_MAP_REG | DPORT_PRO_SLC0_INTR_MAP_REG |
| DPORT_PRO_SLC1_INTR_MAP_REG | DPORT_PRO_SLC1_INTR_MAP_REG |
| DPORT_PRO_SPI1_DMA_INT_MAP_REG | DPORT_PRO_SPI1_DMA_INT_MAP_REG |
| DPORT_PRO_SPI2_DMA_INT_MAP_REG | DPORT_PRO_SPI2_DMA_INT_MAP_REG |
| DPORT_PRO_SPI3_DMA_INT_MAP_REG | DPORT_PRO_SPI3_DMA_INT_MAP_REG |
| DPORT_PRO_SPI_INTR_0_MAP_REG | DPORT_PRO_SPI_INTR_0_MAP_REG |
| DPORT_PRO_SPI_INTR_1_MAP_REG | DPORT_PRO_SPI_INTR_1_MAP_REG |
| DPORT_PRO_SPI_INTR_2_MAP_REG | DPORT_PRO_SPI_INTR_2_MAP_REG |
| DPORT_PRO_SPI_INTR_3_MAP_REG | DPORT_PRO_SPI_INTR_3_MAP_REG |
| DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG | DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG | DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG | DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG |
| DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG | DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG |
| DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG | DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG |
| DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG | DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG | DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG | DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG |
| DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG | DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG |
| DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG | DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG_T0_EDGE_INT_MAP_REG | DPORT_PRO_TG_T0_EDGE_INT_MAP_REG |
| DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG | DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG | DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG |
| DPORT_PRO_TG_T1_EDGE_INT_MAP_REG | DPORT_PRO_TG_T1_EDGE_INT_MAP_REG |
| DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG | DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG |
| DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG | DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG |
| DPORT_PRO_TIMER_INT1_MAP_REG | DPORT_PRO_TIMER_INT1_MAP_REG |
| DPORT_PRO_TIMER_INT2_MAP_REG | DPORT_PRO_TIMER_INT2_MAP_REG |
| DPORT_PRO_TRACEMEM_ENA_REG | DPORT_PRO_TRACEMEM_ENA_REG |
| DPORT_PRO_UART1_INTR_MAP_REG | DPORT_PRO_UART1_INTR_MAP_REG |
| DPORT_PRO_UART2_INTR_MAP_REG | DPORT_PRO_UART2_INTR_MAP_REG |
| DPORT_PRO_UART_INTR_MAP_REG | DPORT_PRO_UART_INTR_MAP_REG |
| DPORT_PRO_UHCI0_INTR_MAP_REG | DPORT_PRO_UHCI0_INTR_MAP_REG |
| DPORT_PRO_UHCI1_INTR_MAP_REG | DPORT_PRO_UHCI1_INTR_MAP_REG |
| DPORT_PRO_VECBASE_CTRL_REG | DPORT_PRO_VECBASE_CTRL_REG |
| DPORT_PRO_VECBASE_SET_REG | DPORT_PRO_VECBASE_SET_REG |
| DPORT_PRO_WDG_INT_MAP_REG | DPORT_PRO_WDG_INT_MAP_REG |
| DPORT_ROM_FO_CTRL_REG | DPORT_ROM_FO_CTRL_REG |
| DPORT_ROM_MPU_ENA_REG | DPORT_ROM_MPU_ENA_REG |
| DPORT_ROM_MPU_TABLE0_REG | DPORT_ROM_MPU_TABLE0_REG |
| DPORT_ROM_MPU_TABLE1_REG | DPORT_ROM_MPU_TABLE1_REG |
| DPORT_ROM_MPU_TABLE2_REG | DPORT_ROM_MPU_TABLE2_REG |
| DPORT_ROM_MPU_TABLE3_REG | DPORT_ROM_MPU_TABLE3_REG |
| DPORT_ROM_PD_CTRL_REG | DPORT_ROM_PD_CTRL_REG |
| DPORT_RSA_PD_CTRL_REG | DPORT_RSA_PD_CTRL_REG |
| DPORT_SECURE_BOOT_CTRL_REG | DPORT_SECURE_BOOT_CTRL_REG |
| DPORT_SHROM_MPU_TABLE0_REG | DPORT_SHROM_MPU_TABLE0_REG |
| DPORT_SHROM_MPU_TABLE1_REG | DPORT_SHROM_MPU_TABLE1_REG |
| DPORT_SHROM_MPU_TABLE2_REG | DPORT_SHROM_MPU_TABLE2_REG |
| DPORT_SHROM_MPU_TABLE3_REG | DPORT_SHROM_MPU_TABLE3_REG |
| DPORT_SHROM_MPU_TABLE4_REG | DPORT_SHROM_MPU_TABLE4_REG |
| DPORT_SHROM_MPU_TABLE5_REG | DPORT_SHROM_MPU_TABLE5_REG |
| DPORT_SHROM_MPU_TABLE6_REG | DPORT_SHROM_MPU_TABLE6_REG |
| DPORT_SHROM_MPU_TABLE7_REG | DPORT_SHROM_MPU_TABLE7_REG |
| DPORT_SHROM_MPU_TABLE8_REG | DPORT_SHROM_MPU_TABLE8_REG |
| DPORT_SHROM_MPU_TABLE9_REG | DPORT_SHROM_MPU_TABLE9_REG |
| DPORT_SHROM_MPU_TABLE10_REG | DPORT_SHROM_MPU_TABLE10_REG |
| DPORT_SHROM_MPU_TABLE11_REG | DPORT_SHROM_MPU_TABLE11_REG |
| DPORT_SHROM_MPU_TABLE12_REG | DPORT_SHROM_MPU_TABLE12_REG |
| DPORT_SHROM_MPU_TABLE13_REG | DPORT_SHROM_MPU_TABLE13_REG |
| DPORT_SHROM_MPU_TABLE14_REG | DPORT_SHROM_MPU_TABLE14_REG |
| DPORT_SHROM_MPU_TABLE15_REG | DPORT_SHROM_MPU_TABLE15_REG |
| DPORT_SHROM_MPU_TABLE16_REG | DPORT_SHROM_MPU_TABLE16_REG |
| DPORT_SHROM_MPU_TABLE17_REG | DPORT_SHROM_MPU_TABLE17_REG |
| DPORT_SHROM_MPU_TABLE18_REG | DPORT_SHROM_MPU_TABLE18_REG |
| DPORT_SHROM_MPU_TABLE19_REG | DPORT_SHROM_MPU_TABLE19_REG |
| DPORT_SHROM_MPU_TABLE20_REG | DPORT_SHROM_MPU_TABLE20_REG |
| DPORT_SHROM_MPU_TABLE21_REG | DPORT_SHROM_MPU_TABLE21_REG |
| DPORT_SHROM_MPU_TABLE22_REG | DPORT_SHROM_MPU_TABLE22_REG |
| DPORT_SHROM_MPU_TABLE23_REG | DPORT_SHROM_MPU_TABLE23_REG |
| DPORT_SPI_DMA_CHAN_SEL_REG | DPORT_SPI_DMA_CHAN_SEL_REG |
| DPORT_SRAM_FO_CTRL_0_REG | DPORT_SRAM_FO_CTRL_0_REG |
| DPORT_SRAM_FO_CTRL_1_REG | DPORT_SRAM_FO_CTRL_1_REG |
| DPORT_SRAM_PD_CTRL_0_REG | DPORT_SRAM_PD_CTRL_0_REG |
| DPORT_SRAM_PD_CTRL_1_REG | DPORT_SRAM_PD_CTRL_1_REG |
| DPORT_TAG_FO_CTRL_REG | DPORT_TAG_FO_CTRL_REG |
| DPORT_TRACEMEM_MUX_MODE_REG | DPORT_TRACEMEM_MUX_MODE_REG |
| DPORT_WIFI_BB_CFG_2_REG | DPORT_WIFI_BB_CFG_2_REG |
| DPORT_WIFI_BB_CFG_REG | DPORT_WIFI_BB_CFG_REG |
| DPORT_WIFI_CLK_EN_REG | DPORT_WIFI_CLK_EN_REG |