#[repr(C)]
#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
pub struct __BindgenBitfieldUnit<Storage, Align> {
storage: Storage,
align: [Align; 0],
}
impl<Storage, Align> __BindgenBitfieldUnit<Storage, Align> {
#[inline]
pub const fn new(storage: Storage) -> Self {
Self { storage, align: [] }
}
}
impl<Storage, Align> __BindgenBitfieldUnit<Storage, Align>
where
Storage: AsRef<[u8]> + AsMut<[u8]>,
{
#[inline]
pub fn get_bit(&self, index: usize) -> bool {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = self.storage.as_ref()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
byte & mask == mask
}
#[inline]
pub fn set_bit(&mut self, index: usize, val: bool) {
debug_assert!(index / 8 < self.storage.as_ref().len());
let byte_index = index / 8;
let byte = &mut self.storage.as_mut()[byte_index];
let bit_index = if cfg!(target_endian = "big") {
7 - (index % 8)
} else {
index % 8
};
let mask = 1 << bit_index;
if val {
*byte |= mask;
} else {
*byte &= !mask;
}
}
#[inline]
pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
let mut val = 0;
for i in 0..(bit_width as usize) {
if self.get_bit(i + bit_offset) {
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
val |= 1 << index;
}
}
val
}
#[inline]
pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
debug_assert!(bit_width <= 64);
debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
for i in 0..(bit_width as usize) {
let mask = 1 << i;
let val_bit_is_set = val & mask == mask;
let index = if cfg!(target_endian = "big") {
bit_width as usize - 1 - i
} else {
i
};
self.set_bit(index + bit_offset, val_bit_is_set);
}
}
}
#[repr(C)]
#[derive(Default)]
pub struct __IncompleteArrayField<T>(::core::marker::PhantomData<T>, [T; 0]);
impl<T> __IncompleteArrayField<T> {
#[inline]
pub const fn new() -> Self {
__IncompleteArrayField(::core::marker::PhantomData, [])
}
#[inline]
pub unsafe fn as_ptr(&self) -> *const T {
::core::mem::transmute(self)
}
#[inline]
pub unsafe fn as_mut_ptr(&mut self) -> *mut T {
::core::mem::transmute(self)
}
#[inline]
pub unsafe fn as_slice(&self, len: usize) -> &[T] {
::core::slice::from_raw_parts(self.as_ptr(), len)
}
#[inline]
pub unsafe fn as_mut_slice(&mut self, len: usize) -> &mut [T] {
::core::slice::from_raw_parts_mut(self.as_mut_ptr(), len)
}
}
impl<T> ::core::fmt::Debug for __IncompleteArrayField<T> {
fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
fmt.write_str("__IncompleteArrayField")
}
}
impl<T> ::core::clone::Clone for __IncompleteArrayField<T> {
#[inline]
fn clone(&self) -> Self {
Self::new()
}
}
pub const __NEWLIB_H__: u32 = 1;
pub const _NEWLIB_VERSION: &'static [u8; 6usize] = b"2.2.0\0";
pub const _WANT_REENT_SMALL: u32 = 1;
pub const _MB_LEN_MAX: u32 = 1;
pub const HAVE_INITFINI_ARRAY: u32 = 1;
pub const _ATEXIT_DYNAMIC_ALLOC: u32 = 1;
pub const _HAVE_LONG_DOUBLE: u32 = 1;
pub const _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL: u32 = 1;
pub const _LDBL_EQ_DBL: u32 = 1;
pub const _FVWRITE_IN_STREAMIO: u32 = 1;
pub const _FSEEK_OPTIMIZATION: u32 = 1;
pub const _WIDE_ORIENT: u32 = 1;
pub const _UNBUF_STREAM_OPT: u32 = 1;
pub const _NANO_FORMATTED_IO: u32 = 1;
pub const __NEWLIB__: u32 = 2;
pub const __NEWLIB_MINOR__: u32 = 1;
pub const _POSIX_THREADS: u32 = 1;
pub const _UNIX98_THREAD_MUTEX_ATTRIBUTES: u32 = 1;
pub const XCHAL_HAVE_BE: u32 = 0;
pub const XCHAL_HAVE_WINDOWED: u32 = 1;
pub const XCHAL_NUM_AREGS: u32 = 64;
pub const XCHAL_NUM_AREGS_LOG2: u32 = 6;
pub const XCHAL_MAX_INSTRUCTION_SIZE: u32 = 3;
pub const XCHAL_HAVE_DEBUG: u32 = 1;
pub const XCHAL_HAVE_DENSITY: u32 = 1;
pub const XCHAL_HAVE_LOOPS: u32 = 1;
pub const XCHAL_LOOP_BUFFER_SIZE: u32 = 256;
pub const XCHAL_HAVE_NSA: u32 = 1;
pub const XCHAL_HAVE_MINMAX: u32 = 1;
pub const XCHAL_HAVE_SEXT: u32 = 1;
pub const XCHAL_HAVE_DEPBITS: u32 = 0;
pub const XCHAL_HAVE_CLAMPS: u32 = 1;
pub const XCHAL_HAVE_MUL16: u32 = 1;
pub const XCHAL_HAVE_MUL32: u32 = 1;
pub const XCHAL_HAVE_MUL32_HIGH: u32 = 1;
pub const XCHAL_HAVE_DIV32: u32 = 1;
pub const XCHAL_HAVE_L32R: u32 = 1;
pub const XCHAL_HAVE_ABSOLUTE_LITERALS: u32 = 0;
pub const XCHAL_HAVE_CONST16: u32 = 0;
pub const XCHAL_HAVE_ADDX: u32 = 1;
pub const XCHAL_HAVE_WIDE_BRANCHES: u32 = 0;
pub const XCHAL_HAVE_PREDICTED_BRANCHES: u32 = 0;
pub const XCHAL_HAVE_CALL4AND12: u32 = 1;
pub const XCHAL_HAVE_ABS: u32 = 1;
pub const XCHAL_HAVE_RELEASE_SYNC: u32 = 1;
pub const XCHAL_HAVE_S32C1I: u32 = 1;
pub const XCHAL_HAVE_SPECULATION: u32 = 0;
pub const XCHAL_HAVE_FULL_RESET: u32 = 1;
pub const XCHAL_NUM_CONTEXTS: u32 = 1;
pub const XCHAL_NUM_MISC_REGS: u32 = 4;
pub const XCHAL_HAVE_TAP_MASTER: u32 = 0;
pub const XCHAL_HAVE_PRID: u32 = 1;
pub const XCHAL_HAVE_EXTERN_REGS: u32 = 1;
pub const XCHAL_HAVE_MX: u32 = 0;
pub const XCHAL_HAVE_MP_INTERRUPTS: u32 = 0;
pub const XCHAL_HAVE_MP_RUNSTALL: u32 = 0;
pub const XCHAL_HAVE_PSO: u32 = 0;
pub const XCHAL_HAVE_PSO_CDM: u32 = 0;
pub const XCHAL_HAVE_PSO_FULL_RETENTION: u32 = 0;
pub const XCHAL_HAVE_THREADPTR: u32 = 1;
pub const XCHAL_HAVE_BOOLEANS: u32 = 1;
pub const XCHAL_HAVE_CP: u32 = 1;
pub const XCHAL_CP_MAXCFG: u32 = 8;
pub const XCHAL_HAVE_MAC16: u32 = 1;
pub const XCHAL_HAVE_FUSION: u32 = 0;
pub const XCHAL_HAVE_FUSION_FP: u32 = 0;
pub const XCHAL_HAVE_FUSION_LOW_POWER: u32 = 0;
pub const XCHAL_HAVE_FUSION_AES: u32 = 0;
pub const XCHAL_HAVE_FUSION_CONVENC: u32 = 0;
pub const XCHAL_HAVE_FUSION_LFSR_CRC: u32 = 0;
pub const XCHAL_HAVE_FUSION_BITOPS: u32 = 0;
pub const XCHAL_HAVE_FUSION_AVS: u32 = 0;
pub const XCHAL_HAVE_FUSION_16BIT_BASEBAND: u32 = 0;
pub const XCHAL_HAVE_FUSION_VITERBI: u32 = 0;
pub const XCHAL_HAVE_FUSION_SOFTDEMAP: u32 = 0;
pub const XCHAL_HAVE_HIFIPRO: u32 = 0;
pub const XCHAL_HAVE_HIFI4: u32 = 0;
pub const XCHAL_HAVE_HIFI4_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI3: u32 = 0;
pub const XCHAL_HAVE_HIFI3_VFPU: u32 = 0;
pub const XCHAL_HAVE_HIFI2: u32 = 0;
pub const XCHAL_HAVE_HIFI2EP: u32 = 0;
pub const XCHAL_HAVE_HIFI_MINI: u32 = 0;
pub const XCHAL_HAVE_VECTORFPU2005: u32 = 0;
pub const XCHAL_HAVE_USER_DPFPU: u32 = 0;
pub const XCHAL_HAVE_USER_SPFPU: u32 = 0;
pub const XCHAL_HAVE_FP: u32 = 1;
pub const XCHAL_HAVE_FP_DIV: u32 = 1;
pub const XCHAL_HAVE_FP_RECIP: u32 = 1;
pub const XCHAL_HAVE_FP_SQRT: u32 = 1;
pub const XCHAL_HAVE_FP_RSQRT: u32 = 1;
pub const XCHAL_HAVE_DFP: u32 = 0;
pub const XCHAL_HAVE_DFP_DIV: u32 = 0;
pub const XCHAL_HAVE_DFP_RECIP: u32 = 0;
pub const XCHAL_HAVE_DFP_SQRT: u32 = 0;
pub const XCHAL_HAVE_DFP_RSQRT: u32 = 0;
pub const XCHAL_HAVE_DFP_ACCEL: u32 = 1;
pub const XCHAL_HAVE_DFP_accel: u32 = 1;
pub const XCHAL_HAVE_DFPU_SINGLE_ONLY: u32 = 1;
pub const XCHAL_HAVE_DFPU_SINGLE_DOUBLE: u32 = 0;
pub const XCHAL_HAVE_VECTRA1: u32 = 0;
pub const XCHAL_HAVE_VECTRALX: u32 = 0;
pub const XCHAL_HAVE_PDX4: u32 = 0;
pub const XCHAL_HAVE_CONNXD2: u32 = 0;
pub const XCHAL_HAVE_CONNXD2_DUALLSFLIX: u32 = 0;
pub const XCHAL_HAVE_BBE16: u32 = 0;
pub const XCHAL_HAVE_BBE16_RSQRT: u32 = 0;
pub const XCHAL_HAVE_BBE16_VECDIV: u32 = 0;
pub const XCHAL_HAVE_BBE16_DESPREAD: u32 = 0;
pub const XCHAL_HAVE_BBENEP: u32 = 0;
pub const XCHAL_HAVE_BSP3: u32 = 0;
pub const XCHAL_HAVE_BSP3_TRANSPOSE: u32 = 0;
pub const XCHAL_HAVE_SSP16: u32 = 0;
pub const XCHAL_HAVE_SSP16_VITERBI: u32 = 0;
pub const XCHAL_HAVE_TURBO16: u32 = 0;
pub const XCHAL_HAVE_BBP16: u32 = 0;
pub const XCHAL_HAVE_FLIX3: u32 = 0;
pub const XCHAL_HAVE_GRIVPEP: u32 = 0;
pub const XCHAL_HAVE_GRIVPEP_HISTOGRAM: u32 = 0;
pub const XCHAL_NUM_LOADSTORE_UNITS: u32 = 1;
pub const XCHAL_NUM_WRITEBUFFER_ENTRIES: u32 = 4;
pub const XCHAL_INST_FETCH_WIDTH: u32 = 4;
pub const XCHAL_DATA_WIDTH: u32 = 4;
pub const XCHAL_DATA_PIPE_DELAY: u32 = 2;
pub const XCHAL_CLOCK_GATING_GLOBAL: u32 = 1;
pub const XCHAL_CLOCK_GATING_FUNCUNIT: u32 = 1;
pub const XCHAL_UNALIGNED_LOAD_EXCEPTION: u32 = 0;
pub const XCHAL_UNALIGNED_STORE_EXCEPTION: u32 = 0;
pub const XCHAL_UNALIGNED_LOAD_HW: u32 = 1;
pub const XCHAL_UNALIGNED_STORE_HW: u32 = 1;
pub const XCHAL_SW_VERSION: u32 = 1100003;
pub const XCHAL_CORE_ID: &'static [u8; 17usize] = b"esp32_v3_49_prod\0";
pub const XCHAL_BUILD_UNIQUE_ID: u32 = 392854;
pub const XCHAL_HW_CONFIGID0: u32 = 3267166206;
pub const XCHAL_HW_CONFIGID1: u32 = 482737814;
pub const XCHAL_HW_VERSION_NAME: &'static [u8; 8usize] = b"LX6.0.3\0";
pub const XCHAL_HW_VERSION_MAJOR: u32 = 2600;
pub const XCHAL_HW_VERSION_MINOR: u32 = 3;
pub const XCHAL_HW_VERSION: u32 = 260003;
pub const XCHAL_HW_REL_LX6: u32 = 1;
pub const XCHAL_HW_REL_LX6_0: u32 = 1;
pub const XCHAL_HW_REL_LX6_0_3: u32 = 1;
pub const XCHAL_HW_CONFIGID_RELIABLE: u32 = 1;
pub const XCHAL_HW_MIN_VERSION_MAJOR: u32 = 2600;
pub const XCHAL_HW_MIN_VERSION_MINOR: u32 = 3;
pub const XCHAL_HW_MIN_VERSION: u32 = 260003;
pub const XCHAL_HW_MAX_VERSION_MAJOR: u32 = 2600;
pub const XCHAL_HW_MAX_VERSION_MINOR: u32 = 3;
pub const XCHAL_HW_MAX_VERSION: u32 = 260003;
pub const XCHAL_ICACHE_LINESIZE: u32 = 4;
pub const XCHAL_DCACHE_LINESIZE: u32 = 4;
pub const XCHAL_ICACHE_LINEWIDTH: u32 = 2;
pub const XCHAL_DCACHE_LINEWIDTH: u32 = 2;
pub const XCHAL_ICACHE_SIZE: u32 = 0;
pub const XCHAL_DCACHE_SIZE: u32 = 0;
pub const XCHAL_DCACHE_IS_WRITEBACK: u32 = 0;
pub const XCHAL_DCACHE_IS_COHERENT: u32 = 0;
pub const XCHAL_HAVE_PREFETCH: u32 = 0;
pub const XCHAL_HAVE_PREFETCH_L1: u32 = 0;
pub const XCHAL_PREFETCH_CASTOUT_LINES: u32 = 0;
pub const XCHAL_PREFETCH_ENTRIES: u32 = 0;
pub const XCHAL_PREFETCH_BLOCK_ENTRIES: u32 = 0;
pub const XCHAL_HAVE_CACHE_BLOCKOPS: u32 = 0;
pub const XCHAL_HAVE_ICACHE_TEST: u32 = 0;
pub const XCHAL_HAVE_DCACHE_TEST: u32 = 0;
pub const XCHAL_HAVE_ICACHE_DYN_WAYS: u32 = 0;
pub const XCHAL_HAVE_DCACHE_DYN_WAYS: u32 = 0;
pub const XCHAL_HAVE_PIF: u32 = 1;
pub const XCHAL_HAVE_AXI: u32 = 0;
pub const XCHAL_HAVE_PIF_WR_RESP: u32 = 0;
pub const XCHAL_HAVE_PIF_REQ_ATTR: u32 = 0;
pub const XCHAL_ICACHE_SETWIDTH: u32 = 0;
pub const XCHAL_DCACHE_SETWIDTH: u32 = 0;
pub const XCHAL_ICACHE_WAYS: u32 = 1;
pub const XCHAL_DCACHE_WAYS: u32 = 1;
pub const XCHAL_ICACHE_LINE_LOCKABLE: u32 = 0;
pub const XCHAL_DCACHE_LINE_LOCKABLE: u32 = 0;
pub const XCHAL_ICACHE_ECC_PARITY: u32 = 0;
pub const XCHAL_DCACHE_ECC_PARITY: u32 = 0;
pub const XCHAL_ICACHE_ACCESS_SIZE: u32 = 1;
pub const XCHAL_DCACHE_ACCESS_SIZE: u32 = 1;
pub const XCHAL_DCACHE_BANKS: u32 = 0;
pub const XCHAL_CA_BITS: u32 = 4;
pub const XCHAL_NUM_INSTROM: u32 = 1;
pub const XCHAL_NUM_INSTRAM: u32 = 2;
pub const XCHAL_NUM_DATAROM: u32 = 1;
pub const XCHAL_NUM_DATARAM: u32 = 2;
pub const XCHAL_NUM_URAM: u32 = 0;
pub const XCHAL_NUM_XLMI: u32 = 1;
pub const XCHAL_INSTROM0_VADDR: u32 = 1082130432;
pub const XCHAL_INSTROM0_PADDR: u32 = 1082130432;
pub const XCHAL_INSTROM0_SIZE: u32 = 4194304;
pub const XCHAL_INSTROM0_ECC_PARITY: u32 = 0;
pub const XCHAL_INSTRAM0_VADDR: u32 = 1073741824;
pub const XCHAL_INSTRAM0_PADDR: u32 = 1073741824;
pub const XCHAL_INSTRAM0_SIZE: u32 = 4194304;
pub const XCHAL_INSTRAM0_ECC_PARITY: u32 = 0;
pub const XCHAL_INSTRAM1_VADDR: u32 = 1077936128;
pub const XCHAL_INSTRAM1_PADDR: u32 = 1077936128;
pub const XCHAL_INSTRAM1_SIZE: u32 = 4194304;
pub const XCHAL_INSTRAM1_ECC_PARITY: u32 = 0;
pub const XCHAL_DATAROM0_VADDR: u32 = 1061158912;
pub const XCHAL_DATAROM0_PADDR: u32 = 1061158912;
pub const XCHAL_DATAROM0_SIZE: u32 = 4194304;
pub const XCHAL_DATAROM0_ECC_PARITY: u32 = 0;
pub const XCHAL_DATAROM0_BANKS: u32 = 1;
pub const XCHAL_DATARAM0_VADDR: u32 = 1073217536;
pub const XCHAL_DATARAM0_PADDR: u32 = 1073217536;
pub const XCHAL_DATARAM0_SIZE: u32 = 524288;
pub const XCHAL_DATARAM0_ECC_PARITY: u32 = 0;
pub const XCHAL_DATARAM0_BANKS: u32 = 1;
pub const XCHAL_DATARAM1_VADDR: u32 = 1065353216;
pub const XCHAL_DATARAM1_PADDR: u32 = 1065353216;
pub const XCHAL_DATARAM1_SIZE: u32 = 4194304;
pub const XCHAL_DATARAM1_ECC_PARITY: u32 = 0;
pub const XCHAL_DATARAM1_BANKS: u32 = 1;
pub const XCHAL_XLMI0_VADDR: u32 = 1072693248;
pub const XCHAL_XLMI0_PADDR: u32 = 1072693248;
pub const XCHAL_XLMI0_SIZE: u32 = 524288;
pub const XCHAL_XLMI0_ECC_PARITY: u32 = 0;
pub const XCHAL_HAVE_IMEM_LOADSTORE: u32 = 1;
pub const XCHAL_HAVE_INTERRUPTS: u32 = 1;
pub const XCHAL_HAVE_HIGHPRI_INTERRUPTS: u32 = 1;
pub const XCHAL_HAVE_NMI: u32 = 1;
pub const XCHAL_HAVE_CCOUNT: u32 = 1;
pub const XCHAL_NUM_TIMERS: u32 = 3;
pub const XCHAL_NUM_INTERRUPTS: u32 = 32;
pub const XCHAL_NUM_INTERRUPTS_LOG2: u32 = 5;
pub const XCHAL_NUM_EXTINTERRUPTS: u32 = 26;
pub const XCHAL_NUM_INTLEVELS: u32 = 6;
pub const XCHAL_EXCM_LEVEL: u32 = 3;
pub const XCHAL_INTLEVEL1_MASK: u32 = 407551;
pub const XCHAL_INTLEVEL2_MASK: u32 = 3670016;
pub const XCHAL_INTLEVEL3_MASK: u32 = 683706368;
pub const XCHAL_INTLEVEL4_MASK: u32 = 1392508928;
pub const XCHAL_INTLEVEL5_MASK: u32 = 2214658048;
pub const XCHAL_INTLEVEL6_MASK: u32 = 0;
pub const XCHAL_INTLEVEL7_MASK: u32 = 16384;
pub const XCHAL_INTLEVEL1_ANDBELOW_MASK: u32 = 407551;
pub const XCHAL_INTLEVEL2_ANDBELOW_MASK: u32 = 4077567;
pub const XCHAL_INTLEVEL3_ANDBELOW_MASK: u32 = 687783935;
pub const XCHAL_INTLEVEL4_ANDBELOW_MASK: u32 = 2080292863;
pub const XCHAL_INTLEVEL5_ANDBELOW_MASK: u32 = 4294950911;
pub const XCHAL_INTLEVEL6_ANDBELOW_MASK: u32 = 4294950911;
pub const XCHAL_INTLEVEL7_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INT0_LEVEL: u32 = 1;
pub const XCHAL_INT1_LEVEL: u32 = 1;
pub const XCHAL_INT2_LEVEL: u32 = 1;
pub const XCHAL_INT3_LEVEL: u32 = 1;
pub const XCHAL_INT4_LEVEL: u32 = 1;
pub const XCHAL_INT5_LEVEL: u32 = 1;
pub const XCHAL_INT6_LEVEL: u32 = 1;
pub const XCHAL_INT7_LEVEL: u32 = 1;
pub const XCHAL_INT8_LEVEL: u32 = 1;
pub const XCHAL_INT9_LEVEL: u32 = 1;
pub const XCHAL_INT10_LEVEL: u32 = 1;
pub const XCHAL_INT11_LEVEL: u32 = 3;
pub const XCHAL_INT12_LEVEL: u32 = 1;
pub const XCHAL_INT13_LEVEL: u32 = 1;
pub const XCHAL_INT14_LEVEL: u32 = 7;
pub const XCHAL_INT15_LEVEL: u32 = 3;
pub const XCHAL_INT16_LEVEL: u32 = 5;
pub const XCHAL_INT17_LEVEL: u32 = 1;
pub const XCHAL_INT18_LEVEL: u32 = 1;
pub const XCHAL_INT19_LEVEL: u32 = 2;
pub const XCHAL_INT20_LEVEL: u32 = 2;
pub const XCHAL_INT21_LEVEL: u32 = 2;
pub const XCHAL_INT22_LEVEL: u32 = 3;
pub const XCHAL_INT23_LEVEL: u32 = 3;
pub const XCHAL_INT24_LEVEL: u32 = 4;
pub const XCHAL_INT25_LEVEL: u32 = 4;
pub const XCHAL_INT26_LEVEL: u32 = 5;
pub const XCHAL_INT27_LEVEL: u32 = 3;
pub const XCHAL_INT28_LEVEL: u32 = 4;
pub const XCHAL_INT29_LEVEL: u32 = 3;
pub const XCHAL_INT30_LEVEL: u32 = 4;
pub const XCHAL_INT31_LEVEL: u32 = 5;
pub const XCHAL_DEBUGLEVEL: u32 = 6;
pub const XCHAL_HAVE_DEBUG_EXTERN_INT: u32 = 1;
pub const XCHAL_NMILEVEL: u32 = 7;
pub const XCHAL_INTTYPE_MASK_UNCONFIGURED: u32 = 0;
pub const XCHAL_INTTYPE_MASK_SOFTWARE: u32 = 536871040;
pub const XCHAL_INTTYPE_MASK_EXTERN_EDGE: u32 = 1346372608;
pub const XCHAL_INTTYPE_MASK_EXTERN_LEVEL: u32 = 2411606847;
pub const XCHAL_INTTYPE_MASK_TIMER: u32 = 98368;
pub const XCHAL_INTTYPE_MASK_NMI: u32 = 16384;
pub const XCHAL_INTTYPE_MASK_WRITE_ERROR: u32 = 0;
pub const XCHAL_INTTYPE_MASK_PROFILING: u32 = 2048;
pub const XCHAL_TIMER0_INTERRUPT: u32 = 6;
pub const XCHAL_TIMER1_INTERRUPT: u32 = 15;
pub const XCHAL_TIMER2_INTERRUPT: u32 = 16;
pub const XCHAL_NMI_INTERRUPT: u32 = 14;
pub const XCHAL_PROFILING_INTERRUPT: u32 = 11;
pub const XCHAL_INTLEVEL7_NUM: u32 = 14;
pub const XCHAL_EXTINT0_NUM: u32 = 0;
pub const XCHAL_EXTINT1_NUM: u32 = 1;
pub const XCHAL_EXTINT2_NUM: u32 = 2;
pub const XCHAL_EXTINT3_NUM: u32 = 3;
pub const XCHAL_EXTINT4_NUM: u32 = 4;
pub const XCHAL_EXTINT5_NUM: u32 = 5;
pub const XCHAL_EXTINT6_NUM: u32 = 8;
pub const XCHAL_EXTINT7_NUM: u32 = 9;
pub const XCHAL_EXTINT8_NUM: u32 = 10;
pub const XCHAL_EXTINT9_NUM: u32 = 12;
pub const XCHAL_EXTINT10_NUM: u32 = 13;
pub const XCHAL_EXTINT11_NUM: u32 = 14;
pub const XCHAL_EXTINT12_NUM: u32 = 17;
pub const XCHAL_EXTINT13_NUM: u32 = 18;
pub const XCHAL_EXTINT14_NUM: u32 = 19;
pub const XCHAL_EXTINT15_NUM: u32 = 20;
pub const XCHAL_EXTINT16_NUM: u32 = 21;
pub const XCHAL_EXTINT17_NUM: u32 = 22;
pub const XCHAL_EXTINT18_NUM: u32 = 23;
pub const XCHAL_EXTINT19_NUM: u32 = 24;
pub const XCHAL_EXTINT20_NUM: u32 = 25;
pub const XCHAL_EXTINT21_NUM: u32 = 26;
pub const XCHAL_EXTINT22_NUM: u32 = 27;
pub const XCHAL_EXTINT23_NUM: u32 = 28;
pub const XCHAL_EXTINT24_NUM: u32 = 30;
pub const XCHAL_EXTINT25_NUM: u32 = 31;
pub const XCHAL_INT0_EXTNUM: u32 = 0;
pub const XCHAL_INT1_EXTNUM: u32 = 1;
pub const XCHAL_INT2_EXTNUM: u32 = 2;
pub const XCHAL_INT3_EXTNUM: u32 = 3;
pub const XCHAL_INT4_EXTNUM: u32 = 4;
pub const XCHAL_INT5_EXTNUM: u32 = 5;
pub const XCHAL_INT8_EXTNUM: u32 = 6;
pub const XCHAL_INT9_EXTNUM: u32 = 7;
pub const XCHAL_INT10_EXTNUM: u32 = 8;
pub const XCHAL_INT12_EXTNUM: u32 = 9;
pub const XCHAL_INT13_EXTNUM: u32 = 10;
pub const XCHAL_INT14_EXTNUM: u32 = 11;
pub const XCHAL_INT17_EXTNUM: u32 = 12;
pub const XCHAL_INT18_EXTNUM: u32 = 13;
pub const XCHAL_INT19_EXTNUM: u32 = 14;
pub const XCHAL_INT20_EXTNUM: u32 = 15;
pub const XCHAL_INT21_EXTNUM: u32 = 16;
pub const XCHAL_INT22_EXTNUM: u32 = 17;
pub const XCHAL_INT23_EXTNUM: u32 = 18;
pub const XCHAL_INT24_EXTNUM: u32 = 19;
pub const XCHAL_INT25_EXTNUM: u32 = 20;
pub const XCHAL_INT26_EXTNUM: u32 = 21;
pub const XCHAL_INT27_EXTNUM: u32 = 22;
pub const XCHAL_INT28_EXTNUM: u32 = 23;
pub const XCHAL_INT30_EXTNUM: u32 = 24;
pub const XCHAL_INT31_EXTNUM: u32 = 25;
pub const XCHAL_XEA_VERSION: u32 = 2;
pub const XCHAL_HAVE_XEA1: u32 = 0;
pub const XCHAL_HAVE_XEA2: u32 = 1;
pub const XCHAL_HAVE_XEAX: u32 = 0;
pub const XCHAL_HAVE_EXCEPTIONS: u32 = 1;
pub const XCHAL_HAVE_HALT: u32 = 0;
pub const XCHAL_HAVE_BOOTLOADER: u32 = 0;
pub const XCHAL_HAVE_MEM_ECC_PARITY: u32 = 0;
pub const XCHAL_HAVE_VECTOR_SELECT: u32 = 1;
pub const XCHAL_HAVE_VECBASE: u32 = 1;
pub const XCHAL_VECBASE_RESET_VADDR: u32 = 1073741824;
pub const XCHAL_VECBASE_RESET_PADDR: u32 = 1073741824;
pub const XCHAL_RESET_VECBASE_OVERLAP: u32 = 0;
pub const XCHAL_RESET_VECTOR0_VADDR: u32 = 1342177280;
pub const XCHAL_RESET_VECTOR0_PADDR: u32 = 1342177280;
pub const XCHAL_RESET_VECTOR1_VADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR1_PADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR_VADDR: u32 = 1073742848;
pub const XCHAL_RESET_VECTOR_PADDR: u32 = 1073742848;
pub const XCHAL_USER_VECOFS: u32 = 832;
pub const XCHAL_USER_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_USER_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_KERNEL_VECOFS: u32 = 768;
pub const XCHAL_KERNEL_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_KERNEL_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_DOUBLEEXC_VECOFS: u32 = 960;
pub const XCHAL_DOUBLEEXC_VECTOR_VADDR: u32 = 1073742784;
pub const XCHAL_DOUBLEEXC_VECTOR_PADDR: u32 = 1073742784;
pub const XCHAL_WINDOW_OF4_VECOFS: u32 = 0;
pub const XCHAL_WINDOW_UF4_VECOFS: u32 = 64;
pub const XCHAL_WINDOW_OF8_VECOFS: u32 = 128;
pub const XCHAL_WINDOW_UF8_VECOFS: u32 = 192;
pub const XCHAL_WINDOW_OF12_VECOFS: u32 = 256;
pub const XCHAL_WINDOW_UF12_VECOFS: u32 = 320;
pub const XCHAL_WINDOW_VECTORS_VADDR: u32 = 1073741824;
pub const XCHAL_WINDOW_VECTORS_PADDR: u32 = 1073741824;
pub const XCHAL_INTLEVEL2_VECOFS: u32 = 384;
pub const XCHAL_INTLEVEL2_VECTOR_VADDR: u32 = 1073742208;
pub const XCHAL_INTLEVEL2_VECTOR_PADDR: u32 = 1073742208;
pub const XCHAL_INTLEVEL3_VECOFS: u32 = 448;
pub const XCHAL_INTLEVEL3_VECTOR_VADDR: u32 = 1073742272;
pub const XCHAL_INTLEVEL3_VECTOR_PADDR: u32 = 1073742272;
pub const XCHAL_INTLEVEL4_VECOFS: u32 = 512;
pub const XCHAL_INTLEVEL4_VECTOR_VADDR: u32 = 1073742336;
pub const XCHAL_INTLEVEL4_VECTOR_PADDR: u32 = 1073742336;
pub const XCHAL_INTLEVEL5_VECOFS: u32 = 576;
pub const XCHAL_INTLEVEL5_VECTOR_VADDR: u32 = 1073742400;
pub const XCHAL_INTLEVEL5_VECTOR_PADDR: u32 = 1073742400;
pub const XCHAL_INTLEVEL6_VECOFS: u32 = 640;
pub const XCHAL_INTLEVEL6_VECTOR_VADDR: u32 = 1073742464;
pub const XCHAL_INTLEVEL6_VECTOR_PADDR: u32 = 1073742464;
pub const XCHAL_DEBUG_VECOFS: u32 = 640;
pub const XCHAL_DEBUG_VECTOR_VADDR: u32 = 1073742464;
pub const XCHAL_DEBUG_VECTOR_PADDR: u32 = 1073742464;
pub const XCHAL_NMI_VECOFS: u32 = 704;
pub const XCHAL_NMI_VECTOR_VADDR: u32 = 1073742528;
pub const XCHAL_NMI_VECTOR_PADDR: u32 = 1073742528;
pub const XCHAL_INTLEVEL7_VECOFS: u32 = 704;
pub const XCHAL_INTLEVEL7_VECTOR_VADDR: u32 = 1073742528;
pub const XCHAL_INTLEVEL7_VECTOR_PADDR: u32 = 1073742528;
pub const XCHAL_HAVE_DEBUG_ERI: u32 = 1;
pub const XCHAL_HAVE_DEBUG_APB: u32 = 1;
pub const XCHAL_HAVE_DEBUG_JTAG: u32 = 1;
pub const XCHAL_HAVE_OCD: u32 = 1;
pub const XCHAL_NUM_IBREAK: u32 = 2;
pub const XCHAL_NUM_DBREAK: u32 = 2;
pub const XCHAL_HAVE_OCD_DIR_ARRAY: u32 = 0;
pub const XCHAL_HAVE_OCD_LS32DDR: u32 = 1;
pub const XCHAL_HAVE_TRAX: u32 = 1;
pub const XCHAL_TRAX_MEM_SIZE: u32 = 16384;
pub const XCHAL_TRAX_MEM_SHAREABLE: u32 = 1;
pub const XCHAL_TRAX_ATB_WIDTH: u32 = 32;
pub const XCHAL_TRAX_TIME_WIDTH: u32 = 0;
pub const XCHAL_NUM_PERF_COUNTERS: u32 = 2;
pub const XCHAL_HAVE_TLBS: u32 = 1;
pub const XCHAL_HAVE_SPANNING_WAY: u32 = 1;
pub const XCHAL_SPANNING_WAY: u32 = 0;
pub const XCHAL_HAVE_IDENTITY_MAP: u32 = 1;
pub const XCHAL_HAVE_CACHEATTR: u32 = 0;
pub const XCHAL_HAVE_MIMIC_CACHEATTR: u32 = 1;
pub const XCHAL_HAVE_XLT_CACHEATTR: u32 = 0;
pub const XCHAL_HAVE_PTP_MMU: u32 = 0;
pub const XCHAL_MMU_ASID_BITS: u32 = 0;
pub const XCHAL_MMU_RINGS: u32 = 1;
pub const XCHAL_MMU_RING_BITS: u32 = 0;
pub const __BUFSIZ__: u32 = 128;
pub const __RAND_MAX: u32 = 2147483647;
pub const ___int8_t_defined: u32 = 1;
pub const ___int16_t_defined: u32 = 1;
pub const ___int32_t_defined: u32 = 1;
pub const ___int64_t_defined: u32 = 1;
pub const _NULL: u32 = 0;
pub const _ATEXIT_SIZE: u32 = 32;
pub const _RAND48_SEED_0: u32 = 13070;
pub const _RAND48_SEED_1: u32 = 43981;
pub const _RAND48_SEED_2: u32 = 4660;
pub const _RAND48_MULT_0: u32 = 58989;
pub const _RAND48_MULT_1: u32 = 57068;
pub const _RAND48_MULT_2: u32 = 5;
pub const _RAND48_ADD: u32 = 11;
pub const _REENT_EMERGENCY_SIZE: u32 = 25;
pub const _REENT_ASCTIME_SIZE: u32 = 26;
pub const _REENT_SIGNAL_SIZE: u32 = 24;
pub const __have_longlong64: u32 = 1;
pub const __int8_t_defined: u32 = 1;
pub const __int_least8_t_defined: u32 = 1;
pub const __int16_t_defined: u32 = 1;
pub const __int_least16_t_defined: u32 = 1;
pub const __int32_t_defined: u32 = 1;
pub const __int_least32_t_defined: u32 = 1;
pub const __int64_t_defined: u32 = 1;
pub const __int_least64_t_defined: u32 = 1;
pub const __int_fast8_t_defined: u32 = 1;
pub const __int_fast16_t_defined: u32 = 1;
pub const __int_fast32_t_defined: u32 = 1;
pub const __int_fast64_t_defined: u32 = 1;
pub const WINT_MIN: u32 = 0;
pub const CONFIG_ESP32_PHY_MAX_TX_POWER: u32 = 20;
pub const CONFIG_TRACEMEM_RESERVE_DRAM: u32 = 0;
pub const CONFIG_FREERTOS_MAX_TASK_NAME_LEN: u32 = 16;
pub const CONFIG_MQTT_TRANSPORT_SSL: u32 = 1;
pub const CONFIG_FATFS_LFN_NONE: u32 = 1;
pub const CONFIG_MB_SERIAL_TASK_PRIO: u32 = 10;
pub const CONFIG_MQTT_PROTOCOL_311: u32 = 1;
pub const CONFIG_TCP_RECVMBOX_SIZE: u32 = 6;
pub const CONFIG_FATFS_CODEPAGE_437: u32 = 1;
pub const CONFIG_TCP_WND_DEFAULT: u32 = 5744;
pub const CONFIG_PARTITION_TABLE_OFFSET: u32 = 32768;
pub const CONFIG_SPIFFS_USE_MAGIC_LENGTH: u32 = 1;
pub const CONFIG_IPC_TASK_STACK_SIZE: u32 = 1024;
pub const CONFIG_FATFS_PER_FILE_CACHE: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHFREQ: &'static [u8; 4usize] = b"40m\0";
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_RSA: u32 = 1;
pub const CONFIG_UDP_RECVMBOX_SIZE: u32 = 6;
pub const CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE: u32 = 0;
pub const CONFIG_MBEDTLS_AES_C: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED: u32 = 1;
pub const CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN: u32 = 752;
pub const CONFIG_MBEDTLS_GCM_C: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHSIZE: &'static [u8; 4usize] = b"2MB\0";
pub const CONFIG_HEAP_POISONING_DISABLED: u32 = 1;
pub const CONFIG_SPIFFS_CACHE_WR: u32 = 1;
pub const CONFIG_BROWNOUT_DET_LVL_SEL_0: u32 = 1;
pub const CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER: u32 = 1;
pub const CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE: u32 = 1;
pub const CONFIG_SPIFFS_CACHE: u32 = 1;
pub const CONFIG_INT_WDT: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1: u32 = 1;
pub const CONFIG_ESP_GRATUITOUS_ARP: u32 = 1;
pub const CONFIG_MBEDTLS_ECDSA_C: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHFREQ_40M: u32 = 1;
pub const CONFIG_LOG_BOOTLOADER_LEVEL_INFO: u32 = 1;
pub const CONFIG_ESPTOOLPY_FLASHSIZE_2MB: u32 = 1;
pub const CONFIG_HTTPD_MAX_REQ_HDR_LEN: u32 = 512;
pub const CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE: u32 = 0;
pub const CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS: u32 = 1;
pub const CONFIG_MBEDTLS_ECDH_C: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE: u32 = 1;
pub const CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM: u32 = 10;
pub const CONFIG_MBEDTLS_SSL_ALPN: u32 = 1;
pub const CONFIG_MBEDTLS_PEM_WRITE_C: u32 = 1;
pub const CONFIG_LOG_DEFAULT_LEVEL_INFO: u32 = 1;
pub const CONFIG_BT_RESERVE_DRAM: u32 = 0;
pub const CONFIG_FATFS_FS_LOCK: u32 = 0;
pub const CONFIG_IP_LOST_TIMER_INTERVAL: u32 = 120;
pub const CONFIG_SPIFFS_META_LENGTH: u32 = 4;
pub const CONFIG_ESP32_PANIC_PRINT_REBOOT: u32 = 1;
pub const CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE: u32 = 20;
pub const CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED: u32 = 1;
pub const CONFIG_MB_SERIAL_BUF_SIZE: u32 = 256;
pub const CONFIG_CONSOLE_UART_BAUDRATE: u32 = 115200;
pub const CONFIG_LWIP_MAX_SOCKETS: u32 = 10;
pub const CONFIG_LWIP_NETIF_LOOPBACK: u32 = 1;
pub const CONFIG_EMAC_TASK_PRIORITY: u32 = 20;
pub const CONFIG_TIMER_TASK_STACK_DEPTH: u32 = 2048;
pub const CONFIG_TCP_MSS: u32 = 1436;
pub const CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED: u32 = 1;
pub const CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF: u32 = 0;
pub const CONFIG_FATFS_CODEPAGE: u32 = 437;
pub const CONFIG_ESP32_DEFAULT_CPU_FREQ_160: u32 = 1;
pub const CONFIG_ULP_COPROC_RESERVE_MEM: u32 = 0;
pub const CONFIG_LWIP_MAX_UDP_PCBS: u32 = 16;
pub const CONFIG_ESPTOOLPY_BAUD: u32 = 115200;
pub const CONFIG_INT_WDT_CHECK_CPU1: u32 = 1;
pub const CONFIG_ADC_CAL_LUT_ENABLE: u32 = 1;
pub const CONFIG_FLASHMODE_DIO: u32 = 1;
pub const CONFIG_ESPTOOLPY_AFTER_RESET: u32 = 1;
pub const CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED: u32 = 1;
pub const CONFIG_LWIP_DHCPS_MAX_STATION_NUM: u32 = 8;
pub const CONFIG_TOOLPREFIX: &'static [u8; 18usize] = b"xtensa-esp32-elf-\0";
pub const CONFIG_MBEDTLS_ECP_C: u32 = 1;
pub const CONFIG_FREERTOS_IDLE_TASK_STACKSIZE: u32 = 1536;
pub const CONFIG_MBEDTLS_RC4_DISABLED: u32 = 1;
pub const CONFIG_CONSOLE_UART_NUM: u32 = 0;
pub const CONFIG_ESP32_APPTRACE_LOCK_ENABLE: u32 = 1;
pub const CONFIG_PTHREAD_STACK_MIN: u32 = 768;
pub const CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC: u32 = 1;
pub const CONFIG_ESPTOOLPY_BAUD_115200B: u32 = 1;
pub const CONFIG_TCP_OVERSIZE_MSS: u32 = 1;
pub const CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS: u32 = 1;
pub const CONFIG_CONSOLE_UART_DEFAULT: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN: u32 = 16384;
pub const CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS: u32 = 4;
pub const CONFIG_ESPTOOLPY_FLASHSIZE_DETECT: u32 = 1;
pub const CONFIG_TIMER_TASK_STACK_SIZE: u32 = 3584;
pub const CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE: u32 = 1;
pub const CONFIG_MBEDTLS_X509_CRL_PARSE_C: u32 = 1;
pub const CONFIG_MB_SERIAL_TASK_STACK_SIZE: u32 = 2048;
pub const CONFIG_LWIP_DHCPS_LEASE_UNIT: u32 = 60;
pub const CONFIG_SPIFFS_USE_MAGIC: u32 = 1;
pub const CONFIG_TCPIP_TASK_STACK_SIZE: u32 = 3072;
pub const CONFIG_TASK_WDT: u32 = 1;
pub const CONFIG_MAIN_TASK_STACK_SIZE: u32 = 3584;
pub const CONFIG_SPIFFS_PAGE_CHECK: u32 = 1;
pub const CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0: u32 = 1;
pub const CONFIG_LWIP_MAX_ACTIVE_TCP: u32 = 16;
pub const CONFIG_TASK_WDT_TIMEOUT_S: u32 = 5;
pub const CONFIG_INT_WDT_TIMEOUT_MS: u32 = 300;
pub const CONFIG_ESPTOOLPY_FLASHMODE: &'static [u8; 4usize] = b"dio\0";
pub const CONFIG_NEWLIB_STDIN_LINE_ENDING_CR: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA: u32 = 1;
pub const CONFIG_ESPTOOLPY_BEFORE: &'static [u8; 14usize] = b"default_reset\0";
pub const CONFIG_ADC2_DISABLE_DAC: u32 = 1;
pub const CONFIG_LOG_DEFAULT_LEVEL: u32 = 3;
pub const CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION: u32 = 1;
pub const CONFIG_TIMER_QUEUE_LENGTH: u32 = 10;
pub const CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT: u32 = 1;
pub const CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY: u32 = 1;
pub const CONFIG_MAKE_WARN_UNDEFINED_VARIABLES: u32 = 1;
pub const CONFIG_FATFS_TIMEOUT_MS: u32 = 10000;
pub const CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM: u32 = 32;
pub const CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS: u32 = 1;
pub const CONFIG_MBEDTLS_CCM_C: u32 = 1;
pub const CONFIG_SPI_MASTER_ISR_IN_IRAM: u32 = 1;
pub const CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER: u32 = 20;
pub const CONFIG_ESP32_RTC_CLK_CAL_CYCLES: u32 = 1024;
pub const CONFIG_ESP32_WIFI_TX_BA_WIN: u32 = 6;
pub const CONFIG_ESP32_WIFI_NVS_ENABLED: u32 = 1;
pub const CONFIG_MDNS_MAX_SERVICES: u32 = 10;
pub const CONFIG_EMAC_CHECK_LINK_PERIOD_MS: u32 = 2000;
pub const CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED: u32 = 1;
pub const CONFIG_LIBSODIUM_USE_MBEDTLS_SHA: u32 = 1;
pub const CONFIG_DMA_RX_BUF_NUM: u32 = 10;
pub const CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED: u32 = 1;
pub const CONFIG_TCP_SYNMAXRTX: u32 = 6;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: u32 = 1;
pub const CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF: u32 = 0;
pub const CONFIG_PYTHON: &'static [u8; 7usize] = b"python\0";
pub const CONFIG_MBEDTLS_ECP_NIST_OPTIM: u32 = 1;
pub const CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1: u32 = 1;
pub const CONFIG_ESPTOOLPY_COMPRESSED: u32 = 1;
pub const CONFIG_PARTITION_TABLE_FILENAME: &'static [u8; 25usize] = b"partitions_singleapp.csv\0";
pub const CONFIG_MB_CONTROLLER_STACK_SIZE: u32 = 4096;
pub const CONFIG_TCP_SND_BUF_DEFAULT: u32 = 5744;
pub const CONFIG_GARP_TMR_INTERVAL: u32 = 60;
pub const CONFIG_LWIP_DHCP_MAX_NTP_SERVERS: u32 = 1;
pub const CONFIG_TCP_MSL: u32 = 60000;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1_1: u32 = 1;
pub const CONFIG_LWIP_SO_REUSE_RXTOALL: u32 = 1;
pub const CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT: u32 = 20;
pub const CONFIG_ESP32_WIFI_MGMT_SBUF_NUM: u32 = 32;
pub const CONFIG_PARTITION_TABLE_SINGLE_APP: u32 = 1;
pub const CONFIG_ESP32_WIFI_RX_BA_WIN: u32 = 6;
pub const CONFIG_MBEDTLS_X509_CSR_PARSE_C: u32 = 1;
pub const CONFIG_SPIFFS_USE_MTIME: u32 = 1;
pub const CONFIG_EMAC_TASK_STACK_SIZE: u32 = 3072;
pub const CONFIG_MB_QUEUE_LENGTH: u32 = 20;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: u32 = 1;
pub const CONFIG_LWIP_DHCP_DOES_ARP_CHECK: u32 = 1;
pub const CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER: u32 = 1;
pub const CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE: u32 = 2304;
pub const CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V: u32 = 1;
pub const CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY: u32 = 2000;
pub const CONFIG_BROWNOUT_DET_LVL: u32 = 0;
pub const CONFIG_MBEDTLS_PEM_PARSE_C: u32 = 1;
pub const CONFIG_SPIFFS_GC_MAX_RUNS: u32 = 10;
pub const CONFIG_ESP32_APPTRACE_DEST_NONE: u32 = 1;
pub const CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_PROTO_TLS1_2: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA: u32 = 1;
pub const CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM: u32 = 32;
pub const CONFIG_HTTPD_MAX_URI_LEN: u32 = 512;
pub const CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED: u32 = 1;
pub const CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1: u32 = 1;
pub const CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ: u32 = 160;
pub const CONFIG_MBEDTLS_HARDWARE_AES: u32 = 1;
pub const CONFIG_FREERTOS_HZ: u32 = 100;
pub const CONFIG_LOG_COLORS: u32 = 1;
pub const CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE: u32 = 1;
pub const CONFIG_STACK_CHECK_NONE: u32 = 1;
pub const CONFIG_ADC_CAL_EFUSE_TP_ENABLE: u32 = 1;
pub const CONFIG_FREERTOS_ASSERT_FAIL_ABORT: u32 = 1;
pub const CONFIG_BROWNOUT_DET: u32 = 1;
pub const CONFIG_ESP32_XTAL_FREQ: u32 = 40;
pub const CONFIG_MONITOR_BAUD_115200B: u32 = 1;
pub const CONFIG_LOG_BOOTLOADER_LEVEL: u32 = 3;
pub const CONFIG_MBEDTLS_TLS_ENABLED: u32 = 1;
pub const CONFIG_LWIP_MAX_RAW_PCBS: u32 = 16;
pub const CONFIG_MBEDTLS_SSL_SESSION_TICKETS: u32 = 1;
pub const CONFIG_SPIFFS_MAX_PARTITIONS: u32 = 3;
pub const CONFIG_ESP_ERR_TO_NAME_LOOKUP: u32 = 1;
pub const CONFIG_MBEDTLS_SSL_RENEGOTIATION: u32 = 1;
pub const CONFIG_ESPTOOLPY_BEFORE_RESET: u32 = 1;
pub const CONFIG_MB_EVENT_QUEUE_TIMEOUT: u32 = 20;
pub const CONFIG_ESPTOOLPY_BAUD_OTHER_VAL: u32 = 115200;
pub const CONFIG_SPIFFS_OBJ_NAME_LEN: u32 = 32;
pub const CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT: u32 = 5;
pub const CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF: u32 = 0;
pub const CONFIG_PARTITION_TABLE_MD5: u32 = 1;
pub const CONFIG_TCPIP_RECVMBOX_SIZE: u32 = 32;
pub const CONFIG_TCP_MAXRTX: u32 = 12;
pub const CONFIG_ESPTOOLPY_AFTER: &'static [u8; 11usize] = b"hard_reset\0";
pub const CONFIG_TCPIP_TASK_AFFINITY: u32 = 2147483647;
pub const CONFIG_LWIP_SO_REUSE: u32 = 1;
pub const CONFIG_ESP32_XTAL_FREQ_40: u32 = 1;
pub const CONFIG_DMA_TX_BUF_NUM: u32 = 10;
pub const CONFIG_LWIP_MAX_LISTENING_TCP: u32 = 16;
pub const CONFIG_FREERTOS_INTERRUPT_BACKTRACE: u32 = 1;
pub const CONFIG_WL_SECTOR_SIZE: u32 = 4096;
pub const CONFIG_ESP32_DEBUG_OCDAWARE: u32 = 1;
pub const CONFIG_MQTT_TRANSPORT_WEBSOCKET: u32 = 1;
pub const CONFIG_TIMER_TASK_PRIORITY: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_CLIENT: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED: u32 = 1;
pub const CONFIG_MONITOR_BAUD: u32 = 115200;
pub const CONFIG_ESP32_DEBUG_STUBS_ENABLE: u32 = 1;
pub const CONFIG_TCPIP_LWIP: u32 = 1;
pub const CONFIG_REDUCE_PHY_TX_POWER: u32 = 1;
pub const CONFIG_BOOTLOADER_WDT_TIME_MS: u32 = 9000;
pub const CONFIG_FREERTOS_CORETIMER_0: u32 = 1;
pub const CONFIG_PARTITION_TABLE_CUSTOM_FILENAME: &'static [u8; 15usize] = b"partitions.csv\0";
pub const CONFIG_MBEDTLS_HAVE_TIME: u32 = 1;
pub const CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY: u32 = 1;
pub const CONFIG_TCP_QUEUE_OOSEQ: u32 = 1;
pub const CONFIG_ADC_CAL_EFUSE_VREF_ENABLE: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_SERVER: u32 = 1;
pub const CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT: u32 = 1;
pub const CONFIG_FREERTOS_ISR_STACKSIZE: u32 = 1536;
pub const CONFIG_SUPPORT_TERMIOS: u32 = 1;
pub const CONFIG_OPENSSL_ASSERT_DO_NOTHING: u32 = 1;
pub const CONFIG_WL_SECTOR_SIZE_4096: u32 = 1;
pub const CONFIG_OPTIMIZATION_LEVEL_DEBUG: u32 = 1;
pub const CONFIG_FREERTOS_NO_AFFINITY: u32 = 2147483647;
pub const CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED: u32 = 1;
pub const CONFIG_MB_TIMER_INDEX: u32 = 0;
pub const CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED: u32 = 1;
pub const CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: u32 = 1;
pub const CONFIG_SPI_SLAVE_ISR_IN_IRAM: u32 = 1;
pub const CONFIG_SYSTEM_EVENT_QUEUE_SIZE: u32 = 32;
pub const CONFIG_ESP32_WIFI_TX_BUFFER_TYPE: u32 = 1;
pub const CONFIG_BOOTLOADER_WDT_ENABLE: u32 = 1;
pub const CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED: u32 = 1;
pub const CONFIG_LWIP_LOOPBACK_MAX_PBUFS: u32 = 8;
pub const CONFIG_MB_TIMER_GROUP: u32 = 0;
pub const CONFIG_SPI_FLASH_ROM_DRIVER_PATCH: u32 = 1;
pub const CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE: u32 = 1;
pub const CONFIG_SPIFFS_PAGE_SIZE: u32 = 256;
pub const CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED: u32 = 1;
pub const CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0: u32 = 1;
pub const CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT: u32 = 3072;
pub const CONFIG_MB_TIMER_PORT_ENABLED: u32 = 1;
pub const CONFIG_MONITOR_BAUD_OTHER_VAL: u32 = 115200;
pub const CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF: u32 = 1;
pub const CONFIG_ESPTOOLPY_PORT: &'static [u8; 13usize] = b"/dev/ttyUSB0\0";
pub const CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS: u32 = 1;
pub const CONFIG_ESP32_WIFI_IRAM_OPT: u32 = 1;
pub const portNUM_PROCESSORS: u32 = 2;
pub const XT_USE_THREAD_SAFE_CLIB: u32 = 0;
pub const configASSERT_2: u32 = 0;
pub const portUSING_MPU_WRAPPERS: u32 = 0;
pub const configUSE_MUTEX: u32 = 1;
pub const XT_TIMER_INDEX: u32 = 0;
pub const configNUM_THREAD_LOCAL_STORAGE_POINTERS: u32 = 1;
pub const configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS: u32 = 1;
pub const XTHAL_RELEASE_MAJOR: u32 = 11000;
pub const XTHAL_RELEASE_MINOR: u32 = 3;
pub const XTHAL_RELEASE_NAME: &'static [u8; 7usize] = b"11.0.3\0";
pub const XTHAL_REL_11: u32 = 1;
pub const XTHAL_REL_11_0: u32 = 1;
pub const XTHAL_REL_11_0_3: u32 = 1;
pub const XTHAL_MAJOR_REV: u32 = 11000;
pub const XTHAL_MINOR_REV: u32 = 3;
pub const XTHAL_MAYBE: i32 = -1;
pub const XTHAL_MAX_CPS: u32 = 8;
pub const XTHAL_LITTLEENDIAN: u32 = 0;
pub const XTHAL_BIGENDIAN: u32 = 1;
pub const XTHAL_PREFETCH_ENABLE: i32 = -1;
pub const XTHAL_PREFETCH_DISABLE: u32 = 4294901760;
pub const XTHAL_DCACHE_PREFETCH_L1_OFF: u32 = 2415919104;
pub const XTHAL_DCACHE_PREFETCH_L1: u32 = 2415923200;
pub const XTHAL_ICACHE_PREFETCH_L1_OFF: u32 = 2684354560;
pub const XTHAL_ICACHE_PREFETCH_L1: u32 = 2684362752;
pub const XTHAL_DISASM_BUFSIZE: u32 = 80;
pub const XTHAL_DISASM_OPT_ADDR: u32 = 1;
pub const XTHAL_DISASM_OPT_OPHEX: u32 = 2;
pub const XTHAL_DISASM_OPT_OPCODE: u32 = 4;
pub const XTHAL_DISASM_OPT_PARMS: u32 = 8;
pub const XTHAL_DISASM_OPT_ALL: u32 = 4095;
pub const XTHAL_MAX_INTERRUPTS: u32 = 32;
pub const XTHAL_MAX_INTLEVELS: u32 = 16;
pub const XTHAL_MAX_TIMERS: u32 = 4;
pub const XTHAL_INTTYPE_UNCONFIGURED: u32 = 0;
pub const XTHAL_INTTYPE_SOFTWARE: u32 = 1;
pub const XTHAL_INTTYPE_EXTERN_EDGE: u32 = 2;
pub const XTHAL_INTTYPE_EXTERN_LEVEL: u32 = 3;
pub const XTHAL_INTTYPE_TIMER: u32 = 4;
pub const XTHAL_INTTYPE_NMI: u32 = 5;
pub const XTHAL_INTTYPE_WRITE_ERROR: u32 = 6;
pub const XTHAL_INTTYPE_PROFILING: u32 = 7;
pub const XTHAL_MAX_INTTYPES: u32 = 8;
pub const XTHAL_TIMER_UNCONFIGURED: i32 = -1;
pub const XTHAL_TIMER_UNASSIGNED: i32 = -1;
pub const XTHAL_MEMEP_PARITY: u32 = 1;
pub const XTHAL_MEMEP_ECC: u32 = 2;
pub const XTHAL_MEMEP_F_LOCAL: u32 = 0;
pub const XTHAL_MEMEP_F_DCACHE_DATA: u32 = 4;
pub const XTHAL_MEMEP_F_DCACHE_TAG: u32 = 5;
pub const XTHAL_MEMEP_F_ICACHE_DATA: u32 = 6;
pub const XTHAL_MEMEP_F_ICACHE_TAG: u32 = 7;
pub const XTHAL_MEMEP_F_CORRECTABLE: u32 = 16;
pub const XTHAL_AMB_EXCEPTION: u32 = 0;
pub const XTHAL_AMB_HITCACHE: u32 = 1;
pub const XTHAL_AMB_ALLOCATE: u32 = 2;
pub const XTHAL_AMB_WRITETHRU: u32 = 3;
pub const XTHAL_AMB_ISOLATE: u32 = 4;
pub const XTHAL_AMB_GUARD: u32 = 5;
pub const XTHAL_AMB_COHERENT: u32 = 6;
pub const XTHAL_AM_EXCEPTION: u32 = 1;
pub const XTHAL_AM_HITCACHE: u32 = 2;
pub const XTHAL_AM_ALLOCATE: u32 = 4;
pub const XTHAL_AM_WRITETHRU: u32 = 8;
pub const XTHAL_AM_ISOLATE: u32 = 16;
pub const XTHAL_AM_GUARD: u32 = 32;
pub const XTHAL_AM_COHERENT: u32 = 64;
pub const XTHAL_FAM_EXCEPTION: u32 = 1;
pub const XTHAL_FAM_BYPASS: u32 = 0;
pub const XTHAL_FAM_CACHED: u32 = 6;
pub const XTHAL_LAM_EXCEPTION: u32 = 1;
pub const XTHAL_LAM_ISOLATE: u32 = 18;
pub const XTHAL_LAM_BYPASS: u32 = 0;
pub const XTHAL_LAM_BYPASSG: u32 = 32;
pub const XTHAL_LAM_CACHED_NOALLOC: u32 = 2;
pub const XTHAL_LAM_NACACHED: u32 = 2;
pub const XTHAL_LAM_NACACHEDG: u32 = 34;
pub const XTHAL_LAM_CACHED: u32 = 6;
pub const XTHAL_LAM_COHCACHED: u32 = 70;
pub const XTHAL_SAM_EXCEPTION: u32 = 1;
pub const XTHAL_SAM_ISOLATE: u32 = 50;
pub const XTHAL_SAM_BYPASS: u32 = 40;
pub const XTHAL_SAM_WRITETHRU: u32 = 42;
pub const XTHAL_SAM_WRITEBACK: u32 = 38;
pub const XTHAL_SAM_WRITEBACK_NOALLOC: u32 = 34;
pub const XTHAL_SAM_COHWRITEBACK: u32 = 102;
pub const XTHAL_PAM_BYPASS: u32 = 0;
pub const XTHAL_PAM_BYPASS_BUF: u32 = 16;
pub const XTHAL_PAM_CACHED_NOALLOC: u32 = 48;
pub const XTHAL_PAM_WRITETHRU: u32 = 176;
pub const XTHAL_PAM_WRITEBACK_NOALLOC: u32 = 240;
pub const XTHAL_PAM_WRITEBACK: u32 = 496;
pub const XTHAL_CAFLAG_EXPAND: u32 = 256;
pub const XTHAL_CAFLAG_EXACT: u32 = 512;
pub const XTHAL_CAFLAG_NO_PARTIAL: u32 = 1024;
pub const XTHAL_CAFLAG_NO_AUTO_WB: u32 = 2048;
pub const XTHAL_CAFLAG_NO_AUTO_INV: u32 = 4096;
pub const XCHAL_SUCCESS: u32 = 0;
pub const XCHAL_ADDRESS_MISALIGNED: i32 = -1;
pub const XCHAL_INEXACT: i32 = -2;
pub const XCHAL_INVALID_ADDRESS: i32 = -3;
pub const XCHAL_UNSUPPORTED_ON_THIS_ARCH: i32 = -4;
pub const XCHAL_NO_PAGES_MAPPED: i32 = -5;
pub const XTHAL_NO_MAPPING: i32 = -6;
pub const XCHAL_CA_R: u32 = 1073742016;
pub const XCHAL_CA_RX: u32 = 1073742032;
pub const XCHAL_CA_RW: u32 = 1073742048;
pub const XCHAL_CA_RWX: u32 = 1073742064;
pub const XTENSA_HWVERSION_T1020_0: u32 = 102000;
pub const XTENSA_HWCIDSCHEME_T1020_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_0: u32 = 2;
pub const XTENSA_HWVERSION_T1020_1: u32 = 102001;
pub const XTENSA_HWCIDSCHEME_T1020_1: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_1: u32 = 3;
pub const XTENSA_HWVERSION_T1020_2B: u32 = 102002;
pub const XTENSA_HWCIDSCHEME_T1020_2B: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_2B: u32 = 5;
pub const XTENSA_HWVERSION_T1020_2: u32 = 102002;
pub const XTENSA_HWCIDSCHEME_T1020_2: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_2: u32 = 4;
pub const XTENSA_HWVERSION_T1020_3: u32 = 102003;
pub const XTENSA_HWCIDSCHEME_T1020_3: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_3: u32 = 6;
pub const XTENSA_HWVERSION_T1020_4: u32 = 102004;
pub const XTENSA_HWCIDSCHEME_T1020_4: u32 = 10;
pub const XTENSA_HWCIDVERS_T1020_4: u32 = 7;
pub const XTENSA_HWVERSION_T1030_0: u32 = 103000;
pub const XTENSA_HWCIDSCHEME_T1030_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_0: u32 = 9;
pub const XTENSA_HWVERSION_T1030_1: u32 = 103001;
pub const XTENSA_HWCIDSCHEME_T1030_1: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_1: u32 = 10;
pub const XTENSA_HWVERSION_T1030_2: u32 = 103002;
pub const XTENSA_HWCIDSCHEME_T1030_2: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_2: u32 = 11;
pub const XTENSA_HWVERSION_T1030_3: u32 = 103003;
pub const XTENSA_HWCIDSCHEME_T1030_3: u32 = 10;
pub const XTENSA_HWCIDVERS_T1030_3: u32 = 12;
pub const XTENSA_HWVERSION_T1040_0: u32 = 104000;
pub const XTENSA_HWCIDSCHEME_T1040_0: u32 = 10;
pub const XTENSA_HWCIDVERS_T1040_0: u32 = 15;
pub const XTENSA_HWVERSION_T1040_1: u32 = 104001;
pub const XTENSA_HWCIDSCHEME_T1040_1: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_1: u32 = 32;
pub const XTENSA_HWVERSION_T1040_1P: u32 = 104001;
pub const XTENSA_HWCIDSCHEME_T1040_1P: u32 = 10;
pub const XTENSA_HWCIDVERS_T1040_1P: u32 = 16;
pub const XTENSA_HWVERSION_T1040_2: u32 = 104002;
pub const XTENSA_HWCIDSCHEME_T1040_2: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_2: u32 = 33;
pub const XTENSA_HWVERSION_T1040_3: u32 = 104003;
pub const XTENSA_HWCIDSCHEME_T1040_3: u32 = 1;
pub const XTENSA_HWCIDVERS_T1040_3: u32 = 34;
pub const XTENSA_HWVERSION_T1050_0: u32 = 105000;
pub const XTENSA_HWCIDSCHEME_T1050_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_0: u32 = 1;
pub const XTENSA_HWVERSION_T1050_1: u32 = 105001;
pub const XTENSA_HWCIDSCHEME_T1050_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_1: u32 = 2;
pub const XTENSA_HWVERSION_T1050_2: u32 = 105002;
pub const XTENSA_HWCIDSCHEME_T1050_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_2: u32 = 4;
pub const XTENSA_HWVERSION_T1050_3: u32 = 105003;
pub const XTENSA_HWCIDSCHEME_T1050_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_3: u32 = 6;
pub const XTENSA_HWVERSION_T1050_4: u32 = 105004;
pub const XTENSA_HWCIDSCHEME_T1050_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_4: u32 = 7;
pub const XTENSA_HWVERSION_T1050_5: u32 = 105005;
pub const XTENSA_HWCIDSCHEME_T1050_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_T1050_5: u32 = 8;
pub const XTENSA_HWVERSION_RA_2004_1: u32 = 210000;
pub const XTENSA_HWCIDSCHEME_RA_2004_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2004_1: u32 = 3;
pub const XTENSA_HWVERSION_RA_2005_1: u32 = 210001;
pub const XTENSA_HWCIDSCHEME_RA_2005_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_1: u32 = 20;
pub const XTENSA_HWVERSION_RA_2005_2: u32 = 210002;
pub const XTENSA_HWCIDSCHEME_RA_2005_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_2: u32 = 21;
pub const XTENSA_HWVERSION_RA_2005_3: u32 = 210003;
pub const XTENSA_HWCIDSCHEME_RA_2005_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2005_3: u32 = 22;
pub const XTENSA_HWVERSION_RA_2006_4: u32 = 210004;
pub const XTENSA_HWCIDSCHEME_RA_2006_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_4: u32 = 23;
pub const XTENSA_HWVERSION_RA_2006_5: u32 = 210005;
pub const XTENSA_HWCIDSCHEME_RA_2006_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_5: u32 = 24;
pub const XTENSA_HWVERSION_RA_2006_6: u32 = 210006;
pub const XTENSA_HWCIDSCHEME_RA_2006_6: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2006_6: u32 = 25;
pub const XTENSA_HWVERSION_RA_2007_7: u32 = 210007;
pub const XTENSA_HWCIDSCHEME_RA_2007_7: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2007_7: u32 = 26;
pub const XTENSA_HWVERSION_RA_2008_8: u32 = 210008;
pub const XTENSA_HWCIDSCHEME_RA_2008_8: u32 = 1100;
pub const XTENSA_HWCIDVERS_RA_2008_8: u32 = 27;
pub const XTENSA_HWVERSION_RB_2006_0: u32 = 220000;
pub const XTENSA_HWCIDSCHEME_RB_2006_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2006_0: u32 = 48;
pub const XTENSA_HWVERSION_RB_2007_1: u32 = 220001;
pub const XTENSA_HWCIDSCHEME_RB_2007_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_1: u32 = 49;
pub const XTENSA_HWVERSION_RB_2007_2: u32 = 221000;
pub const XTENSA_HWCIDSCHEME_RB_2007_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_2: u32 = 52;
pub const XTENSA_HWVERSION_RB_2008_3: u32 = 221001;
pub const XTENSA_HWCIDSCHEME_RB_2008_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2008_3: u32 = 53;
pub const XTENSA_HWVERSION_RB_2008_4: u32 = 221002;
pub const XTENSA_HWCIDSCHEME_RB_2008_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2008_4: u32 = 54;
pub const XTENSA_HWVERSION_RB_2009_5: u32 = 221003;
pub const XTENSA_HWCIDSCHEME_RB_2009_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2009_5: u32 = 55;
pub const XTENSA_HWVERSION_RB_2007_2_MP: u32 = 221100;
pub const XTENSA_HWCIDSCHEME_RB_2007_2_MP: u32 = 1100;
pub const XTENSA_HWCIDVERS_RB_2007_2_MP: u32 = 64;
pub const XTENSA_HWVERSION_RC_2009_0: u32 = 230000;
pub const XTENSA_HWCIDSCHEME_RC_2009_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2009_0: u32 = 65;
pub const XTENSA_HWVERSION_RC_2010_1: u32 = 230001;
pub const XTENSA_HWCIDSCHEME_RC_2010_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2010_1: u32 = 66;
pub const XTENSA_HWVERSION_RC_2010_2: u32 = 230002;
pub const XTENSA_HWCIDSCHEME_RC_2010_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2010_2: u32 = 67;
pub const XTENSA_HWVERSION_RC_2011_3: u32 = 230003;
pub const XTENSA_HWCIDSCHEME_RC_2011_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RC_2011_3: u32 = 68;
pub const XTENSA_HWVERSION_RD_2010_0: u32 = 240000;
pub const XTENSA_HWCIDSCHEME_RD_2010_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2010_0: u32 = 80;
pub const XTENSA_HWVERSION_RD_2011_1: u32 = 240001;
pub const XTENSA_HWCIDSCHEME_RD_2011_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_1: u32 = 81;
pub const XTENSA_HWVERSION_RD_2011_2: u32 = 240002;
pub const XTENSA_HWCIDSCHEME_RD_2011_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_2: u32 = 82;
pub const XTENSA_HWVERSION_RD_2011_3: u32 = 240003;
pub const XTENSA_HWCIDSCHEME_RD_2011_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2011_3: u32 = 83;
pub const XTENSA_HWVERSION_RD_2012_4: u32 = 240004;
pub const XTENSA_HWCIDSCHEME_RD_2012_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2012_4: u32 = 84;
pub const XTENSA_HWVERSION_RD_2012_5: u32 = 240005;
pub const XTENSA_HWCIDSCHEME_RD_2012_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RD_2012_5: u32 = 85;
pub const XTENSA_HWVERSION_RE_2012_0: u32 = 250000;
pub const XTENSA_HWCIDSCHEME_RE_2012_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2012_0: u32 = 96;
pub const XTENSA_HWVERSION_RE_2012_1: u32 = 250001;
pub const XTENSA_HWCIDSCHEME_RE_2012_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2012_1: u32 = 97;
pub const XTENSA_HWVERSION_RE_2013_2: u32 = 250002;
pub const XTENSA_HWCIDSCHEME_RE_2013_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_2: u32 = 98;
pub const XTENSA_HWVERSION_RE_2013_3: u32 = 250003;
pub const XTENSA_HWCIDSCHEME_RE_2013_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_3: u32 = 99;
pub const XTENSA_HWVERSION_RE_2013_4: u32 = 250004;
pub const XTENSA_HWCIDSCHEME_RE_2013_4: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2013_4: u32 = 100;
pub const XTENSA_HWVERSION_RE_2014_5: u32 = 250005;
pub const XTENSA_HWCIDSCHEME_RE_2014_5: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2014_5: u32 = 101;
pub const XTENSA_HWVERSION_RE_2015_6: u32 = 250006;
pub const XTENSA_HWCIDSCHEME_RE_2015_6: u32 = 1100;
pub const XTENSA_HWCIDVERS_RE_2015_6: u32 = 102;
pub const XTENSA_HWVERSION_RF_2014_0: u32 = 260000;
pub const XTENSA_HWCIDSCHEME_RF_2014_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2014_0: u32 = 112;
pub const XTENSA_HWVERSION_RF_2014_1: u32 = 260001;
pub const XTENSA_HWCIDSCHEME_RF_2014_1: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2014_1: u32 = 113;
pub const XTENSA_HWVERSION_RF_2015_2: u32 = 260002;
pub const XTENSA_HWCIDSCHEME_RF_2015_2: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2015_2: u32 = 114;
pub const XTENSA_HWVERSION_RF_2015_3: u32 = 260003;
pub const XTENSA_HWCIDSCHEME_RF_2015_3: u32 = 1100;
pub const XTENSA_HWCIDVERS_RF_2015_3: u32 = 115;
pub const XTENSA_HWVERSION_RG_2015_0: u32 = 270000;
pub const XTENSA_HWCIDSCHEME_RG_2015_0: u32 = 1100;
pub const XTENSA_HWCIDVERS_RG_2015_0: u32 = 128;
pub const XTENSA_SWVERSION_T1020_0: u32 = 102000;
pub const XTENSA_SWVERSION_T1020_1: u32 = 102001;
pub const XTENSA_SWVERSION_T1020_2B: u32 = 102002;
pub const XTENSA_SWVERSION_T1020_2: u32 = 102002;
pub const XTENSA_SWVERSION_T1020_3: u32 = 102003;
pub const XTENSA_SWVERSION_T1020_4: u32 = 102004;
pub const XTENSA_SWVERSION_T1030_0: u32 = 103000;
pub const XTENSA_SWVERSION_T1030_1: u32 = 103001;
pub const XTENSA_SWVERSION_T1030_2: u32 = 103002;
pub const XTENSA_SWVERSION_T1030_3: u32 = 103003;
pub const XTENSA_SWVERSION_T1040_0: u32 = 104000;
pub const XTENSA_SWVERSION_T1040_1: u32 = 104001;
pub const XTENSA_SWVERSION_T1040_1P: u32 = 104001;
pub const XTENSA_SWVERSION_T1040_2: u32 = 104002;
pub const XTENSA_SWVERSION_T1040_3: u32 = 104003;
pub const XTENSA_SWVERSION_T1050_0: u32 = 105000;
pub const XTENSA_SWVERSION_T1050_1: u32 = 105001;
pub const XTENSA_SWVERSION_T1050_2: u32 = 105002;
pub const XTENSA_SWVERSION_T1050_3: u32 = 105003;
pub const XTENSA_SWVERSION_T1050_4: u32 = 105004;
pub const XTENSA_SWVERSION_T1050_5: u32 = 105005;
pub const XTENSA_SWVERSION_RA_2004_1: u32 = 600000;
pub const XTENSA_SWVERSION_RA_2005_1: u32 = 600001;
pub const XTENSA_SWVERSION_RA_2005_2: u32 = 600002;
pub const XTENSA_SWVERSION_RA_2005_3: u32 = 600003;
pub const XTENSA_SWVERSION_RA_2006_4: u32 = 600004;
pub const XTENSA_SWVERSION_RA_2006_5: u32 = 600005;
pub const XTENSA_SWVERSION_RA_2006_6: u32 = 600006;
pub const XTENSA_SWVERSION_RA_2007_7: u32 = 600007;
pub const XTENSA_SWVERSION_RA_2008_8: u32 = 600008;
pub const XTENSA_SWVERSION_RB_2006_0: u32 = 700000;
pub const XTENSA_SWVERSION_RB_2007_1: u32 = 700001;
pub const XTENSA_SWVERSION_RB_2007_2: u32 = 701000;
pub const XTENSA_SWVERSION_RB_2008_3: u32 = 701001;
pub const XTENSA_SWVERSION_RB_2008_4: u32 = 701002;
pub const XTENSA_SWVERSION_RB_2009_5: u32 = 701003;
pub const XTENSA_SWVERSION_RB_2007_2_MP: u32 = 701100;
pub const XTENSA_SWVERSION_RC_2009_0: u32 = 800000;
pub const XTENSA_SWVERSION_RC_2010_1: u32 = 800001;
pub const XTENSA_SWVERSION_RC_2010_2: u32 = 800002;
pub const XTENSA_SWVERSION_RC_2011_3: u32 = 800003;
pub const XTENSA_SWVERSION_RD_2010_0: u32 = 900000;
pub const XTENSA_SWVERSION_RD_2011_1: u32 = 900001;
pub const XTENSA_SWVERSION_RD_2011_2: u32 = 900002;
pub const XTENSA_SWVERSION_RD_2011_3: u32 = 900003;
pub const XTENSA_SWVERSION_RD_2012_4: u32 = 900004;
pub const XTENSA_SWVERSION_RD_2012_5: u32 = 900005;
pub const XTENSA_SWVERSION_RE_2012_0: u32 = 1000000;
pub const XTENSA_SWVERSION_RE_2012_1: u32 = 1000001;
pub const XTENSA_SWVERSION_RE_2013_2: u32 = 1000002;
pub const XTENSA_SWVERSION_RE_2013_3: u32 = 1000003;
pub const XTENSA_SWVERSION_RE_2013_4: u32 = 1000004;
pub const XTENSA_SWVERSION_RE_2014_5: u32 = 1000005;
pub const XTENSA_SWVERSION_RE_2015_6: u32 = 1000006;
pub const XTENSA_SWVERSION_RF_2014_0: u32 = 1100000;
pub const XTENSA_SWVERSION_RF_2014_1: u32 = 1100001;
pub const XTENSA_SWVERSION_RF_2015_2: u32 = 1100002;
pub const XTENSA_SWVERSION_RF_2015_3: u32 = 1100003;
pub const XTENSA_SWVERSION_RG_2015_0: u32 = 1200000;
pub const XTENSA_SWVERSION_T1040_1_PREHOTFIX: u32 = 104001;
pub const XTENSA_SWVERSION_6_0_0: u32 = 600000;
pub const XTENSA_SWVERSION_6_0_1: u32 = 600001;
pub const XTENSA_SWVERSION_6_0_2: u32 = 600002;
pub const XTENSA_SWVERSION_6_0_3: u32 = 600003;
pub const XTENSA_SWVERSION_6_0_4: u32 = 600004;
pub const XTENSA_SWVERSION_6_0_5: u32 = 600005;
pub const XTENSA_SWVERSION_6_0_6: u32 = 600006;
pub const XTENSA_SWVERSION_6_0_7: u32 = 600007;
pub const XTENSA_SWVERSION_6_0_8: u32 = 600008;
pub const XTENSA_SWVERSION_7_0_0: u32 = 700000;
pub const XTENSA_SWVERSION_7_0_1: u32 = 700001;
pub const XTENSA_SWVERSION_7_1_0: u32 = 701000;
pub const XTENSA_SWVERSION_7_1_1: u32 = 701001;
pub const XTENSA_SWVERSION_7_1_2: u32 = 701002;
pub const XTENSA_SWVERSION_7_1_3: u32 = 701003;
pub const XTENSA_SWVERSION_7_1_8_MP: u32 = 701100;
pub const XTENSA_SWVERSION_8_0_0: u32 = 800000;
pub const XTENSA_SWVERSION_8_0_1: u32 = 800001;
pub const XTENSA_SWVERSION_8_0_2: u32 = 800002;
pub const XTENSA_SWVERSION_8_0_3: u32 = 800003;
pub const XTENSA_SWVERSION_9_0_0: u32 = 900000;
pub const XTENSA_SWVERSION_9_0_1: u32 = 900001;
pub const XTENSA_SWVERSION_9_0_2: u32 = 900002;
pub const XTENSA_SWVERSION_9_0_3: u32 = 900003;
pub const XTENSA_SWVERSION_9_0_4: u32 = 900004;
pub const XTENSA_SWVERSION_9_0_5: u32 = 900005;
pub const XTENSA_SWVERSION_10_0_0: u32 = 1000000;
pub const XTENSA_SWVERSION_10_0_1: u32 = 1000001;
pub const XTENSA_SWVERSION_10_0_2: u32 = 1000002;
pub const XTENSA_SWVERSION_10_0_3: u32 = 1000003;
pub const XTENSA_SWVERSION_10_0_4: u32 = 1000004;
pub const XTENSA_SWVERSION_10_0_5: u32 = 1000005;
pub const XTENSA_SWVERSION_10_0_6: u32 = 1000006;
pub const XTENSA_SWVERSION_11_0_0: u32 = 1100000;
pub const XTENSA_SWVERSION_11_0_1: u32 = 1100001;
pub const XTENSA_SWVERSION_11_0_2: u32 = 1100002;
pub const XTENSA_SWVERSION_11_0_3: u32 = 1100003;
pub const XTENSA_SWVERSION_12_0_0: u32 = 1200000;
pub const XTENSA_RELEASE_NAME: &'static [u8; 10usize] = b"RF-2015.3\0";
pub const XTENSA_RELEASE_CANONICAL_NAME: &'static [u8; 10usize] = b"RF-2015.3\0";
pub const XTENSA_SWVERSION: u32 = 1100003;
pub const XTENSA_SWVERSION_NAME: &'static [u8; 7usize] = b"11.0.3\0";
pub const XTENSA_SWVERSION_CANONICAL_NAME: &'static [u8; 7usize] = b"11.0.3\0";
pub const XTENSA_SWVERSION_MAJORMID_NAME: &'static [u8; 5usize] = b"11.0\0";
pub const XTENSA_SWVERSION_MAJOR_NAME: &'static [u8; 3usize] = b"11\0";
pub const XTENSA_SWVERSION_LICENSE_NAME: &'static [u8; 5usize] = b"11.0\0";
pub const XCHAL_CA_BYPASS: u32 = 2;
pub const XCHAL_CA_BYPASSBUF: u32 = 6;
pub const XCHAL_CA_WRITETHRU: u32 = 2;
pub const XCHAL_CA_WRITEBACK: u32 = 2;
pub const XCHAL_HAVE_CA_WRITEBACK_NOALLOC: u32 = 0;
pub const XCHAL_CA_WRITEBACK_NOALLOC: u32 = 2;
pub const XCHAL_CA_BYPASS_RW: u32 = 0;
pub const XCHAL_CA_WRITETHRU_RW: u32 = 0;
pub const XCHAL_CA_WRITEBACK_RW: u32 = 0;
pub const XCHAL_CA_WRITEBACK_NOALLOC_RW: u32 = 0;
pub const XCHAL_CA_ILLEGAL: u32 = 15;
pub const XCHAL_CA_ISOLATE: u32 = 0;
pub const XCHAL_MMU_ASID_INVALID: u32 = 0;
pub const XCHAL_MMU_ASID_KERNEL: u32 = 0;
pub const XCHAL_MMU_SR_BITS: u32 = 0;
pub const XCHAL_MMU_CA_BITS: u32 = 4;
pub const XCHAL_MMU_MAX_PTE_PAGE_SIZE: u32 = 29;
pub const XCHAL_MMU_MIN_PTE_PAGE_SIZE: u32 = 29;
pub const XCHAL_ITLB_WAY_BITS: u32 = 0;
pub const XCHAL_ITLB_WAYS: u32 = 1;
pub const XCHAL_ITLB_ARF_WAYS: u32 = 0;
pub const XCHAL_ITLB_SETS: u32 = 1;
pub const XCHAL_ITLB_WAY0_SET: u32 = 0;
pub const XCHAL_ITLB_ARF_SETS: u32 = 0;
pub const XCHAL_ITLB_MINWIRED_SETS: u32 = 0;
pub const XCHAL_ITLB_SET0_WAY: u32 = 0;
pub const XCHAL_ITLB_SET0_WAYS: u32 = 1;
pub const XCHAL_ITLB_SET0_ENTRIES_LOG2: u32 = 3;
pub const XCHAL_ITLB_SET0_ENTRIES: u32 = 8;
pub const XCHAL_ITLB_SET0_ARF: u32 = 0;
pub const XCHAL_ITLB_SET0_PAGESIZES: u32 = 1;
pub const XCHAL_ITLB_SET0_PAGESZ_BITS: u32 = 0;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN: u32 = 29;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX: u32 = 29;
pub const XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST: u32 = 29;
pub const XCHAL_ITLB_SET0_ASID_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_VPN_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_PPN_CONSTMASK: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_CA_CONSTMASK: u32 = 0;
pub const XCHAL_ITLB_SET0_ASID_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_VPN_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_PPN_RESET: u32 = 0;
pub const XCHAL_ITLB_SET0_CA_RESET: u32 = 1;
pub const XCHAL_ITLB_SET0_E0_VPN_CONST: u32 = 0;
pub const XCHAL_ITLB_SET0_E1_VPN_CONST: u32 = 536870912;
pub const XCHAL_ITLB_SET0_E2_VPN_CONST: u32 = 1073741824;
pub const XCHAL_ITLB_SET0_E3_VPN_CONST: u32 = 1610612736;
pub const XCHAL_ITLB_SET0_E4_VPN_CONST: u32 = 2147483648;
pub const XCHAL_ITLB_SET0_E5_VPN_CONST: u32 = 2684354560;
pub const XCHAL_ITLB_SET0_E6_VPN_CONST: u32 = 3221225472;
pub const XCHAL_ITLB_SET0_E7_VPN_CONST: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_E0_PPN_CONST: u32 = 0;
pub const XCHAL_ITLB_SET0_E1_PPN_CONST: u32 = 536870912;
pub const XCHAL_ITLB_SET0_E2_PPN_CONST: u32 = 1073741824;
pub const XCHAL_ITLB_SET0_E3_PPN_CONST: u32 = 1610612736;
pub const XCHAL_ITLB_SET0_E4_PPN_CONST: u32 = 2147483648;
pub const XCHAL_ITLB_SET0_E5_PPN_CONST: u32 = 2684354560;
pub const XCHAL_ITLB_SET0_E6_PPN_CONST: u32 = 3221225472;
pub const XCHAL_ITLB_SET0_E7_PPN_CONST: u32 = 3758096384;
pub const XCHAL_ITLB_SET0_E0_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E1_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E2_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E3_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E4_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E5_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E6_CA_RESET: u32 = 2;
pub const XCHAL_ITLB_SET0_E7_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_WAY_BITS: u32 = 0;
pub const XCHAL_DTLB_WAYS: u32 = 1;
pub const XCHAL_DTLB_ARF_WAYS: u32 = 0;
pub const XCHAL_DTLB_SETS: u32 = 1;
pub const XCHAL_DTLB_WAY0_SET: u32 = 0;
pub const XCHAL_DTLB_ARF_SETS: u32 = 0;
pub const XCHAL_DTLB_MINWIRED_SETS: u32 = 0;
pub const XCHAL_DTLB_SET0_WAY: u32 = 0;
pub const XCHAL_DTLB_SET0_WAYS: u32 = 1;
pub const XCHAL_DTLB_SET0_ENTRIES_LOG2: u32 = 3;
pub const XCHAL_DTLB_SET0_ENTRIES: u32 = 8;
pub const XCHAL_DTLB_SET0_ARF: u32 = 0;
pub const XCHAL_DTLB_SET0_PAGESIZES: u32 = 1;
pub const XCHAL_DTLB_SET0_PAGESZ_BITS: u32 = 0;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN: u32 = 29;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX: u32 = 29;
pub const XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST: u32 = 29;
pub const XCHAL_DTLB_SET0_ASID_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_VPN_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_PPN_CONSTMASK: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_CA_CONSTMASK: u32 = 0;
pub const XCHAL_DTLB_SET0_ASID_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_VPN_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_PPN_RESET: u32 = 0;
pub const XCHAL_DTLB_SET0_CA_RESET: u32 = 1;
pub const XCHAL_DTLB_SET0_E0_VPN_CONST: u32 = 0;
pub const XCHAL_DTLB_SET0_E1_VPN_CONST: u32 = 536870912;
pub const XCHAL_DTLB_SET0_E2_VPN_CONST: u32 = 1073741824;
pub const XCHAL_DTLB_SET0_E3_VPN_CONST: u32 = 1610612736;
pub const XCHAL_DTLB_SET0_E4_VPN_CONST: u32 = 2147483648;
pub const XCHAL_DTLB_SET0_E5_VPN_CONST: u32 = 2684354560;
pub const XCHAL_DTLB_SET0_E6_VPN_CONST: u32 = 3221225472;
pub const XCHAL_DTLB_SET0_E7_VPN_CONST: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_E0_PPN_CONST: u32 = 0;
pub const XCHAL_DTLB_SET0_E1_PPN_CONST: u32 = 536870912;
pub const XCHAL_DTLB_SET0_E2_PPN_CONST: u32 = 1073741824;
pub const XCHAL_DTLB_SET0_E3_PPN_CONST: u32 = 1610612736;
pub const XCHAL_DTLB_SET0_E4_PPN_CONST: u32 = 2147483648;
pub const XCHAL_DTLB_SET0_E5_PPN_CONST: u32 = 2684354560;
pub const XCHAL_DTLB_SET0_E6_PPN_CONST: u32 = 3221225472;
pub const XCHAL_DTLB_SET0_E7_PPN_CONST: u32 = 3758096384;
pub const XCHAL_DTLB_SET0_E0_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E1_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E2_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E3_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E4_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E5_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E6_CA_RESET: u32 = 2;
pub const XCHAL_DTLB_SET0_E7_CA_RESET: u32 = 2;
pub const XCHAL_CP_NUM: u32 = 1;
pub const XCHAL_CP_MAX: u32 = 1;
pub const XCHAL_CP_MASK: u32 = 1;
pub const XCHAL_CP_PORT_MASK: u32 = 0;
pub const XCHAL_CP0_NAME: &'static [u8; 4usize] = b"FPU\0";
pub const XCHAL_CP0_SA_SIZE: u32 = 72;
pub const XCHAL_CP0_SA_ALIGN: u32 = 4;
pub const XCHAL_CP_ID_FPU: u32 = 0;
pub const XCHAL_CP1_SA_SIZE: u32 = 0;
pub const XCHAL_CP1_SA_ALIGN: u32 = 1;
pub const XCHAL_CP2_SA_SIZE: u32 = 0;
pub const XCHAL_CP2_SA_ALIGN: u32 = 1;
pub const XCHAL_CP3_SA_SIZE: u32 = 0;
pub const XCHAL_CP3_SA_ALIGN: u32 = 1;
pub const XCHAL_CP4_SA_SIZE: u32 = 0;
pub const XCHAL_CP4_SA_ALIGN: u32 = 1;
pub const XCHAL_CP5_SA_SIZE: u32 = 0;
pub const XCHAL_CP5_SA_ALIGN: u32 = 1;
pub const XCHAL_CP6_SA_SIZE: u32 = 0;
pub const XCHAL_CP6_SA_ALIGN: u32 = 1;
pub const XCHAL_CP7_SA_SIZE: u32 = 0;
pub const XCHAL_CP7_SA_ALIGN: u32 = 1;
pub const XCHAL_NCP_SA_SIZE: u32 = 48;
pub const XCHAL_NCP_SA_ALIGN: u32 = 4;
pub const XCHAL_TOTAL_SA_SIZE: u32 = 128;
pub const XCHAL_TOTAL_SA_ALIGN: u32 = 4;
pub const XCHAL_NCP_SA_NUM: u32 = 12;
pub const XCHAL_CP0_SA_NUM: u32 = 18;
pub const XCHAL_CP1_SA_NUM: u32 = 0;
pub const XCHAL_CP2_SA_NUM: u32 = 0;
pub const XCHAL_CP3_SA_NUM: u32 = 0;
pub const XCHAL_CP4_SA_NUM: u32 = 0;
pub const XCHAL_CP5_SA_NUM: u32 = 0;
pub const XCHAL_CP6_SA_NUM: u32 = 0;
pub const XCHAL_CP7_SA_NUM: u32 = 0;
pub const XCHAL_HAVE_LE: u32 = 1;
pub const XCHAL_MEMORY_ORDER: u32 = 0;
pub const XCHAL_HAVE_HIGHLEVEL_INTERRUPTS: u32 = 1;
pub const XCHAL_NUM_LOWPRI_LEVELS: u32 = 1;
pub const XCHAL_FIRST_HIGHPRI_LEVEL: u32 = 2;
pub const XCHAL_INTLEVEL0_MASK: u32 = 0;
pub const XCHAL_INTLEVEL8_MASK: u32 = 0;
pub const XCHAL_INTLEVEL9_MASK: u32 = 0;
pub const XCHAL_INTLEVEL10_MASK: u32 = 0;
pub const XCHAL_INTLEVEL11_MASK: u32 = 0;
pub const XCHAL_INTLEVEL12_MASK: u32 = 0;
pub const XCHAL_INTLEVEL13_MASK: u32 = 0;
pub const XCHAL_INTLEVEL14_MASK: u32 = 0;
pub const XCHAL_INTLEVEL15_MASK: u32 = 0;
pub const XCHAL_INTLEVEL0_ANDBELOW_MASK: u32 = 0;
pub const XCHAL_INTLEVEL8_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL9_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL10_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL11_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL12_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL13_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL14_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_INTLEVEL15_ANDBELOW_MASK: u32 = 4294967295;
pub const XCHAL_LOWPRI_MASK: u32 = 407551;
pub const XCHAL_INTCLEARABLE_MASK: u32 = 1883243648;
pub const XCHAL_INTSETTABLE_MASK: u32 = 536871040;
pub const XCHAL_EXTINT0_MASK: u32 = 1;
pub const XCHAL_EXTINT1_MASK: u32 = 2;
pub const XCHAL_EXTINT2_MASK: u32 = 4;
pub const XCHAL_EXTINT3_MASK: u32 = 8;
pub const XCHAL_EXTINT4_MASK: u32 = 16;
pub const XCHAL_EXTINT5_MASK: u32 = 32;
pub const XCHAL_EXTINT6_MASK: u32 = 256;
pub const XCHAL_EXTINT7_MASK: u32 = 512;
pub const XCHAL_EXTINT8_MASK: u32 = 1024;
pub const XCHAL_EXTINT9_MASK: u32 = 4096;
pub const XCHAL_EXTINT10_MASK: u32 = 8192;
pub const XCHAL_EXTINT11_MASK: u32 = 16384;
pub const XCHAL_EXTINT12_MASK: u32 = 131072;
pub const XCHAL_EXTINT13_MASK: u32 = 262144;
pub const XCHAL_EXTINT14_MASK: u32 = 524288;
pub const XCHAL_EXTINT15_MASK: u32 = 1048576;
pub const XCHAL_EXTINT16_MASK: u32 = 2097152;
pub const XCHAL_EXTINT17_MASK: u32 = 4194304;
pub const XCHAL_EXTINT18_MASK: u32 = 8388608;
pub const XCHAL_EXTINT19_MASK: u32 = 16777216;
pub const XCHAL_EXTINT20_MASK: u32 = 33554432;
pub const XCHAL_EXTINT21_MASK: u32 = 67108864;
pub const XCHAL_EXTINT22_MASK: u32 = 134217728;
pub const XCHAL_EXTINT23_MASK: u32 = 268435456;
pub const XCHAL_EXTINT24_MASK: u32 = 1073741824;
pub const XCHAL_EXTINT25_MASK: u32 = 2147483648;
pub const XCHAL_HAVE_OLD_EXC_ARCH: u32 = 0;
pub const XCHAL_HAVE_EXCM: u32 = 1;
pub const XCHAL_PROGRAMEXC_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_USEREXC_VECTOR_VADDR: u32 = 1073742656;
pub const XCHAL_PROGRAMEXC_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_USEREXC_VECTOR_PADDR: u32 = 1073742656;
pub const XCHAL_STACKEDEXC_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_KERNELEXC_VECTOR_VADDR: u32 = 1073742592;
pub const XCHAL_STACKEDEXC_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_KERNELEXC_VECTOR_PADDR: u32 = 1073742592;
pub const XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION: u32 = 0;
pub const XCHAL_EXCCAUSE_SYSTEM_CALL: u32 = 1;
pub const XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR: u32 = 2;
pub const XCHAL_EXCCAUSE_LOAD_STORE_ERROR: u32 = 3;
pub const XCHAL_EXCCAUSE_LEVEL1_INTERRUPT: u32 = 4;
pub const XCHAL_EXCCAUSE_ALLOCA: u32 = 5;
pub const XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO: u32 = 6;
pub const XCHAL_EXCCAUSE_SPECULATION: u32 = 7;
pub const XCHAL_EXCCAUSE_PRIVILEGED: u32 = 8;
pub const XCHAL_EXCCAUSE_UNALIGNED: u32 = 9;
pub const XCHAL_EXCCAUSE_ITLB_MISS: u32 = 16;
pub const XCHAL_EXCCAUSE_ITLB_MULTIHIT: u32 = 17;
pub const XCHAL_EXCCAUSE_ITLB_PRIVILEGE: u32 = 18;
pub const XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION: u32 = 19;
pub const XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE: u32 = 20;
pub const XCHAL_EXCCAUSE_DTLB_MISS: u32 = 24;
pub const XCHAL_EXCCAUSE_DTLB_MULTIHIT: u32 = 25;
pub const XCHAL_EXCCAUSE_DTLB_PRIVILEGE: u32 = 26;
pub const XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION: u32 = 27;
pub const XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE: u32 = 28;
pub const XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE: u32 = 29;
pub const XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED: u32 = 32;
pub const XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED: u32 = 33;
pub const XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED: u32 = 34;
pub const XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED: u32 = 35;
pub const XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED: u32 = 36;
pub const XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED: u32 = 37;
pub const XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED: u32 = 38;
pub const XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED: u32 = 39;
pub const XCHAL_DBREAKC_VALIDMASK: u32 = 3221225535;
pub const XCHAL_DBREAKC_MASK_BITS: u32 = 6;
pub const XCHAL_DBREAKC_MASK_NUM: u32 = 64;
pub const XCHAL_DBREAKC_MASK_SHIFT: u32 = 0;
pub const XCHAL_DBREAKC_MASK_MASK: u32 = 63;
pub const XCHAL_DBREAKC_LOADBREAK_BITS: u32 = 1;
pub const XCHAL_DBREAKC_LOADBREAK_NUM: u32 = 2;
pub const XCHAL_DBREAKC_LOADBREAK_SHIFT: u32 = 30;
pub const XCHAL_DBREAKC_LOADBREAK_MASK: u32 = 1073741824;
pub const XCHAL_DBREAKC_STOREBREAK_BITS: u32 = 1;
pub const XCHAL_DBREAKC_STOREBREAK_NUM: u32 = 2;
pub const XCHAL_DBREAKC_STOREBREAK_SHIFT: u32 = 31;
pub const XCHAL_DBREAKC_STOREBREAK_MASK: u32 = 2147483648;
pub const XCHAL_PS_VALIDMASK: u32 = 462655;
pub const XCHAL_PS_INTLEVEL_BITS: u32 = 4;
pub const XCHAL_PS_INTLEVEL_NUM: u32 = 16;
pub const XCHAL_PS_INTLEVEL_SHIFT: u32 = 0;
pub const XCHAL_PS_INTLEVEL_MASK: u32 = 15;
pub const XCHAL_PS_EXCM_BITS: u32 = 1;
pub const XCHAL_PS_EXCM_NUM: u32 = 2;
pub const XCHAL_PS_EXCM_SHIFT: u32 = 4;
pub const XCHAL_PS_EXCM_MASK: u32 = 16;
pub const XCHAL_PS_UM_BITS: u32 = 1;
pub const XCHAL_PS_UM_NUM: u32 = 2;
pub const XCHAL_PS_UM_SHIFT: u32 = 5;
pub const XCHAL_PS_UM_MASK: u32 = 32;
pub const XCHAL_PS_RING_BITS: u32 = 2;
pub const XCHAL_PS_RING_NUM: u32 = 4;
pub const XCHAL_PS_RING_SHIFT: u32 = 6;
pub const XCHAL_PS_RING_MASK: u32 = 192;
pub const XCHAL_PS_OWB_BITS: u32 = 4;
pub const XCHAL_PS_OWB_NUM: u32 = 16;
pub const XCHAL_PS_OWB_SHIFT: u32 = 8;
pub const XCHAL_PS_OWB_MASK: u32 = 3840;
pub const XCHAL_PS_CALLINC_BITS: u32 = 2;
pub const XCHAL_PS_CALLINC_NUM: u32 = 4;
pub const XCHAL_PS_CALLINC_SHIFT: u32 = 16;
pub const XCHAL_PS_CALLINC_MASK: u32 = 196608;
pub const XCHAL_PS_WOE_BITS: u32 = 1;
pub const XCHAL_PS_WOE_NUM: u32 = 2;
pub const XCHAL_PS_WOE_SHIFT: u32 = 18;
pub const XCHAL_PS_WOE_MASK: u32 = 262144;
pub const XCHAL_EXCCAUSE_VALIDMASK: u32 = 63;
pub const XCHAL_EXCCAUSE_BITS: u32 = 6;
pub const XCHAL_EXCCAUSE_NUM: u32 = 64;
pub const XCHAL_EXCCAUSE_SHIFT: u32 = 0;
pub const XCHAL_EXCCAUSE_MASK: u32 = 63;
pub const XCHAL_DEBUGCAUSE_VALIDMASK: u32 = 63;
pub const XCHAL_DEBUGCAUSE_ICOUNT_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_ICOUNT_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_ICOUNT_SHIFT: u32 = 0;
pub const XCHAL_DEBUGCAUSE_ICOUNT_MASK: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_IBREAK_SHIFT: u32 = 1;
pub const XCHAL_DEBUGCAUSE_IBREAK_MASK: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_DBREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_SHIFT: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DBREAK_MASK: u32 = 4;
pub const XCHAL_DEBUGCAUSE_BREAK_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_BREAK_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_BREAK_SHIFT: u32 = 3;
pub const XCHAL_DEBUGCAUSE_BREAK_MASK: u32 = 8;
pub const XCHAL_DEBUGCAUSE_BREAKN_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_BREAKN_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_BREAKN_SHIFT: u32 = 4;
pub const XCHAL_DEBUGCAUSE_BREAKN_MASK: u32 = 16;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_BITS: u32 = 1;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_NUM: u32 = 2;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT: u32 = 5;
pub const XCHAL_DEBUGCAUSE_DEBUGINT_MASK: u32 = 32;
pub const XCHAL_NUM_IROM: u32 = 1;
pub const XCHAL_NUM_IRAM: u32 = 2;
pub const XCHAL_NUM_DROM: u32 = 1;
pub const XCHAL_NUM_DRAM: u32 = 2;
pub const XCHAL_IROM0_VADDR: u32 = 1082130432;
pub const XCHAL_IROM0_PADDR: u32 = 1082130432;
pub const XCHAL_IROM0_SIZE: u32 = 4194304;
pub const XCHAL_IRAM0_VADDR: u32 = 1073741824;
pub const XCHAL_IRAM0_PADDR: u32 = 1073741824;
pub const XCHAL_IRAM0_SIZE: u32 = 4194304;
pub const XCHAL_IRAM1_VADDR: u32 = 1077936128;
pub const XCHAL_IRAM1_PADDR: u32 = 1077936128;
pub const XCHAL_IRAM1_SIZE: u32 = 4194304;
pub const XCHAL_DROM0_VADDR: u32 = 1061158912;
pub const XCHAL_DROM0_PADDR: u32 = 1061158912;
pub const XCHAL_DROM0_SIZE: u32 = 4194304;
pub const XCHAL_DRAM0_VADDR: u32 = 1073217536;
pub const XCHAL_DRAM0_PADDR: u32 = 1073217536;
pub const XCHAL_DRAM0_SIZE: u32 = 524288;
pub const XCHAL_DRAM1_VADDR: u32 = 1065353216;
pub const XCHAL_DRAM1_PADDR: u32 = 1065353216;
pub const XCHAL_DRAM1_SIZE: u32 = 4194304;
pub const XCHAL_CACHE_PREFCTL_DEFAULT: u32 = 4164;
pub const XCHAL_CACHE_LINEWIDTH_MAX: u32 = 2;
pub const XCHAL_CACHE_LINESIZE_MAX: u32 = 4;
pub const XCHAL_ICACHE_SETSIZE: u32 = 1;
pub const XCHAL_DCACHE_SETSIZE: u32 = 1;
pub const XCHAL_CACHE_SETWIDTH_MAX: u32 = 0;
pub const XCHAL_CACHE_SETSIZE_MAX: u32 = 1;
pub const XCHAL_ICACHE_TAG_V_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_V: u32 = 1;
pub const XCHAL_ICACHE_TAG_F_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_F: u32 = 0;
pub const XCHAL_ICACHE_TAG_L_SHIFT: u32 = 0;
pub const XCHAL_ICACHE_TAG_L: u32 = 0;
pub const XCHAL_DCACHE_TAG_V_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_V: u32 = 1;
pub const XCHAL_DCACHE_TAG_F_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_F: u32 = 0;
pub const XCHAL_DCACHE_TAG_D_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_D: u32 = 0;
pub const XCHAL_DCACHE_TAG_L_SHIFT: u32 = 0;
pub const XCHAL_DCACHE_TAG_L: u32 = 0;
pub const XCHAL_CACHE_MEMCTL_DEFAULT: u32 = 0;
pub const _MEMCTL_SNOOP_EN: u32 = 0;
pub const _MEMCTL_L0IBUF_EN: u32 = 1;
pub const XCHAL_SNOOP_LB_MEMCTL_DEFAULT: u32 = 1;
pub const XCHAL_ALIGN_MAX: u32 = 4;
pub const XCHAL_HW_RELEASE_MAJOR: u32 = 2600;
pub const XCHAL_HW_RELEASE_MINOR: u32 = 3;
pub const XCHAL_HW_RELEASE_NAME: &'static [u8; 8usize] = b"LX6.0.3\0";
pub const XCHAL_EXTRA_SA_SIZE: u32 = 48;
pub const XCHAL_EXTRA_SA_ALIGN: u32 = 4;
pub const XCHAL_CPEXTRA_SA_SIZE: u32 = 128;
pub const XCHAL_CPEXTRA_SA_ALIGN: u32 = 4;
pub const XCHAL_CP1_NAME: u32 = 0;
pub const XCHAL_CP1_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP2_NAME: u32 = 0;
pub const XCHAL_CP2_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP3_NAME: u32 = 0;
pub const XCHAL_CP3_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP4_NAME: u32 = 0;
pub const XCHAL_CP4_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP5_NAME: u32 = 0;
pub const XCHAL_CP5_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP6_NAME: u32 = 0;
pub const XCHAL_CP6_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CP7_NAME: u32 = 0;
pub const XCHAL_CP7_SA_CONTENTS_LIBDB_NUM: u32 = 0;
pub const XCHAL_CPEXTRA_SA_SIZE_TOR2: u32 = 128;
pub const XCHAL_INST_ILLN: u32 = 61549;
pub const XCHAL_INST_ILLN_BYTE0: u32 = 109;
pub const XCHAL_INST_ILLN_BYTE1: u32 = 240;
pub const XTHAL_INST_ILL: u32 = 0;
pub const XCHAL_ERRATUM_453: u32 = 0;
pub const XCHAL_ERRATUM_497: u32 = 0;
pub const XCHAL_ERRATUM_572: u32 = 1;
pub const XSHAL_USE_ABSOLUTE_LITERALS: u32 = 0;
pub const XSHAL_HAVE_TEXT_SECTION_LITERALS: u32 = 1;
pub const XTHAL_ABI_WINDOWED: u32 = 0;
pub const XTHAL_ABI_CALL0: u32 = 1;
pub const XTHAL_CLIB_NEWLIB: u32 = 0;
pub const XTHAL_CLIB_UCLIBC: u32 = 1;
pub const XTHAL_CLIB_XCLIB: u32 = 2;
pub const XSHAL_USE_FLOATING_POINT: u32 = 1;
pub const XSHAL_FLOATING_POINT_ABI: u32 = 0;
pub const XSHAL_IOBLOCK_CACHED_VADDR: u32 = 1879048192;
pub const XSHAL_IOBLOCK_CACHED_PADDR: u32 = 1879048192;
pub const XSHAL_IOBLOCK_CACHED_SIZE: u32 = 234881024;
pub const XSHAL_IOBLOCK_BYPASS_VADDR: u32 = 2415919104;
pub const XSHAL_IOBLOCK_BYPASS_PADDR: u32 = 2415919104;
pub const XSHAL_IOBLOCK_BYPASS_SIZE: u32 = 234881024;
pub const XSHAL_ROM_VADDR: u32 = 1342177280;
pub const XSHAL_ROM_PADDR: u32 = 1342177280;
pub const XSHAL_ROM_SIZE: u32 = 16777216;
pub const XSHAL_ROM_AVAIL_VADDR: u32 = 1342177280;
pub const XSHAL_ROM_AVAIL_VSIZE: u32 = 16777216;
pub const XSHAL_RAM_VADDR: u32 = 1610612736;
pub const XSHAL_RAM_PADDR: u32 = 1610612736;
pub const XSHAL_RAM_VSIZE: u32 = 536870912;
pub const XSHAL_RAM_PSIZE: u32 = 536870912;
pub const XSHAL_RAM_SIZE: u32 = 536870912;
pub const XSHAL_RAM_AVAIL_VADDR: u32 = 1610612736;
pub const XSHAL_RAM_AVAIL_VSIZE: u32 = 536870912;
pub const XSHAL_RAM_BYPASS_VADDR: u32 = 2684354560;
pub const XSHAL_RAM_BYPASS_PADDR: u32 = 2684354560;
pub const XSHAL_RAM_BYPASS_PSIZE: u32 = 536870912;
pub const XSHAL_SIMIO_CACHED_VADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_BYPASS_VADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_PADDR: u32 = 3221225472;
pub const XSHAL_SIMIO_SIZE: u32 = 536870912;
pub const XSHAL_MAGIC_EXIT: u32 = 0;
pub const XSHAL_ALLVALID_CACHEATTR_WRITEBACK: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_WRITEALLOC: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_WRITETHRU: u32 = 572657938;
pub const XSHAL_ALLVALID_CACHEATTR_BYPASS: u32 = 572662306;
pub const XSHAL_ALLVALID_CACHEATTR_DEFAULT: u32 = 572657938;
pub const XSHAL_STRICT_CACHEATTR_WRITEBACK: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_WRITEALLOC: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_WRITETHRU: u32 = 4294906143;
pub const XSHAL_STRICT_CACHEATTR_BYPASS: u32 = 4294910511;
pub const XSHAL_STRICT_CACHEATTR_DEFAULT: u32 = 4294906143;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITEBACK: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_WRITETHRU: u32 = 572657951;
pub const XSHAL_TRAPNULL_CACHEATTR_BYPASS: u32 = 572662319;
pub const XSHAL_TRAPNULL_CACHEATTR_DEFAULT: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITEBACK: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITEALLOC: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_WRITETHRU: u32 = 572657951;
pub const XSHAL_ISS_CACHEATTR_BYPASS: u32 = 572662319;
pub const XSHAL_ISS_CACHEATTR_DEFAULT: u32 = 572657951;
pub const XSHAL_ISS_PIPE_REGIONS: u32 = 0;
pub const XSHAL_ISS_SDRAM_REGIONS: u32 = 0;
pub const XSHAL_XT2000_CACHEATTR_WRITEBACK: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_WRITEALLOC: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_WRITETHRU: u32 = 4280422687;
pub const XSHAL_XT2000_CACHEATTR_BYPASS: u32 = 4280427055;
pub const XSHAL_XT2000_CACHEATTR_DEFAULT: u32 = 4280422687;
pub const XSHAL_XT2000_PIPE_REGIONS: u32 = 0;
pub const XSHAL_XT2000_SDRAM_REGIONS: u32 = 1088;
pub const XSHAL_VECTORS_PACKED: u32 = 0;
pub const XSHAL_STATIC_VECTOR_SELECT: u32 = 1;
pub const XSHAL_RESET_VECTOR_VADDR: u32 = 1073742848;
pub const XSHAL_RESET_VECTOR_PADDR: u32 = 1073742848;
pub const XSHAL_RESET_VECTOR_SIZE: u32 = 768;
pub const XSHAL_RESET_VECTOR_ISROM: u32 = 0;
pub const XSHAL_USER_VECTOR_SIZE: u32 = 56;
pub const XSHAL_USER_VECTOR_ISROM: u32 = 0;
pub const XSHAL_PROGRAMEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_USEREXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNEL_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNEL_VECTOR_ISROM: u32 = 0;
pub const XSHAL_STACKEDEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_KERNELEXC_VECTOR_SIZE: u32 = 56;
pub const XSHAL_DOUBLEEXC_VECTOR_SIZE: u32 = 64;
pub const XSHAL_DOUBLEEXC_VECTOR_ISROM: u32 = 0;
pub const XSHAL_WINDOW_VECTORS_SIZE: u32 = 376;
pub const XSHAL_WINDOW_VECTORS_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL2_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL2_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL3_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL3_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL4_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL4_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL5_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL5_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL6_VECTOR_SIZE: u32 = 56;
pub const XSHAL_INTLEVEL6_VECTOR_ISROM: u32 = 0;
pub const XSHAL_DEBUG_VECTOR_SIZE: u32 = 56;
pub const XSHAL_DEBUG_VECTOR_ISROM: u32 = 0;
pub const XSHAL_NMI_VECTOR_SIZE: u32 = 56;
pub const XSHAL_NMI_VECTOR_ISROM: u32 = 0;
pub const XSHAL_INTLEVEL7_VECTOR_SIZE: u32 = 56;
pub const EXCCAUSE_EXCCAUSE_SHIFT: u32 = 0;
pub const EXCCAUSE_EXCCAUSE_MASK: u32 = 63;
pub const EXCCAUSE_ILLEGAL: u32 = 0;
pub const EXCCAUSE_SYSCALL: u32 = 1;
pub const EXCCAUSE_INSTR_ERROR: u32 = 2;
pub const EXCCAUSE_IFETCHERROR: u32 = 2;
pub const EXCCAUSE_LOAD_STORE_ERROR: u32 = 3;
pub const EXCCAUSE_LOADSTOREERROR: u32 = 3;
pub const EXCCAUSE_LEVEL1_INTERRUPT: u32 = 4;
pub const EXCCAUSE_LEVEL1INTERRUPT: u32 = 4;
pub const EXCCAUSE_ALLOCA: u32 = 5;
pub const EXCCAUSE_DIVIDE_BY_ZERO: u32 = 6;
pub const EXCCAUSE_SPECULATION: u32 = 7;
pub const EXCCAUSE_PRIVILEGED: u32 = 8;
pub const EXCCAUSE_UNALIGNED: u32 = 9;
pub const EXCCAUSE_INSTR_DATA_ERROR: u32 = 12;
pub const EXCCAUSE_LOAD_STORE_DATA_ERROR: u32 = 13;
pub const EXCCAUSE_INSTR_ADDR_ERROR: u32 = 14;
pub const EXCCAUSE_LOAD_STORE_ADDR_ERROR: u32 = 15;
pub const EXCCAUSE_ITLB_MISS: u32 = 16;
pub const EXCCAUSE_ITLB_MULTIHIT: u32 = 17;
pub const EXCCAUSE_INSTR_RING: u32 = 18;
pub const EXCCAUSE_INSTR_PROHIBITED: u32 = 20;
pub const EXCCAUSE_DTLB_MISS: u32 = 24;
pub const EXCCAUSE_DTLB_MULTIHIT: u32 = 25;
pub const EXCCAUSE_LOAD_STORE_RING: u32 = 26;
pub const EXCCAUSE_LOAD_PROHIBITED: u32 = 28;
pub const EXCCAUSE_STORE_PROHIBITED: u32 = 29;
pub const EXCCAUSE_CP0_DISABLED: u32 = 32;
pub const EXCCAUSE_CP1_DISABLED: u32 = 33;
pub const EXCCAUSE_CP2_DISABLED: u32 = 34;
pub const EXCCAUSE_CP3_DISABLED: u32 = 35;
pub const EXCCAUSE_CP4_DISABLED: u32 = 36;
pub const EXCCAUSE_CP5_DISABLED: u32 = 37;
pub const EXCCAUSE_CP6_DISABLED: u32 = 38;
pub const EXCCAUSE_CP7_DISABLED: u32 = 39;
pub const PS_WOE_SHIFT: u32 = 18;
pub const PS_WOE_MASK: u32 = 262144;
pub const PS_WOE: u32 = 262144;
pub const PS_CALLINC_SHIFT: u32 = 16;
pub const PS_CALLINC_MASK: u32 = 196608;
pub const PS_OWB_SHIFT: u32 = 8;
pub const PS_OWB_MASK: u32 = 3840;
pub const PS_RING_SHIFT: u32 = 6;
pub const PS_RING_MASK: u32 = 192;
pub const PS_UM_SHIFT: u32 = 5;
pub const PS_UM_MASK: u32 = 32;
pub const PS_UM: u32 = 32;
pub const PS_EXCM_SHIFT: u32 = 4;
pub const PS_EXCM_MASK: u32 = 16;
pub const PS_EXCM: u32 = 16;
pub const PS_INTLEVEL_SHIFT: u32 = 0;
pub const PS_INTLEVEL_MASK: u32 = 15;
pub const PS_PROGSTACK_SHIFT: u32 = 5;
pub const PS_PROGSTACK_MASK: u32 = 32;
pub const PS_PROG_SHIFT: u32 = 5;
pub const PS_PROG_MASK: u32 = 32;
pub const PS_PROG: u32 = 32;
pub const DBREAKC_MASK_SHIFT: u32 = 0;
pub const DBREAKC_MASK_MASK: u32 = 63;
pub const DBREAKC_LOADBREAK_SHIFT: u32 = 30;
pub const DBREAKC_LOADBREAK_MASK: u32 = 1073741824;
pub const DBREAKC_STOREBREAK_SHIFT: u32 = 31;
pub const DBREAKC_STOREBREAK_MASK: u32 = 2147483648;
pub const DEBUGCAUSE_DEBUGINT_SHIFT: u32 = 5;
pub const DEBUGCAUSE_DEBUGINT_MASK: u32 = 32;
pub const DEBUGCAUSE_BREAKN_SHIFT: u32 = 4;
pub const DEBUGCAUSE_BREAKN_MASK: u32 = 16;
pub const DEBUGCAUSE_BREAK_SHIFT: u32 = 3;
pub const DEBUGCAUSE_BREAK_MASK: u32 = 8;
pub const DEBUGCAUSE_DBREAK_SHIFT: u32 = 2;
pub const DEBUGCAUSE_DBREAK_MASK: u32 = 4;
pub const DEBUGCAUSE_IBREAK_SHIFT: u32 = 1;
pub const DEBUGCAUSE_IBREAK_MASK: u32 = 2;
pub const DEBUGCAUSE_ICOUNT_SHIFT: u32 = 0;
pub const DEBUGCAUSE_ICOUNT_MASK: u32 = 1;
pub const MESR_MEME: u32 = 1;
pub const MESR_MEME_SHIFT: u32 = 0;
pub const MESR_DME: u32 = 2;
pub const MESR_DME_SHIFT: u32 = 1;
pub const MESR_RCE: u32 = 16;
pub const MESR_RCE_SHIFT: u32 = 4;
pub const MESR_ERRENAB: u32 = 256;
pub const MESR_ERRENAB_SHIFT: u32 = 8;
pub const MESR_ERRTEST: u32 = 512;
pub const MESR_ERRTEST_SHIFT: u32 = 9;
pub const MESR_DATEXC: u32 = 1024;
pub const MESR_DATEXC_SHIFT: u32 = 10;
pub const MESR_INSEXC: u32 = 2048;
pub const MESR_INSEXC_SHIFT: u32 = 11;
pub const MESR_WAYNUM_SHIFT: u32 = 16;
pub const MESR_ACCTYPE_SHIFT: u32 = 20;
pub const MESR_MEMTYPE_SHIFT: u32 = 24;
pub const MESR_ERRTYPE_SHIFT: u32 = 30;
pub const MEMCTL_SNOOP_EN_SHIFT: u32 = 1;
pub const MEMCTL_SNOOP_EN: u32 = 2;
pub const MEMCTL_L0IBUF_EN_SHIFT: u32 = 0;
pub const MEMCTL_L0IBUF_EN: u32 = 1;
pub const MEMCTL_INV_EN_SHIFT: u32 = 23;
pub const MEMCTL_INV_EN: u32 = 8388608;
pub const MEMCTL_DCWU_SHIFT: u32 = 8;
pub const MEMCTL_DCWU_BITS: u32 = 5;
pub const MEMCTL_DCWA_SHIFT: u32 = 13;
pub const MEMCTL_DCWA_BITS: u32 = 5;
pub const MEMCTL_ICWU_SHIFT: u32 = 18;
pub const MEMCTL_ICWU_BITS: u32 = 5;
pub const MEMCTL_DCWU_MASK: u32 = 7936;
pub const MEMCTL_DCWA_MASK: u32 = 253952;
pub const MEMCTL_ICWU_MASK: u32 = 8126464;
pub const MEMCTL_DCWU_CLR_MASK: i32 = -7937;
pub const MEMCTL_DCWA_CLR_MASK: i32 = -253953;
pub const MEMCTL_ICWU_CLR_MASK: i32 = -8126465;
pub const MEMCTL_DCW_CLR_MASK: i32 = -1;
pub const MEMCTL_IDCW_CLR_MASK: i32 = -1;
pub const CALL0_ABI: u32 = 0;
pub const ALIGNPAD: u32 = 2;
pub const KERNELSTACKSIZE: u32 = 1024;
pub const XT_CP0_SA: u32 = 0;
pub const XT_CPENABLE: u32 = 0;
pub const XT_CPSTORED: u32 = 2;
pub const XT_CP_CS_ST: u32 = 4;
pub const XT_CP_ASA: u32 = 8;
pub const CORE_ID_PRO: u32 = 52685;
pub const CORE_ID_APP: u32 = 43947;
pub const STK_INTEXC_EXTRA: u32 = 0;
pub const XT_CLIB_CONTEXT_AREA_SIZE: u32 = 0;
pub const XT_USER_SIZE: u32 = 1024;
pub const __GNUCLIKE_ASM: u32 = 3;
pub const __GNUCLIKE___TYPEOF: u32 = 1;
pub const __GNUCLIKE___OFFSETOF: u32 = 1;
pub const __GNUCLIKE___SECTION: u32 = 1;
pub const __GNUCLIKE_CTOR_SECTION_HANDLING: u32 = 1;
pub const __GNUCLIKE_BUILTIN_CONSTANT_P: u32 = 1;
pub const __GNUCLIKE_BUILTIN_VARARGS: u32 = 1;
pub const __GNUCLIKE_BUILTIN_STDARG: u32 = 1;
pub const __GNUCLIKE_BUILTIN_VAALIST: u32 = 1;
pub const __GNUC_VA_LIST_COMPATIBILITY: u32 = 1;
pub const __GNUCLIKE_BUILTIN_NEXT_ARG: u32 = 1;
pub const __GNUCLIKE_BUILTIN_MEMCPY: u32 = 1;
pub const __CC_SUPPORTS_INLINE: u32 = 1;
pub const __CC_SUPPORTS___INLINE: u32 = 1;
pub const __CC_SUPPORTS___INLINE__: u32 = 1;
pub const __CC_SUPPORTS___FUNC__: u32 = 1;
pub const __CC_SUPPORTS_WARNING: u32 = 1;
pub const __CC_SUPPORTS_VARADIC_XXX: u32 = 1;
pub const __CC_SUPPORTS_DYNAMIC_ARRAY_INIT: u32 = 1;
pub const __POSIX_VISIBLE: u32 = 200809;
pub const __XSI_VISIBLE: u32 = 700;
pub const __BSD_VISIBLE: u32 = 1;
pub const __ISO_C_VISIBLE: u32 = 2011;
pub const EXIT_FAILURE: u32 = 1;
pub const EXIT_SUCCESS: u32 = 0;
pub const RAND_MAX: u32 = 2147483647;
pub const true_: u32 = 1;
pub const false_: u32 = 0;
pub const __bool_true_false_are_defined: u32 = 1;
pub const BIT31: u32 = 2147483648;
pub const BIT30: u32 = 1073741824;
pub const BIT29: u32 = 536870912;
pub const BIT28: u32 = 268435456;
pub const BIT27: u32 = 134217728;
pub const BIT26: u32 = 67108864;
pub const BIT25: u32 = 33554432;
pub const BIT24: u32 = 16777216;
pub const BIT23: u32 = 8388608;
pub const BIT22: u32 = 4194304;
pub const BIT21: u32 = 2097152;
pub const BIT20: u32 = 1048576;
pub const BIT19: u32 = 524288;
pub const BIT18: u32 = 262144;
pub const BIT17: u32 = 131072;
pub const BIT16: u32 = 65536;
pub const BIT15: u32 = 32768;
pub const BIT14: u32 = 16384;
pub const BIT13: u32 = 8192;
pub const BIT12: u32 = 4096;
pub const BIT11: u32 = 2048;
pub const BIT10: u32 = 1024;
pub const BIT9: u32 = 512;
pub const BIT8: u32 = 256;
pub const BIT7: u32 = 128;
pub const BIT6: u32 = 64;
pub const BIT5: u32 = 32;
pub const BIT4: u32 = 16;
pub const BIT3: u32 = 8;
pub const BIT2: u32 = 4;
pub const BIT1: u32 = 2;
pub const BIT0: u32 = 1;
pub const PRO_CPU_NUM: u32 = 0;
pub const APP_CPU_NUM: u32 = 1;
pub const SOC_IROM_LOW: u32 = 1074593792;
pub const SOC_IROM_HIGH: u32 = 1077936128;
pub const SOC_DROM_LOW: u32 = 1061158912;
pub const SOC_DROM_HIGH: u32 = 1065353216;
pub const SOC_DRAM_LOW: u32 = 1068367872;
pub const SOC_DRAM_HIGH: u32 = 1073741824;
pub const SOC_RTC_IRAM_LOW: u32 = 1074528256;
pub const SOC_RTC_IRAM_HIGH: u32 = 1074536448;
pub const SOC_RTC_DATA_LOW: u32 = 1342177280;
pub const SOC_RTC_DATA_HIGH: u32 = 1342185472;
pub const SOC_EXTRAM_DATA_LOW: u32 = 1065353216;
pub const SOC_EXTRAM_DATA_HIGH: u32 = 1069547520;
pub const SOC_MAX_CONTIGUOUS_RAM_SIZE: u32 = 4194304;
pub const DR_REG_DPORT_BASE: u32 = 1072693248;
pub const DR_REG_AES_BASE: u32 = 1072697344;
pub const DR_REG_RSA_BASE: u32 = 1072701440;
pub const DR_REG_SHA_BASE: u32 = 1072705536;
pub const DR_REG_FLASH_MMU_TABLE_PRO: u32 = 1072758784;
pub const DR_REG_FLASH_MMU_TABLE_APP: u32 = 1072766976;
pub const DR_REG_DPORT_END: u32 = 1072775164;
pub const DR_REG_UART_BASE: u32 = 1072955392;
pub const DR_REG_SPI1_BASE: u32 = 1072963584;
pub const DR_REG_SPI0_BASE: u32 = 1072967680;
pub const DR_REG_GPIO_BASE: u32 = 1072971776;
pub const DR_REG_GPIO_SD_BASE: u32 = 1072975616;
pub const DR_REG_FE2_BASE: u32 = 1072975872;
pub const DR_REG_FE_BASE: u32 = 1072979968;
pub const DR_REG_FRC_TIMER_BASE: u32 = 1072984064;
pub const DR_REG_RTCCNTL_BASE: u32 = 1072988160;
pub const DR_REG_RTCIO_BASE: u32 = 1072989184;
pub const DR_REG_SENS_BASE: u32 = 1072990208;
pub const DR_REG_RTC_I2C_BASE: u32 = 1072991232;
pub const DR_REG_IO_MUX_BASE: u32 = 1072992256;
pub const DR_REG_HINF_BASE: u32 = 1073000448;
pub const DR_REG_UHCI1_BASE: u32 = 1073004544;
pub const DR_REG_I2S_BASE: u32 = 1073016832;
pub const DR_REG_UART1_BASE: u32 = 1073020928;
pub const DR_REG_BT_BASE: u32 = 1073025024;
pub const DR_REG_I2C_EXT_BASE: u32 = 1073033216;
pub const DR_REG_UHCI0_BASE: u32 = 1073037312;
pub const DR_REG_SLCHOST_BASE: u32 = 1073041408;
pub const DR_REG_RMT_BASE: u32 = 1073045504;
pub const DR_REG_PCNT_BASE: u32 = 1073049600;
pub const DR_REG_SLC_BASE: u32 = 1073053696;
pub const DR_REG_LEDC_BASE: u32 = 1073057792;
pub const DR_REG_EFUSE_BASE: u32 = 1073061888;
pub const DR_REG_SPI_ENCRYPT_BASE: u32 = 1073065984;
pub const DR_REG_NRX_BASE: u32 = 1073073152;
pub const DR_REG_BB_BASE: u32 = 1073074176;
pub const DR_REG_PWM_BASE: u32 = 1073078272;
pub const DR_REG_TIMERGROUP0_BASE: u32 = 1073082368;
pub const DR_REG_TIMERGROUP1_BASE: u32 = 1073086464;
pub const DR_REG_RTCMEM0_BASE: u32 = 1073090560;
pub const DR_REG_RTCMEM1_BASE: u32 = 1073094656;
pub const DR_REG_RTCMEM2_BASE: u32 = 1073098752;
pub const DR_REG_SPI2_BASE: u32 = 1073102848;
pub const DR_REG_SPI3_BASE: u32 = 1073106944;
pub const DR_REG_SYSCON_BASE: u32 = 1073111040;
pub const DR_REG_APB_CTRL_BASE: u32 = 1073111040;
pub const DR_REG_I2C1_EXT_BASE: u32 = 1073115136;
pub const DR_REG_SDMMC_BASE: u32 = 1073119232;
pub const DR_REG_EMAC_BASE: u32 = 1073123328;
pub const DR_REG_CAN_BASE: u32 = 1073131520;
pub const DR_REG_PWM1_BASE: u32 = 1073135616;
pub const DR_REG_I2S1_BASE: u32 = 1073139712;
pub const DR_REG_UART2_BASE: u32 = 1073143808;
pub const DR_REG_PWM2_BASE: u32 = 1073147904;
pub const DR_REG_PWM3_BASE: u32 = 1073152000;
pub const PERIPHS_SPI_ENCRYPT_BASEADDR: u32 = 1073065984;
pub const APB_CLK_FREQ_ROM: u32 = 26000000;
pub const CPU_CLK_FREQ_ROM: u32 = 26000000;
pub const APB_CLK_FREQ: u32 = 80000000;
pub const REF_CLK_FREQ: u32 = 1000000;
pub const UART_CLK_FREQ: u32 = 80000000;
pub const WDT_CLK_FREQ: u32 = 80000000;
pub const TIMER_CLK_FREQ: u32 = 5000000;
pub const SPI_CLK_DIV: u32 = 4;
pub const TICKS_PER_US_ROM: u32 = 26;
pub const SOC_IROM_MASK_LOW: u32 = 1073741824;
pub const SOC_IROM_MASK_HIGH: u32 = 1074200576;
pub const SOC_CACHE_PRO_LOW: u32 = 1074200576;
pub const SOC_CACHE_PRO_HIGH: u32 = 1074233344;
pub const SOC_CACHE_APP_LOW: u32 = 1074233344;
pub const SOC_CACHE_APP_HIGH: u32 = 1074266112;
pub const SOC_IRAM_LOW: u32 = 1074266112;
pub const SOC_IRAM_HIGH: u32 = 1074397184;
pub const SOC_RTC_DRAM_LOW: u32 = 1073217536;
pub const SOC_RTC_DRAM_HIGH: u32 = 1073225728;
pub const SOC_DIRAM_IRAM_LOW: u32 = 1074397184;
pub const SOC_DIRAM_IRAM_HIGH: u32 = 1074528252;
pub const SOC_DIRAM_DRAM_LOW: u32 = 1073610752;
pub const SOC_DIRAM_DRAM_HIGH: u32 = 1073741820;
pub const SOC_DMA_LOW: u32 = 1073405952;
pub const SOC_DMA_HIGH: u32 = 1073741824;
pub const SOC_BYTE_ACCESSIBLE_LOW: u32 = 1073283072;
pub const SOC_BYTE_ACCESSIBLE_HIGH: u32 = 1073741824;
pub const SOC_MEM_INTERNAL_LOW: u32 = 1073283072;
pub const SOC_MEM_INTERNAL_HIGH: u32 = 1074536448;
pub const ETS_WIFI_MAC_INTR_SOURCE: u32 = 0;
pub const ETS_WIFI_MAC_NMI_SOURCE: u32 = 1;
pub const ETS_WIFI_BB_INTR_SOURCE: u32 = 2;
pub const ETS_BT_MAC_INTR_SOURCE: u32 = 3;
pub const ETS_BT_BB_INTR_SOURCE: u32 = 4;
pub const ETS_BT_BB_NMI_SOURCE: u32 = 5;
pub const ETS_RWBT_INTR_SOURCE: u32 = 6;
pub const ETS_RWBLE_INTR_SOURCE: u32 = 7;
pub const ETS_RWBT_NMI_SOURCE: u32 = 8;
pub const ETS_RWBLE_NMI_SOURCE: u32 = 9;
pub const ETS_SLC0_INTR_SOURCE: u32 = 10;
pub const ETS_SLC1_INTR_SOURCE: u32 = 11;
pub const ETS_UHCI0_INTR_SOURCE: u32 = 12;
pub const ETS_UHCI1_INTR_SOURCE: u32 = 13;
pub const ETS_TG0_T0_LEVEL_INTR_SOURCE: u32 = 14;
pub const ETS_TG0_T1_LEVEL_INTR_SOURCE: u32 = 15;
pub const ETS_TG0_WDT_LEVEL_INTR_SOURCE: u32 = 16;
pub const ETS_TG0_LACT_LEVEL_INTR_SOURCE: u32 = 17;
pub const ETS_TG1_T0_LEVEL_INTR_SOURCE: u32 = 18;
pub const ETS_TG1_T1_LEVEL_INTR_SOURCE: u32 = 19;
pub const ETS_TG1_WDT_LEVEL_INTR_SOURCE: u32 = 20;
pub const ETS_TG1_LACT_LEVEL_INTR_SOURCE: u32 = 21;
pub const ETS_GPIO_INTR_SOURCE: u32 = 22;
pub const ETS_GPIO_NMI_SOURCE: u32 = 23;
pub const ETS_FROM_CPU_INTR0_SOURCE: u32 = 24;
pub const ETS_FROM_CPU_INTR1_SOURCE: u32 = 25;
pub const ETS_FROM_CPU_INTR2_SOURCE: u32 = 26;
pub const ETS_FROM_CPU_INTR3_SOURCE: u32 = 27;
pub const ETS_SPI0_INTR_SOURCE: u32 = 28;
pub const ETS_SPI1_INTR_SOURCE: u32 = 29;
pub const ETS_SPI2_INTR_SOURCE: u32 = 30;
pub const ETS_SPI3_INTR_SOURCE: u32 = 31;
pub const ETS_I2S0_INTR_SOURCE: u32 = 32;
pub const ETS_I2S1_INTR_SOURCE: u32 = 33;
pub const ETS_UART0_INTR_SOURCE: u32 = 34;
pub const ETS_UART1_INTR_SOURCE: u32 = 35;
pub const ETS_UART2_INTR_SOURCE: u32 = 36;
pub const ETS_SDIO_HOST_INTR_SOURCE: u32 = 37;
pub const ETS_ETH_MAC_INTR_SOURCE: u32 = 38;
pub const ETS_PWM0_INTR_SOURCE: u32 = 39;
pub const ETS_PWM1_INTR_SOURCE: u32 = 40;
pub const ETS_PWM2_INTR_SOURCE: u32 = 41;
pub const ETS_PWM3_INTR_SOURCE: u32 = 42;
pub const ETS_LEDC_INTR_SOURCE: u32 = 43;
pub const ETS_EFUSE_INTR_SOURCE: u32 = 44;
pub const ETS_CAN_INTR_SOURCE: u32 = 45;
pub const ETS_RTC_CORE_INTR_SOURCE: u32 = 46;
pub const ETS_RMT_INTR_SOURCE: u32 = 47;
pub const ETS_PCNT_INTR_SOURCE: u32 = 48;
pub const ETS_I2C_EXT0_INTR_SOURCE: u32 = 49;
pub const ETS_I2C_EXT1_INTR_SOURCE: u32 = 50;
pub const ETS_RSA_INTR_SOURCE: u32 = 51;
pub const ETS_SPI1_DMA_INTR_SOURCE: u32 = 52;
pub const ETS_SPI2_DMA_INTR_SOURCE: u32 = 53;
pub const ETS_SPI3_DMA_INTR_SOURCE: u32 = 54;
pub const ETS_WDT_INTR_SOURCE: u32 = 55;
pub const ETS_TIMER1_INTR_SOURCE: u32 = 56;
pub const ETS_TIMER2_INTR_SOURCE: u32 = 57;
pub const ETS_TG0_T0_EDGE_INTR_SOURCE: u32 = 58;
pub const ETS_TG0_T1_EDGE_INTR_SOURCE: u32 = 59;
pub const ETS_TG0_WDT_EDGE_INTR_SOURCE: u32 = 60;
pub const ETS_TG0_LACT_EDGE_INTR_SOURCE: u32 = 61;
pub const ETS_TG1_T0_EDGE_INTR_SOURCE: u32 = 62;
pub const ETS_TG1_T1_EDGE_INTR_SOURCE: u32 = 63;
pub const ETS_TG1_WDT_EDGE_INTR_SOURCE: u32 = 64;
pub const ETS_TG1_LACT_EDGE_INTR_SOURCE: u32 = 65;
pub const ETS_MMU_IA_INTR_SOURCE: u32 = 66;
pub const ETS_MPU_IA_INTR_SOURCE: u32 = 67;
pub const ETS_CACHE_IA_INTR_SOURCE: u32 = 68;
pub const ETS_WMAC_INUM: u32 = 0;
pub const ETS_BT_HOST_INUM: u32 = 1;
pub const ETS_WBB_INUM: u32 = 4;
pub const ETS_TG0_T1_INUM: u32 = 10;
pub const ETS_FRC1_INUM: u32 = 22;
pub const ETS_T1_WDT_INUM: u32 = 24;
pub const ETS_CACHEERR_INUM: u32 = 25;
pub const ETS_DPORT_INUM: u32 = 28;
pub const ETS_SLC_INUM: u32 = 1;
pub const ETS_UART0_INUM: u32 = 5;
pub const ETS_UART1_INUM: u32 = 5;
pub const ETS_INVALID_INUM: u32 = 6;
pub const MACSTR: &'static [u8; 30usize] = b"%02x:%02x:%02x:%02x:%02x:%02x\0";
pub const configUSE_PREEMPTION: u32 = 1;
pub const configUSE_IDLE_HOOK: u32 = 1;
pub const configUSE_TICK_HOOK: u32 = 1;
pub const configTICK_RATE_HZ: u32 = 100;
pub const configMAX_PRIORITIES: u32 = 25;
pub const configMINIMAL_STACK_SIZE: u32 = 768;
pub const configIDLE_TASK_STACK_SIZE: u32 = 1536;
pub const configISR_STACK_SIZE: u32 = 1536;
pub const configAPPLICATION_ALLOCATED_HEAP: u32 = 1;
pub const configMAX_TASK_NAME_LEN: u32 = 16;
pub const configUSE_TRACE_FACILITY_2: u32 = 0;
pub const configBENCHMARK: u32 = 0;
pub const configUSE_16_BIT_TICKS: u32 = 0;
pub const configIDLE_SHOULD_YIELD: u32 = 0;
pub const configQUEUE_REGISTRY_SIZE: u32 = 0;
pub const configUSE_MUTEXES: u32 = 1;
pub const configUSE_RECURSIVE_MUTEXES: u32 = 1;
pub const configUSE_COUNTING_SEMAPHORES: u32 = 1;
pub const configCHECK_FOR_STACK_OVERFLOW: u32 = 2;
pub const configUSE_CO_ROUTINES: u32 = 0;
pub const configMAX_CO_ROUTINE_PRIORITIES: u32 = 2;
pub const INCLUDE_vTaskPrioritySet: u32 = 1;
pub const INCLUDE_uxTaskPriorityGet: u32 = 1;
pub const INCLUDE_vTaskDelete: u32 = 1;
pub const INCLUDE_vTaskCleanUpResources: u32 = 0;
pub const INCLUDE_vTaskSuspend: u32 = 1;
pub const INCLUDE_vTaskDelayUntil: u32 = 1;
pub const INCLUDE_vTaskDelay: u32 = 1;
pub const INCLUDE_uxTaskGetStackHighWaterMark: u32 = 1;
pub const INCLUDE_pcTaskGetTaskName: u32 = 1;
pub const INCLUDE_xTaskGetIdleTaskHandle: u32 = 1;
pub const INCLUDE_pxTaskGetStackStart: u32 = 1;
pub const INCLUDE_xSemaphoreGetMutexHolder: u32 = 1;
pub const configKERNEL_INTERRUPT_PRIORITY: u32 = 1;
pub const configMAX_SYSCALL_INTERRUPT_PRIORITY: u32 = 3;
pub const configUSE_NEWLIB_REENTRANT: u32 = 1;
pub const configSUPPORT_DYNAMIC_ALLOCATION: u32 = 1;
pub const configUSE_TIMERS: u32 = 1;
pub const configTIMER_TASK_PRIORITY: u32 = 1;
pub const configTIMER_QUEUE_LENGTH: u32 = 10;
pub const configTIMER_TASK_STACK_DEPTH: u32 = 2048;
pub const INCLUDE_xTimerPendFunctionCall: u32 = 1;
pub const INCLUDE_eTaskGetState: u32 = 1;
pub const configUSE_QUEUE_SETS: u32 = 1;
pub const configXT_BOARD: u32 = 1;
pub const configXT_SIMULATOR: u32 = 0;
pub const configENABLE_TASK_SNAPSHOT: u32 = 1;
pub const errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY: i32 = -1;
pub const errQUEUE_BLOCKED: i32 = -4;
pub const errQUEUE_YIELD: i32 = -5;
pub const configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES: u32 = 0;
pub const pdINTEGRITY_CHECK_VALUE: u32 = 1515870810;
pub const LBEG: u32 = 0;
pub const LEND: u32 = 1;
pub const LCOUNT: u32 = 2;
pub const SAR: u32 = 3;
pub const BR: u32 = 4;
pub const SCOMPARE1: u32 = 12;
pub const ACCLO: u32 = 16;
pub const ACCHI: u32 = 17;
pub const MR_0: u32 = 32;
pub const MR_1: u32 = 33;
pub const MR_2: u32 = 34;
pub const MR_3: u32 = 35;
pub const WINDOWBASE: u32 = 72;
pub const WINDOWSTART: u32 = 73;
pub const IBREAKENABLE: u32 = 96;
pub const MEMCTL: u32 = 97;
pub const ATOMCTL: u32 = 99;
pub const DDR: u32 = 104;
pub const IBREAKA_0: u32 = 128;
pub const IBREAKA_1: u32 = 129;
pub const DBREAKA_0: u32 = 144;
pub const DBREAKA_1: u32 = 145;
pub const DBREAKC_0: u32 = 160;
pub const DBREAKC_1: u32 = 161;
pub const EPC_1: u32 = 177;
pub const EPC_2: u32 = 178;
pub const EPC_3: u32 = 179;
pub const EPC_4: u32 = 180;
pub const EPC_5: u32 = 181;
pub const EPC_6: u32 = 182;
pub const EPC_7: u32 = 183;
pub const DEPC: u32 = 192;
pub const EPS_2: u32 = 194;
pub const EPS_3: u32 = 195;
pub const EPS_4: u32 = 196;
pub const EPS_5: u32 = 197;
pub const EPS_6: u32 = 198;
pub const EPS_7: u32 = 199;
pub const EXCSAVE_1: u32 = 209;
pub const EXCSAVE_2: u32 = 210;
pub const EXCSAVE_3: u32 = 211;
pub const EXCSAVE_4: u32 = 212;
pub const EXCSAVE_5: u32 = 213;
pub const EXCSAVE_6: u32 = 214;
pub const EXCSAVE_7: u32 = 215;
pub const CPENABLE: u32 = 224;
pub const INTERRUPT: u32 = 226;
pub const INTENABLE: u32 = 228;
pub const PS: u32 = 230;
pub const VECBASE: u32 = 231;
pub const EXCCAUSE: u32 = 232;
pub const DEBUGCAUSE: u32 = 233;
pub const CCOUNT: u32 = 234;
pub const PRID: u32 = 235;
pub const ICOUNT: u32 = 236;
pub const ICOUNTLEVEL: u32 = 237;
pub const EXCVADDR: u32 = 238;
pub const CCOMPARE_0: u32 = 240;
pub const CCOMPARE_1: u32 = 241;
pub const CCOMPARE_2: u32 = 242;
pub const MISC_REG_0: u32 = 244;
pub const MISC_REG_1: u32 = 245;
pub const MISC_REG_2: u32 = 246;
pub const MISC_REG_3: u32 = 247;
pub const MR: u32 = 32;
pub const IBREAKA: u32 = 128;
pub const DBREAKA: u32 = 144;
pub const DBREAKC: u32 = 160;
pub const EPC: u32 = 176;
pub const EPS: u32 = 192;
pub const EXCSAVE: u32 = 208;
pub const CCOMPARE: u32 = 240;
pub const INTREAD: u32 = 226;
pub const INTSET: u32 = 226;
pub const INTCLEAR: u32 = 227;
pub const CORE_STATE_SIGNATURE: u32 = 2982522861;
pub const XTOS_KEEPON_MEM: u32 = 256;
pub const XTOS_KEEPON_MEM_SHIFT: u32 = 8;
pub const XTOS_KEEPON_DEBUG: u32 = 4096;
pub const XTOS_KEEPON_DEBUG_SHIFT: u32 = 12;
pub const XTOS_COREF_PSO: u32 = 1;
pub const XTOS_COREF_PSO_SHIFT: u32 = 0;
pub const __GNUC_VA_LIST: u32 = 1;
pub const NBBY: u32 = 8;
pub const FD_SETSIZE: u32 = 64;
pub const SCHED_OTHER: u32 = 0;
pub const SCHED_FIFO: u32 = 1;
pub const SCHED_RR: u32 = 2;
pub const PTHREAD_SCOPE_PROCESS: u32 = 0;
pub const PTHREAD_SCOPE_SYSTEM: u32 = 1;
pub const PTHREAD_INHERIT_SCHED: u32 = 1;
pub const PTHREAD_EXPLICIT_SCHED: u32 = 2;
pub const PTHREAD_CREATE_DETACHED: u32 = 0;
pub const PTHREAD_CREATE_JOINABLE: u32 = 1;
pub const PTHREAD_MUTEX_NORMAL: u32 = 0;
pub const PTHREAD_MUTEX_RECURSIVE: u32 = 1;
pub const PTHREAD_MUTEX_ERRORCHECK: u32 = 2;
pub const PTHREAD_MUTEX_DEFAULT: u32 = 3;
pub const __SLBF: u32 = 1;
pub const __SNBF: u32 = 2;
pub const __SRD: u32 = 4;
pub const __SWR: u32 = 8;
pub const __SRW: u32 = 16;
pub const __SEOF: u32 = 32;
pub const __SERR: u32 = 64;
pub const __SMBF: u32 = 128;
pub const __SAPP: u32 = 256;
pub const __SSTR: u32 = 512;
pub const __SOPT: u32 = 1024;
pub const __SNPT: u32 = 2048;
pub const __SOFF: u32 = 4096;
pub const __SORD: u32 = 8192;
pub const __SL64: u32 = 32768;
pub const __SNLK: u32 = 1;
pub const __SWID: u32 = 8192;
pub const _IOFBF: u32 = 0;
pub const _IOLBF: u32 = 1;
pub const _IONBF: u32 = 2;
pub const EOF: i32 = -1;
pub const BUFSIZ: u32 = 128;
pub const FOPEN_MAX: u32 = 20;
pub const FILENAME_MAX: u32 = 1024;
pub const L_tmpnam: u32 = 1024;
pub const P_tmpdir: &'static [u8; 5usize] = b"/tmp\0";
pub const SEEK_SET: u32 = 0;
pub const SEEK_CUR: u32 = 1;
pub const SEEK_END: u32 = 2;
pub const TMP_MAX: u32 = 26;
pub const L_cuserid: u32 = 9;
pub const ESP_OK: u32 = 0;
pub const ESP_FAIL: i32 = -1;
pub const ESP_ERR_NO_MEM: u32 = 257;
pub const ESP_ERR_INVALID_ARG: u32 = 258;
pub const ESP_ERR_INVALID_STATE: u32 = 259;
pub const ESP_ERR_INVALID_SIZE: u32 = 260;
pub const ESP_ERR_NOT_FOUND: u32 = 261;
pub const ESP_ERR_NOT_SUPPORTED: u32 = 262;
pub const ESP_ERR_TIMEOUT: u32 = 263;
pub const ESP_ERR_INVALID_RESPONSE: u32 = 264;
pub const ESP_ERR_INVALID_CRC: u32 = 265;
pub const ESP_ERR_INVALID_VERSION: u32 = 266;
pub const ESP_ERR_INVALID_MAC: u32 = 267;
pub const ESP_ERR_WIFI_BASE: u32 = 12288;
pub const ESP_ERR_MESH_BASE: u32 = 16384;
pub const MALLOC_CAP_EXEC: u32 = 1;
pub const MALLOC_CAP_32BIT: u32 = 2;
pub const MALLOC_CAP_8BIT: u32 = 4;
pub const MALLOC_CAP_DMA: u32 = 8;
pub const MALLOC_CAP_PID2: u32 = 16;
pub const MALLOC_CAP_PID3: u32 = 32;
pub const MALLOC_CAP_PID4: u32 = 64;
pub const MALLOC_CAP_PID5: u32 = 128;
pub const MALLOC_CAP_PID6: u32 = 256;
pub const MALLOC_CAP_PID7: u32 = 512;
pub const MALLOC_CAP_SPIRAM: u32 = 1024;
pub const MALLOC_CAP_INTERNAL: u32 = 2048;
pub const MALLOC_CAP_DEFAULT: u32 = 4096;
pub const MALLOC_CAP_INVALID: u32 = 2147483648;
pub const SOC_MEMORY_TYPE_NO_PRIOS: u32 = 3;
pub const portMUX_FREE_VAL: u32 = 3007315967;
pub const portMUX_NO_TIMEOUT: i32 = -1;
pub const portMUX_TRY_LOCK: u32 = 0;
pub const portCRITICAL_NESTING_IN_TCB: u32 = 1;
pub const portTcbMemoryCaps: u32 = 2052;
pub const portStackMemoryCaps: u32 = 2052;
pub const portSTACK_GROWTH: i32 = -1;
pub const portBYTE_ALIGNMENT: u32 = 4;
pub const portBYTE_ALIGNMENT_MASK: u32 = 3;
pub const portNUM_CONFIGURABLE_REGIONS: u32 = 1;
pub const GPIO_BT_SELECT_REG: u32 = 1072971776;
pub const GPIO_BT_SEL: u32 = 4294967295;
pub const GPIO_BT_SEL_V: u32 = 4294967295;
pub const GPIO_BT_SEL_S: u32 = 0;
pub const GPIO_OUT_REG: u32 = 1072971780;
pub const GPIO_OUT_DATA: u32 = 4294967295;
pub const GPIO_OUT_DATA_V: u32 = 4294967295;
pub const GPIO_OUT_DATA_S: u32 = 0;
pub const GPIO_OUT_W1TS_REG: u32 = 1072971784;
pub const GPIO_OUT_DATA_W1TS: u32 = 4294967295;
pub const GPIO_OUT_DATA_W1TS_V: u32 = 4294967295;
pub const GPIO_OUT_DATA_W1TS_S: u32 = 0;
pub const GPIO_OUT_W1TC_REG: u32 = 1072971788;
pub const GPIO_OUT_DATA_W1TC: u32 = 4294967295;
pub const GPIO_OUT_DATA_W1TC_V: u32 = 4294967295;
pub const GPIO_OUT_DATA_W1TC_S: u32 = 0;
pub const GPIO_OUT1_REG: u32 = 1072971792;
pub const GPIO_OUT1_DATA: u32 = 255;
pub const GPIO_OUT1_DATA_V: u32 = 255;
pub const GPIO_OUT1_DATA_S: u32 = 0;
pub const GPIO_OUT1_W1TS_REG: u32 = 1072971796;
pub const GPIO_OUT1_DATA_W1TS: u32 = 255;
pub const GPIO_OUT1_DATA_W1TS_V: u32 = 255;
pub const GPIO_OUT1_DATA_W1TS_S: u32 = 0;
pub const GPIO_OUT1_W1TC_REG: u32 = 1072971800;
pub const GPIO_OUT1_DATA_W1TC: u32 = 255;
pub const GPIO_OUT1_DATA_W1TC_V: u32 = 255;
pub const GPIO_OUT1_DATA_W1TC_S: u32 = 0;
pub const GPIO_SDIO_SELECT_REG: u32 = 1072971804;
pub const GPIO_SDIO_SEL: u32 = 255;
pub const GPIO_SDIO_SEL_V: u32 = 255;
pub const GPIO_SDIO_SEL_S: u32 = 0;
pub const GPIO_ENABLE_REG: u32 = 1072971808;
pub const GPIO_ENABLE_DATA: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_V: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_S: u32 = 0;
pub const GPIO_ENABLE_W1TS_REG: u32 = 1072971812;
pub const GPIO_ENABLE_DATA_W1TS: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_W1TS_V: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_W1TS_S: u32 = 0;
pub const GPIO_ENABLE_W1TC_REG: u32 = 1072971816;
pub const GPIO_ENABLE_DATA_W1TC: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_W1TC_V: u32 = 4294967295;
pub const GPIO_ENABLE_DATA_W1TC_S: u32 = 0;
pub const GPIO_ENABLE1_REG: u32 = 1072971820;
pub const GPIO_ENABLE1_DATA: u32 = 255;
pub const GPIO_ENABLE1_DATA_V: u32 = 255;
pub const GPIO_ENABLE1_DATA_S: u32 = 0;
pub const GPIO_ENABLE1_W1TS_REG: u32 = 1072971824;
pub const GPIO_ENABLE1_DATA_W1TS: u32 = 255;
pub const GPIO_ENABLE1_DATA_W1TS_V: u32 = 255;
pub const GPIO_ENABLE1_DATA_W1TS_S: u32 = 0;
pub const GPIO_ENABLE1_W1TC_REG: u32 = 1072971828;
pub const GPIO_ENABLE1_DATA_W1TC: u32 = 255;
pub const GPIO_ENABLE1_DATA_W1TC_V: u32 = 255;
pub const GPIO_ENABLE1_DATA_W1TC_S: u32 = 0;
pub const GPIO_STRAP_REG: u32 = 1072971832;
pub const GPIO_STRAPPING: u32 = 65535;
pub const GPIO_STRAPPING_V: u32 = 65535;
pub const GPIO_STRAPPING_S: u32 = 0;
pub const GPIO_IN_REG: u32 = 1072971836;
pub const GPIO_IN_DATA: u32 = 4294967295;
pub const GPIO_IN_DATA_V: u32 = 4294967295;
pub const GPIO_IN_DATA_S: u32 = 0;
pub const GPIO_IN1_REG: u32 = 1072971840;
pub const GPIO_IN1_DATA: u32 = 255;
pub const GPIO_IN1_DATA_V: u32 = 255;
pub const GPIO_IN1_DATA_S: u32 = 0;
pub const GPIO_STATUS_REG: u32 = 1072971844;
pub const GPIO_STATUS_INT: u32 = 4294967295;
pub const GPIO_STATUS_INT_V: u32 = 4294967295;
pub const GPIO_STATUS_INT_S: u32 = 0;
pub const GPIO_STATUS_W1TS_REG: u32 = 1072971848;
pub const GPIO_STATUS_INT_W1TS: u32 = 4294967295;
pub const GPIO_STATUS_INT_W1TS_V: u32 = 4294967295;
pub const GPIO_STATUS_INT_W1TS_S: u32 = 0;
pub const GPIO_STATUS_W1TC_REG: u32 = 1072971852;
pub const GPIO_STATUS_INT_W1TC: u32 = 4294967295;
pub const GPIO_STATUS_INT_W1TC_V: u32 = 4294967295;
pub const GPIO_STATUS_INT_W1TC_S: u32 = 0;
pub const GPIO_STATUS1_REG: u32 = 1072971856;
pub const GPIO_STATUS1_INT: u32 = 255;
pub const GPIO_STATUS1_INT_V: u32 = 255;
pub const GPIO_STATUS1_INT_S: u32 = 0;
pub const GPIO_STATUS1_W1TS_REG: u32 = 1072971860;
pub const GPIO_STATUS1_INT_W1TS: u32 = 255;
pub const GPIO_STATUS1_INT_W1TS_V: u32 = 255;
pub const GPIO_STATUS1_INT_W1TS_S: u32 = 0;
pub const GPIO_STATUS1_W1TC_REG: u32 = 1072971864;
pub const GPIO_STATUS1_INT_W1TC: u32 = 255;
pub const GPIO_STATUS1_INT_W1TC_V: u32 = 255;
pub const GPIO_STATUS1_INT_W1TC_S: u32 = 0;
pub const GPIO_ACPU_INT_REG: u32 = 1072971872;
pub const GPIO_APPCPU_INT: u32 = 4294967295;
pub const GPIO_APPCPU_INT_V: u32 = 4294967295;
pub const GPIO_APPCPU_INT_S: u32 = 0;
pub const GPIO_ACPU_NMI_INT_REG: u32 = 1072971876;
pub const GPIO_APPCPU_NMI_INT: u32 = 4294967295;
pub const GPIO_APPCPU_NMI_INT_V: u32 = 4294967295;
pub const GPIO_APPCPU_NMI_INT_S: u32 = 0;
pub const GPIO_PCPU_INT_REG: u32 = 1072971880;
pub const GPIO_PROCPU_INT: u32 = 4294967295;
pub const GPIO_PROCPU_INT_V: u32 = 4294967295;
pub const GPIO_PROCPU_INT_S: u32 = 0;
pub const GPIO_PCPU_NMI_INT_REG: u32 = 1072971884;
pub const GPIO_PROCPU_NMI_INT: u32 = 4294967295;
pub const GPIO_PROCPU_NMI_INT_V: u32 = 4294967295;
pub const GPIO_PROCPU_NMI_INT_S: u32 = 0;
pub const GPIO_CPUSDIO_INT_REG: u32 = 1072971888;
pub const GPIO_SDIO_INT: u32 = 4294967295;
pub const GPIO_SDIO_INT_V: u32 = 4294967295;
pub const GPIO_SDIO_INT_S: u32 = 0;
pub const GPIO_ACPU_INT1_REG: u32 = 1072971892;
pub const GPIO_APPCPU_INT_H: u32 = 255;
pub const GPIO_APPCPU_INT_H_V: u32 = 255;
pub const GPIO_APPCPU_INT_H_S: u32 = 0;
pub const GPIO_ACPU_NMI_INT1_REG: u32 = 1072971896;
pub const GPIO_APPCPU_NMI_INT_H: u32 = 255;
pub const GPIO_APPCPU_NMI_INT_H_V: u32 = 255;
pub const GPIO_APPCPU_NMI_INT_H_S: u32 = 0;
pub const GPIO_PCPU_INT1_REG: u32 = 1072971900;
pub const GPIO_PROCPU_INT_H: u32 = 255;
pub const GPIO_PROCPU_INT_H_V: u32 = 255;
pub const GPIO_PROCPU_INT_H_S: u32 = 0;
pub const GPIO_PCPU_NMI_INT1_REG: u32 = 1072971904;
pub const GPIO_PROCPU_NMI_INT_H: u32 = 255;
pub const GPIO_PROCPU_NMI_INT_H_V: u32 = 255;
pub const GPIO_PROCPU_NMI_INT_H_S: u32 = 0;
pub const GPIO_CPUSDIO_INT1_REG: u32 = 1072971908;
pub const GPIO_SDIO_INT_H: u32 = 255;
pub const GPIO_SDIO_INT_H_V: u32 = 255;
pub const GPIO_SDIO_INT_H_S: u32 = 0;
pub const GPIO_PIN_INT_ENA: u32 = 31;
pub const GPIO_PIN_INT_ENA_V: u32 = 31;
pub const GPIO_PIN_INT_ENA_S: u32 = 13;
pub const GPIO_PIN_CONFIG: u32 = 3;
pub const GPIO_PIN_CONFIG_V: u32 = 3;
pub const GPIO_PIN_CONFIG_S: u32 = 11;
pub const GPIO_PIN_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN_INT_TYPE: u32 = 7;
pub const GPIO_PIN_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN0_REG: u32 = 1072971912;
pub const GPIO_PIN0_INT_ENA: u32 = 31;
pub const GPIO_PIN0_INT_ENA_V: u32 = 31;
pub const GPIO_PIN0_INT_ENA_S: u32 = 13;
pub const GPIO_PIN0_CONFIG: u32 = 3;
pub const GPIO_PIN0_CONFIG_V: u32 = 3;
pub const GPIO_PIN0_CONFIG_S: u32 = 11;
pub const GPIO_PIN0_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN0_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN0_INT_TYPE: u32 = 7;
pub const GPIO_PIN0_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN0_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN0_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN0_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN1_REG: u32 = 1072971916;
pub const GPIO_PIN1_INT_ENA: u32 = 31;
pub const GPIO_PIN1_INT_ENA_V: u32 = 31;
pub const GPIO_PIN1_INT_ENA_S: u32 = 13;
pub const GPIO_PIN1_CONFIG: u32 = 3;
pub const GPIO_PIN1_CONFIG_V: u32 = 3;
pub const GPIO_PIN1_CONFIG_S: u32 = 11;
pub const GPIO_PIN1_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN1_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN1_INT_TYPE: u32 = 7;
pub const GPIO_PIN1_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN1_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN1_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN1_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN2_REG: u32 = 1072971920;
pub const GPIO_PIN2_INT_ENA: u32 = 31;
pub const GPIO_PIN2_INT_ENA_V: u32 = 31;
pub const GPIO_PIN2_INT_ENA_S: u32 = 13;
pub const GPIO_PIN2_CONFIG: u32 = 3;
pub const GPIO_PIN2_CONFIG_V: u32 = 3;
pub const GPIO_PIN2_CONFIG_S: u32 = 11;
pub const GPIO_PIN2_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN2_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN2_INT_TYPE: u32 = 7;
pub const GPIO_PIN2_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN2_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN2_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN2_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN3_REG: u32 = 1072971924;
pub const GPIO_PIN3_INT_ENA: u32 = 31;
pub const GPIO_PIN3_INT_ENA_V: u32 = 31;
pub const GPIO_PIN3_INT_ENA_S: u32 = 13;
pub const GPIO_PIN3_CONFIG: u32 = 3;
pub const GPIO_PIN3_CONFIG_V: u32 = 3;
pub const GPIO_PIN3_CONFIG_S: u32 = 11;
pub const GPIO_PIN3_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN3_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN3_INT_TYPE: u32 = 7;
pub const GPIO_PIN3_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN3_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN3_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN3_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN4_REG: u32 = 1072971928;
pub const GPIO_PIN4_INT_ENA: u32 = 31;
pub const GPIO_PIN4_INT_ENA_V: u32 = 31;
pub const GPIO_PIN4_INT_ENA_S: u32 = 13;
pub const GPIO_PIN4_CONFIG: u32 = 3;
pub const GPIO_PIN4_CONFIG_V: u32 = 3;
pub const GPIO_PIN4_CONFIG_S: u32 = 11;
pub const GPIO_PIN4_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN4_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN4_INT_TYPE: u32 = 7;
pub const GPIO_PIN4_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN4_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN4_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN4_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN5_REG: u32 = 1072971932;
pub const GPIO_PIN5_INT_ENA: u32 = 31;
pub const GPIO_PIN5_INT_ENA_V: u32 = 31;
pub const GPIO_PIN5_INT_ENA_S: u32 = 13;
pub const GPIO_PIN5_CONFIG: u32 = 3;
pub const GPIO_PIN5_CONFIG_V: u32 = 3;
pub const GPIO_PIN5_CONFIG_S: u32 = 11;
pub const GPIO_PIN5_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN5_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN5_INT_TYPE: u32 = 7;
pub const GPIO_PIN5_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN5_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN5_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN5_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN6_REG: u32 = 1072971936;
pub const GPIO_PIN6_INT_ENA: u32 = 31;
pub const GPIO_PIN6_INT_ENA_V: u32 = 31;
pub const GPIO_PIN6_INT_ENA_S: u32 = 13;
pub const GPIO_PIN6_CONFIG: u32 = 3;
pub const GPIO_PIN6_CONFIG_V: u32 = 3;
pub const GPIO_PIN6_CONFIG_S: u32 = 11;
pub const GPIO_PIN6_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN6_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN6_INT_TYPE: u32 = 7;
pub const GPIO_PIN6_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN6_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN6_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN6_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN7_REG: u32 = 1072971940;
pub const GPIO_PIN7_INT_ENA: u32 = 31;
pub const GPIO_PIN7_INT_ENA_V: u32 = 31;
pub const GPIO_PIN7_INT_ENA_S: u32 = 13;
pub const GPIO_PIN7_CONFIG: u32 = 3;
pub const GPIO_PIN7_CONFIG_V: u32 = 3;
pub const GPIO_PIN7_CONFIG_S: u32 = 11;
pub const GPIO_PIN7_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN7_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN7_INT_TYPE: u32 = 7;
pub const GPIO_PIN7_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN7_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN7_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN7_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN8_REG: u32 = 1072971944;
pub const GPIO_PIN8_INT_ENA: u32 = 31;
pub const GPIO_PIN8_INT_ENA_V: u32 = 31;
pub const GPIO_PIN8_INT_ENA_S: u32 = 13;
pub const GPIO_PIN8_CONFIG: u32 = 3;
pub const GPIO_PIN8_CONFIG_V: u32 = 3;
pub const GPIO_PIN8_CONFIG_S: u32 = 11;
pub const GPIO_PIN8_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN8_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN8_INT_TYPE: u32 = 7;
pub const GPIO_PIN8_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN8_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN8_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN8_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN9_REG: u32 = 1072971948;
pub const GPIO_PIN9_INT_ENA: u32 = 31;
pub const GPIO_PIN9_INT_ENA_V: u32 = 31;
pub const GPIO_PIN9_INT_ENA_S: u32 = 13;
pub const GPIO_PIN9_CONFIG: u32 = 3;
pub const GPIO_PIN9_CONFIG_V: u32 = 3;
pub const GPIO_PIN9_CONFIG_S: u32 = 11;
pub const GPIO_PIN9_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN9_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN9_INT_TYPE: u32 = 7;
pub const GPIO_PIN9_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN9_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN9_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN9_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN10_REG: u32 = 1072971952;
pub const GPIO_PIN10_INT_ENA: u32 = 31;
pub const GPIO_PIN10_INT_ENA_V: u32 = 31;
pub const GPIO_PIN10_INT_ENA_S: u32 = 13;
pub const GPIO_PIN10_CONFIG: u32 = 3;
pub const GPIO_PIN10_CONFIG_V: u32 = 3;
pub const GPIO_PIN10_CONFIG_S: u32 = 11;
pub const GPIO_PIN10_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN10_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN10_INT_TYPE: u32 = 7;
pub const GPIO_PIN10_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN10_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN10_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN10_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN11_REG: u32 = 1072971956;
pub const GPIO_PIN11_INT_ENA: u32 = 31;
pub const GPIO_PIN11_INT_ENA_V: u32 = 31;
pub const GPIO_PIN11_INT_ENA_S: u32 = 13;
pub const GPIO_PIN11_CONFIG: u32 = 3;
pub const GPIO_PIN11_CONFIG_V: u32 = 3;
pub const GPIO_PIN11_CONFIG_S: u32 = 11;
pub const GPIO_PIN11_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN11_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN11_INT_TYPE: u32 = 7;
pub const GPIO_PIN11_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN11_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN11_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN11_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN12_REG: u32 = 1072971960;
pub const GPIO_PIN12_INT_ENA: u32 = 31;
pub const GPIO_PIN12_INT_ENA_V: u32 = 31;
pub const GPIO_PIN12_INT_ENA_S: u32 = 13;
pub const GPIO_PIN12_CONFIG: u32 = 3;
pub const GPIO_PIN12_CONFIG_V: u32 = 3;
pub const GPIO_PIN12_CONFIG_S: u32 = 11;
pub const GPIO_PIN12_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN12_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN12_INT_TYPE: u32 = 7;
pub const GPIO_PIN12_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN12_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN12_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN12_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN13_REG: u32 = 1072971964;
pub const GPIO_PIN13_INT_ENA: u32 = 31;
pub const GPIO_PIN13_INT_ENA_V: u32 = 31;
pub const GPIO_PIN13_INT_ENA_S: u32 = 13;
pub const GPIO_PIN13_CONFIG: u32 = 3;
pub const GPIO_PIN13_CONFIG_V: u32 = 3;
pub const GPIO_PIN13_CONFIG_S: u32 = 11;
pub const GPIO_PIN13_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN13_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN13_INT_TYPE: u32 = 7;
pub const GPIO_PIN13_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN13_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN13_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN13_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN14_REG: u32 = 1072971968;
pub const GPIO_PIN14_INT_ENA: u32 = 31;
pub const GPIO_PIN14_INT_ENA_V: u32 = 31;
pub const GPIO_PIN14_INT_ENA_S: u32 = 13;
pub const GPIO_PIN14_CONFIG: u32 = 3;
pub const GPIO_PIN14_CONFIG_V: u32 = 3;
pub const GPIO_PIN14_CONFIG_S: u32 = 11;
pub const GPIO_PIN14_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN14_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN14_INT_TYPE: u32 = 7;
pub const GPIO_PIN14_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN14_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN14_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN14_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN15_REG: u32 = 1072971972;
pub const GPIO_PIN15_INT_ENA: u32 = 31;
pub const GPIO_PIN15_INT_ENA_V: u32 = 31;
pub const GPIO_PIN15_INT_ENA_S: u32 = 13;
pub const GPIO_PIN15_CONFIG: u32 = 3;
pub const GPIO_PIN15_CONFIG_V: u32 = 3;
pub const GPIO_PIN15_CONFIG_S: u32 = 11;
pub const GPIO_PIN15_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN15_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN15_INT_TYPE: u32 = 7;
pub const GPIO_PIN15_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN15_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN15_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN15_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN16_REG: u32 = 1072971976;
pub const GPIO_PIN16_INT_ENA: u32 = 31;
pub const GPIO_PIN16_INT_ENA_V: u32 = 31;
pub const GPIO_PIN16_INT_ENA_S: u32 = 13;
pub const GPIO_PIN16_CONFIG: u32 = 3;
pub const GPIO_PIN16_CONFIG_V: u32 = 3;
pub const GPIO_PIN16_CONFIG_S: u32 = 11;
pub const GPIO_PIN16_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN16_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN16_INT_TYPE: u32 = 7;
pub const GPIO_PIN16_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN16_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN16_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN16_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN17_REG: u32 = 1072971980;
pub const GPIO_PIN17_INT_ENA: u32 = 31;
pub const GPIO_PIN17_INT_ENA_V: u32 = 31;
pub const GPIO_PIN17_INT_ENA_S: u32 = 13;
pub const GPIO_PIN17_CONFIG: u32 = 3;
pub const GPIO_PIN17_CONFIG_V: u32 = 3;
pub const GPIO_PIN17_CONFIG_S: u32 = 11;
pub const GPIO_PIN17_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN17_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN17_INT_TYPE: u32 = 7;
pub const GPIO_PIN17_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN17_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN17_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN17_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN18_REG: u32 = 1072971984;
pub const GPIO_PIN18_INT_ENA: u32 = 31;
pub const GPIO_PIN18_INT_ENA_V: u32 = 31;
pub const GPIO_PIN18_INT_ENA_S: u32 = 13;
pub const GPIO_PIN18_CONFIG: u32 = 3;
pub const GPIO_PIN18_CONFIG_V: u32 = 3;
pub const GPIO_PIN18_CONFIG_S: u32 = 11;
pub const GPIO_PIN18_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN18_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN18_INT_TYPE: u32 = 7;
pub const GPIO_PIN18_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN18_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN18_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN18_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN19_REG: u32 = 1072971988;
pub const GPIO_PIN19_INT_ENA: u32 = 31;
pub const GPIO_PIN19_INT_ENA_V: u32 = 31;
pub const GPIO_PIN19_INT_ENA_S: u32 = 13;
pub const GPIO_PIN19_CONFIG: u32 = 3;
pub const GPIO_PIN19_CONFIG_V: u32 = 3;
pub const GPIO_PIN19_CONFIG_S: u32 = 11;
pub const GPIO_PIN19_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN19_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN19_INT_TYPE: u32 = 7;
pub const GPIO_PIN19_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN19_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN19_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN19_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN20_REG: u32 = 1072971992;
pub const GPIO_PIN20_INT_ENA: u32 = 31;
pub const GPIO_PIN20_INT_ENA_V: u32 = 31;
pub const GPIO_PIN20_INT_ENA_S: u32 = 13;
pub const GPIO_PIN20_CONFIG: u32 = 3;
pub const GPIO_PIN20_CONFIG_V: u32 = 3;
pub const GPIO_PIN20_CONFIG_S: u32 = 11;
pub const GPIO_PIN20_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN20_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN20_INT_TYPE: u32 = 7;
pub const GPIO_PIN20_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN20_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN20_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN20_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN21_REG: u32 = 1072971996;
pub const GPIO_PIN21_INT_ENA: u32 = 31;
pub const GPIO_PIN21_INT_ENA_V: u32 = 31;
pub const GPIO_PIN21_INT_ENA_S: u32 = 13;
pub const GPIO_PIN21_CONFIG: u32 = 3;
pub const GPIO_PIN21_CONFIG_V: u32 = 3;
pub const GPIO_PIN21_CONFIG_S: u32 = 11;
pub const GPIO_PIN21_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN21_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN21_INT_TYPE: u32 = 7;
pub const GPIO_PIN21_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN21_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN21_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN21_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN22_REG: u32 = 1072972000;
pub const GPIO_PIN22_INT_ENA: u32 = 31;
pub const GPIO_PIN22_INT_ENA_V: u32 = 31;
pub const GPIO_PIN22_INT_ENA_S: u32 = 13;
pub const GPIO_PIN22_CONFIG: u32 = 3;
pub const GPIO_PIN22_CONFIG_V: u32 = 3;
pub const GPIO_PIN22_CONFIG_S: u32 = 11;
pub const GPIO_PIN22_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN22_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN22_INT_TYPE: u32 = 7;
pub const GPIO_PIN22_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN22_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN22_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN22_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN23_REG: u32 = 1072972004;
pub const GPIO_PIN23_INT_ENA: u32 = 31;
pub const GPIO_PIN23_INT_ENA_V: u32 = 31;
pub const GPIO_PIN23_INT_ENA_S: u32 = 13;
pub const GPIO_PIN23_CONFIG: u32 = 3;
pub const GPIO_PIN23_CONFIG_V: u32 = 3;
pub const GPIO_PIN23_CONFIG_S: u32 = 11;
pub const GPIO_PIN23_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN23_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN23_INT_TYPE: u32 = 7;
pub const GPIO_PIN23_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN23_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN23_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN23_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN24_REG: u32 = 1072972008;
pub const GPIO_PIN24_INT_ENA: u32 = 31;
pub const GPIO_PIN24_INT_ENA_V: u32 = 31;
pub const GPIO_PIN24_INT_ENA_S: u32 = 13;
pub const GPIO_PIN24_CONFIG: u32 = 3;
pub const GPIO_PIN24_CONFIG_V: u32 = 3;
pub const GPIO_PIN24_CONFIG_S: u32 = 11;
pub const GPIO_PIN24_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN24_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN24_INT_TYPE: u32 = 7;
pub const GPIO_PIN24_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN24_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN24_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN24_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN25_REG: u32 = 1072972012;
pub const GPIO_PIN25_INT_ENA: u32 = 31;
pub const GPIO_PIN25_INT_ENA_V: u32 = 31;
pub const GPIO_PIN25_INT_ENA_S: u32 = 13;
pub const GPIO_PIN25_CONFIG: u32 = 3;
pub const GPIO_PIN25_CONFIG_V: u32 = 3;
pub const GPIO_PIN25_CONFIG_S: u32 = 11;
pub const GPIO_PIN25_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN25_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN25_INT_TYPE: u32 = 7;
pub const GPIO_PIN25_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN25_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN25_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN25_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN26_REG: u32 = 1072972016;
pub const GPIO_PIN26_INT_ENA: u32 = 31;
pub const GPIO_PIN26_INT_ENA_V: u32 = 31;
pub const GPIO_PIN26_INT_ENA_S: u32 = 13;
pub const GPIO_PIN26_CONFIG: u32 = 3;
pub const GPIO_PIN26_CONFIG_V: u32 = 3;
pub const GPIO_PIN26_CONFIG_S: u32 = 11;
pub const GPIO_PIN26_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN26_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN26_INT_TYPE: u32 = 7;
pub const GPIO_PIN26_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN26_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN26_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN26_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN27_REG: u32 = 1072972020;
pub const GPIO_PIN27_INT_ENA: u32 = 31;
pub const GPIO_PIN27_INT_ENA_V: u32 = 31;
pub const GPIO_PIN27_INT_ENA_S: u32 = 13;
pub const GPIO_PIN27_CONFIG: u32 = 3;
pub const GPIO_PIN27_CONFIG_V: u32 = 3;
pub const GPIO_PIN27_CONFIG_S: u32 = 11;
pub const GPIO_PIN27_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN27_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN27_INT_TYPE: u32 = 7;
pub const GPIO_PIN27_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN27_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN27_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN27_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN28_REG: u32 = 1072972024;
pub const GPIO_PIN28_INT_ENA: u32 = 31;
pub const GPIO_PIN28_INT_ENA_V: u32 = 31;
pub const GPIO_PIN28_INT_ENA_S: u32 = 13;
pub const GPIO_PIN28_CONFIG: u32 = 3;
pub const GPIO_PIN28_CONFIG_V: u32 = 3;
pub const GPIO_PIN28_CONFIG_S: u32 = 11;
pub const GPIO_PIN28_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN28_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN28_INT_TYPE: u32 = 7;
pub const GPIO_PIN28_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN28_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN28_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN28_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN29_REG: u32 = 1072972028;
pub const GPIO_PIN29_INT_ENA: u32 = 31;
pub const GPIO_PIN29_INT_ENA_V: u32 = 31;
pub const GPIO_PIN29_INT_ENA_S: u32 = 13;
pub const GPIO_PIN29_CONFIG: u32 = 3;
pub const GPIO_PIN29_CONFIG_V: u32 = 3;
pub const GPIO_PIN29_CONFIG_S: u32 = 11;
pub const GPIO_PIN29_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN29_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN29_INT_TYPE: u32 = 7;
pub const GPIO_PIN29_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN29_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN29_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN29_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN30_REG: u32 = 1072972032;
pub const GPIO_PIN30_INT_ENA: u32 = 31;
pub const GPIO_PIN30_INT_ENA_V: u32 = 31;
pub const GPIO_PIN30_INT_ENA_S: u32 = 13;
pub const GPIO_PIN30_CONFIG: u32 = 3;
pub const GPIO_PIN30_CONFIG_V: u32 = 3;
pub const GPIO_PIN30_CONFIG_S: u32 = 11;
pub const GPIO_PIN30_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN30_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN30_INT_TYPE: u32 = 7;
pub const GPIO_PIN30_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN30_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN30_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN30_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN31_REG: u32 = 1072972036;
pub const GPIO_PIN31_INT_ENA: u32 = 31;
pub const GPIO_PIN31_INT_ENA_V: u32 = 31;
pub const GPIO_PIN31_INT_ENA_S: u32 = 13;
pub const GPIO_PIN31_CONFIG: u32 = 3;
pub const GPIO_PIN31_CONFIG_V: u32 = 3;
pub const GPIO_PIN31_CONFIG_S: u32 = 11;
pub const GPIO_PIN31_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN31_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN31_INT_TYPE: u32 = 7;
pub const GPIO_PIN31_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN31_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN31_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN31_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN32_REG: u32 = 1072972040;
pub const GPIO_PIN32_INT_ENA: u32 = 31;
pub const GPIO_PIN32_INT_ENA_V: u32 = 31;
pub const GPIO_PIN32_INT_ENA_S: u32 = 13;
pub const GPIO_PIN32_CONFIG: u32 = 3;
pub const GPIO_PIN32_CONFIG_V: u32 = 3;
pub const GPIO_PIN32_CONFIG_S: u32 = 11;
pub const GPIO_PIN32_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN32_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN32_INT_TYPE: u32 = 7;
pub const GPIO_PIN32_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN32_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN32_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN32_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN33_REG: u32 = 1072972044;
pub const GPIO_PIN33_INT_ENA: u32 = 31;
pub const GPIO_PIN33_INT_ENA_V: u32 = 31;
pub const GPIO_PIN33_INT_ENA_S: u32 = 13;
pub const GPIO_PIN33_CONFIG: u32 = 3;
pub const GPIO_PIN33_CONFIG_V: u32 = 3;
pub const GPIO_PIN33_CONFIG_S: u32 = 11;
pub const GPIO_PIN33_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN33_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN33_INT_TYPE: u32 = 7;
pub const GPIO_PIN33_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN33_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN33_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN33_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN34_REG: u32 = 1072972048;
pub const GPIO_PIN34_INT_ENA: u32 = 31;
pub const GPIO_PIN34_INT_ENA_V: u32 = 31;
pub const GPIO_PIN34_INT_ENA_S: u32 = 13;
pub const GPIO_PIN34_CONFIG: u32 = 3;
pub const GPIO_PIN34_CONFIG_V: u32 = 3;
pub const GPIO_PIN34_CONFIG_S: u32 = 11;
pub const GPIO_PIN34_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN34_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN34_INT_TYPE: u32 = 7;
pub const GPIO_PIN34_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN34_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN34_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN34_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN35_REG: u32 = 1072972052;
pub const GPIO_PIN35_INT_ENA: u32 = 31;
pub const GPIO_PIN35_INT_ENA_V: u32 = 31;
pub const GPIO_PIN35_INT_ENA_S: u32 = 13;
pub const GPIO_PIN35_CONFIG: u32 = 3;
pub const GPIO_PIN35_CONFIG_V: u32 = 3;
pub const GPIO_PIN35_CONFIG_S: u32 = 11;
pub const GPIO_PIN35_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN35_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN35_INT_TYPE: u32 = 7;
pub const GPIO_PIN35_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN35_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN35_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN35_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN36_REG: u32 = 1072972056;
pub const GPIO_PIN36_INT_ENA: u32 = 31;
pub const GPIO_PIN36_INT_ENA_V: u32 = 31;
pub const GPIO_PIN36_INT_ENA_S: u32 = 13;
pub const GPIO_PIN36_CONFIG: u32 = 3;
pub const GPIO_PIN36_CONFIG_V: u32 = 3;
pub const GPIO_PIN36_CONFIG_S: u32 = 11;
pub const GPIO_PIN36_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN36_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN36_INT_TYPE: u32 = 7;
pub const GPIO_PIN36_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN36_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN36_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN36_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN37_REG: u32 = 1072972060;
pub const GPIO_PIN37_INT_ENA: u32 = 31;
pub const GPIO_PIN37_INT_ENA_V: u32 = 31;
pub const GPIO_PIN37_INT_ENA_S: u32 = 13;
pub const GPIO_PIN37_CONFIG: u32 = 3;
pub const GPIO_PIN37_CONFIG_V: u32 = 3;
pub const GPIO_PIN37_CONFIG_S: u32 = 11;
pub const GPIO_PIN37_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN37_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN37_INT_TYPE: u32 = 7;
pub const GPIO_PIN37_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN37_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN37_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN37_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN38_REG: u32 = 1072972064;
pub const GPIO_PIN38_INT_ENA: u32 = 31;
pub const GPIO_PIN38_INT_ENA_V: u32 = 31;
pub const GPIO_PIN38_INT_ENA_S: u32 = 13;
pub const GPIO_PIN38_CONFIG: u32 = 3;
pub const GPIO_PIN38_CONFIG_V: u32 = 3;
pub const GPIO_PIN38_CONFIG_S: u32 = 11;
pub const GPIO_PIN38_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN38_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN38_INT_TYPE: u32 = 7;
pub const GPIO_PIN38_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN38_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN38_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN38_PAD_DRIVER_S: u32 = 2;
pub const GPIO_PIN39_REG: u32 = 1072972068;
pub const GPIO_PIN39_INT_ENA: u32 = 31;
pub const GPIO_PIN39_INT_ENA_V: u32 = 31;
pub const GPIO_PIN39_INT_ENA_S: u32 = 13;
pub const GPIO_PIN39_CONFIG: u32 = 3;
pub const GPIO_PIN39_CONFIG_V: u32 = 3;
pub const GPIO_PIN39_CONFIG_S: u32 = 11;
pub const GPIO_PIN39_WAKEUP_ENABLE_V: u32 = 1;
pub const GPIO_PIN39_WAKEUP_ENABLE_S: u32 = 10;
pub const GPIO_PIN39_INT_TYPE: u32 = 7;
pub const GPIO_PIN39_INT_TYPE_V: u32 = 7;
pub const GPIO_PIN39_INT_TYPE_S: u32 = 7;
pub const GPIO_PIN39_PAD_DRIVER_V: u32 = 1;
pub const GPIO_PIN39_PAD_DRIVER_S: u32 = 2;
pub const GPIO_cali_conf_REG: u32 = 1072972072;
pub const GPIO_CALI_START_V: u32 = 1;
pub const GPIO_CALI_START_S: u32 = 31;
pub const GPIO_CALI_RTC_MAX: u32 = 1023;
pub const GPIO_CALI_RTC_MAX_V: u32 = 1023;
pub const GPIO_CALI_RTC_MAX_S: u32 = 0;
pub const GPIO_cali_data_REG: u32 = 1072972076;
pub const GPIO_CALI_RDY_SYNC2_V: u32 = 1;
pub const GPIO_CALI_RDY_SYNC2_S: u32 = 31;
pub const GPIO_CALI_RDY_REAL_V: u32 = 1;
pub const GPIO_CALI_RDY_REAL_S: u32 = 30;
pub const GPIO_CALI_VALUE_SYNC2: u32 = 1048575;
pub const GPIO_CALI_VALUE_SYNC2_V: u32 = 1048575;
pub const GPIO_CALI_VALUE_SYNC2_S: u32 = 0;
pub const GPIO_FUNC0_IN_SEL_CFG_REG: u32 = 1072972080;
pub const GPIO_SIG0_IN_SEL_V: u32 = 1;
pub const GPIO_SIG0_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC0_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC0_IN_SEL: u32 = 63;
pub const GPIO_FUNC0_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC0_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC1_IN_SEL_CFG_REG: u32 = 1072972084;
pub const GPIO_SIG1_IN_SEL_V: u32 = 1;
pub const GPIO_SIG1_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC1_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC1_IN_SEL: u32 = 63;
pub const GPIO_FUNC1_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC1_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC2_IN_SEL_CFG_REG: u32 = 1072972088;
pub const GPIO_SIG2_IN_SEL_V: u32 = 1;
pub const GPIO_SIG2_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC2_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC2_IN_SEL: u32 = 63;
pub const GPIO_FUNC2_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC2_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC3_IN_SEL_CFG_REG: u32 = 1072972092;
pub const GPIO_SIG3_IN_SEL_V: u32 = 1;
pub const GPIO_SIG3_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC3_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC3_IN_SEL: u32 = 63;
pub const GPIO_FUNC3_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC3_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC4_IN_SEL_CFG_REG: u32 = 1072972096;
pub const GPIO_SIG4_IN_SEL_V: u32 = 1;
pub const GPIO_SIG4_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC4_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC4_IN_SEL: u32 = 63;
pub const GPIO_FUNC4_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC4_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC5_IN_SEL_CFG_REG: u32 = 1072972100;
pub const GPIO_SIG5_IN_SEL_V: u32 = 1;
pub const GPIO_SIG5_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC5_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC5_IN_SEL: u32 = 63;
pub const GPIO_FUNC5_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC5_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC6_IN_SEL_CFG_REG: u32 = 1072972104;
pub const GPIO_SIG6_IN_SEL_V: u32 = 1;
pub const GPIO_SIG6_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC6_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC6_IN_SEL: u32 = 63;
pub const GPIO_FUNC6_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC6_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC7_IN_SEL_CFG_REG: u32 = 1072972108;
pub const GPIO_SIG7_IN_SEL_V: u32 = 1;
pub const GPIO_SIG7_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC7_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC7_IN_SEL: u32 = 63;
pub const GPIO_FUNC7_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC7_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC8_IN_SEL_CFG_REG: u32 = 1072972112;
pub const GPIO_SIG8_IN_SEL_V: u32 = 1;
pub const GPIO_SIG8_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC8_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC8_IN_SEL: u32 = 63;
pub const GPIO_FUNC8_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC8_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC9_IN_SEL_CFG_REG: u32 = 1072972116;
pub const GPIO_SIG9_IN_SEL_V: u32 = 1;
pub const GPIO_SIG9_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC9_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC9_IN_SEL: u32 = 63;
pub const GPIO_FUNC9_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC9_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC10_IN_SEL_CFG_REG: u32 = 1072972120;
pub const GPIO_SIG10_IN_SEL_V: u32 = 1;
pub const GPIO_SIG10_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC10_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC10_IN_SEL: u32 = 63;
pub const GPIO_FUNC10_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC10_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC11_IN_SEL_CFG_REG: u32 = 1072972124;
pub const GPIO_SIG11_IN_SEL_V: u32 = 1;
pub const GPIO_SIG11_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC11_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC11_IN_SEL: u32 = 63;
pub const GPIO_FUNC11_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC11_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC12_IN_SEL_CFG_REG: u32 = 1072972128;
pub const GPIO_SIG12_IN_SEL_V: u32 = 1;
pub const GPIO_SIG12_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC12_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC12_IN_SEL: u32 = 63;
pub const GPIO_FUNC12_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC12_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC13_IN_SEL_CFG_REG: u32 = 1072972132;
pub const GPIO_SIG13_IN_SEL_V: u32 = 1;
pub const GPIO_SIG13_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC13_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC13_IN_SEL: u32 = 63;
pub const GPIO_FUNC13_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC13_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC14_IN_SEL_CFG_REG: u32 = 1072972136;
pub const GPIO_SIG14_IN_SEL_V: u32 = 1;
pub const GPIO_SIG14_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC14_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC14_IN_SEL: u32 = 63;
pub const GPIO_FUNC14_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC14_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC15_IN_SEL_CFG_REG: u32 = 1072972140;
pub const GPIO_SIG15_IN_SEL_V: u32 = 1;
pub const GPIO_SIG15_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC15_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC15_IN_SEL: u32 = 63;
pub const GPIO_FUNC15_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC15_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC16_IN_SEL_CFG_REG: u32 = 1072972144;
pub const GPIO_SIG16_IN_SEL_V: u32 = 1;
pub const GPIO_SIG16_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC16_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC16_IN_SEL: u32 = 63;
pub const GPIO_FUNC16_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC16_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC17_IN_SEL_CFG_REG: u32 = 1072972148;
pub const GPIO_SIG17_IN_SEL_V: u32 = 1;
pub const GPIO_SIG17_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC17_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC17_IN_SEL: u32 = 63;
pub const GPIO_FUNC17_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC17_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC18_IN_SEL_CFG_REG: u32 = 1072972152;
pub const GPIO_SIG18_IN_SEL_V: u32 = 1;
pub const GPIO_SIG18_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC18_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC18_IN_SEL: u32 = 63;
pub const GPIO_FUNC18_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC18_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC19_IN_SEL_CFG_REG: u32 = 1072972156;
pub const GPIO_SIG19_IN_SEL_V: u32 = 1;
pub const GPIO_SIG19_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC19_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC19_IN_SEL: u32 = 63;
pub const GPIO_FUNC19_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC19_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC20_IN_SEL_CFG_REG: u32 = 1072972160;
pub const GPIO_SIG20_IN_SEL_V: u32 = 1;
pub const GPIO_SIG20_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC20_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC20_IN_SEL: u32 = 63;
pub const GPIO_FUNC20_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC20_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC21_IN_SEL_CFG_REG: u32 = 1072972164;
pub const GPIO_SIG21_IN_SEL_V: u32 = 1;
pub const GPIO_SIG21_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC21_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC21_IN_SEL: u32 = 63;
pub const GPIO_FUNC21_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC21_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC22_IN_SEL_CFG_REG: u32 = 1072972168;
pub const GPIO_SIG22_IN_SEL_V: u32 = 1;
pub const GPIO_SIG22_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC22_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC22_IN_SEL: u32 = 63;
pub const GPIO_FUNC22_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC22_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC23_IN_SEL_CFG_REG: u32 = 1072972172;
pub const GPIO_SIG23_IN_SEL_V: u32 = 1;
pub const GPIO_SIG23_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC23_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC23_IN_SEL: u32 = 63;
pub const GPIO_FUNC23_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC23_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC24_IN_SEL_CFG_REG: u32 = 1072972176;
pub const GPIO_SIG24_IN_SEL_V: u32 = 1;
pub const GPIO_SIG24_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC24_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC24_IN_SEL: u32 = 63;
pub const GPIO_FUNC24_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC24_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC25_IN_SEL_CFG_REG: u32 = 1072972180;
pub const GPIO_SIG25_IN_SEL_V: u32 = 1;
pub const GPIO_SIG25_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC25_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC25_IN_SEL: u32 = 63;
pub const GPIO_FUNC25_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC25_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC26_IN_SEL_CFG_REG: u32 = 1072972184;
pub const GPIO_SIG26_IN_SEL_V: u32 = 1;
pub const GPIO_SIG26_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC26_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC26_IN_SEL: u32 = 63;
pub const GPIO_FUNC26_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC26_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC27_IN_SEL_CFG_REG: u32 = 1072972188;
pub const GPIO_SIG27_IN_SEL_V: u32 = 1;
pub const GPIO_SIG27_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC27_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC27_IN_SEL: u32 = 63;
pub const GPIO_FUNC27_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC27_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC28_IN_SEL_CFG_REG: u32 = 1072972192;
pub const GPIO_SIG28_IN_SEL_V: u32 = 1;
pub const GPIO_SIG28_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC28_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC28_IN_SEL: u32 = 63;
pub const GPIO_FUNC28_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC28_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC29_IN_SEL_CFG_REG: u32 = 1072972196;
pub const GPIO_SIG29_IN_SEL_V: u32 = 1;
pub const GPIO_SIG29_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC29_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC29_IN_SEL: u32 = 63;
pub const GPIO_FUNC29_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC29_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC30_IN_SEL_CFG_REG: u32 = 1072972200;
pub const GPIO_SIG30_IN_SEL_V: u32 = 1;
pub const GPIO_SIG30_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC30_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC30_IN_SEL: u32 = 63;
pub const GPIO_FUNC30_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC30_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC31_IN_SEL_CFG_REG: u32 = 1072972204;
pub const GPIO_SIG31_IN_SEL_V: u32 = 1;
pub const GPIO_SIG31_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC31_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC31_IN_SEL: u32 = 63;
pub const GPIO_FUNC31_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC31_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC32_IN_SEL_CFG_REG: u32 = 1072972208;
pub const GPIO_SIG32_IN_SEL_V: u32 = 1;
pub const GPIO_SIG32_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC32_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC32_IN_SEL: u32 = 63;
pub const GPIO_FUNC32_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC32_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC33_IN_SEL_CFG_REG: u32 = 1072972212;
pub const GPIO_SIG33_IN_SEL_V: u32 = 1;
pub const GPIO_SIG33_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC33_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC33_IN_SEL: u32 = 63;
pub const GPIO_FUNC33_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC33_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC34_IN_SEL_CFG_REG: u32 = 1072972216;
pub const GPIO_SIG34_IN_SEL_V: u32 = 1;
pub const GPIO_SIG34_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC34_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC34_IN_SEL: u32 = 63;
pub const GPIO_FUNC34_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC34_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC35_IN_SEL_CFG_REG: u32 = 1072972220;
pub const GPIO_SIG35_IN_SEL_V: u32 = 1;
pub const GPIO_SIG35_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC35_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC35_IN_SEL: u32 = 63;
pub const GPIO_FUNC35_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC35_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC36_IN_SEL_CFG_REG: u32 = 1072972224;
pub const GPIO_SIG36_IN_SEL_V: u32 = 1;
pub const GPIO_SIG36_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC36_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC36_IN_SEL: u32 = 63;
pub const GPIO_FUNC36_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC36_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC37_IN_SEL_CFG_REG: u32 = 1072972228;
pub const GPIO_SIG37_IN_SEL_V: u32 = 1;
pub const GPIO_SIG37_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC37_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC37_IN_SEL: u32 = 63;
pub const GPIO_FUNC37_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC37_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC38_IN_SEL_CFG_REG: u32 = 1072972232;
pub const GPIO_SIG38_IN_SEL_V: u32 = 1;
pub const GPIO_SIG38_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC38_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC38_IN_SEL: u32 = 63;
pub const GPIO_FUNC38_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC38_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC39_IN_SEL_CFG_REG: u32 = 1072972236;
pub const GPIO_SIG39_IN_SEL_V: u32 = 1;
pub const GPIO_SIG39_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC39_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC39_IN_SEL: u32 = 63;
pub const GPIO_FUNC39_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC39_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC40_IN_SEL_CFG_REG: u32 = 1072972240;
pub const GPIO_SIG40_IN_SEL_V: u32 = 1;
pub const GPIO_SIG40_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC40_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC40_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC40_IN_SEL: u32 = 63;
pub const GPIO_FUNC40_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC40_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC41_IN_SEL_CFG_REG: u32 = 1072972244;
pub const GPIO_SIG41_IN_SEL_V: u32 = 1;
pub const GPIO_SIG41_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC41_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC41_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC41_IN_SEL: u32 = 63;
pub const GPIO_FUNC41_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC41_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC42_IN_SEL_CFG_REG: u32 = 1072972248;
pub const GPIO_SIG42_IN_SEL_V: u32 = 1;
pub const GPIO_SIG42_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC42_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC42_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC42_IN_SEL: u32 = 63;
pub const GPIO_FUNC42_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC42_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC43_IN_SEL_CFG_REG: u32 = 1072972252;
pub const GPIO_SIG43_IN_SEL_V: u32 = 1;
pub const GPIO_SIG43_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC43_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC43_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC43_IN_SEL: u32 = 63;
pub const GPIO_FUNC43_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC43_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC44_IN_SEL_CFG_REG: u32 = 1072972256;
pub const GPIO_SIG44_IN_SEL_V: u32 = 1;
pub const GPIO_SIG44_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC44_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC44_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC44_IN_SEL: u32 = 63;
pub const GPIO_FUNC44_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC44_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC45_IN_SEL_CFG_REG: u32 = 1072972260;
pub const GPIO_SIG45_IN_SEL_V: u32 = 1;
pub const GPIO_SIG45_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC45_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC45_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC45_IN_SEL: u32 = 63;
pub const GPIO_FUNC45_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC45_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC46_IN_SEL_CFG_REG: u32 = 1072972264;
pub const GPIO_SIG46_IN_SEL_V: u32 = 1;
pub const GPIO_SIG46_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC46_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC46_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC46_IN_SEL: u32 = 63;
pub const GPIO_FUNC46_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC46_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC47_IN_SEL_CFG_REG: u32 = 1072972268;
pub const GPIO_SIG47_IN_SEL_V: u32 = 1;
pub const GPIO_SIG47_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC47_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC47_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC47_IN_SEL: u32 = 63;
pub const GPIO_FUNC47_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC47_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC48_IN_SEL_CFG_REG: u32 = 1072972272;
pub const GPIO_SIG48_IN_SEL_V: u32 = 1;
pub const GPIO_SIG48_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC48_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC48_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC48_IN_SEL: u32 = 63;
pub const GPIO_FUNC48_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC48_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC49_IN_SEL_CFG_REG: u32 = 1072972276;
pub const GPIO_SIG49_IN_SEL_V: u32 = 1;
pub const GPIO_SIG49_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC49_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC49_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC49_IN_SEL: u32 = 63;
pub const GPIO_FUNC49_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC49_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC50_IN_SEL_CFG_REG: u32 = 1072972280;
pub const GPIO_SIG50_IN_SEL_V: u32 = 1;
pub const GPIO_SIG50_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC50_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC50_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC50_IN_SEL: u32 = 63;
pub const GPIO_FUNC50_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC50_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC51_IN_SEL_CFG_REG: u32 = 1072972284;
pub const GPIO_SIG51_IN_SEL_V: u32 = 1;
pub const GPIO_SIG51_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC51_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC51_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC51_IN_SEL: u32 = 63;
pub const GPIO_FUNC51_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC51_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC52_IN_SEL_CFG_REG: u32 = 1072972288;
pub const GPIO_SIG52_IN_SEL_V: u32 = 1;
pub const GPIO_SIG52_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC52_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC52_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC52_IN_SEL: u32 = 63;
pub const GPIO_FUNC52_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC52_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC53_IN_SEL_CFG_REG: u32 = 1072972292;
pub const GPIO_SIG53_IN_SEL_V: u32 = 1;
pub const GPIO_SIG53_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC53_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC53_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC53_IN_SEL: u32 = 63;
pub const GPIO_FUNC53_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC53_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC54_IN_SEL_CFG_REG: u32 = 1072972296;
pub const GPIO_SIG54_IN_SEL_V: u32 = 1;
pub const GPIO_SIG54_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC54_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC54_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC54_IN_SEL: u32 = 63;
pub const GPIO_FUNC54_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC54_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC55_IN_SEL_CFG_REG: u32 = 1072972300;
pub const GPIO_SIG55_IN_SEL_V: u32 = 1;
pub const GPIO_SIG55_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC55_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC55_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC55_IN_SEL: u32 = 63;
pub const GPIO_FUNC55_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC55_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC56_IN_SEL_CFG_REG: u32 = 1072972304;
pub const GPIO_SIG56_IN_SEL_V: u32 = 1;
pub const GPIO_SIG56_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC56_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC56_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC56_IN_SEL: u32 = 63;
pub const GPIO_FUNC56_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC56_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC57_IN_SEL_CFG_REG: u32 = 1072972308;
pub const GPIO_SIG57_IN_SEL_V: u32 = 1;
pub const GPIO_SIG57_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC57_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC57_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC57_IN_SEL: u32 = 63;
pub const GPIO_FUNC57_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC57_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC58_IN_SEL_CFG_REG: u32 = 1072972312;
pub const GPIO_SIG58_IN_SEL_V: u32 = 1;
pub const GPIO_SIG58_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC58_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC58_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC58_IN_SEL: u32 = 63;
pub const GPIO_FUNC58_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC58_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC59_IN_SEL_CFG_REG: u32 = 1072972316;
pub const GPIO_SIG59_IN_SEL_V: u32 = 1;
pub const GPIO_SIG59_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC59_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC59_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC59_IN_SEL: u32 = 63;
pub const GPIO_FUNC59_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC59_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC60_IN_SEL_CFG_REG: u32 = 1072972320;
pub const GPIO_SIG60_IN_SEL_V: u32 = 1;
pub const GPIO_SIG60_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC60_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC60_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC60_IN_SEL: u32 = 63;
pub const GPIO_FUNC60_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC60_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC61_IN_SEL_CFG_REG: u32 = 1072972324;
pub const GPIO_SIG61_IN_SEL_V: u32 = 1;
pub const GPIO_SIG61_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC61_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC61_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC61_IN_SEL: u32 = 63;
pub const GPIO_FUNC61_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC61_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC62_IN_SEL_CFG_REG: u32 = 1072972328;
pub const GPIO_SIG62_IN_SEL_V: u32 = 1;
pub const GPIO_SIG62_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC62_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC62_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC62_IN_SEL: u32 = 63;
pub const GPIO_FUNC62_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC62_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC63_IN_SEL_CFG_REG: u32 = 1072972332;
pub const GPIO_SIG63_IN_SEL_V: u32 = 1;
pub const GPIO_SIG63_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC63_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC63_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC63_IN_SEL: u32 = 63;
pub const GPIO_FUNC63_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC63_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC64_IN_SEL_CFG_REG: u32 = 1072972336;
pub const GPIO_SIG64_IN_SEL_V: u32 = 1;
pub const GPIO_SIG64_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC64_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC64_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC64_IN_SEL: u32 = 63;
pub const GPIO_FUNC64_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC64_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC65_IN_SEL_CFG_REG: u32 = 1072972340;
pub const GPIO_SIG65_IN_SEL_V: u32 = 1;
pub const GPIO_SIG65_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC65_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC65_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC65_IN_SEL: u32 = 63;
pub const GPIO_FUNC65_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC65_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC66_IN_SEL_CFG_REG: u32 = 1072972344;
pub const GPIO_SIG66_IN_SEL_V: u32 = 1;
pub const GPIO_SIG66_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC66_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC66_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC66_IN_SEL: u32 = 63;
pub const GPIO_FUNC66_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC66_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC67_IN_SEL_CFG_REG: u32 = 1072972348;
pub const GPIO_SIG67_IN_SEL_V: u32 = 1;
pub const GPIO_SIG67_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC67_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC67_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC67_IN_SEL: u32 = 63;
pub const GPIO_FUNC67_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC67_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC68_IN_SEL_CFG_REG: u32 = 1072972352;
pub const GPIO_SIG68_IN_SEL_V: u32 = 1;
pub const GPIO_SIG68_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC68_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC68_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC68_IN_SEL: u32 = 63;
pub const GPIO_FUNC68_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC68_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC69_IN_SEL_CFG_REG: u32 = 1072972356;
pub const GPIO_SIG69_IN_SEL_V: u32 = 1;
pub const GPIO_SIG69_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC69_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC69_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC69_IN_SEL: u32 = 63;
pub const GPIO_FUNC69_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC69_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC70_IN_SEL_CFG_REG: u32 = 1072972360;
pub const GPIO_SIG70_IN_SEL_V: u32 = 1;
pub const GPIO_SIG70_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC70_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC70_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC70_IN_SEL: u32 = 63;
pub const GPIO_FUNC70_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC70_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC71_IN_SEL_CFG_REG: u32 = 1072972364;
pub const GPIO_SIG71_IN_SEL_V: u32 = 1;
pub const GPIO_SIG71_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC71_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC71_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC71_IN_SEL: u32 = 63;
pub const GPIO_FUNC71_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC71_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC72_IN_SEL_CFG_REG: u32 = 1072972368;
pub const GPIO_SIG72_IN_SEL_V: u32 = 1;
pub const GPIO_SIG72_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC72_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC72_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC72_IN_SEL: u32 = 63;
pub const GPIO_FUNC72_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC72_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC73_IN_SEL_CFG_REG: u32 = 1072972372;
pub const GPIO_SIG73_IN_SEL_V: u32 = 1;
pub const GPIO_SIG73_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC73_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC73_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC73_IN_SEL: u32 = 63;
pub const GPIO_FUNC73_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC73_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC74_IN_SEL_CFG_REG: u32 = 1072972376;
pub const GPIO_SIG74_IN_SEL_V: u32 = 1;
pub const GPIO_SIG74_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC74_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC74_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC74_IN_SEL: u32 = 63;
pub const GPIO_FUNC74_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC74_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC75_IN_SEL_CFG_REG: u32 = 1072972380;
pub const GPIO_SIG75_IN_SEL_V: u32 = 1;
pub const GPIO_SIG75_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC75_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC75_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC75_IN_SEL: u32 = 63;
pub const GPIO_FUNC75_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC75_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC76_IN_SEL_CFG_REG: u32 = 1072972384;
pub const GPIO_SIG76_IN_SEL_V: u32 = 1;
pub const GPIO_SIG76_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC76_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC76_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC76_IN_SEL: u32 = 63;
pub const GPIO_FUNC76_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC76_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC77_IN_SEL_CFG_REG: u32 = 1072972388;
pub const GPIO_SIG77_IN_SEL_V: u32 = 1;
pub const GPIO_SIG77_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC77_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC77_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC77_IN_SEL: u32 = 63;
pub const GPIO_FUNC77_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC77_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC78_IN_SEL_CFG_REG: u32 = 1072972392;
pub const GPIO_SIG78_IN_SEL_V: u32 = 1;
pub const GPIO_SIG78_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC78_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC78_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC78_IN_SEL: u32 = 63;
pub const GPIO_FUNC78_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC78_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC79_IN_SEL_CFG_REG: u32 = 1072972396;
pub const GPIO_SIG79_IN_SEL_V: u32 = 1;
pub const GPIO_SIG79_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC79_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC79_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC79_IN_SEL: u32 = 63;
pub const GPIO_FUNC79_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC79_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC80_IN_SEL_CFG_REG: u32 = 1072972400;
pub const GPIO_SIG80_IN_SEL_V: u32 = 1;
pub const GPIO_SIG80_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC80_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC80_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC80_IN_SEL: u32 = 63;
pub const GPIO_FUNC80_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC80_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC81_IN_SEL_CFG_REG: u32 = 1072972404;
pub const GPIO_SIG81_IN_SEL_V: u32 = 1;
pub const GPIO_SIG81_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC81_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC81_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC81_IN_SEL: u32 = 63;
pub const GPIO_FUNC81_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC81_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC82_IN_SEL_CFG_REG: u32 = 1072972408;
pub const GPIO_SIG82_IN_SEL_V: u32 = 1;
pub const GPIO_SIG82_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC82_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC82_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC82_IN_SEL: u32 = 63;
pub const GPIO_FUNC82_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC82_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC83_IN_SEL_CFG_REG: u32 = 1072972412;
pub const GPIO_SIG83_IN_SEL_V: u32 = 1;
pub const GPIO_SIG83_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC83_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC83_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC83_IN_SEL: u32 = 63;
pub const GPIO_FUNC83_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC83_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC84_IN_SEL_CFG_REG: u32 = 1072972416;
pub const GPIO_SIG84_IN_SEL_V: u32 = 1;
pub const GPIO_SIG84_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC84_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC84_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC84_IN_SEL: u32 = 63;
pub const GPIO_FUNC84_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC84_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC85_IN_SEL_CFG_REG: u32 = 1072972420;
pub const GPIO_SIG85_IN_SEL_V: u32 = 1;
pub const GPIO_SIG85_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC85_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC85_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC85_IN_SEL: u32 = 63;
pub const GPIO_FUNC85_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC85_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC86_IN_SEL_CFG_REG: u32 = 1072972424;
pub const GPIO_SIG86_IN_SEL_V: u32 = 1;
pub const GPIO_SIG86_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC86_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC86_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC86_IN_SEL: u32 = 63;
pub const GPIO_FUNC86_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC86_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC87_IN_SEL_CFG_REG: u32 = 1072972428;
pub const GPIO_SIG87_IN_SEL_V: u32 = 1;
pub const GPIO_SIG87_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC87_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC87_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC87_IN_SEL: u32 = 63;
pub const GPIO_FUNC87_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC87_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC88_IN_SEL_CFG_REG: u32 = 1072972432;
pub const GPIO_SIG88_IN_SEL_V: u32 = 1;
pub const GPIO_SIG88_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC88_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC88_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC88_IN_SEL: u32 = 63;
pub const GPIO_FUNC88_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC88_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC89_IN_SEL_CFG_REG: u32 = 1072972436;
pub const GPIO_SIG89_IN_SEL_V: u32 = 1;
pub const GPIO_SIG89_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC89_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC89_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC89_IN_SEL: u32 = 63;
pub const GPIO_FUNC89_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC89_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC90_IN_SEL_CFG_REG: u32 = 1072972440;
pub const GPIO_SIG90_IN_SEL_V: u32 = 1;
pub const GPIO_SIG90_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC90_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC90_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC90_IN_SEL: u32 = 63;
pub const GPIO_FUNC90_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC90_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC91_IN_SEL_CFG_REG: u32 = 1072972444;
pub const GPIO_SIG91_IN_SEL_V: u32 = 1;
pub const GPIO_SIG91_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC91_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC91_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC91_IN_SEL: u32 = 63;
pub const GPIO_FUNC91_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC91_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC92_IN_SEL_CFG_REG: u32 = 1072972448;
pub const GPIO_SIG92_IN_SEL_V: u32 = 1;
pub const GPIO_SIG92_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC92_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC92_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC92_IN_SEL: u32 = 63;
pub const GPIO_FUNC92_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC92_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC93_IN_SEL_CFG_REG: u32 = 1072972452;
pub const GPIO_SIG93_IN_SEL_V: u32 = 1;
pub const GPIO_SIG93_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC93_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC93_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC93_IN_SEL: u32 = 63;
pub const GPIO_FUNC93_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC93_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC94_IN_SEL_CFG_REG: u32 = 1072972456;
pub const GPIO_SIG94_IN_SEL_V: u32 = 1;
pub const GPIO_SIG94_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC94_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC94_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC94_IN_SEL: u32 = 63;
pub const GPIO_FUNC94_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC94_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC95_IN_SEL_CFG_REG: u32 = 1072972460;
pub const GPIO_SIG95_IN_SEL_V: u32 = 1;
pub const GPIO_SIG95_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC95_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC95_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC95_IN_SEL: u32 = 63;
pub const GPIO_FUNC95_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC95_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC96_IN_SEL_CFG_REG: u32 = 1072972464;
pub const GPIO_SIG96_IN_SEL_V: u32 = 1;
pub const GPIO_SIG96_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC96_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC96_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC96_IN_SEL: u32 = 63;
pub const GPIO_FUNC96_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC96_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC97_IN_SEL_CFG_REG: u32 = 1072972468;
pub const GPIO_SIG97_IN_SEL_V: u32 = 1;
pub const GPIO_SIG97_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC97_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC97_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC97_IN_SEL: u32 = 63;
pub const GPIO_FUNC97_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC97_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC98_IN_SEL_CFG_REG: u32 = 1072972472;
pub const GPIO_SIG98_IN_SEL_V: u32 = 1;
pub const GPIO_SIG98_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC98_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC98_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC98_IN_SEL: u32 = 63;
pub const GPIO_FUNC98_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC98_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC99_IN_SEL_CFG_REG: u32 = 1072972476;
pub const GPIO_SIG99_IN_SEL_V: u32 = 1;
pub const GPIO_SIG99_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC99_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC99_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC99_IN_SEL: u32 = 63;
pub const GPIO_FUNC99_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC99_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC100_IN_SEL_CFG_REG: u32 = 1072972480;
pub const GPIO_SIG100_IN_SEL_V: u32 = 1;
pub const GPIO_SIG100_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC100_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC100_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC100_IN_SEL: u32 = 63;
pub const GPIO_FUNC100_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC100_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC101_IN_SEL_CFG_REG: u32 = 1072972484;
pub const GPIO_SIG101_IN_SEL_V: u32 = 1;
pub const GPIO_SIG101_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC101_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC101_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC101_IN_SEL: u32 = 63;
pub const GPIO_FUNC101_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC101_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC102_IN_SEL_CFG_REG: u32 = 1072972488;
pub const GPIO_SIG102_IN_SEL_V: u32 = 1;
pub const GPIO_SIG102_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC102_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC102_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC102_IN_SEL: u32 = 63;
pub const GPIO_FUNC102_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC102_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC103_IN_SEL_CFG_REG: u32 = 1072972492;
pub const GPIO_SIG103_IN_SEL_V: u32 = 1;
pub const GPIO_SIG103_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC103_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC103_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC103_IN_SEL: u32 = 63;
pub const GPIO_FUNC103_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC103_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC104_IN_SEL_CFG_REG: u32 = 1072972496;
pub const GPIO_SIG104_IN_SEL_V: u32 = 1;
pub const GPIO_SIG104_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC104_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC104_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC104_IN_SEL: u32 = 63;
pub const GPIO_FUNC104_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC104_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC105_IN_SEL_CFG_REG: u32 = 1072972500;
pub const GPIO_SIG105_IN_SEL_V: u32 = 1;
pub const GPIO_SIG105_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC105_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC105_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC105_IN_SEL: u32 = 63;
pub const GPIO_FUNC105_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC105_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC106_IN_SEL_CFG_REG: u32 = 1072972504;
pub const GPIO_SIG106_IN_SEL_V: u32 = 1;
pub const GPIO_SIG106_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC106_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC106_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC106_IN_SEL: u32 = 63;
pub const GPIO_FUNC106_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC106_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC107_IN_SEL_CFG_REG: u32 = 1072972508;
pub const GPIO_SIG107_IN_SEL_V: u32 = 1;
pub const GPIO_SIG107_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC107_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC107_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC107_IN_SEL: u32 = 63;
pub const GPIO_FUNC107_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC107_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC108_IN_SEL_CFG_REG: u32 = 1072972512;
pub const GPIO_SIG108_IN_SEL_V: u32 = 1;
pub const GPIO_SIG108_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC108_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC108_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC108_IN_SEL: u32 = 63;
pub const GPIO_FUNC108_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC108_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC109_IN_SEL_CFG_REG: u32 = 1072972516;
pub const GPIO_SIG109_IN_SEL_V: u32 = 1;
pub const GPIO_SIG109_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC109_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC109_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC109_IN_SEL: u32 = 63;
pub const GPIO_FUNC109_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC109_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC110_IN_SEL_CFG_REG: u32 = 1072972520;
pub const GPIO_SIG110_IN_SEL_V: u32 = 1;
pub const GPIO_SIG110_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC110_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC110_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC110_IN_SEL: u32 = 63;
pub const GPIO_FUNC110_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC110_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC111_IN_SEL_CFG_REG: u32 = 1072972524;
pub const GPIO_SIG111_IN_SEL_V: u32 = 1;
pub const GPIO_SIG111_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC111_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC111_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC111_IN_SEL: u32 = 63;
pub const GPIO_FUNC111_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC111_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC112_IN_SEL_CFG_REG: u32 = 1072972528;
pub const GPIO_SIG112_IN_SEL_V: u32 = 1;
pub const GPIO_SIG112_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC112_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC112_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC112_IN_SEL: u32 = 63;
pub const GPIO_FUNC112_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC112_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC113_IN_SEL_CFG_REG: u32 = 1072972532;
pub const GPIO_SIG113_IN_SEL_V: u32 = 1;
pub const GPIO_SIG113_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC113_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC113_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC113_IN_SEL: u32 = 63;
pub const GPIO_FUNC113_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC113_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC114_IN_SEL_CFG_REG: u32 = 1072972536;
pub const GPIO_SIG114_IN_SEL_V: u32 = 1;
pub const GPIO_SIG114_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC114_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC114_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC114_IN_SEL: u32 = 63;
pub const GPIO_FUNC114_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC114_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC115_IN_SEL_CFG_REG: u32 = 1072972540;
pub const GPIO_SIG115_IN_SEL_V: u32 = 1;
pub const GPIO_SIG115_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC115_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC115_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC115_IN_SEL: u32 = 63;
pub const GPIO_FUNC115_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC115_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC116_IN_SEL_CFG_REG: u32 = 1072972544;
pub const GPIO_SIG116_IN_SEL_V: u32 = 1;
pub const GPIO_SIG116_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC116_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC116_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC116_IN_SEL: u32 = 63;
pub const GPIO_FUNC116_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC116_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC117_IN_SEL_CFG_REG: u32 = 1072972548;
pub const GPIO_SIG117_IN_SEL_V: u32 = 1;
pub const GPIO_SIG117_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC117_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC117_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC117_IN_SEL: u32 = 63;
pub const GPIO_FUNC117_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC117_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC118_IN_SEL_CFG_REG: u32 = 1072972552;
pub const GPIO_SIG118_IN_SEL_V: u32 = 1;
pub const GPIO_SIG118_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC118_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC118_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC118_IN_SEL: u32 = 63;
pub const GPIO_FUNC118_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC118_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC119_IN_SEL_CFG_REG: u32 = 1072972556;
pub const GPIO_SIG119_IN_SEL_V: u32 = 1;
pub const GPIO_SIG119_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC119_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC119_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC119_IN_SEL: u32 = 63;
pub const GPIO_FUNC119_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC119_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC120_IN_SEL_CFG_REG: u32 = 1072972560;
pub const GPIO_SIG120_IN_SEL_V: u32 = 1;
pub const GPIO_SIG120_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC120_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC120_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC120_IN_SEL: u32 = 63;
pub const GPIO_FUNC120_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC120_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC121_IN_SEL_CFG_REG: u32 = 1072972564;
pub const GPIO_SIG121_IN_SEL_V: u32 = 1;
pub const GPIO_SIG121_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC121_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC121_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC121_IN_SEL: u32 = 63;
pub const GPIO_FUNC121_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC121_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC122_IN_SEL_CFG_REG: u32 = 1072972568;
pub const GPIO_SIG122_IN_SEL_V: u32 = 1;
pub const GPIO_SIG122_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC122_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC122_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC122_IN_SEL: u32 = 63;
pub const GPIO_FUNC122_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC122_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC123_IN_SEL_CFG_REG: u32 = 1072972572;
pub const GPIO_SIG123_IN_SEL_V: u32 = 1;
pub const GPIO_SIG123_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC123_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC123_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC123_IN_SEL: u32 = 63;
pub const GPIO_FUNC123_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC123_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC124_IN_SEL_CFG_REG: u32 = 1072972576;
pub const GPIO_SIG124_IN_SEL_V: u32 = 1;
pub const GPIO_SIG124_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC124_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC124_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC124_IN_SEL: u32 = 63;
pub const GPIO_FUNC124_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC124_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC125_IN_SEL_CFG_REG: u32 = 1072972580;
pub const GPIO_SIG125_IN_SEL_V: u32 = 1;
pub const GPIO_SIG125_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC125_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC125_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC125_IN_SEL: u32 = 63;
pub const GPIO_FUNC125_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC125_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC126_IN_SEL_CFG_REG: u32 = 1072972584;
pub const GPIO_SIG126_IN_SEL_V: u32 = 1;
pub const GPIO_SIG126_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC126_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC126_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC126_IN_SEL: u32 = 63;
pub const GPIO_FUNC126_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC126_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC127_IN_SEL_CFG_REG: u32 = 1072972588;
pub const GPIO_SIG127_IN_SEL_V: u32 = 1;
pub const GPIO_SIG127_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC127_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC127_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC127_IN_SEL: u32 = 63;
pub const GPIO_FUNC127_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC127_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC128_IN_SEL_CFG_REG: u32 = 1072972592;
pub const GPIO_SIG128_IN_SEL_V: u32 = 1;
pub const GPIO_SIG128_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC128_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC128_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC128_IN_SEL: u32 = 63;
pub const GPIO_FUNC128_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC128_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC129_IN_SEL_CFG_REG: u32 = 1072972596;
pub const GPIO_SIG129_IN_SEL_V: u32 = 1;
pub const GPIO_SIG129_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC129_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC129_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC129_IN_SEL: u32 = 63;
pub const GPIO_FUNC129_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC129_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC130_IN_SEL_CFG_REG: u32 = 1072972600;
pub const GPIO_SIG130_IN_SEL_V: u32 = 1;
pub const GPIO_SIG130_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC130_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC130_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC130_IN_SEL: u32 = 63;
pub const GPIO_FUNC130_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC130_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC131_IN_SEL_CFG_REG: u32 = 1072972604;
pub const GPIO_SIG131_IN_SEL_V: u32 = 1;
pub const GPIO_SIG131_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC131_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC131_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC131_IN_SEL: u32 = 63;
pub const GPIO_FUNC131_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC131_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC132_IN_SEL_CFG_REG: u32 = 1072972608;
pub const GPIO_SIG132_IN_SEL_V: u32 = 1;
pub const GPIO_SIG132_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC132_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC132_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC132_IN_SEL: u32 = 63;
pub const GPIO_FUNC132_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC132_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC133_IN_SEL_CFG_REG: u32 = 1072972612;
pub const GPIO_SIG133_IN_SEL_V: u32 = 1;
pub const GPIO_SIG133_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC133_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC133_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC133_IN_SEL: u32 = 63;
pub const GPIO_FUNC133_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC133_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC134_IN_SEL_CFG_REG: u32 = 1072972616;
pub const GPIO_SIG134_IN_SEL_V: u32 = 1;
pub const GPIO_SIG134_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC134_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC134_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC134_IN_SEL: u32 = 63;
pub const GPIO_FUNC134_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC134_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC135_IN_SEL_CFG_REG: u32 = 1072972620;
pub const GPIO_SIG135_IN_SEL_V: u32 = 1;
pub const GPIO_SIG135_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC135_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC135_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC135_IN_SEL: u32 = 63;
pub const GPIO_FUNC135_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC135_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC136_IN_SEL_CFG_REG: u32 = 1072972624;
pub const GPIO_SIG136_IN_SEL_V: u32 = 1;
pub const GPIO_SIG136_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC136_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC136_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC136_IN_SEL: u32 = 63;
pub const GPIO_FUNC136_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC136_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC137_IN_SEL_CFG_REG: u32 = 1072972628;
pub const GPIO_SIG137_IN_SEL_V: u32 = 1;
pub const GPIO_SIG137_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC137_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC137_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC137_IN_SEL: u32 = 63;
pub const GPIO_FUNC137_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC137_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC138_IN_SEL_CFG_REG: u32 = 1072972632;
pub const GPIO_SIG138_IN_SEL_V: u32 = 1;
pub const GPIO_SIG138_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC138_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC138_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC138_IN_SEL: u32 = 63;
pub const GPIO_FUNC138_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC138_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC139_IN_SEL_CFG_REG: u32 = 1072972636;
pub const GPIO_SIG139_IN_SEL_V: u32 = 1;
pub const GPIO_SIG139_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC139_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC139_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC139_IN_SEL: u32 = 63;
pub const GPIO_FUNC139_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC139_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC140_IN_SEL_CFG_REG: u32 = 1072972640;
pub const GPIO_SIG140_IN_SEL_V: u32 = 1;
pub const GPIO_SIG140_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC140_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC140_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC140_IN_SEL: u32 = 63;
pub const GPIO_FUNC140_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC140_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC141_IN_SEL_CFG_REG: u32 = 1072972644;
pub const GPIO_SIG141_IN_SEL_V: u32 = 1;
pub const GPIO_SIG141_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC141_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC141_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC141_IN_SEL: u32 = 63;
pub const GPIO_FUNC141_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC141_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC142_IN_SEL_CFG_REG: u32 = 1072972648;
pub const GPIO_SIG142_IN_SEL_V: u32 = 1;
pub const GPIO_SIG142_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC142_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC142_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC142_IN_SEL: u32 = 63;
pub const GPIO_FUNC142_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC142_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC143_IN_SEL_CFG_REG: u32 = 1072972652;
pub const GPIO_SIG143_IN_SEL_V: u32 = 1;
pub const GPIO_SIG143_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC143_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC143_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC143_IN_SEL: u32 = 63;
pub const GPIO_FUNC143_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC143_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC144_IN_SEL_CFG_REG: u32 = 1072972656;
pub const GPIO_SIG144_IN_SEL_V: u32 = 1;
pub const GPIO_SIG144_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC144_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC144_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC144_IN_SEL: u32 = 63;
pub const GPIO_FUNC144_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC144_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC145_IN_SEL_CFG_REG: u32 = 1072972660;
pub const GPIO_SIG145_IN_SEL_V: u32 = 1;
pub const GPIO_SIG145_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC145_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC145_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC145_IN_SEL: u32 = 63;
pub const GPIO_FUNC145_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC145_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC146_IN_SEL_CFG_REG: u32 = 1072972664;
pub const GPIO_SIG146_IN_SEL_V: u32 = 1;
pub const GPIO_SIG146_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC146_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC146_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC146_IN_SEL: u32 = 63;
pub const GPIO_FUNC146_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC146_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC147_IN_SEL_CFG_REG: u32 = 1072972668;
pub const GPIO_SIG147_IN_SEL_V: u32 = 1;
pub const GPIO_SIG147_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC147_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC147_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC147_IN_SEL: u32 = 63;
pub const GPIO_FUNC147_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC147_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC148_IN_SEL_CFG_REG: u32 = 1072972672;
pub const GPIO_SIG148_IN_SEL_V: u32 = 1;
pub const GPIO_SIG148_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC148_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC148_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC148_IN_SEL: u32 = 63;
pub const GPIO_FUNC148_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC148_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC149_IN_SEL_CFG_REG: u32 = 1072972676;
pub const GPIO_SIG149_IN_SEL_V: u32 = 1;
pub const GPIO_SIG149_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC149_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC149_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC149_IN_SEL: u32 = 63;
pub const GPIO_FUNC149_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC149_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC150_IN_SEL_CFG_REG: u32 = 1072972680;
pub const GPIO_SIG150_IN_SEL_V: u32 = 1;
pub const GPIO_SIG150_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC150_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC150_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC150_IN_SEL: u32 = 63;
pub const GPIO_FUNC150_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC150_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC151_IN_SEL_CFG_REG: u32 = 1072972684;
pub const GPIO_SIG151_IN_SEL_V: u32 = 1;
pub const GPIO_SIG151_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC151_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC151_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC151_IN_SEL: u32 = 63;
pub const GPIO_FUNC151_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC151_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC152_IN_SEL_CFG_REG: u32 = 1072972688;
pub const GPIO_SIG152_IN_SEL_V: u32 = 1;
pub const GPIO_SIG152_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC152_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC152_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC152_IN_SEL: u32 = 63;
pub const GPIO_FUNC152_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC152_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC153_IN_SEL_CFG_REG: u32 = 1072972692;
pub const GPIO_SIG153_IN_SEL_V: u32 = 1;
pub const GPIO_SIG153_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC153_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC153_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC153_IN_SEL: u32 = 63;
pub const GPIO_FUNC153_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC153_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC154_IN_SEL_CFG_REG: u32 = 1072972696;
pub const GPIO_SIG154_IN_SEL_V: u32 = 1;
pub const GPIO_SIG154_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC154_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC154_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC154_IN_SEL: u32 = 63;
pub const GPIO_FUNC154_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC154_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC155_IN_SEL_CFG_REG: u32 = 1072972700;
pub const GPIO_SIG155_IN_SEL_V: u32 = 1;
pub const GPIO_SIG155_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC155_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC155_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC155_IN_SEL: u32 = 63;
pub const GPIO_FUNC155_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC155_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC156_IN_SEL_CFG_REG: u32 = 1072972704;
pub const GPIO_SIG156_IN_SEL_V: u32 = 1;
pub const GPIO_SIG156_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC156_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC156_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC156_IN_SEL: u32 = 63;
pub const GPIO_FUNC156_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC156_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC157_IN_SEL_CFG_REG: u32 = 1072972708;
pub const GPIO_SIG157_IN_SEL_V: u32 = 1;
pub const GPIO_SIG157_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC157_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC157_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC157_IN_SEL: u32 = 63;
pub const GPIO_FUNC157_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC157_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC158_IN_SEL_CFG_REG: u32 = 1072972712;
pub const GPIO_SIG158_IN_SEL_V: u32 = 1;
pub const GPIO_SIG158_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC158_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC158_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC158_IN_SEL: u32 = 63;
pub const GPIO_FUNC158_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC158_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC159_IN_SEL_CFG_REG: u32 = 1072972716;
pub const GPIO_SIG159_IN_SEL_V: u32 = 1;
pub const GPIO_SIG159_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC159_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC159_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC159_IN_SEL: u32 = 63;
pub const GPIO_FUNC159_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC159_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC160_IN_SEL_CFG_REG: u32 = 1072972720;
pub const GPIO_SIG160_IN_SEL_V: u32 = 1;
pub const GPIO_SIG160_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC160_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC160_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC160_IN_SEL: u32 = 63;
pub const GPIO_FUNC160_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC160_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC161_IN_SEL_CFG_REG: u32 = 1072972724;
pub const GPIO_SIG161_IN_SEL_V: u32 = 1;
pub const GPIO_SIG161_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC161_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC161_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC161_IN_SEL: u32 = 63;
pub const GPIO_FUNC161_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC161_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC162_IN_SEL_CFG_REG: u32 = 1072972728;
pub const GPIO_SIG162_IN_SEL_V: u32 = 1;
pub const GPIO_SIG162_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC162_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC162_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC162_IN_SEL: u32 = 63;
pub const GPIO_FUNC162_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC162_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC163_IN_SEL_CFG_REG: u32 = 1072972732;
pub const GPIO_SIG163_IN_SEL_V: u32 = 1;
pub const GPIO_SIG163_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC163_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC163_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC163_IN_SEL: u32 = 63;
pub const GPIO_FUNC163_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC163_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC164_IN_SEL_CFG_REG: u32 = 1072972736;
pub const GPIO_SIG164_IN_SEL_V: u32 = 1;
pub const GPIO_SIG164_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC164_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC164_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC164_IN_SEL: u32 = 63;
pub const GPIO_FUNC164_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC164_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC165_IN_SEL_CFG_REG: u32 = 1072972740;
pub const GPIO_SIG165_IN_SEL_V: u32 = 1;
pub const GPIO_SIG165_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC165_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC165_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC165_IN_SEL: u32 = 63;
pub const GPIO_FUNC165_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC165_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC166_IN_SEL_CFG_REG: u32 = 1072972744;
pub const GPIO_SIG166_IN_SEL_V: u32 = 1;
pub const GPIO_SIG166_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC166_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC166_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC166_IN_SEL: u32 = 63;
pub const GPIO_FUNC166_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC166_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC167_IN_SEL_CFG_REG: u32 = 1072972748;
pub const GPIO_SIG167_IN_SEL_V: u32 = 1;
pub const GPIO_SIG167_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC167_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC167_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC167_IN_SEL: u32 = 63;
pub const GPIO_FUNC167_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC167_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC168_IN_SEL_CFG_REG: u32 = 1072972752;
pub const GPIO_SIG168_IN_SEL_V: u32 = 1;
pub const GPIO_SIG168_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC168_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC168_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC168_IN_SEL: u32 = 63;
pub const GPIO_FUNC168_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC168_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC169_IN_SEL_CFG_REG: u32 = 1072972756;
pub const GPIO_SIG169_IN_SEL_V: u32 = 1;
pub const GPIO_SIG169_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC169_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC169_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC169_IN_SEL: u32 = 63;
pub const GPIO_FUNC169_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC169_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC170_IN_SEL_CFG_REG: u32 = 1072972760;
pub const GPIO_SIG170_IN_SEL_V: u32 = 1;
pub const GPIO_SIG170_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC170_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC170_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC170_IN_SEL: u32 = 63;
pub const GPIO_FUNC170_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC170_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC171_IN_SEL_CFG_REG: u32 = 1072972764;
pub const GPIO_SIG171_IN_SEL_V: u32 = 1;
pub const GPIO_SIG171_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC171_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC171_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC171_IN_SEL: u32 = 63;
pub const GPIO_FUNC171_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC171_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC172_IN_SEL_CFG_REG: u32 = 1072972768;
pub const GPIO_SIG172_IN_SEL_V: u32 = 1;
pub const GPIO_SIG172_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC172_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC172_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC172_IN_SEL: u32 = 63;
pub const GPIO_FUNC172_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC172_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC173_IN_SEL_CFG_REG: u32 = 1072972772;
pub const GPIO_SIG173_IN_SEL_V: u32 = 1;
pub const GPIO_SIG173_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC173_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC173_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC173_IN_SEL: u32 = 63;
pub const GPIO_FUNC173_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC173_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC174_IN_SEL_CFG_REG: u32 = 1072972776;
pub const GPIO_SIG174_IN_SEL_V: u32 = 1;
pub const GPIO_SIG174_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC174_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC174_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC174_IN_SEL: u32 = 63;
pub const GPIO_FUNC174_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC174_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC175_IN_SEL_CFG_REG: u32 = 1072972780;
pub const GPIO_SIG175_IN_SEL_V: u32 = 1;
pub const GPIO_SIG175_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC175_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC175_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC175_IN_SEL: u32 = 63;
pub const GPIO_FUNC175_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC175_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC176_IN_SEL_CFG_REG: u32 = 1072972784;
pub const GPIO_SIG176_IN_SEL_V: u32 = 1;
pub const GPIO_SIG176_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC176_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC176_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC176_IN_SEL: u32 = 63;
pub const GPIO_FUNC176_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC176_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC177_IN_SEL_CFG_REG: u32 = 1072972788;
pub const GPIO_SIG177_IN_SEL_V: u32 = 1;
pub const GPIO_SIG177_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC177_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC177_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC177_IN_SEL: u32 = 63;
pub const GPIO_FUNC177_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC177_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC178_IN_SEL_CFG_REG: u32 = 1072972792;
pub const GPIO_SIG178_IN_SEL_V: u32 = 1;
pub const GPIO_SIG178_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC178_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC178_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC178_IN_SEL: u32 = 63;
pub const GPIO_FUNC178_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC178_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC179_IN_SEL_CFG_REG: u32 = 1072972796;
pub const GPIO_SIG179_IN_SEL_V: u32 = 1;
pub const GPIO_SIG179_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC179_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC179_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC179_IN_SEL: u32 = 63;
pub const GPIO_FUNC179_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC179_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC180_IN_SEL_CFG_REG: u32 = 1072972800;
pub const GPIO_SIG180_IN_SEL_V: u32 = 1;
pub const GPIO_SIG180_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC180_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC180_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC180_IN_SEL: u32 = 63;
pub const GPIO_FUNC180_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC180_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC181_IN_SEL_CFG_REG: u32 = 1072972804;
pub const GPIO_SIG181_IN_SEL_V: u32 = 1;
pub const GPIO_SIG181_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC181_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC181_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC181_IN_SEL: u32 = 63;
pub const GPIO_FUNC181_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC181_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC182_IN_SEL_CFG_REG: u32 = 1072972808;
pub const GPIO_SIG182_IN_SEL_V: u32 = 1;
pub const GPIO_SIG182_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC182_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC182_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC182_IN_SEL: u32 = 63;
pub const GPIO_FUNC182_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC182_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC183_IN_SEL_CFG_REG: u32 = 1072972812;
pub const GPIO_SIG183_IN_SEL_V: u32 = 1;
pub const GPIO_SIG183_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC183_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC183_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC183_IN_SEL: u32 = 63;
pub const GPIO_FUNC183_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC183_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC184_IN_SEL_CFG_REG: u32 = 1072972816;
pub const GPIO_SIG184_IN_SEL_V: u32 = 1;
pub const GPIO_SIG184_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC184_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC184_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC184_IN_SEL: u32 = 63;
pub const GPIO_FUNC184_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC184_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC185_IN_SEL_CFG_REG: u32 = 1072972820;
pub const GPIO_SIG185_IN_SEL_V: u32 = 1;
pub const GPIO_SIG185_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC185_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC185_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC185_IN_SEL: u32 = 63;
pub const GPIO_FUNC185_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC185_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC186_IN_SEL_CFG_REG: u32 = 1072972824;
pub const GPIO_SIG186_IN_SEL_V: u32 = 1;
pub const GPIO_SIG186_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC186_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC186_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC186_IN_SEL: u32 = 63;
pub const GPIO_FUNC186_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC186_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC187_IN_SEL_CFG_REG: u32 = 1072972828;
pub const GPIO_SIG187_IN_SEL_V: u32 = 1;
pub const GPIO_SIG187_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC187_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC187_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC187_IN_SEL: u32 = 63;
pub const GPIO_FUNC187_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC187_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC188_IN_SEL_CFG_REG: u32 = 1072972832;
pub const GPIO_SIG188_IN_SEL_V: u32 = 1;
pub const GPIO_SIG188_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC188_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC188_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC188_IN_SEL: u32 = 63;
pub const GPIO_FUNC188_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC188_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC189_IN_SEL_CFG_REG: u32 = 1072972836;
pub const GPIO_SIG189_IN_SEL_V: u32 = 1;
pub const GPIO_SIG189_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC189_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC189_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC189_IN_SEL: u32 = 63;
pub const GPIO_FUNC189_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC189_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC190_IN_SEL_CFG_REG: u32 = 1072972840;
pub const GPIO_SIG190_IN_SEL_V: u32 = 1;
pub const GPIO_SIG190_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC190_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC190_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC190_IN_SEL: u32 = 63;
pub const GPIO_FUNC190_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC190_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC191_IN_SEL_CFG_REG: u32 = 1072972844;
pub const GPIO_SIG191_IN_SEL_V: u32 = 1;
pub const GPIO_SIG191_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC191_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC191_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC191_IN_SEL: u32 = 63;
pub const GPIO_FUNC191_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC191_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC192_IN_SEL_CFG_REG: u32 = 1072972848;
pub const GPIO_SIG192_IN_SEL_V: u32 = 1;
pub const GPIO_SIG192_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC192_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC192_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC192_IN_SEL: u32 = 63;
pub const GPIO_FUNC192_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC192_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC193_IN_SEL_CFG_REG: u32 = 1072972852;
pub const GPIO_SIG193_IN_SEL_V: u32 = 1;
pub const GPIO_SIG193_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC193_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC193_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC193_IN_SEL: u32 = 63;
pub const GPIO_FUNC193_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC193_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC194_IN_SEL_CFG_REG: u32 = 1072972856;
pub const GPIO_SIG194_IN_SEL_V: u32 = 1;
pub const GPIO_SIG194_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC194_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC194_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC194_IN_SEL: u32 = 63;
pub const GPIO_FUNC194_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC194_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC195_IN_SEL_CFG_REG: u32 = 1072972860;
pub const GPIO_SIG195_IN_SEL_V: u32 = 1;
pub const GPIO_SIG195_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC195_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC195_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC195_IN_SEL: u32 = 63;
pub const GPIO_FUNC195_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC195_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC196_IN_SEL_CFG_REG: u32 = 1072972864;
pub const GPIO_SIG196_IN_SEL_V: u32 = 1;
pub const GPIO_SIG196_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC196_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC196_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC196_IN_SEL: u32 = 63;
pub const GPIO_FUNC196_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC196_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC197_IN_SEL_CFG_REG: u32 = 1072972868;
pub const GPIO_SIG197_IN_SEL_V: u32 = 1;
pub const GPIO_SIG197_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC197_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC197_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC197_IN_SEL: u32 = 63;
pub const GPIO_FUNC197_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC197_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC198_IN_SEL_CFG_REG: u32 = 1072972872;
pub const GPIO_SIG198_IN_SEL_V: u32 = 1;
pub const GPIO_SIG198_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC198_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC198_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC198_IN_SEL: u32 = 63;
pub const GPIO_FUNC198_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC198_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC199_IN_SEL_CFG_REG: u32 = 1072972876;
pub const GPIO_SIG199_IN_SEL_V: u32 = 1;
pub const GPIO_SIG199_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC199_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC199_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC199_IN_SEL: u32 = 63;
pub const GPIO_FUNC199_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC199_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC200_IN_SEL_CFG_REG: u32 = 1072972880;
pub const GPIO_SIG200_IN_SEL_V: u32 = 1;
pub const GPIO_SIG200_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC200_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC200_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC200_IN_SEL: u32 = 63;
pub const GPIO_FUNC200_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC200_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC201_IN_SEL_CFG_REG: u32 = 1072972884;
pub const GPIO_SIG201_IN_SEL_V: u32 = 1;
pub const GPIO_SIG201_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC201_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC201_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC201_IN_SEL: u32 = 63;
pub const GPIO_FUNC201_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC201_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC202_IN_SEL_CFG_REG: u32 = 1072972888;
pub const GPIO_SIG202_IN_SEL_V: u32 = 1;
pub const GPIO_SIG202_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC202_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC202_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC202_IN_SEL: u32 = 63;
pub const GPIO_FUNC202_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC202_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC203_IN_SEL_CFG_REG: u32 = 1072972892;
pub const GPIO_SIG203_IN_SEL_V: u32 = 1;
pub const GPIO_SIG203_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC203_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC203_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC203_IN_SEL: u32 = 63;
pub const GPIO_FUNC203_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC203_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC204_IN_SEL_CFG_REG: u32 = 1072972896;
pub const GPIO_SIG204_IN_SEL_V: u32 = 1;
pub const GPIO_SIG204_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC204_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC204_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC204_IN_SEL: u32 = 63;
pub const GPIO_FUNC204_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC204_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC205_IN_SEL_CFG_REG: u32 = 1072972900;
pub const GPIO_SIG205_IN_SEL_V: u32 = 1;
pub const GPIO_SIG205_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC205_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC205_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC205_IN_SEL: u32 = 63;
pub const GPIO_FUNC205_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC205_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC206_IN_SEL_CFG_REG: u32 = 1072972904;
pub const GPIO_SIG206_IN_SEL_V: u32 = 1;
pub const GPIO_SIG206_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC206_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC206_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC206_IN_SEL: u32 = 63;
pub const GPIO_FUNC206_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC206_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC207_IN_SEL_CFG_REG: u32 = 1072972908;
pub const GPIO_SIG207_IN_SEL_V: u32 = 1;
pub const GPIO_SIG207_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC207_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC207_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC207_IN_SEL: u32 = 63;
pub const GPIO_FUNC207_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC207_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC208_IN_SEL_CFG_REG: u32 = 1072972912;
pub const GPIO_SIG208_IN_SEL_V: u32 = 1;
pub const GPIO_SIG208_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC208_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC208_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC208_IN_SEL: u32 = 63;
pub const GPIO_FUNC208_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC208_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC209_IN_SEL_CFG_REG: u32 = 1072972916;
pub const GPIO_SIG209_IN_SEL_V: u32 = 1;
pub const GPIO_SIG209_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC209_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC209_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC209_IN_SEL: u32 = 63;
pub const GPIO_FUNC209_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC209_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC210_IN_SEL_CFG_REG: u32 = 1072972920;
pub const GPIO_SIG210_IN_SEL_V: u32 = 1;
pub const GPIO_SIG210_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC210_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC210_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC210_IN_SEL: u32 = 63;
pub const GPIO_FUNC210_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC210_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC211_IN_SEL_CFG_REG: u32 = 1072972924;
pub const GPIO_SIG211_IN_SEL_V: u32 = 1;
pub const GPIO_SIG211_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC211_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC211_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC211_IN_SEL: u32 = 63;
pub const GPIO_FUNC211_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC211_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC212_IN_SEL_CFG_REG: u32 = 1072972928;
pub const GPIO_SIG212_IN_SEL_V: u32 = 1;
pub const GPIO_SIG212_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC212_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC212_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC212_IN_SEL: u32 = 63;
pub const GPIO_FUNC212_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC212_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC213_IN_SEL_CFG_REG: u32 = 1072972932;
pub const GPIO_SIG213_IN_SEL_V: u32 = 1;
pub const GPIO_SIG213_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC213_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC213_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC213_IN_SEL: u32 = 63;
pub const GPIO_FUNC213_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC213_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC214_IN_SEL_CFG_REG: u32 = 1072972936;
pub const GPIO_SIG214_IN_SEL_V: u32 = 1;
pub const GPIO_SIG214_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC214_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC214_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC214_IN_SEL: u32 = 63;
pub const GPIO_FUNC214_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC214_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC215_IN_SEL_CFG_REG: u32 = 1072972940;
pub const GPIO_SIG215_IN_SEL_V: u32 = 1;
pub const GPIO_SIG215_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC215_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC215_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC215_IN_SEL: u32 = 63;
pub const GPIO_FUNC215_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC215_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC216_IN_SEL_CFG_REG: u32 = 1072972944;
pub const GPIO_SIG216_IN_SEL_V: u32 = 1;
pub const GPIO_SIG216_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC216_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC216_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC216_IN_SEL: u32 = 63;
pub const GPIO_FUNC216_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC216_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC217_IN_SEL_CFG_REG: u32 = 1072972948;
pub const GPIO_SIG217_IN_SEL_V: u32 = 1;
pub const GPIO_SIG217_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC217_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC217_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC217_IN_SEL: u32 = 63;
pub const GPIO_FUNC217_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC217_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC218_IN_SEL_CFG_REG: u32 = 1072972952;
pub const GPIO_SIG218_IN_SEL_V: u32 = 1;
pub const GPIO_SIG218_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC218_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC218_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC218_IN_SEL: u32 = 63;
pub const GPIO_FUNC218_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC218_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC219_IN_SEL_CFG_REG: u32 = 1072972956;
pub const GPIO_SIG219_IN_SEL_V: u32 = 1;
pub const GPIO_SIG219_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC219_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC219_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC219_IN_SEL: u32 = 63;
pub const GPIO_FUNC219_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC219_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC220_IN_SEL_CFG_REG: u32 = 1072972960;
pub const GPIO_SIG220_IN_SEL_V: u32 = 1;
pub const GPIO_SIG220_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC220_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC220_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC220_IN_SEL: u32 = 63;
pub const GPIO_FUNC220_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC220_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC221_IN_SEL_CFG_REG: u32 = 1072972964;
pub const GPIO_SIG221_IN_SEL_V: u32 = 1;
pub const GPIO_SIG221_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC221_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC221_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC221_IN_SEL: u32 = 63;
pub const GPIO_FUNC221_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC221_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC222_IN_SEL_CFG_REG: u32 = 1072972968;
pub const GPIO_SIG222_IN_SEL_V: u32 = 1;
pub const GPIO_SIG222_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC222_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC222_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC222_IN_SEL: u32 = 63;
pub const GPIO_FUNC222_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC222_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC223_IN_SEL_CFG_REG: u32 = 1072972972;
pub const GPIO_SIG223_IN_SEL_V: u32 = 1;
pub const GPIO_SIG223_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC223_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC223_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC223_IN_SEL: u32 = 63;
pub const GPIO_FUNC223_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC223_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC224_IN_SEL_CFG_REG: u32 = 1072972976;
pub const GPIO_SIG224_IN_SEL_V: u32 = 1;
pub const GPIO_SIG224_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC224_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC224_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC224_IN_SEL: u32 = 63;
pub const GPIO_FUNC224_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC224_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC225_IN_SEL_CFG_REG: u32 = 1072972980;
pub const GPIO_SIG225_IN_SEL_V: u32 = 1;
pub const GPIO_SIG225_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC225_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC225_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC225_IN_SEL: u32 = 63;
pub const GPIO_FUNC225_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC225_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC226_IN_SEL_CFG_REG: u32 = 1072972984;
pub const GPIO_SIG226_IN_SEL_V: u32 = 1;
pub const GPIO_SIG226_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC226_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC226_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC226_IN_SEL: u32 = 63;
pub const GPIO_FUNC226_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC226_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC227_IN_SEL_CFG_REG: u32 = 1072972988;
pub const GPIO_SIG227_IN_SEL_V: u32 = 1;
pub const GPIO_SIG227_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC227_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC227_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC227_IN_SEL: u32 = 63;
pub const GPIO_FUNC227_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC227_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC228_IN_SEL_CFG_REG: u32 = 1072972992;
pub const GPIO_SIG228_IN_SEL_V: u32 = 1;
pub const GPIO_SIG228_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC228_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC228_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC228_IN_SEL: u32 = 63;
pub const GPIO_FUNC228_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC228_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC229_IN_SEL_CFG_REG: u32 = 1072972996;
pub const GPIO_SIG229_IN_SEL_V: u32 = 1;
pub const GPIO_SIG229_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC229_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC229_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC229_IN_SEL: u32 = 63;
pub const GPIO_FUNC229_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC229_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC230_IN_SEL_CFG_REG: u32 = 1072973000;
pub const GPIO_SIG230_IN_SEL_V: u32 = 1;
pub const GPIO_SIG230_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC230_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC230_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC230_IN_SEL: u32 = 63;
pub const GPIO_FUNC230_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC230_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC231_IN_SEL_CFG_REG: u32 = 1072973004;
pub const GPIO_SIG231_IN_SEL_V: u32 = 1;
pub const GPIO_SIG231_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC231_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC231_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC231_IN_SEL: u32 = 63;
pub const GPIO_FUNC231_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC231_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC232_IN_SEL_CFG_REG: u32 = 1072973008;
pub const GPIO_SIG232_IN_SEL_V: u32 = 1;
pub const GPIO_SIG232_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC232_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC232_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC232_IN_SEL: u32 = 63;
pub const GPIO_FUNC232_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC232_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC233_IN_SEL_CFG_REG: u32 = 1072973012;
pub const GPIO_SIG233_IN_SEL_V: u32 = 1;
pub const GPIO_SIG233_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC233_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC233_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC233_IN_SEL: u32 = 63;
pub const GPIO_FUNC233_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC233_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC234_IN_SEL_CFG_REG: u32 = 1072973016;
pub const GPIO_SIG234_IN_SEL_V: u32 = 1;
pub const GPIO_SIG234_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC234_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC234_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC234_IN_SEL: u32 = 63;
pub const GPIO_FUNC234_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC234_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC235_IN_SEL_CFG_REG: u32 = 1072973020;
pub const GPIO_SIG235_IN_SEL_V: u32 = 1;
pub const GPIO_SIG235_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC235_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC235_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC235_IN_SEL: u32 = 63;
pub const GPIO_FUNC235_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC235_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC236_IN_SEL_CFG_REG: u32 = 1072973024;
pub const GPIO_SIG236_IN_SEL_V: u32 = 1;
pub const GPIO_SIG236_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC236_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC236_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC236_IN_SEL: u32 = 63;
pub const GPIO_FUNC236_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC236_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC237_IN_SEL_CFG_REG: u32 = 1072973028;
pub const GPIO_SIG237_IN_SEL_V: u32 = 1;
pub const GPIO_SIG237_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC237_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC237_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC237_IN_SEL: u32 = 63;
pub const GPIO_FUNC237_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC237_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC238_IN_SEL_CFG_REG: u32 = 1072973032;
pub const GPIO_SIG238_IN_SEL_V: u32 = 1;
pub const GPIO_SIG238_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC238_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC238_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC238_IN_SEL: u32 = 63;
pub const GPIO_FUNC238_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC238_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC239_IN_SEL_CFG_REG: u32 = 1072973036;
pub const GPIO_SIG239_IN_SEL_V: u32 = 1;
pub const GPIO_SIG239_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC239_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC239_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC239_IN_SEL: u32 = 63;
pub const GPIO_FUNC239_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC239_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC240_IN_SEL_CFG_REG: u32 = 1072973040;
pub const GPIO_SIG240_IN_SEL_V: u32 = 1;
pub const GPIO_SIG240_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC240_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC240_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC240_IN_SEL: u32 = 63;
pub const GPIO_FUNC240_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC240_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC241_IN_SEL_CFG_REG: u32 = 1072973044;
pub const GPIO_SIG241_IN_SEL_V: u32 = 1;
pub const GPIO_SIG241_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC241_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC241_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC241_IN_SEL: u32 = 63;
pub const GPIO_FUNC241_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC241_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC242_IN_SEL_CFG_REG: u32 = 1072973048;
pub const GPIO_SIG242_IN_SEL_V: u32 = 1;
pub const GPIO_SIG242_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC242_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC242_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC242_IN_SEL: u32 = 63;
pub const GPIO_FUNC242_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC242_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC243_IN_SEL_CFG_REG: u32 = 1072973052;
pub const GPIO_SIG243_IN_SEL_V: u32 = 1;
pub const GPIO_SIG243_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC243_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC243_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC243_IN_SEL: u32 = 63;
pub const GPIO_FUNC243_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC243_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC244_IN_SEL_CFG_REG: u32 = 1072973056;
pub const GPIO_SIG244_IN_SEL_V: u32 = 1;
pub const GPIO_SIG244_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC244_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC244_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC244_IN_SEL: u32 = 63;
pub const GPIO_FUNC244_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC244_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC245_IN_SEL_CFG_REG: u32 = 1072973060;
pub const GPIO_SIG245_IN_SEL_V: u32 = 1;
pub const GPIO_SIG245_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC245_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC245_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC245_IN_SEL: u32 = 63;
pub const GPIO_FUNC245_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC245_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC246_IN_SEL_CFG_REG: u32 = 1072973064;
pub const GPIO_SIG246_IN_SEL_V: u32 = 1;
pub const GPIO_SIG246_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC246_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC246_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC246_IN_SEL: u32 = 63;
pub const GPIO_FUNC246_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC246_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC247_IN_SEL_CFG_REG: u32 = 1072973068;
pub const GPIO_SIG247_IN_SEL_V: u32 = 1;
pub const GPIO_SIG247_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC247_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC247_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC247_IN_SEL: u32 = 63;
pub const GPIO_FUNC247_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC247_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC248_IN_SEL_CFG_REG: u32 = 1072973072;
pub const GPIO_SIG248_IN_SEL_V: u32 = 1;
pub const GPIO_SIG248_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC248_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC248_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC248_IN_SEL: u32 = 63;
pub const GPIO_FUNC248_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC248_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC249_IN_SEL_CFG_REG: u32 = 1072973076;
pub const GPIO_SIG249_IN_SEL_V: u32 = 1;
pub const GPIO_SIG249_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC249_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC249_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC249_IN_SEL: u32 = 63;
pub const GPIO_FUNC249_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC249_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC250_IN_SEL_CFG_REG: u32 = 1072973080;
pub const GPIO_SIG250_IN_SEL_V: u32 = 1;
pub const GPIO_SIG250_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC250_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC250_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC250_IN_SEL: u32 = 63;
pub const GPIO_FUNC250_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC250_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC251_IN_SEL_CFG_REG: u32 = 1072973084;
pub const GPIO_SIG251_IN_SEL_V: u32 = 1;
pub const GPIO_SIG251_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC251_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC251_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC251_IN_SEL: u32 = 63;
pub const GPIO_FUNC251_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC251_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC252_IN_SEL_CFG_REG: u32 = 1072973088;
pub const GPIO_SIG252_IN_SEL_V: u32 = 1;
pub const GPIO_SIG252_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC252_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC252_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC252_IN_SEL: u32 = 63;
pub const GPIO_FUNC252_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC252_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC253_IN_SEL_CFG_REG: u32 = 1072973092;
pub const GPIO_SIG253_IN_SEL_V: u32 = 1;
pub const GPIO_SIG253_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC253_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC253_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC253_IN_SEL: u32 = 63;
pub const GPIO_FUNC253_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC253_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC254_IN_SEL_CFG_REG: u32 = 1072973096;
pub const GPIO_SIG254_IN_SEL_V: u32 = 1;
pub const GPIO_SIG254_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC254_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC254_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC254_IN_SEL: u32 = 63;
pub const GPIO_FUNC254_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC254_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC255_IN_SEL_CFG_REG: u32 = 1072973100;
pub const GPIO_SIG255_IN_SEL_V: u32 = 1;
pub const GPIO_SIG255_IN_SEL_S: u32 = 7;
pub const GPIO_FUNC255_IN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC255_IN_INV_SEL_S: u32 = 6;
pub const GPIO_FUNC255_IN_SEL: u32 = 63;
pub const GPIO_FUNC255_IN_SEL_V: u32 = 63;
pub const GPIO_FUNC255_IN_SEL_S: u32 = 0;
pub const GPIO_FUNC0_OUT_SEL_CFG_REG: u32 = 1072973104;
pub const GPIO_FUNC0_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC0_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC0_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC0_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC0_OUT_SEL: u32 = 511;
pub const GPIO_FUNC0_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC0_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC1_OUT_SEL_CFG_REG: u32 = 1072973108;
pub const GPIO_FUNC1_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC1_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC1_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC1_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC1_OUT_SEL: u32 = 511;
pub const GPIO_FUNC1_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC1_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC2_OUT_SEL_CFG_REG: u32 = 1072973112;
pub const GPIO_FUNC2_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC2_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC2_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC2_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC2_OUT_SEL: u32 = 511;
pub const GPIO_FUNC2_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC2_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC3_OUT_SEL_CFG_REG: u32 = 1072973116;
pub const GPIO_FUNC3_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC3_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC3_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC3_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC3_OUT_SEL: u32 = 511;
pub const GPIO_FUNC3_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC3_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC4_OUT_SEL_CFG_REG: u32 = 1072973120;
pub const GPIO_FUNC4_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC4_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC4_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC4_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC4_OUT_SEL: u32 = 511;
pub const GPIO_FUNC4_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC4_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC5_OUT_SEL_CFG_REG: u32 = 1072973124;
pub const GPIO_FUNC5_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC5_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC5_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC5_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC5_OUT_SEL: u32 = 511;
pub const GPIO_FUNC5_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC5_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC6_OUT_SEL_CFG_REG: u32 = 1072973128;
pub const GPIO_FUNC6_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC6_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC6_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC6_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC6_OUT_SEL: u32 = 511;
pub const GPIO_FUNC6_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC6_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC7_OUT_SEL_CFG_REG: u32 = 1072973132;
pub const GPIO_FUNC7_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC7_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC7_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC7_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC7_OUT_SEL: u32 = 511;
pub const GPIO_FUNC7_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC7_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC8_OUT_SEL_CFG_REG: u32 = 1072973136;
pub const GPIO_FUNC8_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC8_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC8_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC8_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC8_OUT_SEL: u32 = 511;
pub const GPIO_FUNC8_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC8_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC9_OUT_SEL_CFG_REG: u32 = 1072973140;
pub const GPIO_FUNC9_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC9_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC9_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC9_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC9_OUT_SEL: u32 = 511;
pub const GPIO_FUNC9_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC9_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC10_OUT_SEL_CFG_REG: u32 = 1072973144;
pub const GPIO_FUNC10_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC10_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC10_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC10_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC10_OUT_SEL: u32 = 511;
pub const GPIO_FUNC10_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC10_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC11_OUT_SEL_CFG_REG: u32 = 1072973148;
pub const GPIO_FUNC11_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC11_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC11_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC11_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC11_OUT_SEL: u32 = 511;
pub const GPIO_FUNC11_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC11_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC12_OUT_SEL_CFG_REG: u32 = 1072973152;
pub const GPIO_FUNC12_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC12_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC12_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC12_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC12_OUT_SEL: u32 = 511;
pub const GPIO_FUNC12_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC12_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC13_OUT_SEL_CFG_REG: u32 = 1072973156;
pub const GPIO_FUNC13_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC13_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC13_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC13_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC13_OUT_SEL: u32 = 511;
pub const GPIO_FUNC13_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC13_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC14_OUT_SEL_CFG_REG: u32 = 1072973160;
pub const GPIO_FUNC14_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC14_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC14_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC14_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC14_OUT_SEL: u32 = 511;
pub const GPIO_FUNC14_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC14_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC15_OUT_SEL_CFG_REG: u32 = 1072973164;
pub const GPIO_FUNC15_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC15_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC15_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC15_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC15_OUT_SEL: u32 = 511;
pub const GPIO_FUNC15_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC15_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC16_OUT_SEL_CFG_REG: u32 = 1072973168;
pub const GPIO_FUNC16_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC16_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC16_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC16_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC16_OUT_SEL: u32 = 511;
pub const GPIO_FUNC16_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC16_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC17_OUT_SEL_CFG_REG: u32 = 1072973172;
pub const GPIO_FUNC17_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC17_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC17_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC17_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC17_OUT_SEL: u32 = 511;
pub const GPIO_FUNC17_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC17_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC18_OUT_SEL_CFG_REG: u32 = 1072973176;
pub const GPIO_FUNC18_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC18_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC18_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC18_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC18_OUT_SEL: u32 = 511;
pub const GPIO_FUNC18_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC18_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC19_OUT_SEL_CFG_REG: u32 = 1072973180;
pub const GPIO_FUNC19_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC19_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC19_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC19_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC19_OUT_SEL: u32 = 511;
pub const GPIO_FUNC19_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC19_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC20_OUT_SEL_CFG_REG: u32 = 1072973184;
pub const GPIO_FUNC20_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC20_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC20_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC20_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC20_OUT_SEL: u32 = 511;
pub const GPIO_FUNC20_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC20_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC21_OUT_SEL_CFG_REG: u32 = 1072973188;
pub const GPIO_FUNC21_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC21_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC21_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC21_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC21_OUT_SEL: u32 = 511;
pub const GPIO_FUNC21_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC21_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC22_OUT_SEL_CFG_REG: u32 = 1072973192;
pub const GPIO_FUNC22_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC22_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC22_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC22_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC22_OUT_SEL: u32 = 511;
pub const GPIO_FUNC22_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC22_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC23_OUT_SEL_CFG_REG: u32 = 1072973196;
pub const GPIO_FUNC23_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC23_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC23_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC23_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC23_OUT_SEL: u32 = 511;
pub const GPIO_FUNC23_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC23_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC24_OUT_SEL_CFG_REG: u32 = 1072973200;
pub const GPIO_FUNC24_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC24_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC24_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC24_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC24_OUT_SEL: u32 = 511;
pub const GPIO_FUNC24_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC24_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC25_OUT_SEL_CFG_REG: u32 = 1072973204;
pub const GPIO_FUNC25_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC25_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC25_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC25_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC25_OUT_SEL: u32 = 511;
pub const GPIO_FUNC25_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC25_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC26_OUT_SEL_CFG_REG: u32 = 1072973208;
pub const GPIO_FUNC26_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC26_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC26_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC26_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC26_OUT_SEL: u32 = 511;
pub const GPIO_FUNC26_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC26_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC27_OUT_SEL_CFG_REG: u32 = 1072973212;
pub const GPIO_FUNC27_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC27_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC27_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC27_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC27_OUT_SEL: u32 = 511;
pub const GPIO_FUNC27_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC27_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC28_OUT_SEL_CFG_REG: u32 = 1072973216;
pub const GPIO_FUNC28_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC28_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC28_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC28_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC28_OUT_SEL: u32 = 511;
pub const GPIO_FUNC28_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC28_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC29_OUT_SEL_CFG_REG: u32 = 1072973220;
pub const GPIO_FUNC29_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC29_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC29_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC29_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC29_OUT_SEL: u32 = 511;
pub const GPIO_FUNC29_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC29_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC30_OUT_SEL_CFG_REG: u32 = 1072973224;
pub const GPIO_FUNC30_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC30_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC30_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC30_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC30_OUT_SEL: u32 = 511;
pub const GPIO_FUNC30_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC30_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC31_OUT_SEL_CFG_REG: u32 = 1072973228;
pub const GPIO_FUNC31_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC31_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC31_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC31_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC31_OUT_SEL: u32 = 511;
pub const GPIO_FUNC31_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC31_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC32_OUT_SEL_CFG_REG: u32 = 1072973232;
pub const GPIO_FUNC32_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC32_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC32_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC32_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC32_OUT_SEL: u32 = 511;
pub const GPIO_FUNC32_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC32_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC33_OUT_SEL_CFG_REG: u32 = 1072973236;
pub const GPIO_FUNC33_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC33_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC33_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC33_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC33_OUT_SEL: u32 = 511;
pub const GPIO_FUNC33_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC33_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC34_OUT_SEL_CFG_REG: u32 = 1072973240;
pub const GPIO_FUNC34_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC34_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC34_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC34_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC34_OUT_SEL: u32 = 511;
pub const GPIO_FUNC34_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC34_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC35_OUT_SEL_CFG_REG: u32 = 1072973244;
pub const GPIO_FUNC35_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC35_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC35_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC35_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC35_OUT_SEL: u32 = 511;
pub const GPIO_FUNC35_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC35_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC36_OUT_SEL_CFG_REG: u32 = 1072973248;
pub const GPIO_FUNC36_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC36_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC36_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC36_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC36_OUT_SEL: u32 = 511;
pub const GPIO_FUNC36_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC36_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC37_OUT_SEL_CFG_REG: u32 = 1072973252;
pub const GPIO_FUNC37_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC37_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC37_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC37_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC37_OUT_SEL: u32 = 511;
pub const GPIO_FUNC37_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC37_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC38_OUT_SEL_CFG_REG: u32 = 1072973256;
pub const GPIO_FUNC38_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC38_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC38_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC38_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC38_OUT_SEL: u32 = 511;
pub const GPIO_FUNC38_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC38_OUT_SEL_S: u32 = 0;
pub const GPIO_FUNC39_OUT_SEL_CFG_REG: u32 = 1072973260;
pub const GPIO_FUNC39_OEN_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OEN_INV_SEL_S: u32 = 11;
pub const GPIO_FUNC39_OEN_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OEN_SEL_S: u32 = 10;
pub const GPIO_FUNC39_OUT_INV_SEL_V: u32 = 1;
pub const GPIO_FUNC39_OUT_INV_SEL_S: u32 = 9;
pub const GPIO_FUNC39_OUT_SEL: u32 = 511;
pub const GPIO_FUNC39_OUT_SEL_V: u32 = 511;
pub const GPIO_FUNC39_OUT_SEL_S: u32 = 0;
pub const RTC_GPIO_OUT_REG: u32 = 1072989184;
pub const RTC_GPIO_OUT_DATA: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_V: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_S: u32 = 14;
pub const RTC_GPIO_OUT_W1TS_REG: u32 = 1072989188;
pub const RTC_GPIO_OUT_DATA_W1TS: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_W1TS_V: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_W1TS_S: u32 = 14;
pub const RTC_GPIO_OUT_W1TC_REG: u32 = 1072989192;
pub const RTC_GPIO_OUT_DATA_W1TC: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_W1TC_V: u32 = 262143;
pub const RTC_GPIO_OUT_DATA_W1TC_S: u32 = 14;
pub const RTC_GPIO_ENABLE_REG: u32 = 1072989196;
pub const RTC_GPIO_ENABLE: u32 = 262143;
pub const RTC_GPIO_ENABLE_V: u32 = 262143;
pub const RTC_GPIO_ENABLE_S: u32 = 14;
pub const RTC_GPIO_ENABLE_W1TS_REG: u32 = 1072989200;
pub const RTC_GPIO_ENABLE_W1TS: u32 = 262143;
pub const RTC_GPIO_ENABLE_W1TS_V: u32 = 262143;
pub const RTC_GPIO_ENABLE_W1TS_S: u32 = 14;
pub const RTC_GPIO_ENABLE_W1TC_REG: u32 = 1072989204;
pub const RTC_GPIO_ENABLE_W1TC: u32 = 262143;
pub const RTC_GPIO_ENABLE_W1TC_V: u32 = 262143;
pub const RTC_GPIO_ENABLE_W1TC_S: u32 = 14;
pub const RTC_GPIO_STATUS_REG: u32 = 1072989208;
pub const RTC_GPIO_STATUS_INT: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_V: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_S: u32 = 14;
pub const RTC_GPIO_STATUS_W1TS_REG: u32 = 1072989212;
pub const RTC_GPIO_STATUS_INT_W1TS: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_W1TS_V: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_W1TS_S: u32 = 14;
pub const RTC_GPIO_STATUS_W1TC_REG: u32 = 1072989216;
pub const RTC_GPIO_STATUS_INT_W1TC: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_W1TC_V: u32 = 262143;
pub const RTC_GPIO_STATUS_INT_W1TC_S: u32 = 14;
pub const RTC_GPIO_IN_REG: u32 = 1072989220;
pub const RTC_GPIO_IN_NEXT: u32 = 262143;
pub const RTC_GPIO_IN_NEXT_V: u32 = 262143;
pub const RTC_GPIO_IN_NEXT_S: u32 = 14;
pub const RTC_GPIO_PIN0_REG: u32 = 1072989224;
pub const RTC_GPIO_PIN0_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN0_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN0_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN0_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN0_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN0_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN0_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN1_REG: u32 = 1072989228;
pub const RTC_GPIO_PIN1_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN1_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN1_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN1_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN1_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN1_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN1_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN2_REG: u32 = 1072989232;
pub const RTC_GPIO_PIN2_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN2_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN2_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN2_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN2_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN2_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN2_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN3_REG: u32 = 1072989236;
pub const RTC_GPIO_PIN3_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN3_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN3_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN3_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN3_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN3_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN3_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN4_REG: u32 = 1072989240;
pub const RTC_GPIO_PIN4_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN4_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN4_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN4_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN4_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN4_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN4_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN5_REG: u32 = 1072989244;
pub const RTC_GPIO_PIN5_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN5_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN5_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN5_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN5_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN5_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN5_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN6_REG: u32 = 1072989248;
pub const RTC_GPIO_PIN6_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN6_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN6_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN6_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN6_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN6_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN6_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN7_REG: u32 = 1072989252;
pub const RTC_GPIO_PIN7_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN7_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN7_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN7_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN7_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN7_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN7_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN8_REG: u32 = 1072989256;
pub const RTC_GPIO_PIN8_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN8_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN8_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN8_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN8_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN8_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN8_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN9_REG: u32 = 1072989260;
pub const RTC_GPIO_PIN9_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN9_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN9_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN9_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN9_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN9_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN9_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN10_REG: u32 = 1072989264;
pub const RTC_GPIO_PIN10_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN10_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN10_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN10_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN10_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN10_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN10_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN11_REG: u32 = 1072989268;
pub const RTC_GPIO_PIN11_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN11_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN11_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN11_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN11_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN11_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN11_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN12_REG: u32 = 1072989272;
pub const RTC_GPIO_PIN12_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN12_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN12_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN12_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN12_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN12_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN12_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN13_REG: u32 = 1072989276;
pub const RTC_GPIO_PIN13_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN13_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN13_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN13_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN13_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN13_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN13_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN14_REG: u32 = 1072989280;
pub const RTC_GPIO_PIN14_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN14_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN14_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN14_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN14_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN14_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN14_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN15_REG: u32 = 1072989284;
pub const RTC_GPIO_PIN15_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN15_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN15_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN15_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN15_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN15_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN15_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN16_REG: u32 = 1072989288;
pub const RTC_GPIO_PIN16_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN16_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN16_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN16_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN16_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN16_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN16_PAD_DRIVER_S: u32 = 2;
pub const RTC_GPIO_PIN17_REG: u32 = 1072989292;
pub const RTC_GPIO_PIN17_WAKEUP_ENABLE_V: u32 = 1;
pub const RTC_GPIO_PIN17_WAKEUP_ENABLE_S: u32 = 10;
pub const RTC_GPIO_PIN17_INT_TYPE: u32 = 7;
pub const RTC_GPIO_PIN17_INT_TYPE_V: u32 = 7;
pub const RTC_GPIO_PIN17_INT_TYPE_S: u32 = 7;
pub const RTC_GPIO_PIN17_PAD_DRIVER_V: u32 = 1;
pub const RTC_GPIO_PIN17_PAD_DRIVER_S: u32 = 2;
pub const RTC_IO_RTC_DEBUG_SEL_REG: u32 = 1072989296;
pub const RTC_IO_DEBUG_12M_NO_GATING_V: u32 = 1;
pub const RTC_IO_DEBUG_12M_NO_GATING_S: u32 = 25;
pub const RTC_IO_DEBUG_SEL4: u32 = 31;
pub const RTC_IO_DEBUG_SEL4_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL4_S: u32 = 20;
pub const RTC_IO_DEBUG_SEL3: u32 = 31;
pub const RTC_IO_DEBUG_SEL3_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL3_S: u32 = 15;
pub const RTC_IO_DEBUG_SEL2: u32 = 31;
pub const RTC_IO_DEBUG_SEL2_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL2_S: u32 = 10;
pub const RTC_IO_DEBUG_SEL1: u32 = 31;
pub const RTC_IO_DEBUG_SEL1_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL1_S: u32 = 5;
pub const RTC_IO_DEBUG_SEL0: u32 = 31;
pub const RTC_IO_DEBUG_SEL0_V: u32 = 31;
pub const RTC_IO_DEBUG_SEL0_S: u32 = 0;
pub const RTC_IO_DEBUG_SEL0_8M: u32 = 1;
pub const RTC_IO_DEBUG_SEL0_32K_XTAL: u32 = 4;
pub const RTC_IO_DEBUG_SEL0_150K_OSC: u32 = 5;
pub const RTC_IO_DIG_PAD_HOLD_REG: u32 = 1072989300;
pub const RTC_IO_DIG_PAD_HOLD: u32 = 4294967295;
pub const RTC_IO_DIG_PAD_HOLD_V: u32 = 4294967295;
pub const RTC_IO_DIG_PAD_HOLD_S: u32 = 0;
pub const RTC_IO_HALL_SENS_REG: u32 = 1072989304;
pub const RTC_IO_XPD_HALL_V: u32 = 1;
pub const RTC_IO_XPD_HALL_S: u32 = 31;
pub const RTC_IO_HALL_PHASE_V: u32 = 1;
pub const RTC_IO_HALL_PHASE_S: u32 = 30;
pub const RTC_IO_SENSOR_PADS_REG: u32 = 1072989308;
pub const RTC_IO_SENSE1_HOLD_V: u32 = 1;
pub const RTC_IO_SENSE1_HOLD_S: u32 = 31;
pub const RTC_IO_SENSE2_HOLD_V: u32 = 1;
pub const RTC_IO_SENSE2_HOLD_S: u32 = 30;
pub const RTC_IO_SENSE3_HOLD_V: u32 = 1;
pub const RTC_IO_SENSE3_HOLD_S: u32 = 29;
pub const RTC_IO_SENSE4_HOLD_V: u32 = 1;
pub const RTC_IO_SENSE4_HOLD_S: u32 = 28;
pub const RTC_IO_SENSE1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_SENSE1_MUX_SEL_S: u32 = 27;
pub const RTC_IO_SENSE2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_SENSE2_MUX_SEL_S: u32 = 26;
pub const RTC_IO_SENSE3_MUX_SEL_V: u32 = 1;
pub const RTC_IO_SENSE3_MUX_SEL_S: u32 = 25;
pub const RTC_IO_SENSE4_MUX_SEL_V: u32 = 1;
pub const RTC_IO_SENSE4_MUX_SEL_S: u32 = 24;
pub const RTC_IO_SENSE1_FUN_SEL: u32 = 3;
pub const RTC_IO_SENSE1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_SENSE1_FUN_SEL_S: u32 = 22;
pub const RTC_IO_SENSE1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_SENSE1_SLP_SEL_S: u32 = 21;
pub const RTC_IO_SENSE1_SLP_IE_V: u32 = 1;
pub const RTC_IO_SENSE1_SLP_IE_S: u32 = 20;
pub const RTC_IO_SENSE1_FUN_IE_V: u32 = 1;
pub const RTC_IO_SENSE1_FUN_IE_S: u32 = 19;
pub const RTC_IO_SENSE2_FUN_SEL: u32 = 3;
pub const RTC_IO_SENSE2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_SENSE2_FUN_SEL_S: u32 = 17;
pub const RTC_IO_SENSE2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_SENSE2_SLP_SEL_S: u32 = 16;
pub const RTC_IO_SENSE2_SLP_IE_V: u32 = 1;
pub const RTC_IO_SENSE2_SLP_IE_S: u32 = 15;
pub const RTC_IO_SENSE2_FUN_IE_V: u32 = 1;
pub const RTC_IO_SENSE2_FUN_IE_S: u32 = 14;
pub const RTC_IO_SENSE3_FUN_SEL: u32 = 3;
pub const RTC_IO_SENSE3_FUN_SEL_V: u32 = 3;
pub const RTC_IO_SENSE3_FUN_SEL_S: u32 = 12;
pub const RTC_IO_SENSE3_SLP_SEL_V: u32 = 1;
pub const RTC_IO_SENSE3_SLP_SEL_S: u32 = 11;
pub const RTC_IO_SENSE3_SLP_IE_V: u32 = 1;
pub const RTC_IO_SENSE3_SLP_IE_S: u32 = 10;
pub const RTC_IO_SENSE3_FUN_IE_V: u32 = 1;
pub const RTC_IO_SENSE3_FUN_IE_S: u32 = 9;
pub const RTC_IO_SENSE4_FUN_SEL: u32 = 3;
pub const RTC_IO_SENSE4_FUN_SEL_V: u32 = 3;
pub const RTC_IO_SENSE4_FUN_SEL_S: u32 = 7;
pub const RTC_IO_SENSE4_SLP_SEL_V: u32 = 1;
pub const RTC_IO_SENSE4_SLP_SEL_S: u32 = 6;
pub const RTC_IO_SENSE4_SLP_IE_V: u32 = 1;
pub const RTC_IO_SENSE4_SLP_IE_S: u32 = 5;
pub const RTC_IO_SENSE4_FUN_IE_V: u32 = 1;
pub const RTC_IO_SENSE4_FUN_IE_S: u32 = 4;
pub const RTC_IO_ADC_PAD_REG: u32 = 1072989312;
pub const RTC_IO_ADC1_HOLD_V: u32 = 1;
pub const RTC_IO_ADC1_HOLD_S: u32 = 31;
pub const RTC_IO_ADC2_HOLD_V: u32 = 1;
pub const RTC_IO_ADC2_HOLD_S: u32 = 30;
pub const RTC_IO_ADC1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_ADC1_MUX_SEL_S: u32 = 29;
pub const RTC_IO_ADC2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_ADC2_MUX_SEL_S: u32 = 28;
pub const RTC_IO_ADC1_FUN_SEL: u32 = 3;
pub const RTC_IO_ADC1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_ADC1_FUN_SEL_S: u32 = 26;
pub const RTC_IO_ADC1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_ADC1_SLP_SEL_S: u32 = 25;
pub const RTC_IO_ADC1_SLP_IE_V: u32 = 1;
pub const RTC_IO_ADC1_SLP_IE_S: u32 = 24;
pub const RTC_IO_ADC1_FUN_IE_V: u32 = 1;
pub const RTC_IO_ADC1_FUN_IE_S: u32 = 23;
pub const RTC_IO_ADC2_FUN_SEL: u32 = 3;
pub const RTC_IO_ADC2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_ADC2_FUN_SEL_S: u32 = 21;
pub const RTC_IO_ADC2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_ADC2_SLP_SEL_S: u32 = 20;
pub const RTC_IO_ADC2_SLP_IE_V: u32 = 1;
pub const RTC_IO_ADC2_SLP_IE_S: u32 = 19;
pub const RTC_IO_ADC2_FUN_IE_V: u32 = 1;
pub const RTC_IO_ADC2_FUN_IE_S: u32 = 18;
pub const RTC_IO_PAD_DAC1_REG: u32 = 1072989316;
pub const RTC_IO_PDAC1_DRV: u32 = 3;
pub const RTC_IO_PDAC1_DRV_V: u32 = 3;
pub const RTC_IO_PDAC1_DRV_S: u32 = 30;
pub const RTC_IO_PDAC1_HOLD_V: u32 = 1;
pub const RTC_IO_PDAC1_HOLD_S: u32 = 29;
pub const RTC_IO_PDAC1_RDE_V: u32 = 1;
pub const RTC_IO_PDAC1_RDE_S: u32 = 28;
pub const RTC_IO_PDAC1_RUE_V: u32 = 1;
pub const RTC_IO_PDAC1_RUE_S: u32 = 27;
pub const RTC_IO_PDAC1_DAC: u32 = 255;
pub const RTC_IO_PDAC1_DAC_V: u32 = 255;
pub const RTC_IO_PDAC1_DAC_S: u32 = 19;
pub const RTC_IO_PDAC1_XPD_DAC_V: u32 = 1;
pub const RTC_IO_PDAC1_XPD_DAC_S: u32 = 18;
pub const RTC_IO_PDAC1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PDAC1_MUX_SEL_S: u32 = 17;
pub const RTC_IO_PDAC1_FUN_SEL: u32 = 3;
pub const RTC_IO_PDAC1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PDAC1_FUN_SEL_S: u32 = 15;
pub const RTC_IO_PDAC1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_SEL_S: u32 = 14;
pub const RTC_IO_PDAC1_SLP_IE_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_IE_S: u32 = 13;
pub const RTC_IO_PDAC1_SLP_OE_V: u32 = 1;
pub const RTC_IO_PDAC1_SLP_OE_S: u32 = 12;
pub const RTC_IO_PDAC1_FUN_IE_V: u32 = 1;
pub const RTC_IO_PDAC1_FUN_IE_S: u32 = 11;
pub const RTC_IO_PDAC1_DAC_XPD_FORCE_V: u32 = 1;
pub const RTC_IO_PDAC1_DAC_XPD_FORCE_S: u32 = 10;
pub const RTC_IO_PAD_DAC2_REG: u32 = 1072989320;
pub const RTC_IO_PDAC2_DRV: u32 = 3;
pub const RTC_IO_PDAC2_DRV_V: u32 = 3;
pub const RTC_IO_PDAC2_DRV_S: u32 = 30;
pub const RTC_IO_PDAC2_HOLD_V: u32 = 1;
pub const RTC_IO_PDAC2_HOLD_S: u32 = 29;
pub const RTC_IO_PDAC2_RDE_V: u32 = 1;
pub const RTC_IO_PDAC2_RDE_S: u32 = 28;
pub const RTC_IO_PDAC2_RUE_V: u32 = 1;
pub const RTC_IO_PDAC2_RUE_S: u32 = 27;
pub const RTC_IO_PDAC2_DAC: u32 = 255;
pub const RTC_IO_PDAC2_DAC_V: u32 = 255;
pub const RTC_IO_PDAC2_DAC_S: u32 = 19;
pub const RTC_IO_PDAC2_XPD_DAC_V: u32 = 1;
pub const RTC_IO_PDAC2_XPD_DAC_S: u32 = 18;
pub const RTC_IO_PDAC2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_PDAC2_MUX_SEL_S: u32 = 17;
pub const RTC_IO_PDAC2_FUN_SEL: u32 = 3;
pub const RTC_IO_PDAC2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_PDAC2_FUN_SEL_S: u32 = 15;
pub const RTC_IO_PDAC2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_SEL_S: u32 = 14;
pub const RTC_IO_PDAC2_SLP_IE_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_IE_S: u32 = 13;
pub const RTC_IO_PDAC2_SLP_OE_V: u32 = 1;
pub const RTC_IO_PDAC2_SLP_OE_S: u32 = 12;
pub const RTC_IO_PDAC2_FUN_IE_V: u32 = 1;
pub const RTC_IO_PDAC2_FUN_IE_S: u32 = 11;
pub const RTC_IO_PDAC2_DAC_XPD_FORCE_V: u32 = 1;
pub const RTC_IO_PDAC2_DAC_XPD_FORCE_S: u32 = 10;
pub const RTC_IO_XTAL_32K_PAD_REG: u32 = 1072989324;
pub const RTC_IO_X32N_DRV: u32 = 3;
pub const RTC_IO_X32N_DRV_V: u32 = 3;
pub const RTC_IO_X32N_DRV_S: u32 = 30;
pub const RTC_IO_X32N_HOLD_V: u32 = 1;
pub const RTC_IO_X32N_HOLD_S: u32 = 29;
pub const RTC_IO_X32N_RDE_V: u32 = 1;
pub const RTC_IO_X32N_RDE_S: u32 = 28;
pub const RTC_IO_X32N_RUE_V: u32 = 1;
pub const RTC_IO_X32N_RUE_S: u32 = 27;
pub const RTC_IO_X32P_DRV: u32 = 3;
pub const RTC_IO_X32P_DRV_V: u32 = 3;
pub const RTC_IO_X32P_DRV_S: u32 = 25;
pub const RTC_IO_X32P_HOLD_V: u32 = 1;
pub const RTC_IO_X32P_HOLD_S: u32 = 24;
pub const RTC_IO_X32P_RDE_V: u32 = 1;
pub const RTC_IO_X32P_RDE_S: u32 = 23;
pub const RTC_IO_X32P_RUE_V: u32 = 1;
pub const RTC_IO_X32P_RUE_S: u32 = 22;
pub const RTC_IO_DAC_XTAL_32K: u32 = 3;
pub const RTC_IO_DAC_XTAL_32K_V: u32 = 3;
pub const RTC_IO_DAC_XTAL_32K_S: u32 = 20;
pub const RTC_IO_XPD_XTAL_32K_V: u32 = 1;
pub const RTC_IO_XPD_XTAL_32K_S: u32 = 19;
pub const RTC_IO_X32N_MUX_SEL_V: u32 = 1;
pub const RTC_IO_X32N_MUX_SEL_S: u32 = 18;
pub const RTC_IO_X32P_MUX_SEL_V: u32 = 1;
pub const RTC_IO_X32P_MUX_SEL_S: u32 = 17;
pub const RTC_IO_X32N_FUN_SEL: u32 = 3;
pub const RTC_IO_X32N_FUN_SEL_V: u32 = 3;
pub const RTC_IO_X32N_FUN_SEL_S: u32 = 15;
pub const RTC_IO_X32N_SLP_SEL_V: u32 = 1;
pub const RTC_IO_X32N_SLP_SEL_S: u32 = 14;
pub const RTC_IO_X32N_SLP_IE_V: u32 = 1;
pub const RTC_IO_X32N_SLP_IE_S: u32 = 13;
pub const RTC_IO_X32N_SLP_OE_V: u32 = 1;
pub const RTC_IO_X32N_SLP_OE_S: u32 = 12;
pub const RTC_IO_X32N_FUN_IE_V: u32 = 1;
pub const RTC_IO_X32N_FUN_IE_S: u32 = 11;
pub const RTC_IO_X32P_FUN_SEL: u32 = 3;
pub const RTC_IO_X32P_FUN_SEL_V: u32 = 3;
pub const RTC_IO_X32P_FUN_SEL_S: u32 = 9;
pub const RTC_IO_X32P_SLP_SEL_V: u32 = 1;
pub const RTC_IO_X32P_SLP_SEL_S: u32 = 8;
pub const RTC_IO_X32P_SLP_IE_V: u32 = 1;
pub const RTC_IO_X32P_SLP_IE_S: u32 = 7;
pub const RTC_IO_X32P_SLP_OE_V: u32 = 1;
pub const RTC_IO_X32P_SLP_OE_S: u32 = 6;
pub const RTC_IO_X32P_FUN_IE_V: u32 = 1;
pub const RTC_IO_X32P_FUN_IE_S: u32 = 5;
pub const RTC_IO_DRES_XTAL_32K: u32 = 3;
pub const RTC_IO_DRES_XTAL_32K_V: u32 = 3;
pub const RTC_IO_DRES_XTAL_32K_S: u32 = 3;
pub const RTC_IO_DBIAS_XTAL_32K: u32 = 3;
pub const RTC_IO_DBIAS_XTAL_32K_V: u32 = 3;
pub const RTC_IO_DBIAS_XTAL_32K_S: u32 = 1;
pub const RTC_IO_TOUCH_CFG_REG: u32 = 1072989328;
pub const RTC_IO_TOUCH_XPD_BIAS_V: u32 = 1;
pub const RTC_IO_TOUCH_XPD_BIAS_S: u32 = 31;
pub const RTC_IO_TOUCH_DREFH: u32 = 3;
pub const RTC_IO_TOUCH_DREFH_V: u32 = 3;
pub const RTC_IO_TOUCH_DREFH_S: u32 = 29;
pub const RTC_IO_TOUCH_DREFL: u32 = 3;
pub const RTC_IO_TOUCH_DREFL_V: u32 = 3;
pub const RTC_IO_TOUCH_DREFL_S: u32 = 27;
pub const RTC_IO_TOUCH_DRANGE: u32 = 3;
pub const RTC_IO_TOUCH_DRANGE_V: u32 = 3;
pub const RTC_IO_TOUCH_DRANGE_S: u32 = 25;
pub const RTC_IO_TOUCH_DCUR: u32 = 3;
pub const RTC_IO_TOUCH_DCUR_V: u32 = 3;
pub const RTC_IO_TOUCH_DCUR_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD0_REG: u32 = 1072989332;
pub const RTC_IO_TOUCH_PAD0_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD0_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD0_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD0_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD0_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD0_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD0_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD0_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD0_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD0_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD0_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD0_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD0_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD0_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD0_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD0_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD0_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD0_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD1_REG: u32 = 1072989336;
pub const RTC_IO_TOUCH_PAD1_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD1_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD1_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD1_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD1_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD1_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD1_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD1_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD1_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD1_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD1_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD1_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD1_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD1_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD1_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD1_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD1_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD1_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD2_REG: u32 = 1072989340;
pub const RTC_IO_TOUCH_PAD2_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD2_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD2_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD2_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD2_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD2_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD2_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD2_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD2_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD2_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD2_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD2_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD2_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD2_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD2_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD2_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD2_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD2_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD3_REG: u32 = 1072989344;
pub const RTC_IO_TOUCH_PAD3_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD3_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD3_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD3_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD3_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD3_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD3_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD3_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD3_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD3_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD3_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD3_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD3_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD3_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD3_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD3_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD3_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD3_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD4_REG: u32 = 1072989348;
pub const RTC_IO_TOUCH_PAD4_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD4_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD4_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD4_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD4_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD4_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD4_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD4_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD4_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD4_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD4_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD4_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD4_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD4_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD4_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD4_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD4_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD4_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD5_REG: u32 = 1072989352;
pub const RTC_IO_TOUCH_PAD5_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD5_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD5_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD5_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD5_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD5_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD5_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD5_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD5_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD5_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD5_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD5_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD5_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD5_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD5_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD5_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD5_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD5_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD6_REG: u32 = 1072989356;
pub const RTC_IO_TOUCH_PAD6_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD6_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD6_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD6_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD6_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD6_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD6_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD6_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD6_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD6_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD6_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD6_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD6_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD6_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD6_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD6_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD6_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD6_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD7_REG: u32 = 1072989360;
pub const RTC_IO_TOUCH_PAD7_HOLD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_HOLD_S: u32 = 31;
pub const RTC_IO_TOUCH_PAD7_DRV: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_DRV_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_DRV_S: u32 = 29;
pub const RTC_IO_TOUCH_PAD7_RDE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_RDE_S: u32 = 28;
pub const RTC_IO_TOUCH_PAD7_RUE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_RUE_S: u32 = 27;
pub const RTC_IO_TOUCH_PAD7_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD7_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD7_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD7_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD7_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD7_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD7_MUX_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_MUX_SEL_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL_V: u32 = 3;
pub const RTC_IO_TOUCH_PAD7_FUN_SEL_S: u32 = 17;
pub const RTC_IO_TOUCH_PAD7_SLP_SEL_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_SEL_S: u32 = 16;
pub const RTC_IO_TOUCH_PAD7_SLP_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_IE_S: u32 = 15;
pub const RTC_IO_TOUCH_PAD7_SLP_OE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_SLP_OE_S: u32 = 14;
pub const RTC_IO_TOUCH_PAD7_FUN_IE_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_FUN_IE_S: u32 = 13;
pub const RTC_IO_TOUCH_PAD7_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD7_TO_GPIO_S: u32 = 12;
pub const RTC_IO_TOUCH_PAD8_REG: u32 = 1072989364;
pub const RTC_IO_TOUCH_PAD8_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD8_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD8_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD8_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD8_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD8_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD8_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD8_TO_GPIO_S: u32 = 19;
pub const RTC_IO_TOUCH_PAD9_REG: u32 = 1072989368;
pub const RTC_IO_TOUCH_PAD9_DAC: u32 = 7;
pub const RTC_IO_TOUCH_PAD9_DAC_V: u32 = 7;
pub const RTC_IO_TOUCH_PAD9_DAC_S: u32 = 23;
pub const RTC_IO_TOUCH_PAD9_START_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_START_S: u32 = 22;
pub const RTC_IO_TOUCH_PAD9_TIE_OPT_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_TIE_OPT_S: u32 = 21;
pub const RTC_IO_TOUCH_PAD9_XPD_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_XPD_S: u32 = 20;
pub const RTC_IO_TOUCH_PAD9_TO_GPIO_V: u32 = 1;
pub const RTC_IO_TOUCH_PAD9_TO_GPIO_S: u32 = 19;
pub const RTC_IO_EXT_WAKEUP0_REG: u32 = 1072989372;
pub const RTC_IO_EXT_WAKEUP0_SEL: u32 = 31;
pub const RTC_IO_EXT_WAKEUP0_SEL_V: u32 = 31;
pub const RTC_IO_EXT_WAKEUP0_SEL_S: u32 = 27;
pub const RTC_IO_XTL_EXT_CTR_REG: u32 = 1072989376;
pub const RTC_IO_XTL_EXT_CTR_SEL: u32 = 31;
pub const RTC_IO_XTL_EXT_CTR_SEL_V: u32 = 31;
pub const RTC_IO_XTL_EXT_CTR_SEL_S: u32 = 27;
pub const RTC_IO_SAR_I2C_IO_REG: u32 = 1072989380;
pub const RTC_IO_SAR_I2C_SDA_SEL: u32 = 3;
pub const RTC_IO_SAR_I2C_SDA_SEL_V: u32 = 3;
pub const RTC_IO_SAR_I2C_SDA_SEL_S: u32 = 30;
pub const RTC_IO_SAR_I2C_SCL_SEL: u32 = 3;
pub const RTC_IO_SAR_I2C_SCL_SEL_V: u32 = 3;
pub const RTC_IO_SAR_I2C_SCL_SEL_S: u32 = 28;
pub const RTC_IO_SAR_DEBUG_BIT_SEL: u32 = 31;
pub const RTC_IO_SAR_DEBUG_BIT_SEL_V: u32 = 31;
pub const RTC_IO_SAR_DEBUG_BIT_SEL_S: u32 = 23;
pub const RTC_IO_DATE_REG: u32 = 1072989384;
pub const RTC_IO_IO_DATE: u32 = 268435455;
pub const RTC_IO_IO_DATE_V: u32 = 268435455;
pub const RTC_IO_IO_DATE_S: u32 = 0;
pub const RTC_IO_RTC_IO_DATE_VERSION: u32 = 24129888;
pub const SLP_OE_V: u32 = 1;
pub const SLP_OE_S: u32 = 0;
pub const SLP_SEL_V: u32 = 1;
pub const SLP_SEL_S: u32 = 1;
pub const SLP_PD_V: u32 = 1;
pub const SLP_PD_S: u32 = 2;
pub const SLP_PU_V: u32 = 1;
pub const SLP_PU_S: u32 = 3;
pub const SLP_IE_V: u32 = 1;
pub const SLP_IE_S: u32 = 4;
pub const SLP_DRV: u32 = 3;
pub const SLP_DRV_V: u32 = 3;
pub const SLP_DRV_S: u32 = 5;
pub const FUN_PD_V: u32 = 1;
pub const FUN_PD_S: u32 = 7;
pub const FUN_PU_V: u32 = 1;
pub const FUN_PU_S: u32 = 8;
pub const FUN_IE_V: u32 = 1;
pub const FUN_IE_S: u32 = 9;
pub const FUN_DRV: u32 = 3;
pub const FUN_DRV_V: u32 = 3;
pub const FUN_DRV_S: u32 = 10;
pub const MCU_SEL: u32 = 7;
pub const MCU_SEL_V: u32 = 7;
pub const MCU_SEL_S: u32 = 12;
pub const PIN_FUNC_GPIO: u32 = 2;
pub const PIN_CTRL: u32 = 1072992256;
pub const CLK_OUT3: u32 = 15;
pub const CLK_OUT3_V: u32 = 15;
pub const CLK_OUT3_S: u32 = 8;
pub const CLK_OUT3_M: u32 = 3840;
pub const CLK_OUT2: u32 = 15;
pub const CLK_OUT2_V: u32 = 15;
pub const CLK_OUT2_S: u32 = 4;
pub const CLK_OUT2_M: u32 = 240;
pub const CLK_OUT1: u32 = 15;
pub const CLK_OUT1_V: u32 = 15;
pub const CLK_OUT1_S: u32 = 0;
pub const CLK_OUT1_M: u32 = 15;
pub const PERIPHS_IO_MUX_GPIO0_U: u32 = 1072992324;
pub const IO_MUX_GPIO0_REG: u32 = 1072992324;
pub const FUNC_GPIO0_EMAC_TX_CLK: u32 = 5;
pub const FUNC_GPIO0_GPIO0: u32 = 2;
pub const FUNC_GPIO0_CLK_OUT1: u32 = 1;
pub const FUNC_GPIO0_GPIO0_0: u32 = 0;
pub const PERIPHS_IO_MUX_U0TXD_U: u32 = 1072992392;
pub const IO_MUX_GPIO1_REG: u32 = 1072992392;
pub const FUNC_U0TXD_EMAC_RXD2: u32 = 5;
pub const FUNC_U0TXD_GPIO1: u32 = 2;
pub const FUNC_U0TXD_CLK_OUT3: u32 = 1;
pub const FUNC_U0TXD_U0TXD: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO2_U: u32 = 1072992320;
pub const IO_MUX_GPIO2_REG: u32 = 1072992320;
pub const FUNC_GPIO2_SD_DATA0: u32 = 4;
pub const FUNC_GPIO2_HS2_DATA0: u32 = 3;
pub const FUNC_GPIO2_GPIO2: u32 = 2;
pub const FUNC_GPIO2_HSPIWP: u32 = 1;
pub const FUNC_GPIO2_GPIO2_0: u32 = 0;
pub const PERIPHS_IO_MUX_U0RXD_U: u32 = 1072992388;
pub const IO_MUX_GPIO3_REG: u32 = 1072992388;
pub const FUNC_U0RXD_GPIO3: u32 = 2;
pub const FUNC_U0RXD_CLK_OUT2: u32 = 1;
pub const FUNC_U0RXD_U0RXD: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO4_U: u32 = 1072992328;
pub const IO_MUX_GPIO4_REG: u32 = 1072992328;
pub const FUNC_GPIO4_EMAC_TX_ER: u32 = 5;
pub const FUNC_GPIO4_SD_DATA1: u32 = 4;
pub const FUNC_GPIO4_HS2_DATA1: u32 = 3;
pub const FUNC_GPIO4_GPIO4: u32 = 2;
pub const FUNC_GPIO4_HSPIHD: u32 = 1;
pub const FUNC_GPIO4_GPIO4_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO5_U: u32 = 1072992364;
pub const IO_MUX_GPIO5_REG: u32 = 1072992364;
pub const FUNC_GPIO5_EMAC_RX_CLK: u32 = 5;
pub const FUNC_GPIO5_HS1_DATA6: u32 = 3;
pub const FUNC_GPIO5_GPIO5: u32 = 2;
pub const FUNC_GPIO5_VSPICS0: u32 = 1;
pub const FUNC_GPIO5_GPIO5_0: u32 = 0;
pub const PERIPHS_IO_MUX_SD_CLK_U: u32 = 1072992352;
pub const IO_MUX_GPIO6_REG: u32 = 1072992352;
pub const FUNC_SD_CLK_U1CTS: u32 = 4;
pub const FUNC_SD_CLK_HS1_CLK: u32 = 3;
pub const FUNC_SD_CLK_GPIO6: u32 = 2;
pub const FUNC_SD_CLK_SPICLK: u32 = 1;
pub const FUNC_SD_CLK_SD_CLK: u32 = 0;
pub const PERIPHS_IO_MUX_SD_DATA0_U: u32 = 1072992356;
pub const IO_MUX_GPIO7_REG: u32 = 1072992356;
pub const FUNC_SD_DATA0_U2RTS: u32 = 4;
pub const FUNC_SD_DATA0_HS1_DATA0: u32 = 3;
pub const FUNC_SD_DATA0_GPIO7: u32 = 2;
pub const FUNC_SD_DATA0_SPIQ: u32 = 1;
pub const FUNC_SD_DATA0_SD_DATA0: u32 = 0;
pub const PERIPHS_IO_MUX_SD_DATA1_U: u32 = 1072992360;
pub const IO_MUX_GPIO8_REG: u32 = 1072992360;
pub const FUNC_SD_DATA1_U2CTS: u32 = 4;
pub const FUNC_SD_DATA1_HS1_DATA1: u32 = 3;
pub const FUNC_SD_DATA1_GPIO8: u32 = 2;
pub const FUNC_SD_DATA1_SPID: u32 = 1;
pub const FUNC_SD_DATA1_SD_DATA1: u32 = 0;
pub const PERIPHS_IO_MUX_SD_DATA2_U: u32 = 1072992340;
pub const IO_MUX_GPIO9_REG: u32 = 1072992340;
pub const FUNC_SD_DATA2_U1RXD: u32 = 4;
pub const FUNC_SD_DATA2_HS1_DATA2: u32 = 3;
pub const FUNC_SD_DATA2_GPIO9: u32 = 2;
pub const FUNC_SD_DATA2_SPIHD: u32 = 1;
pub const FUNC_SD_DATA2_SD_DATA2: u32 = 0;
pub const PERIPHS_IO_MUX_SD_DATA3_U: u32 = 1072992344;
pub const IO_MUX_GPIO10_REG: u32 = 1072992344;
pub const FUNC_SD_DATA3_U1TXD: u32 = 4;
pub const FUNC_SD_DATA3_HS1_DATA3: u32 = 3;
pub const FUNC_SD_DATA3_GPIO10: u32 = 2;
pub const FUNC_SD_DATA3_SPIWP: u32 = 1;
pub const FUNC_SD_DATA3_SD_DATA3: u32 = 0;
pub const PERIPHS_IO_MUX_SD_CMD_U: u32 = 1072992348;
pub const IO_MUX_GPIO11_REG: u32 = 1072992348;
pub const FUNC_SD_CMD_U1RTS: u32 = 4;
pub const FUNC_SD_CMD_HS1_CMD: u32 = 3;
pub const FUNC_SD_CMD_GPIO11: u32 = 2;
pub const FUNC_SD_CMD_SPICS0: u32 = 1;
pub const FUNC_SD_CMD_SD_CMD: u32 = 0;
pub const PERIPHS_IO_MUX_MTDI_U: u32 = 1072992308;
pub const IO_MUX_GPIO12_REG: u32 = 1072992308;
pub const FUNC_MTDI_EMAC_TXD3: u32 = 5;
pub const FUNC_MTDI_SD_DATA2: u32 = 4;
pub const FUNC_MTDI_HS2_DATA2: u32 = 3;
pub const FUNC_MTDI_GPIO12: u32 = 2;
pub const FUNC_MTDI_HSPIQ: u32 = 1;
pub const FUNC_MTDI_MTDI: u32 = 0;
pub const PERIPHS_IO_MUX_MTCK_U: u32 = 1072992312;
pub const IO_MUX_GPIO13_REG: u32 = 1072992312;
pub const FUNC_MTCK_EMAC_RX_ER: u32 = 5;
pub const FUNC_MTCK_SD_DATA3: u32 = 4;
pub const FUNC_MTCK_HS2_DATA3: u32 = 3;
pub const FUNC_MTCK_GPIO13: u32 = 2;
pub const FUNC_MTCK_HSPID: u32 = 1;
pub const FUNC_MTCK_MTCK: u32 = 0;
pub const PERIPHS_IO_MUX_MTMS_U: u32 = 1072992304;
pub const IO_MUX_GPIO14_REG: u32 = 1072992304;
pub const FUNC_MTMS_EMAC_TXD2: u32 = 5;
pub const FUNC_MTMS_SD_CLK: u32 = 4;
pub const FUNC_MTMS_HS2_CLK: u32 = 3;
pub const FUNC_MTMS_GPIO14: u32 = 2;
pub const FUNC_MTMS_HSPICLK: u32 = 1;
pub const FUNC_MTMS_MTMS: u32 = 0;
pub const PERIPHS_IO_MUX_MTDO_U: u32 = 1072992316;
pub const IO_MUX_GPIO15_REG: u32 = 1072992316;
pub const FUNC_MTDO_EMAC_RXD3: u32 = 5;
pub const FUNC_MTDO_SD_CMD: u32 = 4;
pub const FUNC_MTDO_HS2_CMD: u32 = 3;
pub const FUNC_MTDO_GPIO15: u32 = 2;
pub const FUNC_MTDO_HSPICS0: u32 = 1;
pub const FUNC_MTDO_MTDO: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO16_U: u32 = 1072992332;
pub const IO_MUX_GPIO16_REG: u32 = 1072992332;
pub const FUNC_GPIO16_EMAC_CLK_OUT: u32 = 5;
pub const FUNC_GPIO16_U2RXD: u32 = 4;
pub const FUNC_GPIO16_HS1_DATA4: u32 = 3;
pub const FUNC_GPIO16_GPIO16: u32 = 2;
pub const FUNC_GPIO16_GPIO16_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO17_U: u32 = 1072992336;
pub const IO_MUX_GPIO17_REG: u32 = 1072992336;
pub const FUNC_GPIO17_EMAC_CLK_OUT_180: u32 = 5;
pub const FUNC_GPIO17_U2TXD: u32 = 4;
pub const FUNC_GPIO17_HS1_DATA5: u32 = 3;
pub const FUNC_GPIO17_GPIO17: u32 = 2;
pub const FUNC_GPIO17_GPIO17_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO18_U: u32 = 1072992368;
pub const IO_MUX_GPIO18_REG: u32 = 1072992368;
pub const FUNC_GPIO18_HS1_DATA7: u32 = 3;
pub const FUNC_GPIO18_GPIO18: u32 = 2;
pub const FUNC_GPIO18_VSPICLK: u32 = 1;
pub const FUNC_GPIO18_GPIO18_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO19_U: u32 = 1072992372;
pub const IO_MUX_GPIO19_REG: u32 = 1072992372;
pub const FUNC_GPIO19_EMAC_TXD0: u32 = 5;
pub const FUNC_GPIO19_U0CTS: u32 = 3;
pub const FUNC_GPIO19_GPIO19: u32 = 2;
pub const FUNC_GPIO19_VSPIQ: u32 = 1;
pub const FUNC_GPIO19_GPIO19_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO20_U: u32 = 1072992376;
pub const IO_MUX_GPIO20_REG: u32 = 1072992376;
pub const FUNC_GPIO20_GPIO20: u32 = 2;
pub const FUNC_GPIO20_GPIO20_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO21_U: u32 = 1072992380;
pub const IO_MUX_GPIO21_REG: u32 = 1072992380;
pub const FUNC_GPIO21_EMAC_TX_EN: u32 = 5;
pub const FUNC_GPIO21_GPIO21: u32 = 2;
pub const FUNC_GPIO21_VSPIHD: u32 = 1;
pub const FUNC_GPIO21_GPIO21_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO22_U: u32 = 1072992384;
pub const IO_MUX_GPIO22_REG: u32 = 1072992384;
pub const FUNC_GPIO22_EMAC_TXD1: u32 = 5;
pub const FUNC_GPIO22_U0RTS: u32 = 3;
pub const FUNC_GPIO22_GPIO22: u32 = 2;
pub const FUNC_GPIO22_VSPIWP: u32 = 1;
pub const FUNC_GPIO22_GPIO22_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO23_U: u32 = 1072992396;
pub const IO_MUX_GPIO23_REG: u32 = 1072992396;
pub const FUNC_GPIO23_HS1_STROBE: u32 = 3;
pub const FUNC_GPIO23_GPIO23: u32 = 2;
pub const FUNC_GPIO23_VSPID: u32 = 1;
pub const FUNC_GPIO23_GPIO23_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO24_U: u32 = 1072992400;
pub const IO_MUX_GPIO24_REG: u32 = 1072992400;
pub const FUNC_GPIO24_GPIO24: u32 = 2;
pub const FUNC_GPIO24_GPIO24_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO25_U: u32 = 1072992292;
pub const IO_MUX_GPIO25_REG: u32 = 1072992292;
pub const FUNC_GPIO25_EMAC_RXD0: u32 = 5;
pub const FUNC_GPIO25_GPIO25: u32 = 2;
pub const FUNC_GPIO25_GPIO25_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO26_U: u32 = 1072992296;
pub const IO_MUX_GPIO26_REG: u32 = 1072992296;
pub const FUNC_GPIO26_EMAC_RXD1: u32 = 5;
pub const FUNC_GPIO26_GPIO26: u32 = 2;
pub const FUNC_GPIO26_GPIO26_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO27_U: u32 = 1072992300;
pub const IO_MUX_GPIO27_REG: u32 = 1072992300;
pub const FUNC_GPIO27_EMAC_RX_DV: u32 = 5;
pub const FUNC_GPIO27_GPIO27: u32 = 2;
pub const FUNC_GPIO27_GPIO27_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO32_U: u32 = 1072992284;
pub const IO_MUX_GPIO32_REG: u32 = 1072992284;
pub const FUNC_GPIO32_GPIO32: u32 = 2;
pub const FUNC_GPIO32_GPIO32_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO33_U: u32 = 1072992288;
pub const IO_MUX_GPIO33_REG: u32 = 1072992288;
pub const FUNC_GPIO33_GPIO33: u32 = 2;
pub const FUNC_GPIO33_GPIO33_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO34_U: u32 = 1072992276;
pub const IO_MUX_GPIO34_REG: u32 = 1072992276;
pub const FUNC_GPIO34_GPIO34: u32 = 2;
pub const FUNC_GPIO34_GPIO34_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO35_U: u32 = 1072992280;
pub const IO_MUX_GPIO35_REG: u32 = 1072992280;
pub const FUNC_GPIO35_GPIO35: u32 = 2;
pub const FUNC_GPIO35_GPIO35_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO36_U: u32 = 1072992260;
pub const IO_MUX_GPIO36_REG: u32 = 1072992260;
pub const FUNC_GPIO36_GPIO36: u32 = 2;
pub const FUNC_GPIO36_GPIO36_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO37_U: u32 = 1072992264;
pub const IO_MUX_GPIO37_REG: u32 = 1072992264;
pub const FUNC_GPIO37_GPIO37: u32 = 2;
pub const FUNC_GPIO37_GPIO37_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO38_U: u32 = 1072992268;
pub const IO_MUX_GPIO38_REG: u32 = 1072992268;
pub const FUNC_GPIO38_GPIO38: u32 = 2;
pub const FUNC_GPIO38_GPIO38_0: u32 = 0;
pub const PERIPHS_IO_MUX_GPIO39_U: u32 = 1072992272;
pub const IO_MUX_GPIO39_REG: u32 = 1072992272;
pub const FUNC_GPIO39_GPIO39: u32 = 2;
pub const FUNC_GPIO39_GPIO39_0: u32 = 0;
pub const SPICLK_IN_IDX: u32 = 0;
pub const SPICLK_OUT_IDX: u32 = 0;
pub const SPIQ_IN_IDX: u32 = 1;
pub const SPIQ_OUT_IDX: u32 = 1;
pub const SPID_IN_IDX: u32 = 2;
pub const SPID_OUT_IDX: u32 = 2;
pub const SPIHD_IN_IDX: u32 = 3;
pub const SPIHD_OUT_IDX: u32 = 3;
pub const SPIWP_IN_IDX: u32 = 4;
pub const SPIWP_OUT_IDX: u32 = 4;
pub const SPICS0_IN_IDX: u32 = 5;
pub const SPICS0_OUT_IDX: u32 = 5;
pub const SPICS1_IN_IDX: u32 = 6;
pub const SPICS1_OUT_IDX: u32 = 6;
pub const SPICS2_IN_IDX: u32 = 7;
pub const SPICS2_OUT_IDX: u32 = 7;
pub const HSPICLK_IN_IDX: u32 = 8;
pub const HSPICLK_OUT_IDX: u32 = 8;
pub const HSPIQ_IN_IDX: u32 = 9;
pub const HSPIQ_OUT_IDX: u32 = 9;
pub const HSPID_IN_IDX: u32 = 10;
pub const HSPID_OUT_IDX: u32 = 10;
pub const HSPICS0_IN_IDX: u32 = 11;
pub const HSPICS0_OUT_IDX: u32 = 11;
pub const HSPIHD_IN_IDX: u32 = 12;
pub const HSPIHD_OUT_IDX: u32 = 12;
pub const HSPIWP_IN_IDX: u32 = 13;
pub const HSPIWP_OUT_IDX: u32 = 13;
pub const U0RXD_IN_IDX: u32 = 14;
pub const U0TXD_OUT_IDX: u32 = 14;
pub const U0CTS_IN_IDX: u32 = 15;
pub const U0RTS_OUT_IDX: u32 = 15;
pub const U0DSR_IN_IDX: u32 = 16;
pub const U0DTR_OUT_IDX: u32 = 16;
pub const U1RXD_IN_IDX: u32 = 17;
pub const U1TXD_OUT_IDX: u32 = 17;
pub const U1CTS_IN_IDX: u32 = 18;
pub const U1RTS_OUT_IDX: u32 = 18;
pub const I2CM_SCL_O_IDX: u32 = 19;
pub const I2CM_SDA_I_IDX: u32 = 20;
pub const I2CM_SDA_O_IDX: u32 = 20;
pub const EXT_I2C_SCL_O_IDX: u32 = 21;
pub const EXT_I2C_SDA_O_IDX: u32 = 22;
pub const EXT_I2C_SDA_I_IDX: u32 = 22;
pub const I2S0O_BCK_IN_IDX: u32 = 23;
pub const I2S0O_BCK_OUT_IDX: u32 = 23;
pub const I2S1O_BCK_IN_IDX: u32 = 24;
pub const I2S1O_BCK_OUT_IDX: u32 = 24;
pub const I2S0O_WS_IN_IDX: u32 = 25;
pub const I2S0O_WS_OUT_IDX: u32 = 25;
pub const I2S1O_WS_IN_IDX: u32 = 26;
pub const I2S1O_WS_OUT_IDX: u32 = 26;
pub const I2S0I_BCK_IN_IDX: u32 = 27;
pub const I2S0I_BCK_OUT_IDX: u32 = 27;
pub const I2S0I_WS_IN_IDX: u32 = 28;
pub const I2S0I_WS_OUT_IDX: u32 = 28;
pub const I2CEXT0_SCL_IN_IDX: u32 = 29;
pub const I2CEXT0_SCL_OUT_IDX: u32 = 29;
pub const I2CEXT0_SDA_IN_IDX: u32 = 30;
pub const I2CEXT0_SDA_OUT_IDX: u32 = 30;
pub const PWM0_SYNC0_IN_IDX: u32 = 31;
pub const SDIO_TOHOST_INT_OUT_IDX: u32 = 31;
pub const PWM0_SYNC1_IN_IDX: u32 = 32;
pub const PWM0_OUT0A_IDX: u32 = 32;
pub const PWM0_SYNC2_IN_IDX: u32 = 33;
pub const PWM0_OUT0B_IDX: u32 = 33;
pub const PWM0_F0_IN_IDX: u32 = 34;
pub const PWM0_OUT1A_IDX: u32 = 34;
pub const PWM0_F1_IN_IDX: u32 = 35;
pub const PWM0_OUT1B_IDX: u32 = 35;
pub const PWM0_F2_IN_IDX: u32 = 36;
pub const PWM0_OUT2A_IDX: u32 = 36;
pub const GPIO_BT_ACTIVE_IDX: u32 = 37;
pub const PWM0_OUT2B_IDX: u32 = 37;
pub const GPIO_BT_PRIORITY_IDX: u32 = 38;
pub const PCNT_SIG_CH0_IN0_IDX: u32 = 39;
pub const PCNT_SIG_CH1_IN0_IDX: u32 = 40;
pub const GPIO_WLAN_ACTIVE_IDX: u32 = 40;
pub const PCNT_CTRL_CH0_IN0_IDX: u32 = 41;
pub const BB_DIAG0_IDX: u32 = 41;
pub const PCNT_CTRL_CH1_IN0_IDX: u32 = 42;
pub const BB_DIAG1_IDX: u32 = 42;
pub const PCNT_SIG_CH0_IN1_IDX: u32 = 43;
pub const BB_DIAG2_IDX: u32 = 43;
pub const PCNT_SIG_CH1_IN1_IDX: u32 = 44;
pub const BB_DIAG3_IDX: u32 = 44;
pub const PCNT_CTRL_CH0_IN1_IDX: u32 = 45;
pub const BB_DIAG4_IDX: u32 = 45;
pub const PCNT_CTRL_CH1_IN1_IDX: u32 = 46;
pub const BB_DIAG5_IDX: u32 = 46;
pub const PCNT_SIG_CH0_IN2_IDX: u32 = 47;
pub const BB_DIAG6_IDX: u32 = 47;
pub const PCNT_SIG_CH1_IN2_IDX: u32 = 48;
pub const BB_DIAG7_IDX: u32 = 48;
pub const PCNT_CTRL_CH0_IN2_IDX: u32 = 49;
pub const BB_DIAG8_IDX: u32 = 49;
pub const PCNT_CTRL_CH1_IN2_IDX: u32 = 50;
pub const BB_DIAG9_IDX: u32 = 50;
pub const PCNT_SIG_CH0_IN3_IDX: u32 = 51;
pub const BB_DIAG10_IDX: u32 = 51;
pub const PCNT_SIG_CH1_IN3_IDX: u32 = 52;
pub const BB_DIAG11_IDX: u32 = 52;
pub const PCNT_CTRL_CH0_IN3_IDX: u32 = 53;
pub const BB_DIAG12_IDX: u32 = 53;
pub const PCNT_CTRL_CH1_IN3_IDX: u32 = 54;
pub const BB_DIAG13_IDX: u32 = 54;
pub const PCNT_SIG_CH0_IN4_IDX: u32 = 55;
pub const BB_DIAG14_IDX: u32 = 55;
pub const PCNT_SIG_CH1_IN4_IDX: u32 = 56;
pub const BB_DIAG15_IDX: u32 = 56;
pub const PCNT_CTRL_CH0_IN4_IDX: u32 = 57;
pub const BB_DIAG16_IDX: u32 = 57;
pub const PCNT_CTRL_CH1_IN4_IDX: u32 = 58;
pub const BB_DIAG17_IDX: u32 = 58;
pub const BB_DIAG18_IDX: u32 = 59;
pub const BB_DIAG19_IDX: u32 = 60;
pub const HSPICS1_IN_IDX: u32 = 61;
pub const HSPICS1_OUT_IDX: u32 = 61;
pub const HSPICS2_IN_IDX: u32 = 62;
pub const HSPICS2_OUT_IDX: u32 = 62;
pub const VSPICLK_IN_IDX: u32 = 63;
pub const VSPICLK_OUT_IDX: u32 = 63;
pub const VSPIQ_IN_IDX: u32 = 64;
pub const VSPIQ_OUT_IDX: u32 = 64;
pub const VSPID_IN_IDX: u32 = 65;
pub const VSPID_OUT_IDX: u32 = 65;
pub const VSPIHD_IN_IDX: u32 = 66;
pub const VSPIHD_OUT_IDX: u32 = 66;
pub const VSPIWP_IN_IDX: u32 = 67;
pub const VSPIWP_OUT_IDX: u32 = 67;
pub const VSPICS0_IN_IDX: u32 = 68;
pub const VSPICS0_OUT_IDX: u32 = 68;
pub const VSPICS1_IN_IDX: u32 = 69;
pub const VSPICS1_OUT_IDX: u32 = 69;
pub const VSPICS2_IN_IDX: u32 = 70;
pub const VSPICS2_OUT_IDX: u32 = 70;
pub const PCNT_SIG_CH0_IN5_IDX: u32 = 71;
pub const LEDC_HS_SIG_OUT0_IDX: u32 = 71;
pub const PCNT_SIG_CH1_IN5_IDX: u32 = 72;
pub const LEDC_HS_SIG_OUT1_IDX: u32 = 72;
pub const PCNT_CTRL_CH0_IN5_IDX: u32 = 73;
pub const LEDC_HS_SIG_OUT2_IDX: u32 = 73;
pub const PCNT_CTRL_CH1_IN5_IDX: u32 = 74;
pub const LEDC_HS_SIG_OUT3_IDX: u32 = 74;
pub const PCNT_SIG_CH0_IN6_IDX: u32 = 75;
pub const LEDC_HS_SIG_OUT4_IDX: u32 = 75;
pub const PCNT_SIG_CH1_IN6_IDX: u32 = 76;
pub const LEDC_HS_SIG_OUT5_IDX: u32 = 76;
pub const PCNT_CTRL_CH0_IN6_IDX: u32 = 77;
pub const LEDC_HS_SIG_OUT6_IDX: u32 = 77;
pub const PCNT_CTRL_CH1_IN6_IDX: u32 = 78;
pub const LEDC_HS_SIG_OUT7_IDX: u32 = 78;
pub const PCNT_SIG_CH0_IN7_IDX: u32 = 79;
pub const LEDC_LS_SIG_OUT0_IDX: u32 = 79;
pub const PCNT_SIG_CH1_IN7_IDX: u32 = 80;
pub const LEDC_LS_SIG_OUT1_IDX: u32 = 80;
pub const PCNT_CTRL_CH0_IN7_IDX: u32 = 81;
pub const LEDC_LS_SIG_OUT2_IDX: u32 = 81;
pub const PCNT_CTRL_CH1_IN7_IDX: u32 = 82;
pub const LEDC_LS_SIG_OUT3_IDX: u32 = 82;
pub const RMT_SIG_IN0_IDX: u32 = 83;
pub const LEDC_LS_SIG_OUT4_IDX: u32 = 83;
pub const RMT_SIG_IN1_IDX: u32 = 84;
pub const LEDC_LS_SIG_OUT5_IDX: u32 = 84;
pub const RMT_SIG_IN2_IDX: u32 = 85;
pub const LEDC_LS_SIG_OUT6_IDX: u32 = 85;
pub const RMT_SIG_IN3_IDX: u32 = 86;
pub const LEDC_LS_SIG_OUT7_IDX: u32 = 86;
pub const RMT_SIG_IN4_IDX: u32 = 87;
pub const RMT_SIG_OUT0_IDX: u32 = 87;
pub const RMT_SIG_IN5_IDX: u32 = 88;
pub const RMT_SIG_OUT1_IDX: u32 = 88;
pub const RMT_SIG_IN6_IDX: u32 = 89;
pub const RMT_SIG_OUT2_IDX: u32 = 89;
pub const RMT_SIG_IN7_IDX: u32 = 90;
pub const RMT_SIG_OUT3_IDX: u32 = 90;
pub const RMT_SIG_OUT4_IDX: u32 = 91;
pub const RMT_SIG_OUT5_IDX: u32 = 92;
pub const EXT_ADC_START_IDX: u32 = 93;
pub const RMT_SIG_OUT6_IDX: u32 = 93;
pub const CAN_RX_IDX: u32 = 94;
pub const RMT_SIG_OUT7_IDX: u32 = 94;
pub const I2CEXT1_SCL_IN_IDX: u32 = 95;
pub const I2CEXT1_SCL_OUT_IDX: u32 = 95;
pub const I2CEXT1_SDA_IN_IDX: u32 = 96;
pub const I2CEXT1_SDA_OUT_IDX: u32 = 96;
pub const HOST_CARD_DETECT_N_1_IDX: u32 = 97;
pub const HOST_CCMD_OD_PULLUP_EN_N_IDX: u32 = 97;
pub const HOST_CARD_DETECT_N_2_IDX: u32 = 98;
pub const HOST_RST_N_1_IDX: u32 = 98;
pub const HOST_CARD_WRITE_PRT_1_IDX: u32 = 99;
pub const HOST_RST_N_2_IDX: u32 = 99;
pub const HOST_CARD_WRITE_PRT_2_IDX: u32 = 100;
pub const GPIO_SD0_OUT_IDX: u32 = 100;
pub const HOST_CARD_INT_N_1_IDX: u32 = 101;
pub const GPIO_SD1_OUT_IDX: u32 = 101;
pub const HOST_CARD_INT_N_2_IDX: u32 = 102;
pub const GPIO_SD2_OUT_IDX: u32 = 102;
pub const PWM1_SYNC0_IN_IDX: u32 = 103;
pub const GPIO_SD3_OUT_IDX: u32 = 103;
pub const PWM1_SYNC1_IN_IDX: u32 = 104;
pub const GPIO_SD4_OUT_IDX: u32 = 104;
pub const PWM1_SYNC2_IN_IDX: u32 = 105;
pub const GPIO_SD5_OUT_IDX: u32 = 105;
pub const PWM1_F0_IN_IDX: u32 = 106;
pub const GPIO_SD6_OUT_IDX: u32 = 106;
pub const PWM1_F1_IN_IDX: u32 = 107;
pub const GPIO_SD7_OUT_IDX: u32 = 107;
pub const PWM1_F2_IN_IDX: u32 = 108;
pub const PWM1_OUT0A_IDX: u32 = 108;
pub const PWM0_CAP0_IN_IDX: u32 = 109;
pub const PWM1_OUT0B_IDX: u32 = 109;
pub const PWM0_CAP1_IN_IDX: u32 = 110;
pub const PWM1_OUT1A_IDX: u32 = 110;
pub const PWM0_CAP2_IN_IDX: u32 = 111;
pub const PWM1_OUT1B_IDX: u32 = 111;
pub const PWM1_CAP0_IN_IDX: u32 = 112;
pub const PWM1_OUT2A_IDX: u32 = 112;
pub const PWM1_CAP1_IN_IDX: u32 = 113;
pub const PWM1_OUT2B_IDX: u32 = 113;
pub const PWM1_CAP2_IN_IDX: u32 = 114;
pub const PWM2_OUT1H_IDX: u32 = 114;
pub const PWM2_FLTA_IDX: u32 = 115;
pub const PWM2_OUT1L_IDX: u32 = 115;
pub const PWM2_FLTB_IDX: u32 = 116;
pub const PWM2_OUT2H_IDX: u32 = 116;
pub const PWM2_CAP1_IN_IDX: u32 = 117;
pub const PWM2_OUT2L_IDX: u32 = 117;
pub const PWM2_CAP2_IN_IDX: u32 = 118;
pub const PWM2_OUT3H_IDX: u32 = 118;
pub const PWM2_CAP3_IN_IDX: u32 = 119;
pub const PWM2_OUT3L_IDX: u32 = 119;
pub const PWM3_FLTA_IDX: u32 = 120;
pub const PWM2_OUT4H_IDX: u32 = 120;
pub const PWM3_FLTB_IDX: u32 = 121;
pub const PWM2_OUT4L_IDX: u32 = 121;
pub const PWM3_CAP1_IN_IDX: u32 = 122;
pub const PWM3_CAP2_IN_IDX: u32 = 123;
pub const CAN_TX_IDX: u32 = 123;
pub const PWM3_CAP3_IN_IDX: u32 = 124;
pub const CAN_BUS_OFF_ON_IDX: u32 = 124;
pub const CAN_CLKOUT_IDX: u32 = 125;
pub const SPID4_IN_IDX: u32 = 128;
pub const SPID4_OUT_IDX: u32 = 128;
pub const SPID5_IN_IDX: u32 = 129;
pub const SPID5_OUT_IDX: u32 = 129;
pub const SPID6_IN_IDX: u32 = 130;
pub const SPID6_OUT_IDX: u32 = 130;
pub const SPID7_IN_IDX: u32 = 131;
pub const SPID7_OUT_IDX: u32 = 131;
pub const HSPID4_IN_IDX: u32 = 132;
pub const HSPID4_OUT_IDX: u32 = 132;
pub const HSPID5_IN_IDX: u32 = 133;
pub const HSPID5_OUT_IDX: u32 = 133;
pub const HSPID6_IN_IDX: u32 = 134;
pub const HSPID6_OUT_IDX: u32 = 134;
pub const HSPID7_IN_IDX: u32 = 135;
pub const HSPID7_OUT_IDX: u32 = 135;
pub const VSPID4_IN_IDX: u32 = 136;
pub const VSPID4_OUT_IDX: u32 = 136;
pub const VSPID5_IN_IDX: u32 = 137;
pub const VSPID5_OUT_IDX: u32 = 137;
pub const VSPID6_IN_IDX: u32 = 138;
pub const VSPID6_OUT_IDX: u32 = 138;
pub const VSPID7_IN_IDX: u32 = 139;
pub const VSPID7_OUT_IDX: u32 = 139;
pub const I2S0I_DATA_IN0_IDX: u32 = 140;
pub const I2S0O_DATA_OUT0_IDX: u32 = 140;
pub const I2S0I_DATA_IN1_IDX: u32 = 141;
pub const I2S0O_DATA_OUT1_IDX: u32 = 141;
pub const I2S0I_DATA_IN2_IDX: u32 = 142;
pub const I2S0O_DATA_OUT2_IDX: u32 = 142;
pub const I2S0I_DATA_IN3_IDX: u32 = 143;
pub const I2S0O_DATA_OUT3_IDX: u32 = 143;
pub const I2S0I_DATA_IN4_IDX: u32 = 144;
pub const I2S0O_DATA_OUT4_IDX: u32 = 144;
pub const I2S0I_DATA_IN5_IDX: u32 = 145;
pub const I2S0O_DATA_OUT5_IDX: u32 = 145;
pub const I2S0I_DATA_IN6_IDX: u32 = 146;
pub const I2S0O_DATA_OUT6_IDX: u32 = 146;
pub const I2S0I_DATA_IN7_IDX: u32 = 147;
pub const I2S0O_DATA_OUT7_IDX: u32 = 147;
pub const I2S0I_DATA_IN8_IDX: u32 = 148;
pub const I2S0O_DATA_OUT8_IDX: u32 = 148;
pub const I2S0I_DATA_IN9_IDX: u32 = 149;
pub const I2S0O_DATA_OUT9_IDX: u32 = 149;
pub const I2S0I_DATA_IN10_IDX: u32 = 150;
pub const I2S0O_DATA_OUT10_IDX: u32 = 150;
pub const I2S0I_DATA_IN11_IDX: u32 = 151;
pub const I2S0O_DATA_OUT11_IDX: u32 = 151;
pub const I2S0I_DATA_IN12_IDX: u32 = 152;
pub const I2S0O_DATA_OUT12_IDX: u32 = 152;
pub const I2S0I_DATA_IN13_IDX: u32 = 153;
pub const I2S0O_DATA_OUT13_IDX: u32 = 153;
pub const I2S0I_DATA_IN14_IDX: u32 = 154;
pub const I2S0O_DATA_OUT14_IDX: u32 = 154;
pub const I2S0I_DATA_IN15_IDX: u32 = 155;
pub const I2S0O_DATA_OUT15_IDX: u32 = 155;
pub const I2S0O_DATA_OUT16_IDX: u32 = 156;
pub const I2S0O_DATA_OUT17_IDX: u32 = 157;
pub const I2S0O_DATA_OUT18_IDX: u32 = 158;
pub const I2S0O_DATA_OUT19_IDX: u32 = 159;
pub const I2S0O_DATA_OUT20_IDX: u32 = 160;
pub const I2S0O_DATA_OUT21_IDX: u32 = 161;
pub const I2S0O_DATA_OUT22_IDX: u32 = 162;
pub const I2S0O_DATA_OUT23_IDX: u32 = 163;
pub const I2S1I_BCK_IN_IDX: u32 = 164;
pub const I2S1I_BCK_OUT_IDX: u32 = 164;
pub const I2S1I_WS_IN_IDX: u32 = 165;
pub const I2S1I_WS_OUT_IDX: u32 = 165;
pub const I2S1I_DATA_IN0_IDX: u32 = 166;
pub const I2S1O_DATA_OUT0_IDX: u32 = 166;
pub const I2S1I_DATA_IN1_IDX: u32 = 167;
pub const I2S1O_DATA_OUT1_IDX: u32 = 167;
pub const I2S1I_DATA_IN2_IDX: u32 = 168;
pub const I2S1O_DATA_OUT2_IDX: u32 = 168;
pub const I2S1I_DATA_IN3_IDX: u32 = 169;
pub const I2S1O_DATA_OUT3_IDX: u32 = 169;
pub const I2S1I_DATA_IN4_IDX: u32 = 170;
pub const I2S1O_DATA_OUT4_IDX: u32 = 170;
pub const I2S1I_DATA_IN5_IDX: u32 = 171;
pub const I2S1O_DATA_OUT5_IDX: u32 = 171;
pub const I2S1I_DATA_IN6_IDX: u32 = 172;
pub const I2S1O_DATA_OUT6_IDX: u32 = 172;
pub const I2S1I_DATA_IN7_IDX: u32 = 173;
pub const I2S1O_DATA_OUT7_IDX: u32 = 173;
pub const I2S1I_DATA_IN8_IDX: u32 = 174;
pub const I2S1O_DATA_OUT8_IDX: u32 = 174;
pub const I2S1I_DATA_IN9_IDX: u32 = 175;
pub const I2S1O_DATA_OUT9_IDX: u32 = 175;
pub const I2S1I_DATA_IN10_IDX: u32 = 176;
pub const I2S1O_DATA_OUT10_IDX: u32 = 176;
pub const I2S1I_DATA_IN11_IDX: u32 = 177;
pub const I2S1O_DATA_OUT11_IDX: u32 = 177;
pub const I2S1I_DATA_IN12_IDX: u32 = 178;
pub const I2S1O_DATA_OUT12_IDX: u32 = 178;
pub const I2S1I_DATA_IN13_IDX: u32 = 179;
pub const I2S1O_DATA_OUT13_IDX: u32 = 179;
pub const I2S1I_DATA_IN14_IDX: u32 = 180;
pub const I2S1O_DATA_OUT14_IDX: u32 = 180;
pub const I2S1I_DATA_IN15_IDX: u32 = 181;
pub const I2S1O_DATA_OUT15_IDX: u32 = 181;
pub const I2S1O_DATA_OUT16_IDX: u32 = 182;
pub const I2S1O_DATA_OUT17_IDX: u32 = 183;
pub const I2S1O_DATA_OUT18_IDX: u32 = 184;
pub const I2S1O_DATA_OUT19_IDX: u32 = 185;
pub const I2S1O_DATA_OUT20_IDX: u32 = 186;
pub const I2S1O_DATA_OUT21_IDX: u32 = 187;
pub const I2S1O_DATA_OUT22_IDX: u32 = 188;
pub const I2S1O_DATA_OUT23_IDX: u32 = 189;
pub const I2S0I_H_SYNC_IDX: u32 = 190;
pub const PWM3_OUT1H_IDX: u32 = 190;
pub const I2S0I_V_SYNC_IDX: u32 = 191;
pub const PWM3_OUT1L_IDX: u32 = 191;
pub const I2S0I_H_ENABLE_IDX: u32 = 192;
pub const PWM3_OUT2H_IDX: u32 = 192;
pub const I2S1I_H_SYNC_IDX: u32 = 193;
pub const PWM3_OUT2L_IDX: u32 = 193;
pub const I2S1I_V_SYNC_IDX: u32 = 194;
pub const PWM3_OUT3H_IDX: u32 = 194;
pub const I2S1I_H_ENABLE_IDX: u32 = 195;
pub const PWM3_OUT3L_IDX: u32 = 195;
pub const PWM3_OUT4H_IDX: u32 = 196;
pub const PWM3_OUT4L_IDX: u32 = 197;
pub const U2RXD_IN_IDX: u32 = 198;
pub const U2TXD_OUT_IDX: u32 = 198;
pub const U2CTS_IN_IDX: u32 = 199;
pub const U2RTS_OUT_IDX: u32 = 199;
pub const EMAC_MDC_I_IDX: u32 = 200;
pub const EMAC_MDC_O_IDX: u32 = 200;
pub const EMAC_MDI_I_IDX: u32 = 201;
pub const EMAC_MDO_O_IDX: u32 = 201;
pub const EMAC_CRS_I_IDX: u32 = 202;
pub const EMAC_CRS_O_IDX: u32 = 202;
pub const EMAC_COL_I_IDX: u32 = 203;
pub const EMAC_COL_O_IDX: u32 = 203;
pub const PCMFSYNC_IN_IDX: u32 = 204;
pub const BT_AUDIO0_IRQ_IDX: u32 = 204;
pub const PCMCLK_IN_IDX: u32 = 205;
pub const BT_AUDIO1_IRQ_IDX: u32 = 205;
pub const PCMDIN_IDX: u32 = 206;
pub const BT_AUDIO2_IRQ_IDX: u32 = 206;
pub const BLE_AUDIO0_IRQ_IDX: u32 = 207;
pub const BLE_AUDIO1_IRQ_IDX: u32 = 208;
pub const BLE_AUDIO2_IRQ_IDX: u32 = 209;
pub const PCMFSYNC_OUT_IDX: u32 = 210;
pub const PCMCLK_OUT_IDX: u32 = 211;
pub const PCMDOUT_IDX: u32 = 212;
pub const BLE_AUDIO_SYNC0_P_IDX: u32 = 213;
pub const BLE_AUDIO_SYNC1_P_IDX: u32 = 214;
pub const BLE_AUDIO_SYNC2_P_IDX: u32 = 215;
pub const ANT_SEL0_IDX: u32 = 216;
pub const ANT_SEL1_IDX: u32 = 217;
pub const ANT_SEL2_IDX: u32 = 218;
pub const ANT_SEL3_IDX: u32 = 219;
pub const ANT_SEL4_IDX: u32 = 220;
pub const ANT_SEL5_IDX: u32 = 221;
pub const ANT_SEL6_IDX: u32 = 222;
pub const ANT_SEL7_IDX: u32 = 223;
pub const SIG_IN_FUNC224_IDX: u32 = 224;
pub const SIG_IN_FUNC225_IDX: u32 = 225;
pub const SIG_IN_FUNC226_IDX: u32 = 226;
pub const SIG_IN_FUNC227_IDX: u32 = 227;
pub const SIG_IN_FUNC228_IDX: u32 = 228;
pub const SIG_GPIO_OUT_IDX: u32 = 256;
pub const GPIO_PIN_COUNT: u32 = 40;
pub const GPIO_ID_PIN0: u32 = 0;
pub const GPIO_FUNC_IN_HIGH: u32 = 56;
pub const GPIO_FUNC_IN_LOW: u32 = 48;
pub const ESP_INTR_FLAG_LEVEL1: u32 = 2;
pub const ESP_INTR_FLAG_LEVEL2: u32 = 4;
pub const ESP_INTR_FLAG_LEVEL3: u32 = 8;
pub const ESP_INTR_FLAG_LEVEL4: u32 = 16;
pub const ESP_INTR_FLAG_LEVEL5: u32 = 32;
pub const ESP_INTR_FLAG_LEVEL6: u32 = 64;
pub const ESP_INTR_FLAG_NMI: u32 = 128;
pub const ESP_INTR_FLAG_SHARED: u32 = 256;
pub const ESP_INTR_FLAG_EDGE: u32 = 512;
pub const ESP_INTR_FLAG_IRAM: u32 = 1024;
pub const ESP_INTR_FLAG_INTRDISABLED: u32 = 2048;
pub const ESP_INTR_FLAG_LOWMED: u32 = 14;
pub const ESP_INTR_FLAG_HIGH: u32 = 240;
pub const ESP_INTR_FLAG_LEVELMASK: u32 = 254;
pub const ETS_INTERNAL_TIMER0_INTR_SOURCE: i32 = -1;
pub const ETS_INTERNAL_TIMER1_INTR_SOURCE: i32 = -2;
pub const ETS_INTERNAL_TIMER2_INTR_SOURCE: i32 = -3;
pub const ETS_INTERNAL_SW0_INTR_SOURCE: i32 = -4;
pub const ETS_INTERNAL_SW1_INTR_SOURCE: i32 = -5;
pub const ETS_INTERNAL_PROFILING_INTR_SOURCE: i32 = -6;
pub const ETS_INTERNAL_INTR_SOURCE_OFF: u32 = 6;
pub const GPIO_PIN_REG_0: u32 = 1072992324;
pub const GPIO_PIN_REG_1: u32 = 1072992392;
pub const GPIO_PIN_REG_2: u32 = 1072992320;
pub const GPIO_PIN_REG_3: u32 = 1072992388;
pub const GPIO_PIN_REG_4: u32 = 1072992328;
pub const GPIO_PIN_REG_5: u32 = 1072992364;
pub const GPIO_PIN_REG_6: u32 = 1072992352;
pub const GPIO_PIN_REG_7: u32 = 1072992356;
pub const GPIO_PIN_REG_8: u32 = 1072992360;
pub const GPIO_PIN_REG_9: u32 = 1072992340;
pub const GPIO_PIN_REG_10: u32 = 1072992344;
pub const GPIO_PIN_REG_11: u32 = 1072992348;
pub const GPIO_PIN_REG_12: u32 = 1072992308;
pub const GPIO_PIN_REG_13: u32 = 1072992312;
pub const GPIO_PIN_REG_14: u32 = 1072992304;
pub const GPIO_PIN_REG_15: u32 = 1072992316;
pub const GPIO_PIN_REG_16: u32 = 1072992332;
pub const GPIO_PIN_REG_17: u32 = 1072992336;
pub const GPIO_PIN_REG_18: u32 = 1072992368;
pub const GPIO_PIN_REG_19: u32 = 1072992372;
pub const GPIO_PIN_REG_20: u32 = 1072992376;
pub const GPIO_PIN_REG_21: u32 = 1072992380;
pub const GPIO_PIN_REG_22: u32 = 1072992384;
pub const GPIO_PIN_REG_23: u32 = 1072992396;
pub const GPIO_PIN_REG_25: u32 = 1072992292;
pub const GPIO_PIN_REG_26: u32 = 1072992296;
pub const GPIO_PIN_REG_27: u32 = 1072992300;
pub const GPIO_PIN_REG_32: u32 = 1072992284;
pub const GPIO_PIN_REG_33: u32 = 1072992288;
pub const GPIO_PIN_REG_34: u32 = 1072992276;
pub const GPIO_PIN_REG_35: u32 = 1072992280;
pub const GPIO_PIN_REG_36: u32 = 1072992260;
pub const GPIO_PIN_REG_37: u32 = 1072992264;
pub const GPIO_PIN_REG_38: u32 = 1072992268;
pub const GPIO_PIN_REG_39: u32 = 1072992272;
pub const GPIO_MODE_DEF_DISABLE: u32 = 0;
pub const GPIO_MODE_DEF_INPUT: u32 = 1;
pub const GPIO_MODE_DEF_OUTPUT: u32 = 2;
pub const GPIO_MODE_DEF_OD: u32 = 4;
pub const TOUCH_PAD_NUM0_GPIO_NUM: u32 = 4;
pub const TOUCH_PAD_NUM1_GPIO_NUM: u32 = 0;
pub const TOUCH_PAD_NUM2_GPIO_NUM: u32 = 2;
pub const TOUCH_PAD_NUM3_GPIO_NUM: u32 = 15;
pub const TOUCH_PAD_NUM4_GPIO_NUM: u32 = 13;
pub const TOUCH_PAD_NUM5_GPIO_NUM: u32 = 12;
pub const TOUCH_PAD_NUM6_GPIO_NUM: u32 = 14;
pub const TOUCH_PAD_NUM7_GPIO_NUM: u32 = 27;
pub const TOUCH_PAD_NUM8_GPIO_NUM: u32 = 33;
pub const TOUCH_PAD_NUM9_GPIO_NUM: u32 = 32;
pub const TOUCH_PAD_SLEEP_CYCLE_DEFAULT: u32 = 4096;
pub const TOUCH_PAD_MEASURE_CYCLE_DEFAULT: u32 = 32767;
pub const TOUCH_PAD_MEASURE_WAIT_DEFAULT: u32 = 255;
pub const TOUCH_PAD_BIT_MASK_MAX: u32 = 1023;
pub const TWO_UNIVERSAL_MAC_ADDR: u32 = 2;
pub const FOUR_UNIVERSAL_MAC_ADDR: u32 = 4;
pub const UNIVERSAL_MAC_ADDR_NUM: u32 = 4;
pub const INCLUDE_xTimerGetTimerDaemonTaskHandle: u32 = 0;
pub const INCLUDE_xQueueGetMutexHolder: u32 = 0;
pub const configUSE_APPLICATION_TASK_TAG: u32 = 0;
pub const configUSE_ALTERNATIVE_API: u32 = 0;
pub const INCLUDE_xTaskResumeFromISR: u32 = 1;
pub const INCLUDE_xEventGroupSetBitFromISR: u32 = 0;
pub const configASSERT_DEFINED: u32 = 1;
pub const INCLUDE_xTaskGetSchedulerState: u32 = 0;
pub const INCLUDE_xTaskGetCurrentTaskHandle: u32 = 0;
pub const configGENERATE_RUN_TIME_STATS: u32 = 0;
pub const configUSE_MALLOC_FAILED_HOOK: u32 = 0;
pub const configEXPECTED_IDLE_TIME_BEFORE_SLEEP: u32 = 2;
pub const configUSE_TIME_SLICING: u32 = 1;
pub const configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS: u32 = 0;
pub const configUSE_STATS_FORMATTING_FUNCTIONS: u32 = 0;
pub const configTASKLIST_INCLUDE_COREID: u32 = 0;
pub const configUSE_TRACE_FACILITY: u32 = 0;
pub const configUSE_PORT_OPTIMISED_TASK_SELECTION: u32 = 0;
pub const configUSE_TASK_NOTIFICATIONS: u32 = 1;
pub const portTICK_TYPE_IS_ATOMIC: u32 = 0;
pub const configENABLE_BACKWARD_COMPATIBILITY: u32 = 1;
pub const configESP32_PER_TASK_DATA: u32 = 1;
pub const _LIBC_LIMITS_H_: u32 = 1;
pub const MB_LEN_MAX: u32 = 1;
pub const NL_ARGMAX: u32 = 32;
pub const _POSIX2_RE_DUP_MAX: u32 = 255;
pub const ARG_MAX: u32 = 4096;
pub const PATH_MAX: u32 = 4096;
pub const tskKERNEL_VERSION_NUMBER: &'static [u8; 7usize] = b"V8.2.0\0";
pub const tskKERNEL_VERSION_MAJOR: u32 = 8;
pub const tskKERNEL_VERSION_MINOR: u32 = 2;
pub const tskKERNEL_VERSION_BUILD: u32 = 0;
pub const ADC1_CHANNEL_0_GPIO_NUM: u32 = 36;
pub const ADC1_CHANNEL_1_GPIO_NUM: u32 = 37;
pub const ADC1_CHANNEL_2_GPIO_NUM: u32 = 38;
pub const ADC1_CHANNEL_3_GPIO_NUM: u32 = 39;
pub const ADC1_CHANNEL_4_GPIO_NUM: u32 = 32;
pub const ADC1_CHANNEL_5_GPIO_NUM: u32 = 33;
pub const ADC1_CHANNEL_6_GPIO_NUM: u32 = 34;
pub const ADC1_CHANNEL_7_GPIO_NUM: u32 = 35;
pub const ADC2_CHANNEL_0_GPIO_NUM: u32 = 4;
pub const ADC2_CHANNEL_1_GPIO_NUM: u32 = 0;
pub const ADC2_CHANNEL_2_GPIO_NUM: u32 = 2;
pub const ADC2_CHANNEL_3_GPIO_NUM: u32 = 15;
pub const ADC2_CHANNEL_4_GPIO_NUM: u32 = 13;
pub const ADC2_CHANNEL_5_GPIO_NUM: u32 = 12;
pub const ADC2_CHANNEL_6_GPIO_NUM: u32 = 14;
pub const ADC2_CHANNEL_7_GPIO_NUM: u32 = 27;
pub const ADC2_CHANNEL_8_GPIO_NUM: u32 = 25;
pub const ADC2_CHANNEL_9_GPIO_NUM: u32 = 26;
pub const CAN_ALERT_TX_IDLE: u32 = 1;
pub const CAN_ALERT_TX_SUCCESS: u32 = 2;
pub const CAN_ALERT_BELOW_ERR_WARN: u32 = 4;
pub const CAN_ALERT_ERR_ACTIVE: u32 = 8;
pub const CAN_ALERT_RECOVERY_IN_PROGRESS: u32 = 16;
pub const CAN_ALERT_BUS_RECOVERED: u32 = 32;
pub const CAN_ALERT_ARB_LOST: u32 = 64;
pub const CAN_ALERT_ABOVE_ERR_WARN: u32 = 128;
pub const CAN_ALERT_BUS_ERROR: u32 = 256;
pub const CAN_ALERT_TX_FAILED: u32 = 512;
pub const CAN_ALERT_RX_QUEUE_FULL: u32 = 1024;
pub const CAN_ALERT_ERR_PASS: u32 = 2048;
pub const CAN_ALERT_BUS_OFF: u32 = 4096;
pub const CAN_ALERT_ALL: u32 = 8191;
pub const CAN_ALERT_NONE: u32 = 0;
pub const CAN_ALERT_AND_LOG: u32 = 8192;
pub const CAN_MSG_FLAG_NONE: u32 = 0;
pub const CAN_MSG_FLAG_EXTD: u32 = 1;
pub const CAN_MSG_FLAG_RTR: u32 = 2;
pub const CAN_MSG_FLAG_SS: u32 = 4;
pub const CAN_MSG_FLAG_SELF: u32 = 8;
pub const CAN_MSG_FLAG_DLC_NON_COMP: u32 = 16;
pub const CAN_EXTD_ID_MASK: u32 = 536870911;
pub const CAN_STD_ID_MASK: u32 = 2047;
pub const CAN_MAX_DATA_LEN: u32 = 8;
pub const CAN_IO_UNUSED: i32 = -1;
pub const DAC_CHANNEL_1_GPIO_NUM: u32 = 25;
pub const DAC_CHANNEL_2_GPIO_NUM: u32 = 26;
pub const I2C_APB_CLK_FREQ: u32 = 80000000;
pub const I2C_FIFO_LEN: u32 = 32;
pub const I2S_SIG_LOOPBACK_V: u32 = 1;
pub const I2S_SIG_LOOPBACK_S: u32 = 18;
pub const I2S_RX_MSB_RIGHT_V: u32 = 1;
pub const I2S_RX_MSB_RIGHT_S: u32 = 17;
pub const I2S_TX_MSB_RIGHT_V: u32 = 1;
pub const I2S_TX_MSB_RIGHT_S: u32 = 16;
pub const I2S_RX_MONO_V: u32 = 1;
pub const I2S_RX_MONO_S: u32 = 15;
pub const I2S_TX_MONO_V: u32 = 1;
pub const I2S_TX_MONO_S: u32 = 14;
pub const I2S_RX_SHORT_SYNC_V: u32 = 1;
pub const I2S_RX_SHORT_SYNC_S: u32 = 13;
pub const I2S_TX_SHORT_SYNC_V: u32 = 1;
pub const I2S_TX_SHORT_SYNC_S: u32 = 12;
pub const I2S_RX_MSB_SHIFT_V: u32 = 1;
pub const I2S_RX_MSB_SHIFT_S: u32 = 11;
pub const I2S_TX_MSB_SHIFT_V: u32 = 1;
pub const I2S_TX_MSB_SHIFT_S: u32 = 10;
pub const I2S_RX_RIGHT_FIRST_V: u32 = 1;
pub const I2S_RX_RIGHT_FIRST_S: u32 = 9;
pub const I2S_TX_RIGHT_FIRST_V: u32 = 1;
pub const I2S_TX_RIGHT_FIRST_S: u32 = 8;
pub const I2S_RX_SLAVE_MOD_V: u32 = 1;
pub const I2S_RX_SLAVE_MOD_S: u32 = 7;
pub const I2S_TX_SLAVE_MOD_V: u32 = 1;
pub const I2S_TX_SLAVE_MOD_S: u32 = 6;
pub const I2S_RX_START_V: u32 = 1;
pub const I2S_RX_START_S: u32 = 5;
pub const I2S_TX_START_V: u32 = 1;
pub const I2S_TX_START_S: u32 = 4;
pub const I2S_RX_FIFO_RESET_V: u32 = 1;
pub const I2S_RX_FIFO_RESET_S: u32 = 3;
pub const I2S_TX_FIFO_RESET_V: u32 = 1;
pub const I2S_TX_FIFO_RESET_S: u32 = 2;
pub const I2S_RX_RESET_V: u32 = 1;
pub const I2S_RX_RESET_S: u32 = 1;
pub const I2S_TX_RESET_V: u32 = 1;
pub const I2S_TX_RESET_S: u32 = 0;
pub const I2S_OUT_TOTAL_EOF_INT_RAW_V: u32 = 1;
pub const I2S_OUT_TOTAL_EOF_INT_RAW_S: u32 = 16;
pub const I2S_IN_DSCR_EMPTY_INT_RAW_V: u32 = 1;
pub const I2S_IN_DSCR_EMPTY_INT_RAW_S: u32 = 15;
pub const I2S_OUT_DSCR_ERR_INT_RAW_V: u32 = 1;
pub const I2S_OUT_DSCR_ERR_INT_RAW_S: u32 = 14;
pub const I2S_IN_DSCR_ERR_INT_RAW_V: u32 = 1;
pub const I2S_IN_DSCR_ERR_INT_RAW_S: u32 = 13;
pub const I2S_OUT_EOF_INT_RAW_V: u32 = 1;
pub const I2S_OUT_EOF_INT_RAW_S: u32 = 12;
pub const I2S_OUT_DONE_INT_RAW_V: u32 = 1;
pub const I2S_OUT_DONE_INT_RAW_S: u32 = 11;
pub const I2S_IN_ERR_EOF_INT_RAW_V: u32 = 1;
pub const I2S_IN_ERR_EOF_INT_RAW_S: u32 = 10;
pub const I2S_IN_SUC_EOF_INT_RAW_V: u32 = 1;
pub const I2S_IN_SUC_EOF_INT_RAW_S: u32 = 9;
pub const I2S_IN_DONE_INT_RAW_V: u32 = 1;
pub const I2S_IN_DONE_INT_RAW_S: u32 = 8;
pub const I2S_TX_HUNG_INT_RAW_V: u32 = 1;
pub const I2S_TX_HUNG_INT_RAW_S: u32 = 7;
pub const I2S_RX_HUNG_INT_RAW_V: u32 = 1;
pub const I2S_RX_HUNG_INT_RAW_S: u32 = 6;
pub const I2S_TX_REMPTY_INT_RAW_V: u32 = 1;
pub const I2S_TX_REMPTY_INT_RAW_S: u32 = 5;
pub const I2S_TX_WFULL_INT_RAW_V: u32 = 1;
pub const I2S_TX_WFULL_INT_RAW_S: u32 = 4;
pub const I2S_RX_REMPTY_INT_RAW_V: u32 = 1;
pub const I2S_RX_REMPTY_INT_RAW_S: u32 = 3;
pub const I2S_RX_WFULL_INT_RAW_V: u32 = 1;
pub const I2S_RX_WFULL_INT_RAW_S: u32 = 2;
pub const I2S_TX_PUT_DATA_INT_RAW_V: u32 = 1;
pub const I2S_TX_PUT_DATA_INT_RAW_S: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_RAW_V: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_RAW_S: u32 = 0;
pub const I2S_OUT_TOTAL_EOF_INT_ST_V: u32 = 1;
pub const I2S_OUT_TOTAL_EOF_INT_ST_S: u32 = 16;
pub const I2S_IN_DSCR_EMPTY_INT_ST_V: u32 = 1;
pub const I2S_IN_DSCR_EMPTY_INT_ST_S: u32 = 15;
pub const I2S_OUT_DSCR_ERR_INT_ST_V: u32 = 1;
pub const I2S_OUT_DSCR_ERR_INT_ST_S: u32 = 14;
pub const I2S_IN_DSCR_ERR_INT_ST_V: u32 = 1;
pub const I2S_IN_DSCR_ERR_INT_ST_S: u32 = 13;
pub const I2S_OUT_EOF_INT_ST_V: u32 = 1;
pub const I2S_OUT_EOF_INT_ST_S: u32 = 12;
pub const I2S_OUT_DONE_INT_ST_V: u32 = 1;
pub const I2S_OUT_DONE_INT_ST_S: u32 = 11;
pub const I2S_IN_ERR_EOF_INT_ST_V: u32 = 1;
pub const I2S_IN_ERR_EOF_INT_ST_S: u32 = 10;
pub const I2S_IN_SUC_EOF_INT_ST_V: u32 = 1;
pub const I2S_IN_SUC_EOF_INT_ST_S: u32 = 9;
pub const I2S_IN_DONE_INT_ST_V: u32 = 1;
pub const I2S_IN_DONE_INT_ST_S: u32 = 8;
pub const I2S_TX_HUNG_INT_ST_V: u32 = 1;
pub const I2S_TX_HUNG_INT_ST_S: u32 = 7;
pub const I2S_RX_HUNG_INT_ST_V: u32 = 1;
pub const I2S_RX_HUNG_INT_ST_S: u32 = 6;
pub const I2S_TX_REMPTY_INT_ST_V: u32 = 1;
pub const I2S_TX_REMPTY_INT_ST_S: u32 = 5;
pub const I2S_TX_WFULL_INT_ST_V: u32 = 1;
pub const I2S_TX_WFULL_INT_ST_S: u32 = 4;
pub const I2S_RX_REMPTY_INT_ST_V: u32 = 1;
pub const I2S_RX_REMPTY_INT_ST_S: u32 = 3;
pub const I2S_RX_WFULL_INT_ST_V: u32 = 1;
pub const I2S_RX_WFULL_INT_ST_S: u32 = 2;
pub const I2S_TX_PUT_DATA_INT_ST_V: u32 = 1;
pub const I2S_TX_PUT_DATA_INT_ST_S: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_ST_V: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_ST_S: u32 = 0;
pub const I2S_OUT_TOTAL_EOF_INT_ENA_V: u32 = 1;
pub const I2S_OUT_TOTAL_EOF_INT_ENA_S: u32 = 16;
pub const I2S_IN_DSCR_EMPTY_INT_ENA_V: u32 = 1;
pub const I2S_IN_DSCR_EMPTY_INT_ENA_S: u32 = 15;
pub const I2S_OUT_DSCR_ERR_INT_ENA_V: u32 = 1;
pub const I2S_OUT_DSCR_ERR_INT_ENA_S: u32 = 14;
pub const I2S_IN_DSCR_ERR_INT_ENA_V: u32 = 1;
pub const I2S_IN_DSCR_ERR_INT_ENA_S: u32 = 13;
pub const I2S_OUT_EOF_INT_ENA_V: u32 = 1;
pub const I2S_OUT_EOF_INT_ENA_S: u32 = 12;
pub const I2S_OUT_DONE_INT_ENA_V: u32 = 1;
pub const I2S_OUT_DONE_INT_ENA_S: u32 = 11;
pub const I2S_IN_ERR_EOF_INT_ENA_V: u32 = 1;
pub const I2S_IN_ERR_EOF_INT_ENA_S: u32 = 10;
pub const I2S_IN_SUC_EOF_INT_ENA_V: u32 = 1;
pub const I2S_IN_SUC_EOF_INT_ENA_S: u32 = 9;
pub const I2S_IN_DONE_INT_ENA_V: u32 = 1;
pub const I2S_IN_DONE_INT_ENA_S: u32 = 8;
pub const I2S_TX_HUNG_INT_ENA_V: u32 = 1;
pub const I2S_TX_HUNG_INT_ENA_S: u32 = 7;
pub const I2S_RX_HUNG_INT_ENA_V: u32 = 1;
pub const I2S_RX_HUNG_INT_ENA_S: u32 = 6;
pub const I2S_TX_REMPTY_INT_ENA_V: u32 = 1;
pub const I2S_TX_REMPTY_INT_ENA_S: u32 = 5;
pub const I2S_TX_WFULL_INT_ENA_V: u32 = 1;
pub const I2S_TX_WFULL_INT_ENA_S: u32 = 4;
pub const I2S_RX_REMPTY_INT_ENA_V: u32 = 1;
pub const I2S_RX_REMPTY_INT_ENA_S: u32 = 3;
pub const I2S_RX_WFULL_INT_ENA_V: u32 = 1;
pub const I2S_RX_WFULL_INT_ENA_S: u32 = 2;
pub const I2S_TX_PUT_DATA_INT_ENA_V: u32 = 1;
pub const I2S_TX_PUT_DATA_INT_ENA_S: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_ENA_V: u32 = 1;
pub const I2S_RX_TAKE_DATA_INT_ENA_S: u32 = 0;
pub const I2S_OUT_TOTAL_EOF_INT_CLR_V: u32 = 1;
pub const I2S_OUT_TOTAL_EOF_INT_CLR_S: u32 = 16;
pub const I2S_IN_DSCR_EMPTY_INT_CLR_V: u32 = 1;
pub const I2S_IN_DSCR_EMPTY_INT_CLR_S: u32 = 15;
pub const I2S_OUT_DSCR_ERR_INT_CLR_V: u32 = 1;
pub const I2S_OUT_DSCR_ERR_INT_CLR_S: u32 = 14;
pub const I2S_IN_DSCR_ERR_INT_CLR_V: u32 = 1;
pub const I2S_IN_DSCR_ERR_INT_CLR_S: u32 = 13;
pub const I2S_OUT_EOF_INT_CLR_V: u32 = 1;
pub const I2S_OUT_EOF_INT_CLR_S: u32 = 12;
pub const I2S_OUT_DONE_INT_CLR_V: u32 = 1;
pub const I2S_OUT_DONE_INT_CLR_S: u32 = 11;
pub const I2S_IN_ERR_EOF_INT_CLR_V: u32 = 1;
pub const I2S_IN_ERR_EOF_INT_CLR_S: u32 = 10;
pub const I2S_IN_SUC_EOF_INT_CLR_V: u32 = 1;
pub const I2S_IN_SUC_EOF_INT_CLR_S: u32 = 9;
pub const I2S_IN_DONE_INT_CLR_V: u32 = 1;
pub const I2S_IN_DONE_INT_CLR_S: u32 = 8;
pub const I2S_TX_HUNG_INT_CLR_V: u32 = 1;
pub const I2S_TX_HUNG_INT_CLR_S: u32 = 7;
pub const I2S_RX_HUNG_INT_CLR_V: u32 = 1;
pub const I2S_RX_HUNG_INT_CLR_S: u32 = 6;
pub const I2S_TX_REMPTY_INT_CLR_V: u32 = 1;
pub const I2S_TX_REMPTY_INT_CLR_S: u32 = 5;
pub const I2S_TX_WFULL_INT_CLR_V: u32 = 1;
pub const I2S_TX_WFULL_INT_CLR_S: u32 = 4;
pub const I2S_RX_REMPTY_INT_CLR_V: u32 = 1;
pub const I2S_RX_REMPTY_INT_CLR_S: u32 = 3;
pub const I2S_RX_WFULL_INT_CLR_V: u32 = 1;
pub const I2S_RX_WFULL_INT_CLR_S: u32 = 2;
pub const I2S_PUT_DATA_INT_CLR_V: u32 = 1;
pub const I2S_PUT_DATA_INT_CLR_S: u32 = 1;
pub const I2S_TAKE_DATA_INT_CLR_V: u32 = 1;
pub const I2S_TAKE_DATA_INT_CLR_S: u32 = 0;
pub const I2S_TX_BCK_IN_INV_V: u32 = 1;
pub const I2S_TX_BCK_IN_INV_S: u32 = 24;
pub const I2S_DATA_ENABLE_DELAY: u32 = 3;
pub const I2S_DATA_ENABLE_DELAY_V: u32 = 3;
pub const I2S_DATA_ENABLE_DELAY_S: u32 = 22;
pub const I2S_RX_DSYNC_SW_V: u32 = 1;
pub const I2S_RX_DSYNC_SW_S: u32 = 21;
pub const I2S_TX_DSYNC_SW_V: u32 = 1;
pub const I2S_TX_DSYNC_SW_S: u32 = 20;
pub const I2S_RX_BCK_OUT_DELAY: u32 = 3;
pub const I2S_RX_BCK_OUT_DELAY_V: u32 = 3;
pub const I2S_RX_BCK_OUT_DELAY_S: u32 = 18;
pub const I2S_RX_WS_OUT_DELAY: u32 = 3;
pub const I2S_RX_WS_OUT_DELAY_V: u32 = 3;
pub const I2S_RX_WS_OUT_DELAY_S: u32 = 16;
pub const I2S_TX_SD_OUT_DELAY: u32 = 3;
pub const I2S_TX_SD_OUT_DELAY_V: u32 = 3;
pub const I2S_TX_SD_OUT_DELAY_S: u32 = 14;
pub const I2S_TX_WS_OUT_DELAY: u32 = 3;
pub const I2S_TX_WS_OUT_DELAY_V: u32 = 3;
pub const I2S_TX_WS_OUT_DELAY_S: u32 = 12;
pub const I2S_TX_BCK_OUT_DELAY: u32 = 3;
pub const I2S_TX_BCK_OUT_DELAY_V: u32 = 3;
pub const I2S_TX_BCK_OUT_DELAY_S: u32 = 10;
pub const I2S_RX_SD_IN_DELAY: u32 = 3;
pub const I2S_RX_SD_IN_DELAY_V: u32 = 3;
pub const I2S_RX_SD_IN_DELAY_S: u32 = 8;
pub const I2S_RX_WS_IN_DELAY: u32 = 3;
pub const I2S_RX_WS_IN_DELAY_V: u32 = 3;
pub const I2S_RX_WS_IN_DELAY_S: u32 = 6;
pub const I2S_RX_BCK_IN_DELAY: u32 = 3;
pub const I2S_RX_BCK_IN_DELAY_V: u32 = 3;
pub const I2S_RX_BCK_IN_DELAY_S: u32 = 4;
pub const I2S_TX_WS_IN_DELAY: u32 = 3;
pub const I2S_TX_WS_IN_DELAY_V: u32 = 3;
pub const I2S_TX_WS_IN_DELAY_S: u32 = 2;
pub const I2S_TX_BCK_IN_DELAY: u32 = 3;
pub const I2S_TX_BCK_IN_DELAY_V: u32 = 3;
pub const I2S_TX_BCK_IN_DELAY_S: u32 = 0;
pub const I2S_RX_FIFO_MOD_FORCE_EN_V: u32 = 1;
pub const I2S_RX_FIFO_MOD_FORCE_EN_S: u32 = 20;
pub const I2S_TX_FIFO_MOD_FORCE_EN_V: u32 = 1;
pub const I2S_TX_FIFO_MOD_FORCE_EN_S: u32 = 19;
pub const I2S_RX_FIFO_MOD: u32 = 7;
pub const I2S_RX_FIFO_MOD_V: u32 = 7;
pub const I2S_RX_FIFO_MOD_S: u32 = 16;
pub const I2S_TX_FIFO_MOD: u32 = 7;
pub const I2S_TX_FIFO_MOD_V: u32 = 7;
pub const I2S_TX_FIFO_MOD_S: u32 = 13;
pub const I2S_DSCR_EN_V: u32 = 1;
pub const I2S_DSCR_EN_S: u32 = 12;
pub const I2S_TX_DATA_NUM: u32 = 63;
pub const I2S_TX_DATA_NUM_V: u32 = 63;
pub const I2S_TX_DATA_NUM_S: u32 = 6;
pub const I2S_RX_DATA_NUM: u32 = 63;
pub const I2S_RX_DATA_NUM_V: u32 = 63;
pub const I2S_RX_DATA_NUM_S: u32 = 0;
pub const I2S_RX_EOF_NUM: u32 = 4294967295;
pub const I2S_RX_EOF_NUM_V: u32 = 4294967295;
pub const I2S_RX_EOF_NUM_S: u32 = 0;
pub const I2S_SIGLE_DATA: u32 = 4294967295;
pub const I2S_SIGLE_DATA_V: u32 = 4294967295;
pub const I2S_SIGLE_DATA_S: u32 = 0;
pub const I2S_RX_CHAN_MOD: u32 = 3;
pub const I2S_RX_CHAN_MOD_V: u32 = 3;
pub const I2S_RX_CHAN_MOD_S: u32 = 3;
pub const I2S_TX_CHAN_MOD: u32 = 7;
pub const I2S_TX_CHAN_MOD_V: u32 = 7;
pub const I2S_TX_CHAN_MOD_S: u32 = 0;
pub const I2S_OUTLINK_PARK_V: u32 = 1;
pub const I2S_OUTLINK_PARK_S: u32 = 31;
pub const I2S_OUTLINK_RESTART_V: u32 = 1;
pub const I2S_OUTLINK_RESTART_S: u32 = 30;
pub const I2S_OUTLINK_START_V: u32 = 1;
pub const I2S_OUTLINK_START_S: u32 = 29;
pub const I2S_OUTLINK_STOP_V: u32 = 1;
pub const I2S_OUTLINK_STOP_S: u32 = 28;
pub const I2S_OUTLINK_ADDR: u32 = 1048575;
pub const I2S_OUTLINK_ADDR_V: u32 = 1048575;
pub const I2S_OUTLINK_ADDR_S: u32 = 0;
pub const I2S_INLINK_PARK_V: u32 = 1;
pub const I2S_INLINK_PARK_S: u32 = 31;
pub const I2S_INLINK_RESTART_V: u32 = 1;
pub const I2S_INLINK_RESTART_S: u32 = 30;
pub const I2S_INLINK_START_V: u32 = 1;
pub const I2S_INLINK_START_S: u32 = 29;
pub const I2S_INLINK_STOP_V: u32 = 1;
pub const I2S_INLINK_STOP_S: u32 = 28;
pub const I2S_INLINK_ADDR: u32 = 1048575;
pub const I2S_INLINK_ADDR_V: u32 = 1048575;
pub const I2S_INLINK_ADDR_S: u32 = 0;
pub const I2S_OUT_EOF_DES_ADDR: u32 = 4294967295;
pub const I2S_OUT_EOF_DES_ADDR_V: u32 = 4294967295;
pub const I2S_OUT_EOF_DES_ADDR_S: u32 = 0;
pub const I2S_IN_SUC_EOF_DES_ADDR: u32 = 4294967295;
pub const I2S_IN_SUC_EOF_DES_ADDR_V: u32 = 4294967295;
pub const I2S_IN_SUC_EOF_DES_ADDR_S: u32 = 0;
pub const I2S_OUT_EOF_BFR_DES_ADDR: u32 = 4294967295;
pub const I2S_OUT_EOF_BFR_DES_ADDR_V: u32 = 4294967295;
pub const I2S_OUT_EOF_BFR_DES_ADDR_S: u32 = 0;
pub const I2S_AHB_TESTADDR: u32 = 3;
pub const I2S_AHB_TESTADDR_V: u32 = 3;
pub const I2S_AHB_TESTADDR_S: u32 = 4;
pub const I2S_AHB_TESTMODE: u32 = 7;
pub const I2S_AHB_TESTMODE_V: u32 = 7;
pub const I2S_AHB_TESTMODE_S: u32 = 0;
pub const I2S_INLINK_DSCR: u32 = 4294967295;
pub const I2S_INLINK_DSCR_V: u32 = 4294967295;
pub const I2S_INLINK_DSCR_S: u32 = 0;
pub const I2S_INLINK_DSCR_BF0: u32 = 4294967295;
pub const I2S_INLINK_DSCR_BF0_V: u32 = 4294967295;
pub const I2S_INLINK_DSCR_BF0_S: u32 = 0;
pub const I2S_INLINK_DSCR_BF1: u32 = 4294967295;
pub const I2S_INLINK_DSCR_BF1_V: u32 = 4294967295;
pub const I2S_INLINK_DSCR_BF1_S: u32 = 0;
pub const I2S_OUTLINK_DSCR: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_V: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_S: u32 = 0;
pub const I2S_OUTLINK_DSCR_BF0: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_BF0_V: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_BF0_S: u32 = 0;
pub const I2S_OUTLINK_DSCR_BF1: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_BF1_V: u32 = 4294967295;
pub const I2S_OUTLINK_DSCR_BF1_S: u32 = 0;
pub const I2S_MEM_TRANS_EN_V: u32 = 1;
pub const I2S_MEM_TRANS_EN_S: u32 = 13;
pub const I2S_CHECK_OWNER_V: u32 = 1;
pub const I2S_CHECK_OWNER_S: u32 = 12;
pub const I2S_OUT_DATA_BURST_EN_V: u32 = 1;
pub const I2S_OUT_DATA_BURST_EN_S: u32 = 11;
pub const I2S_INDSCR_BURST_EN_V: u32 = 1;
pub const I2S_INDSCR_BURST_EN_S: u32 = 10;
pub const I2S_OUTDSCR_BURST_EN_V: u32 = 1;
pub const I2S_OUTDSCR_BURST_EN_S: u32 = 9;
pub const I2S_OUT_EOF_MODE_V: u32 = 1;
pub const I2S_OUT_EOF_MODE_S: u32 = 8;
pub const I2S_OUT_NO_RESTART_CLR_V: u32 = 1;
pub const I2S_OUT_NO_RESTART_CLR_S: u32 = 7;
pub const I2S_OUT_AUTO_WRBACK_V: u32 = 1;
pub const I2S_OUT_AUTO_WRBACK_S: u32 = 6;
pub const I2S_IN_LOOP_TEST_V: u32 = 1;
pub const I2S_IN_LOOP_TEST_S: u32 = 5;
pub const I2S_OUT_LOOP_TEST_V: u32 = 1;
pub const I2S_OUT_LOOP_TEST_S: u32 = 4;
pub const I2S_AHBM_RST_V: u32 = 1;
pub const I2S_AHBM_RST_S: u32 = 3;
pub const I2S_AHBM_FIFO_RST_V: u32 = 1;
pub const I2S_AHBM_FIFO_RST_S: u32 = 2;
pub const I2S_OUT_RST_V: u32 = 1;
pub const I2S_OUT_RST_S: u32 = 1;
pub const I2S_IN_RST_V: u32 = 1;
pub const I2S_IN_RST_S: u32 = 0;
pub const I2S_OUTFIFO_PUSH_V: u32 = 1;
pub const I2S_OUTFIFO_PUSH_S: u32 = 16;
pub const I2S_OUTFIFO_WDATA: u32 = 511;
pub const I2S_OUTFIFO_WDATA_V: u32 = 511;
pub const I2S_OUTFIFO_WDATA_S: u32 = 0;
pub const I2S_INFIFO_POP_V: u32 = 1;
pub const I2S_INFIFO_POP_S: u32 = 16;
pub const I2S_INFIFO_RDATA: u32 = 4095;
pub const I2S_INFIFO_RDATA_V: u32 = 4095;
pub const I2S_INFIFO_RDATA_S: u32 = 0;
pub const I2S_LC_STATE0: u32 = 4294967295;
pub const I2S_LC_STATE0_V: u32 = 4294967295;
pub const I2S_LC_STATE0_S: u32 = 0;
pub const I2S_LC_STATE1: u32 = 4294967295;
pub const I2S_LC_STATE1_V: u32 = 4294967295;
pub const I2S_LC_STATE1_S: u32 = 0;
pub const I2S_LC_FIFO_TIMEOUT_ENA_V: u32 = 1;
pub const I2S_LC_FIFO_TIMEOUT_ENA_S: u32 = 11;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT: u32 = 7;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT_V: u32 = 7;
pub const I2S_LC_FIFO_TIMEOUT_SHIFT_S: u32 = 8;
pub const I2S_LC_FIFO_TIMEOUT: u32 = 255;
pub const I2S_LC_FIFO_TIMEOUT_V: u32 = 255;
pub const I2S_LC_FIFO_TIMEOUT_S: u32 = 0;
pub const I2S_CVSD_Y_MIN: u32 = 65535;
pub const I2S_CVSD_Y_MIN_V: u32 = 65535;
pub const I2S_CVSD_Y_MIN_S: u32 = 16;
pub const I2S_CVSD_Y_MAX: u32 = 65535;
pub const I2S_CVSD_Y_MAX_V: u32 = 65535;
pub const I2S_CVSD_Y_MAX_S: u32 = 0;
pub const I2S_CVSD_SIGMA_MIN: u32 = 65535;
pub const I2S_CVSD_SIGMA_MIN_V: u32 = 65535;
pub const I2S_CVSD_SIGMA_MIN_S: u32 = 16;
pub const I2S_CVSD_SIGMA_MAX: u32 = 65535;
pub const I2S_CVSD_SIGMA_MAX_V: u32 = 65535;
pub const I2S_CVSD_SIGMA_MAX_S: u32 = 0;
pub const I2S_CVSD_H: u32 = 7;
pub const I2S_CVSD_H_V: u32 = 7;
pub const I2S_CVSD_H_S: u32 = 16;
pub const I2S_CVSD_BETA: u32 = 1023;
pub const I2S_CVSD_BETA_V: u32 = 1023;
pub const I2S_CVSD_BETA_S: u32 = 6;
pub const I2S_CVSD_J: u32 = 7;
pub const I2S_CVSD_J_V: u32 = 7;
pub const I2S_CVSD_J_S: u32 = 3;
pub const I2S_CVSD_K: u32 = 7;
pub const I2S_CVSD_K_V: u32 = 7;
pub const I2S_CVSD_K_S: u32 = 0;
pub const I2S_N_MIN_ERR: u32 = 7;
pub const I2S_N_MIN_ERR_V: u32 = 7;
pub const I2S_N_MIN_ERR_S: u32 = 25;
pub const I2S_PACK_LEN_8K: u32 = 31;
pub const I2S_PACK_LEN_8K_V: u32 = 31;
pub const I2S_PACK_LEN_8K_S: u32 = 20;
pub const I2S_MAX_SLIDE_SAMPLE: u32 = 255;
pub const I2S_MAX_SLIDE_SAMPLE_V: u32 = 255;
pub const I2S_MAX_SLIDE_SAMPLE_S: u32 = 12;
pub const I2S_SHIFT_RATE: u32 = 7;
pub const I2S_SHIFT_RATE_V: u32 = 7;
pub const I2S_SHIFT_RATE_S: u32 = 9;
pub const I2S_N_ERR_SEG: u32 = 7;
pub const I2S_N_ERR_SEG_V: u32 = 7;
pub const I2S_N_ERR_SEG_S: u32 = 6;
pub const I2S_GOOD_PACK_MAX: u32 = 63;
pub const I2S_GOOD_PACK_MAX_V: u32 = 63;
pub const I2S_GOOD_PACK_MAX_S: u32 = 0;
pub const I2S_SLIDE_WIN_LEN: u32 = 255;
pub const I2S_SLIDE_WIN_LEN_V: u32 = 255;
pub const I2S_SLIDE_WIN_LEN_S: u32 = 24;
pub const I2S_BAD_OLA_WIN2_PARA: u32 = 255;
pub const I2S_BAD_OLA_WIN2_PARA_V: u32 = 255;
pub const I2S_BAD_OLA_WIN2_PARA_S: u32 = 16;
pub const I2S_BAD_OLA_WIN2_PARA_SHIFT: u32 = 15;
pub const I2S_BAD_OLA_WIN2_PARA_SHIFT_V: u32 = 15;
pub const I2S_BAD_OLA_WIN2_PARA_SHIFT_S: u32 = 12;
pub const I2S_BAD_CEF_ATTEN_PARA_SHIFT: u32 = 15;
pub const I2S_BAD_CEF_ATTEN_PARA_SHIFT_V: u32 = 15;
pub const I2S_BAD_CEF_ATTEN_PARA_SHIFT_S: u32 = 8;
pub const I2S_BAD_CEF_ATTEN_PARA: u32 = 255;
pub const I2S_BAD_CEF_ATTEN_PARA_V: u32 = 255;
pub const I2S_BAD_CEF_ATTEN_PARA_S: u32 = 0;
pub const I2S_MIN_PERIOD: u32 = 31;
pub const I2S_MIN_PERIOD_V: u32 = 31;
pub const I2S_MIN_PERIOD_S: u32 = 2;
pub const I2S_CVSD_SEG_MOD: u32 = 3;
pub const I2S_CVSD_SEG_MOD_V: u32 = 3;
pub const I2S_CVSD_SEG_MOD_S: u32 = 0;
pub const I2S_PLC2DMA_EN_V: u32 = 1;
pub const I2S_PLC2DMA_EN_S: u32 = 12;
pub const I2S_PLC_EN_V: u32 = 1;
pub const I2S_PLC_EN_S: u32 = 11;
pub const I2S_CVSD_DEC_RESET_V: u32 = 1;
pub const I2S_CVSD_DEC_RESET_S: u32 = 10;
pub const I2S_CVSD_DEC_START_V: u32 = 1;
pub const I2S_CVSD_DEC_START_S: u32 = 9;
pub const I2S_ESCO_CVSD_INF_EN_V: u32 = 1;
pub const I2S_ESCO_CVSD_INF_EN_S: u32 = 8;
pub const I2S_ESCO_CVSD_PACK_LEN_8K: u32 = 31;
pub const I2S_ESCO_CVSD_PACK_LEN_8K_V: u32 = 31;
pub const I2S_ESCO_CVSD_PACK_LEN_8K_S: u32 = 3;
pub const I2S_ESCO_CVSD_DEC_PACK_ERR_V: u32 = 1;
pub const I2S_ESCO_CVSD_DEC_PACK_ERR_S: u32 = 2;
pub const I2S_ESCO_CHAN_MOD_V: u32 = 1;
pub const I2S_ESCO_CHAN_MOD_S: u32 = 1;
pub const I2S_ESCO_EN_V: u32 = 1;
pub const I2S_ESCO_EN_S: u32 = 0;
pub const I2S_CVSD_ENC_RESET_V: u32 = 1;
pub const I2S_CVSD_ENC_RESET_S: u32 = 3;
pub const I2S_CVSD_ENC_START_V: u32 = 1;
pub const I2S_CVSD_ENC_START_S: u32 = 2;
pub const I2S_SCO_NO_I2S_EN_V: u32 = 1;
pub const I2S_SCO_NO_I2S_EN_S: u32 = 1;
pub const I2S_SCO_WITH_I2S_EN_V: u32 = 1;
pub const I2S_SCO_WITH_I2S_EN_S: u32 = 0;
pub const I2S_TX_ZEROS_RM_EN_V: u32 = 1;
pub const I2S_TX_ZEROS_RM_EN_S: u32 = 9;
pub const I2S_TX_STOP_EN_V: u32 = 1;
pub const I2S_TX_STOP_EN_S: u32 = 8;
pub const I2S_RX_PCM_BYPASS_V: u32 = 1;
pub const I2S_RX_PCM_BYPASS_S: u32 = 7;
pub const I2S_RX_PCM_CONF: u32 = 7;
pub const I2S_RX_PCM_CONF_V: u32 = 7;
pub const I2S_RX_PCM_CONF_S: u32 = 4;
pub const I2S_TX_PCM_BYPASS_V: u32 = 1;
pub const I2S_TX_PCM_BYPASS_S: u32 = 3;
pub const I2S_TX_PCM_CONF: u32 = 7;
pub const I2S_TX_PCM_CONF_V: u32 = 7;
pub const I2S_TX_PCM_CONF_S: u32 = 0;
pub const I2S_PLC_MEM_FORCE_PU_V: u32 = 1;
pub const I2S_PLC_MEM_FORCE_PU_S: u32 = 3;
pub const I2S_PLC_MEM_FORCE_PD_V: u32 = 1;
pub const I2S_PLC_MEM_FORCE_PD_S: u32 = 2;
pub const I2S_FIFO_FORCE_PU_V: u32 = 1;
pub const I2S_FIFO_FORCE_PU_S: u32 = 1;
pub const I2S_FIFO_FORCE_PD_V: u32 = 1;
pub const I2S_FIFO_FORCE_PD_S: u32 = 0;
pub const I2S_INTER_VALID_EN_V: u32 = 1;
pub const I2S_INTER_VALID_EN_S: u32 = 7;
pub const I2S_EXT_ADC_START_EN_V: u32 = 1;
pub const I2S_EXT_ADC_START_EN_S: u32 = 6;
pub const I2S_LCD_EN_V: u32 = 1;
pub const I2S_LCD_EN_S: u32 = 5;
pub const I2S_DATA_ENABLE_V: u32 = 1;
pub const I2S_DATA_ENABLE_S: u32 = 4;
pub const I2S_DATA_ENABLE_TEST_EN_V: u32 = 1;
pub const I2S_DATA_ENABLE_TEST_EN_S: u32 = 3;
pub const I2S_LCD_TX_SDX2_EN_V: u32 = 1;
pub const I2S_LCD_TX_SDX2_EN_S: u32 = 2;
pub const I2S_LCD_TX_WRX2_EN_V: u32 = 1;
pub const I2S_LCD_TX_WRX2_EN_S: u32 = 1;
pub const I2S_CAMERA_EN_V: u32 = 1;
pub const I2S_CAMERA_EN_S: u32 = 0;
pub const I2S_CLKA_ENA_V: u32 = 1;
pub const I2S_CLKA_ENA_S: u32 = 21;
pub const I2S_CLK_EN_V: u32 = 1;
pub const I2S_CLK_EN_S: u32 = 20;
pub const I2S_CLKM_DIV_A: u32 = 63;
pub const I2S_CLKM_DIV_A_V: u32 = 63;
pub const I2S_CLKM_DIV_A_S: u32 = 14;
pub const I2S_CLKM_DIV_B: u32 = 63;
pub const I2S_CLKM_DIV_B_V: u32 = 63;
pub const I2S_CLKM_DIV_B_S: u32 = 8;
pub const I2S_CLKM_DIV_NUM: u32 = 255;
pub const I2S_CLKM_DIV_NUM_V: u32 = 255;
pub const I2S_CLKM_DIV_NUM_S: u32 = 0;
pub const I2S_RX_BITS_MOD: u32 = 63;
pub const I2S_RX_BITS_MOD_V: u32 = 63;
pub const I2S_RX_BITS_MOD_S: u32 = 18;
pub const I2S_TX_BITS_MOD: u32 = 63;
pub const I2S_TX_BITS_MOD_V: u32 = 63;
pub const I2S_TX_BITS_MOD_S: u32 = 12;
pub const I2S_RX_BCK_DIV_NUM: u32 = 63;
pub const I2S_RX_BCK_DIV_NUM_V: u32 = 63;
pub const I2S_RX_BCK_DIV_NUM_S: u32 = 6;
pub const I2S_TX_BCK_DIV_NUM: u32 = 63;
pub const I2S_TX_BCK_DIV_NUM_V: u32 = 63;
pub const I2S_TX_BCK_DIV_NUM_S: u32 = 0;
pub const I2S_TX_PDM_HP_BYPASS_V: u32 = 1;
pub const I2S_TX_PDM_HP_BYPASS_S: u32 = 25;
pub const I2S_RX_PDM_SINC_DSR_16_EN_V: u32 = 1;
pub const I2S_RX_PDM_SINC_DSR_16_EN_S: u32 = 24;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S: u32 = 22;
pub const I2S_TX_PDM_SINC_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_SINC_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_SINC_IN_SHIFT_S: u32 = 20;
pub const I2S_TX_PDM_LP_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_LP_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_LP_IN_SHIFT_S: u32 = 18;
pub const I2S_TX_PDM_HP_IN_SHIFT: u32 = 3;
pub const I2S_TX_PDM_HP_IN_SHIFT_V: u32 = 3;
pub const I2S_TX_PDM_HP_IN_SHIFT_S: u32 = 16;
pub const I2S_TX_PDM_PRESCALE: u32 = 255;
pub const I2S_TX_PDM_PRESCALE_V: u32 = 255;
pub const I2S_TX_PDM_PRESCALE_S: u32 = 8;
pub const I2S_TX_PDM_SINC_OSR2: u32 = 15;
pub const I2S_TX_PDM_SINC_OSR2_V: u32 = 15;
pub const I2S_TX_PDM_SINC_OSR2_S: u32 = 4;
pub const I2S_PDM2PCM_CONV_EN_V: u32 = 1;
pub const I2S_PDM2PCM_CONV_EN_S: u32 = 3;
pub const I2S_PCM2PDM_CONV_EN_V: u32 = 1;
pub const I2S_PCM2PDM_CONV_EN_S: u32 = 2;
pub const I2S_RX_PDM_EN_V: u32 = 1;
pub const I2S_RX_PDM_EN_S: u32 = 1;
pub const I2S_TX_PDM_EN_V: u32 = 1;
pub const I2S_TX_PDM_EN_S: u32 = 0;
pub const I2S_TX_PDM_FP: u32 = 1023;
pub const I2S_TX_PDM_FP_V: u32 = 1023;
pub const I2S_TX_PDM_FP_S: u32 = 10;
pub const I2S_TX_PDM_FS: u32 = 1023;
pub const I2S_TX_PDM_FS_V: u32 = 1023;
pub const I2S_TX_PDM_FS_S: u32 = 0;
pub const I2S_RX_FIFO_RESET_BACK_V: u32 = 1;
pub const I2S_RX_FIFO_RESET_BACK_S: u32 = 2;
pub const I2S_TX_FIFO_RESET_BACK_V: u32 = 1;
pub const I2S_TX_FIFO_RESET_BACK_S: u32 = 1;
pub const I2S_TX_IDLE_V: u32 = 1;
pub const I2S_TX_IDLE_S: u32 = 0;
pub const I2S_I2SDATE: u32 = 4294967295;
pub const I2S_I2SDATE_V: u32 = 4294967295;
pub const I2S_I2SDATE_S: u32 = 0;
pub const UART_RXFIFO_RD_BYTE: u32 = 255;
pub const UART_RXFIFO_RD_BYTE_V: u32 = 255;
pub const UART_RXFIFO_RD_BYTE_S: u32 = 0;
pub const UART_AT_CMD_CHAR_DET_INT_RAW_V: u32 = 1;
pub const UART_AT_CMD_CHAR_DET_INT_RAW_S: u32 = 18;
pub const UART_RS485_CLASH_INT_RAW_V: u32 = 1;
pub const UART_RS485_CLASH_INT_RAW_S: u32 = 17;
pub const UART_RS485_FRM_ERR_INT_RAW_V: u32 = 1;
pub const UART_RS485_FRM_ERR_INT_RAW_S: u32 = 16;
pub const UART_RS485_PARITY_ERR_INT_RAW_V: u32 = 1;
pub const UART_RS485_PARITY_ERR_INT_RAW_S: u32 = 15;
pub const UART_TX_DONE_INT_RAW_V: u32 = 1;
pub const UART_TX_DONE_INT_RAW_S: u32 = 14;
pub const UART_TX_BRK_IDLE_DONE_INT_RAW_V: u32 = 1;
pub const UART_TX_BRK_IDLE_DONE_INT_RAW_S: u32 = 13;
pub const UART_TX_BRK_DONE_INT_RAW_V: u32 = 1;
pub const UART_TX_BRK_DONE_INT_RAW_S: u32 = 12;
pub const UART_GLITCH_DET_INT_RAW_V: u32 = 1;
pub const UART_GLITCH_DET_INT_RAW_S: u32 = 11;
pub const UART_SW_XOFF_INT_RAW_V: u32 = 1;
pub const UART_SW_XOFF_INT_RAW_S: u32 = 10;
pub const UART_SW_XON_INT_RAW_V: u32 = 1;
pub const UART_SW_XON_INT_RAW_S: u32 = 9;
pub const UART_RXFIFO_TOUT_INT_RAW_V: u32 = 1;
pub const UART_RXFIFO_TOUT_INT_RAW_S: u32 = 8;
pub const UART_BRK_DET_INT_RAW_V: u32 = 1;
pub const UART_BRK_DET_INT_RAW_S: u32 = 7;
pub const UART_CTS_CHG_INT_RAW_V: u32 = 1;
pub const UART_CTS_CHG_INT_RAW_S: u32 = 6;
pub const UART_DSR_CHG_INT_RAW_V: u32 = 1;
pub const UART_DSR_CHG_INT_RAW_S: u32 = 5;
pub const UART_RXFIFO_OVF_INT_RAW_V: u32 = 1;
pub const UART_RXFIFO_OVF_INT_RAW_S: u32 = 4;
pub const UART_FRM_ERR_INT_RAW_V: u32 = 1;
pub const UART_FRM_ERR_INT_RAW_S: u32 = 3;
pub const UART_PARITY_ERR_INT_RAW_V: u32 = 1;
pub const UART_PARITY_ERR_INT_RAW_S: u32 = 2;
pub const UART_TXFIFO_EMPTY_INT_RAW_V: u32 = 1;
pub const UART_TXFIFO_EMPTY_INT_RAW_S: u32 = 1;
pub const UART_RXFIFO_FULL_INT_RAW_V: u32 = 1;
pub const UART_RXFIFO_FULL_INT_RAW_S: u32 = 0;
pub const UART_AT_CMD_CHAR_DET_INT_ST_V: u32 = 1;
pub const UART_AT_CMD_CHAR_DET_INT_ST_S: u32 = 18;
pub const UART_RS485_CLASH_INT_ST_V: u32 = 1;
pub const UART_RS485_CLASH_INT_ST_S: u32 = 17;
pub const UART_RS485_FRM_ERR_INT_ST_V: u32 = 1;
pub const UART_RS485_FRM_ERR_INT_ST_S: u32 = 16;
pub const UART_RS485_PARITY_ERR_INT_ST_V: u32 = 1;
pub const UART_RS485_PARITY_ERR_INT_ST_S: u32 = 15;
pub const UART_TX_DONE_INT_ST_V: u32 = 1;
pub const UART_TX_DONE_INT_ST_S: u32 = 14;
pub const UART_TX_BRK_IDLE_DONE_INT_ST_V: u32 = 1;
pub const UART_TX_BRK_IDLE_DONE_INT_ST_S: u32 = 13;
pub const UART_TX_BRK_DONE_INT_ST_V: u32 = 1;
pub const UART_TX_BRK_DONE_INT_ST_S: u32 = 12;
pub const UART_GLITCH_DET_INT_ST_V: u32 = 1;
pub const UART_GLITCH_DET_INT_ST_S: u32 = 11;
pub const UART_SW_XOFF_INT_ST_V: u32 = 1;
pub const UART_SW_XOFF_INT_ST_S: u32 = 10;
pub const UART_SW_XON_INT_ST_V: u32 = 1;
pub const UART_SW_XON_INT_ST_S: u32 = 9;
pub const UART_RXFIFO_TOUT_INT_ST_V: u32 = 1;
pub const UART_RXFIFO_TOUT_INT_ST_S: u32 = 8;
pub const UART_BRK_DET_INT_ST_V: u32 = 1;
pub const UART_BRK_DET_INT_ST_S: u32 = 7;
pub const UART_CTS_CHG_INT_ST_V: u32 = 1;
pub const UART_CTS_CHG_INT_ST_S: u32 = 6;
pub const UART_DSR_CHG_INT_ST_V: u32 = 1;
pub const UART_DSR_CHG_INT_ST_S: u32 = 5;
pub const UART_RXFIFO_OVF_INT_ST_V: u32 = 1;
pub const UART_RXFIFO_OVF_INT_ST_S: u32 = 4;
pub const UART_FRM_ERR_INT_ST_V: u32 = 1;
pub const UART_FRM_ERR_INT_ST_S: u32 = 3;
pub const UART_PARITY_ERR_INT_ST_V: u32 = 1;
pub const UART_PARITY_ERR_INT_ST_S: u32 = 2;
pub const UART_TXFIFO_EMPTY_INT_ST_V: u32 = 1;
pub const UART_TXFIFO_EMPTY_INT_ST_S: u32 = 1;
pub const UART_RXFIFO_FULL_INT_ST_V: u32 = 1;
pub const UART_RXFIFO_FULL_INT_ST_S: u32 = 0;
pub const UART_AT_CMD_CHAR_DET_INT_ENA_V: u32 = 1;
pub const UART_AT_CMD_CHAR_DET_INT_ENA_S: u32 = 18;
pub const UART_RS485_CLASH_INT_ENA_V: u32 = 1;
pub const UART_RS485_CLASH_INT_ENA_S: u32 = 17;
pub const UART_RS485_FRM_ERR_INT_ENA_V: u32 = 1;
pub const UART_RS485_FRM_ERR_INT_ENA_S: u32 = 16;
pub const UART_RS485_PARITY_ERR_INT_ENA_V: u32 = 1;
pub const UART_RS485_PARITY_ERR_INT_ENA_S: u32 = 15;
pub const UART_TX_DONE_INT_ENA_V: u32 = 1;
pub const UART_TX_DONE_INT_ENA_S: u32 = 14;
pub const UART_TX_BRK_IDLE_DONE_INT_ENA_V: u32 = 1;
pub const UART_TX_BRK_IDLE_DONE_INT_ENA_S: u32 = 13;
pub const UART_TX_BRK_DONE_INT_ENA_V: u32 = 1;
pub const UART_TX_BRK_DONE_INT_ENA_S: u32 = 12;
pub const UART_GLITCH_DET_INT_ENA_V: u32 = 1;
pub const UART_GLITCH_DET_INT_ENA_S: u32 = 11;
pub const UART_SW_XOFF_INT_ENA_V: u32 = 1;
pub const UART_SW_XOFF_INT_ENA_S: u32 = 10;
pub const UART_SW_XON_INT_ENA_V: u32 = 1;
pub const UART_SW_XON_INT_ENA_S: u32 = 9;
pub const UART_RXFIFO_TOUT_INT_ENA_V: u32 = 1;
pub const UART_RXFIFO_TOUT_INT_ENA_S: u32 = 8;
pub const UART_BRK_DET_INT_ENA_V: u32 = 1;
pub const UART_BRK_DET_INT_ENA_S: u32 = 7;
pub const UART_CTS_CHG_INT_ENA_V: u32 = 1;
pub const UART_CTS_CHG_INT_ENA_S: u32 = 6;
pub const UART_DSR_CHG_INT_ENA_V: u32 = 1;
pub const UART_DSR_CHG_INT_ENA_S: u32 = 5;
pub const UART_RXFIFO_OVF_INT_ENA_V: u32 = 1;
pub const UART_RXFIFO_OVF_INT_ENA_S: u32 = 4;
pub const UART_FRM_ERR_INT_ENA_V: u32 = 1;
pub const UART_FRM_ERR_INT_ENA_S: u32 = 3;
pub const UART_PARITY_ERR_INT_ENA_V: u32 = 1;
pub const UART_PARITY_ERR_INT_ENA_S: u32 = 2;
pub const UART_TXFIFO_EMPTY_INT_ENA_V: u32 = 1;
pub const UART_TXFIFO_EMPTY_INT_ENA_S: u32 = 1;
pub const UART_RXFIFO_FULL_INT_ENA_V: u32 = 1;
pub const UART_RXFIFO_FULL_INT_ENA_S: u32 = 0;
pub const UART_AT_CMD_CHAR_DET_INT_CLR_V: u32 = 1;
pub const UART_AT_CMD_CHAR_DET_INT_CLR_S: u32 = 18;
pub const UART_RS485_CLASH_INT_CLR_V: u32 = 1;
pub const UART_RS485_CLASH_INT_CLR_S: u32 = 17;
pub const UART_RS485_FRM_ERR_INT_CLR_V: u32 = 1;
pub const UART_RS485_FRM_ERR_INT_CLR_S: u32 = 16;
pub const UART_RS485_PARITY_ERR_INT_CLR_V: u32 = 1;
pub const UART_RS485_PARITY_ERR_INT_CLR_S: u32 = 15;
pub const UART_TX_DONE_INT_CLR_V: u32 = 1;
pub const UART_TX_DONE_INT_CLR_S: u32 = 14;
pub const UART_TX_BRK_IDLE_DONE_INT_CLR_V: u32 = 1;
pub const UART_TX_BRK_IDLE_DONE_INT_CLR_S: u32 = 13;
pub const UART_TX_BRK_DONE_INT_CLR_V: u32 = 1;
pub const UART_TX_BRK_DONE_INT_CLR_S: u32 = 12;
pub const UART_GLITCH_DET_INT_CLR_V: u32 = 1;
pub const UART_GLITCH_DET_INT_CLR_S: u32 = 11;
pub const UART_SW_XOFF_INT_CLR_V: u32 = 1;
pub const UART_SW_XOFF_INT_CLR_S: u32 = 10;
pub const UART_SW_XON_INT_CLR_V: u32 = 1;
pub const UART_SW_XON_INT_CLR_S: u32 = 9;
pub const UART_RXFIFO_TOUT_INT_CLR_V: u32 = 1;
pub const UART_RXFIFO_TOUT_INT_CLR_S: u32 = 8;
pub const UART_BRK_DET_INT_CLR_V: u32 = 1;
pub const UART_BRK_DET_INT_CLR_S: u32 = 7;
pub const UART_CTS_CHG_INT_CLR_V: u32 = 1;
pub const UART_CTS_CHG_INT_CLR_S: u32 = 6;
pub const UART_DSR_CHG_INT_CLR_V: u32 = 1;
pub const UART_DSR_CHG_INT_CLR_S: u32 = 5;
pub const UART_RXFIFO_OVF_INT_CLR_V: u32 = 1;
pub const UART_RXFIFO_OVF_INT_CLR_S: u32 = 4;
pub const UART_FRM_ERR_INT_CLR_V: u32 = 1;
pub const UART_FRM_ERR_INT_CLR_S: u32 = 3;
pub const UART_PARITY_ERR_INT_CLR_V: u32 = 1;
pub const UART_PARITY_ERR_INT_CLR_S: u32 = 2;
pub const UART_TXFIFO_EMPTY_INT_CLR_V: u32 = 1;
pub const UART_TXFIFO_EMPTY_INT_CLR_S: u32 = 1;
pub const UART_RXFIFO_FULL_INT_CLR_V: u32 = 1;
pub const UART_RXFIFO_FULL_INT_CLR_S: u32 = 0;
pub const UART_CLKDIV_FRAG: u32 = 15;
pub const UART_CLKDIV_FRAG_V: u32 = 15;
pub const UART_CLKDIV_FRAG_S: u32 = 20;
pub const UART_CLKDIV: u32 = 1048575;
pub const UART_CLKDIV_V: u32 = 1048575;
pub const UART_CLKDIV_S: u32 = 0;
pub const UART_GLITCH_FILT: u32 = 255;
pub const UART_GLITCH_FILT_V: u32 = 255;
pub const UART_GLITCH_FILT_S: u32 = 8;
pub const UART_AUTOBAUD_EN_V: u32 = 1;
pub const UART_AUTOBAUD_EN_S: u32 = 0;
pub const UART_TXD_V: u32 = 1;
pub const UART_TXD_S: u32 = 31;
pub const UART_RTSN_V: u32 = 1;
pub const UART_RTSN_S: u32 = 30;
pub const UART_DTRN_V: u32 = 1;
pub const UART_DTRN_S: u32 = 29;
pub const UART_ST_UTX_OUT: u32 = 15;
pub const UART_ST_UTX_OUT_V: u32 = 15;
pub const UART_ST_UTX_OUT_S: u32 = 24;
pub const UART_TXFIFO_CNT: u32 = 255;
pub const UART_TXFIFO_CNT_V: u32 = 255;
pub const UART_TXFIFO_CNT_S: u32 = 16;
pub const UART_RXD_V: u32 = 1;
pub const UART_RXD_S: u32 = 15;
pub const UART_CTSN_V: u32 = 1;
pub const UART_CTSN_S: u32 = 14;
pub const UART_DSRN_V: u32 = 1;
pub const UART_DSRN_S: u32 = 13;
pub const UART_ST_URX_OUT: u32 = 15;
pub const UART_ST_URX_OUT_V: u32 = 15;
pub const UART_ST_URX_OUT_S: u32 = 8;
pub const UART_RXFIFO_CNT: u32 = 255;
pub const UART_RXFIFO_CNT_V: u32 = 255;
pub const UART_RXFIFO_CNT_S: u32 = 0;
pub const UART_TICK_REF_ALWAYS_ON_V: u32 = 1;
pub const UART_TICK_REF_ALWAYS_ON_S: u32 = 27;
pub const UART_ERR_WR_MASK_V: u32 = 1;
pub const UART_ERR_WR_MASK_S: u32 = 26;
pub const UART_CLK_EN_V: u32 = 1;
pub const UART_CLK_EN_S: u32 = 25;
pub const UART_DTR_INV_V: u32 = 1;
pub const UART_DTR_INV_S: u32 = 24;
pub const UART_RTS_INV_V: u32 = 1;
pub const UART_RTS_INV_S: u32 = 23;
pub const UART_TXD_INV_V: u32 = 1;
pub const UART_TXD_INV_S: u32 = 22;
pub const UART_DSR_INV_V: u32 = 1;
pub const UART_DSR_INV_S: u32 = 21;
pub const UART_CTS_INV_V: u32 = 1;
pub const UART_CTS_INV_S: u32 = 20;
pub const UART_RXD_INV_V: u32 = 1;
pub const UART_RXD_INV_S: u32 = 19;
pub const UART_TXFIFO_RST_V: u32 = 1;
pub const UART_TXFIFO_RST_S: u32 = 18;
pub const UART_RXFIFO_RST_V: u32 = 1;
pub const UART_RXFIFO_RST_S: u32 = 17;
pub const UART_IRDA_EN_V: u32 = 1;
pub const UART_IRDA_EN_S: u32 = 16;
pub const UART_TX_FLOW_EN_V: u32 = 1;
pub const UART_TX_FLOW_EN_S: u32 = 15;
pub const UART_LOOPBACK_V: u32 = 1;
pub const UART_LOOPBACK_S: u32 = 14;
pub const UART_IRDA_RX_INV_V: u32 = 1;
pub const UART_IRDA_RX_INV_S: u32 = 13;
pub const UART_IRDA_TX_INV_V: u32 = 1;
pub const UART_IRDA_TX_INV_S: u32 = 12;
pub const UART_IRDA_WCTL_V: u32 = 1;
pub const UART_IRDA_WCTL_S: u32 = 11;
pub const UART_IRDA_TX_EN_V: u32 = 1;
pub const UART_IRDA_TX_EN_S: u32 = 10;
pub const UART_IRDA_DPLX_V: u32 = 1;
pub const UART_IRDA_DPLX_S: u32 = 9;
pub const UART_TXD_BRK_V: u32 = 1;
pub const UART_TXD_BRK_S: u32 = 8;
pub const UART_SW_DTR_V: u32 = 1;
pub const UART_SW_DTR_S: u32 = 7;
pub const UART_SW_RTS_V: u32 = 1;
pub const UART_SW_RTS_S: u32 = 6;
pub const UART_STOP_BIT_NUM: u32 = 3;
pub const UART_STOP_BIT_NUM_V: u32 = 3;
pub const UART_STOP_BIT_NUM_S: u32 = 4;
pub const UART_BIT_NUM: u32 = 3;
pub const UART_BIT_NUM_V: u32 = 3;
pub const UART_BIT_NUM_S: u32 = 2;
pub const UART_PARITY_EN_V: u32 = 1;
pub const UART_PARITY_EN_S: u32 = 1;
pub const UART_PARITY_V: u32 = 1;
pub const UART_PARITY_S: u32 = 0;
pub const UART_RX_TOUT_EN_V: u32 = 1;
pub const UART_RX_TOUT_EN_S: u32 = 31;
pub const UART_RX_TOUT_THRHD: u32 = 127;
pub const UART_RX_TOUT_THRHD_V: u32 = 127;
pub const UART_RX_TOUT_THRHD_S: u32 = 24;
pub const UART_RX_FLOW_EN_V: u32 = 1;
pub const UART_RX_FLOW_EN_S: u32 = 23;
pub const UART_RX_FLOW_THRHD: u32 = 127;
pub const UART_RX_FLOW_THRHD_V: u32 = 127;
pub const UART_RX_FLOW_THRHD_S: u32 = 16;
pub const UART_TXFIFO_EMPTY_THRHD: u32 = 127;
pub const UART_TXFIFO_EMPTY_THRHD_V: u32 = 127;
pub const UART_TXFIFO_EMPTY_THRHD_S: u32 = 8;
pub const UART_RXFIFO_FULL_THRHD: u32 = 127;
pub const UART_RXFIFO_FULL_THRHD_V: u32 = 127;
pub const UART_RXFIFO_FULL_THRHD_S: u32 = 0;
pub const UART_LOWPULSE_MIN_CNT: u32 = 1048575;
pub const UART_LOWPULSE_MIN_CNT_V: u32 = 1048575;
pub const UART_LOWPULSE_MIN_CNT_S: u32 = 0;
pub const UART_HIGHPULSE_MIN_CNT: u32 = 1048575;
pub const UART_HIGHPULSE_MIN_CNT_V: u32 = 1048575;
pub const UART_HIGHPULSE_MIN_CNT_S: u32 = 0;
pub const UART_RXD_EDGE_CNT: u32 = 1023;
pub const UART_RXD_EDGE_CNT_V: u32 = 1023;
pub const UART_RXD_EDGE_CNT_S: u32 = 0;
pub const UART_SEND_XOFF_V: u32 = 1;
pub const UART_SEND_XOFF_S: u32 = 5;
pub const UART_SEND_XON_V: u32 = 1;
pub const UART_SEND_XON_S: u32 = 4;
pub const UART_FORCE_XOFF_V: u32 = 1;
pub const UART_FORCE_XOFF_S: u32 = 3;
pub const UART_FORCE_XON_V: u32 = 1;
pub const UART_FORCE_XON_S: u32 = 2;
pub const UART_XONOFF_DEL_V: u32 = 1;
pub const UART_XONOFF_DEL_S: u32 = 1;
pub const UART_SW_FLOW_CON_EN_V: u32 = 1;
pub const UART_SW_FLOW_CON_EN_S: u32 = 0;
pub const UART_ACTIVE_THRESHOLD: u32 = 1023;
pub const UART_ACTIVE_THRESHOLD_V: u32 = 1023;
pub const UART_ACTIVE_THRESHOLD_S: u32 = 0;
pub const UART_XOFF_CHAR: u32 = 255;
pub const UART_XOFF_CHAR_V: u32 = 255;
pub const UART_XOFF_CHAR_S: u32 = 24;
pub const UART_XON_CHAR: u32 = 255;
pub const UART_XON_CHAR_V: u32 = 255;
pub const UART_XON_CHAR_S: u32 = 16;
pub const UART_XOFF_THRESHOLD: u32 = 255;
pub const UART_XOFF_THRESHOLD_V: u32 = 255;
pub const UART_XOFF_THRESHOLD_S: u32 = 8;
pub const UART_XON_THRESHOLD: u32 = 255;
pub const UART_XON_THRESHOLD_V: u32 = 255;
pub const UART_XON_THRESHOLD_S: u32 = 0;
pub const UART_TX_BRK_NUM: u32 = 255;
pub const UART_TX_BRK_NUM_V: u32 = 255;
pub const UART_TX_BRK_NUM_S: u32 = 20;
pub const UART_TX_IDLE_NUM: u32 = 1023;
pub const UART_TX_IDLE_NUM_V: u32 = 1023;
pub const UART_TX_IDLE_NUM_S: u32 = 10;
pub const UART_RX_IDLE_THRHD: u32 = 1023;
pub const UART_RX_IDLE_THRHD_V: u32 = 1023;
pub const UART_RX_IDLE_THRHD_S: u32 = 0;
pub const UART_RS485_TX_DLY_NUM: u32 = 15;
pub const UART_RS485_TX_DLY_NUM_V: u32 = 15;
pub const UART_RS485_TX_DLY_NUM_S: u32 = 6;
pub const UART_RS485_RX_DLY_NUM_V: u32 = 1;
pub const UART_RS485_RX_DLY_NUM_S: u32 = 5;
pub const UART_RS485RXBY_TX_EN_V: u32 = 1;
pub const UART_RS485RXBY_TX_EN_S: u32 = 4;
pub const UART_RS485TX_RX_EN_V: u32 = 1;
pub const UART_RS485TX_RX_EN_S: u32 = 3;
pub const UART_DL1_EN_V: u32 = 1;
pub const UART_DL1_EN_S: u32 = 2;
pub const UART_DL0_EN_V: u32 = 1;
pub const UART_DL0_EN_S: u32 = 1;
pub const UART_RS485_EN_V: u32 = 1;
pub const UART_RS485_EN_S: u32 = 0;
pub const UART_PRE_IDLE_NUM: u32 = 16777215;
pub const UART_PRE_IDLE_NUM_V: u32 = 16777215;
pub const UART_PRE_IDLE_NUM_S: u32 = 0;
pub const UART_POST_IDLE_NUM: u32 = 16777215;
pub const UART_POST_IDLE_NUM_V: u32 = 16777215;
pub const UART_POST_IDLE_NUM_S: u32 = 0;
pub const UART_RX_GAP_TOUT: u32 = 16777215;
pub const UART_RX_GAP_TOUT_V: u32 = 16777215;
pub const UART_RX_GAP_TOUT_S: u32 = 0;
pub const UART_CHAR_NUM: u32 = 255;
pub const UART_CHAR_NUM_V: u32 = 255;
pub const UART_CHAR_NUM_S: u32 = 8;
pub const UART_AT_CMD_CHAR: u32 = 255;
pub const UART_AT_CMD_CHAR_V: u32 = 255;
pub const UART_AT_CMD_CHAR_S: u32 = 0;
pub const UART_TX_MEM_EMPTY_THRHD: u32 = 7;
pub const UART_TX_MEM_EMPTY_THRHD_V: u32 = 7;
pub const UART_TX_MEM_EMPTY_THRHD_S: u32 = 28;
pub const UART_RX_MEM_FULL_THRHD: u32 = 7;
pub const UART_RX_MEM_FULL_THRHD_V: u32 = 7;
pub const UART_RX_MEM_FULL_THRHD_S: u32 = 25;
pub const UART_XOFF_THRESHOLD_H2: u32 = 3;
pub const UART_XOFF_THRESHOLD_H2_V: u32 = 3;
pub const UART_XOFF_THRESHOLD_H2_S: u32 = 23;
pub const UART_XON_THRESHOLD_H2: u32 = 3;
pub const UART_XON_THRESHOLD_H2_V: u32 = 3;
pub const UART_XON_THRESHOLD_H2_S: u32 = 21;
pub const UART_RX_TOUT_THRHD_H3: u32 = 7;
pub const UART_RX_TOUT_THRHD_H3_V: u32 = 7;
pub const UART_RX_TOUT_THRHD_H3_S: u32 = 18;
pub const UART_RX_FLOW_THRHD_H3: u32 = 7;
pub const UART_RX_FLOW_THRHD_H3_V: u32 = 7;
pub const UART_RX_FLOW_THRHD_H3_S: u32 = 15;
pub const UART_TX_SIZE: u32 = 15;
pub const UART_TX_SIZE_V: u32 = 15;
pub const UART_TX_SIZE_S: u32 = 7;
pub const UART_RX_SIZE: u32 = 15;
pub const UART_RX_SIZE_V: u32 = 15;
pub const UART_RX_SIZE_S: u32 = 3;
pub const UART_MEM_PD_V: u32 = 1;
pub const UART_MEM_PD_S: u32 = 0;
pub const UART_MEM_TX_STATUS: u32 = 16777215;
pub const UART_MEM_TX_STATUS_V: u32 = 16777215;
pub const UART_MEM_TX_STATUS_S: u32 = 0;
pub const UART_MEM_RX_STATUS: u32 = 16777215;
pub const UART_MEM_RX_STATUS_V: u32 = 16777215;
pub const UART_MEM_RX_STATUS_S: u32 = 0;
pub const UART_MEM_RX_RD_ADDR: u32 = 2047;
pub const UART_MEM_RX_RD_ADDR_V: u32 = 2047;
pub const UART_MEM_RX_RD_ADDR_S: u32 = 2;
pub const UART_MEM_RX_WR_ADDR: u32 = 2047;
pub const UART_MEM_RX_WR_ADDR_V: u32 = 2047;
pub const UART_MEM_RX_WR_ADDR_S: u32 = 13;
pub const UART_TX_MEM_CNT: u32 = 7;
pub const UART_TX_MEM_CNT_V: u32 = 7;
pub const UART_TX_MEM_CNT_S: u32 = 3;
pub const UART_RX_MEM_CNT: u32 = 7;
pub const UART_RX_MEM_CNT_V: u32 = 7;
pub const UART_RX_MEM_CNT_S: u32 = 0;
pub const UART_POSEDGE_MIN_CNT: u32 = 1048575;
pub const UART_POSEDGE_MIN_CNT_V: u32 = 1048575;
pub const UART_POSEDGE_MIN_CNT_S: u32 = 0;
pub const UART_NEGEDGE_MIN_CNT: u32 = 1048575;
pub const UART_NEGEDGE_MIN_CNT_V: u32 = 1048575;
pub const UART_NEGEDGE_MIN_CNT_S: u32 = 0;
pub const UART_DATE: u32 = 4294967295;
pub const UART_DATE_V: u32 = 4294967295;
pub const UART_DATE_S: u32 = 0;
pub const UART_ID: u32 = 4294967295;
pub const UART_ID_V: u32 = 4294967295;
pub const UART_ID_S: u32 = 0;
pub const DPORT_PRO_BOOT_REMAP_CTRL_REG: u32 = 1072693248;
pub const DPORT_PRO_BOOT_REMAP_V: u32 = 1;
pub const DPORT_PRO_BOOT_REMAP_S: u32 = 0;
pub const DPORT_APP_BOOT_REMAP_CTRL_REG: u32 = 1072693252;
pub const DPORT_APP_BOOT_REMAP_V: u32 = 1;
pub const DPORT_APP_BOOT_REMAP_S: u32 = 0;
pub const DPORT_ACCESS_CHECK_REG: u32 = 1072693256;
pub const DPORT_ACCESS_CHECK_APP_V: u32 = 1;
pub const DPORT_ACCESS_CHECK_APP_S: u32 = 8;
pub const DPORT_ACCESS_CHECK_PRO_V: u32 = 1;
pub const DPORT_ACCESS_CHECK_PRO_S: u32 = 0;
pub const DPORT_PRO_DPORT_APB_MASK0_REG: u32 = 1072693260;
pub const DPORT_PRODPORT_APB_MASK0: u32 = 4294967295;
pub const DPORT_PRODPORT_APB_MASK0_V: u32 = 4294967295;
pub const DPORT_PRODPORT_APB_MASK0_S: u32 = 0;
pub const DPORT_PRO_DPORT_APB_MASK1_REG: u32 = 1072693264;
pub const DPORT_PRODPORT_APB_MASK1: u32 = 4294967295;
pub const DPORT_PRODPORT_APB_MASK1_V: u32 = 4294967295;
pub const DPORT_PRODPORT_APB_MASK1_S: u32 = 0;
pub const DPORT_APP_DPORT_APB_MASK0_REG: u32 = 1072693268;
pub const DPORT_APPDPORT_APB_MASK0: u32 = 4294967295;
pub const DPORT_APPDPORT_APB_MASK0_V: u32 = 4294967295;
pub const DPORT_APPDPORT_APB_MASK0_S: u32 = 0;
pub const DPORT_APP_DPORT_APB_MASK1_REG: u32 = 1072693272;
pub const DPORT_APPDPORT_APB_MASK1: u32 = 4294967295;
pub const DPORT_APPDPORT_APB_MASK1_V: u32 = 4294967295;
pub const DPORT_APPDPORT_APB_MASK1_S: u32 = 0;
pub const DPORT_PERI_CLK_EN_REG: u32 = 1072693276;
pub const DPORT_PERI_CLK_EN: u32 = 4294967295;
pub const DPORT_PERI_CLK_EN_V: u32 = 4294967295;
pub const DPORT_PERI_CLK_EN_S: u32 = 0;
pub const DPORT_PERI_RST_EN_REG: u32 = 1072693280;
pub const DPORT_PERI_RST_EN: u32 = 4294967295;
pub const DPORT_PERI_RST_EN_V: u32 = 4294967295;
pub const DPORT_PERI_RST_EN_S: u32 = 0;
pub const DPORT_PERI_EN_AES: u32 = 1;
pub const DPORT_PERI_EN_SHA: u32 = 2;
pub const DPORT_PERI_EN_RSA: u32 = 4;
pub const DPORT_PERI_EN_SECUREBOOT: u32 = 8;
pub const DPORT_PERI_EN_DIGITAL_SIGNATURE: u32 = 16;
pub const DPORT_WIFI_BB_CFG_REG: u32 = 1072693284;
pub const DPORT_WIFI_BB_CFG: u32 = 4294967295;
pub const DPORT_WIFI_BB_CFG_V: u32 = 4294967295;
pub const DPORT_WIFI_BB_CFG_S: u32 = 0;
pub const DPORT_WIFI_BB_CFG_2_REG: u32 = 1072693288;
pub const DPORT_WIFI_BB_CFG_2: u32 = 4294967295;
pub const DPORT_WIFI_BB_CFG_2_V: u32 = 4294967295;
pub const DPORT_WIFI_BB_CFG_2_S: u32 = 0;
pub const DPORT_APPCPU_CTRL_A_REG: u32 = 1072693292;
pub const DPORT_APPCPU_RESETTING_V: u32 = 1;
pub const DPORT_APPCPU_RESETTING_S: u32 = 0;
pub const DPORT_APPCPU_CTRL_B_REG: u32 = 1072693296;
pub const DPORT_APPCPU_CLKGATE_EN_V: u32 = 1;
pub const DPORT_APPCPU_CLKGATE_EN_S: u32 = 0;
pub const DPORT_APPCPU_CTRL_C_REG: u32 = 1072693300;
pub const DPORT_APPCPU_RUNSTALL_V: u32 = 1;
pub const DPORT_APPCPU_RUNSTALL_S: u32 = 0;
pub const DPORT_APPCPU_CTRL_D_REG: u32 = 1072693304;
pub const DPORT_APPCPU_BOOT_ADDR: u32 = 4294967295;
pub const DPORT_APPCPU_BOOT_ADDR_V: u32 = 4294967295;
pub const DPORT_APPCPU_BOOT_ADDR_S: u32 = 0;
pub const DPORT_CPU_PER_CONF_REG: u32 = 1072693308;
pub const DPORT_FAST_CLK_RTC_SEL_V: u32 = 1;
pub const DPORT_FAST_CLK_RTC_SEL_S: u32 = 3;
pub const DPORT_LOWSPEED_CLK_SEL_V: u32 = 1;
pub const DPORT_LOWSPEED_CLK_SEL_S: u32 = 2;
pub const DPORT_CPUPERIOD_SEL: u32 = 3;
pub const DPORT_CPUPERIOD_SEL_V: u32 = 3;
pub const DPORT_CPUPERIOD_SEL_S: u32 = 0;
pub const DPORT_CPUPERIOD_SEL_80: u32 = 0;
pub const DPORT_CPUPERIOD_SEL_160: u32 = 1;
pub const DPORT_CPUPERIOD_SEL_240: u32 = 2;
pub const DPORT_PRO_CACHE_CTRL_REG: u32 = 1072693312;
pub const DPORT_PRO_DRAM_HL_V: u32 = 1;
pub const DPORT_PRO_DRAM_HL_S: u32 = 16;
pub const DPORT_SLAVE_REQ_V: u32 = 1;
pub const DPORT_SLAVE_REQ_S: u32 = 15;
pub const DPORT_AHB_SPI_REQ_V: u32 = 1;
pub const DPORT_AHB_SPI_REQ_S: u32 = 14;
pub const DPORT_PRO_SLAVE_REQ_V: u32 = 1;
pub const DPORT_PRO_SLAVE_REQ_S: u32 = 13;
pub const DPORT_PRO_AHB_SPI_REQ_V: u32 = 1;
pub const DPORT_PRO_AHB_SPI_REQ_S: u32 = 12;
pub const DPORT_PRO_DRAM_SPLIT_V: u32 = 1;
pub const DPORT_PRO_DRAM_SPLIT_S: u32 = 11;
pub const DPORT_PRO_SINGLE_IRAM_ENA_V: u32 = 1;
pub const DPORT_PRO_SINGLE_IRAM_ENA_S: u32 = 10;
pub const DPORT_PRO_CACHE_LOCK_3_EN_V: u32 = 1;
pub const DPORT_PRO_CACHE_LOCK_3_EN_S: u32 = 9;
pub const DPORT_PRO_CACHE_LOCK_2_EN_V: u32 = 1;
pub const DPORT_PRO_CACHE_LOCK_2_EN_S: u32 = 8;
pub const DPORT_PRO_CACHE_LOCK_1_EN_V: u32 = 1;
pub const DPORT_PRO_CACHE_LOCK_1_EN_S: u32 = 7;
pub const DPORT_PRO_CACHE_LOCK_0_EN_V: u32 = 1;
pub const DPORT_PRO_CACHE_LOCK_0_EN_S: u32 = 6;
pub const DPORT_PRO_CACHE_FLUSH_DONE_V: u32 = 1;
pub const DPORT_PRO_CACHE_FLUSH_DONE_S: u32 = 5;
pub const DPORT_PRO_CACHE_FLUSH_ENA_V: u32 = 1;
pub const DPORT_PRO_CACHE_FLUSH_ENA_S: u32 = 4;
pub const DPORT_PRO_CACHE_ENABLE_V: u32 = 1;
pub const DPORT_PRO_CACHE_ENABLE_S: u32 = 3;
pub const DPORT_PRO_CACHE_MODE_V: u32 = 1;
pub const DPORT_PRO_CACHE_MODE_S: u32 = 2;
pub const DPORT_PRO_CACHE_CTRL1_REG: u32 = 1072693316;
pub const DPORT_PRO_CACHE_MMU_IA_CLR_V: u32 = 1;
pub const DPORT_PRO_CACHE_MMU_IA_CLR_S: u32 = 13;
pub const DPORT_PRO_CMMU_PD_V: u32 = 1;
pub const DPORT_PRO_CMMU_PD_S: u32 = 12;
pub const DPORT_PRO_CMMU_FORCE_ON_V: u32 = 1;
pub const DPORT_PRO_CMMU_FORCE_ON_S: u32 = 11;
pub const DPORT_PRO_CMMU_FLASH_PAGE_MODE: u32 = 3;
pub const DPORT_PRO_CMMU_FLASH_PAGE_MODE_V: u32 = 3;
pub const DPORT_PRO_CMMU_FLASH_PAGE_MODE_S: u32 = 9;
pub const DPORT_PRO_CMMU_SRAM_PAGE_MODE: u32 = 7;
pub const DPORT_PRO_CMMU_SRAM_PAGE_MODE_V: u32 = 7;
pub const DPORT_PRO_CMMU_SRAM_PAGE_MODE_S: u32 = 6;
pub const DPORT_PRO_CACHE_MASK_OPSDRAM_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_OPSDRAM_S: u32 = 5;
pub const DPORT_PRO_CACHE_MASK_DROM0_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_DROM0_S: u32 = 4;
pub const DPORT_PRO_CACHE_MASK_DRAM1_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_DRAM1_S: u32 = 3;
pub const DPORT_PRO_CACHE_MASK_IROM0_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_IROM0_S: u32 = 2;
pub const DPORT_PRO_CACHE_MASK_IRAM1_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_IRAM1_S: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_IRAM0_V: u32 = 1;
pub const DPORT_PRO_CACHE_MASK_IRAM0_S: u32 = 0;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_REG: u32 = 1072693320;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MAX: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S: u32 = 18;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MIN: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S: u32 = 14;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_PRE: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S: u32 = 0;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_REG: u32 = 1072693324;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MAX: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S: u32 = 18;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MIN: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S: u32 = 14;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_PRE: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S: u32 = 0;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_REG: u32 = 1072693328;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MAX: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S: u32 = 18;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MIN: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S: u32 = 14;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_PRE: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S: u32 = 0;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_REG: u32 = 1072693332;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MAX: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S: u32 = 18;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MIN: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V: u32 = 15;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S: u32 = 14;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_PRE: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V: u32 = 16383;
pub const DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S: u32 = 0;
pub const DPORT_APP_CACHE_CTRL_REG: u32 = 1072693336;
pub const DPORT_APP_DRAM_HL_V: u32 = 1;
pub const DPORT_APP_DRAM_HL_S: u32 = 14;
pub const DPORT_APP_SLAVE_REQ_V: u32 = 1;
pub const DPORT_APP_SLAVE_REQ_S: u32 = 13;
pub const DPORT_APP_AHB_SPI_REQ_V: u32 = 1;
pub const DPORT_APP_AHB_SPI_REQ_S: u32 = 12;
pub const DPORT_APP_DRAM_SPLIT_V: u32 = 1;
pub const DPORT_APP_DRAM_SPLIT_S: u32 = 11;
pub const DPORT_APP_SINGLE_IRAM_ENA_V: u32 = 1;
pub const DPORT_APP_SINGLE_IRAM_ENA_S: u32 = 10;
pub const DPORT_APP_CACHE_LOCK_3_EN_V: u32 = 1;
pub const DPORT_APP_CACHE_LOCK_3_EN_S: u32 = 9;
pub const DPORT_APP_CACHE_LOCK_2_EN_V: u32 = 1;
pub const DPORT_APP_CACHE_LOCK_2_EN_S: u32 = 8;
pub const DPORT_APP_CACHE_LOCK_1_EN_V: u32 = 1;
pub const DPORT_APP_CACHE_LOCK_1_EN_S: u32 = 7;
pub const DPORT_APP_CACHE_LOCK_0_EN_V: u32 = 1;
pub const DPORT_APP_CACHE_LOCK_0_EN_S: u32 = 6;
pub const DPORT_APP_CACHE_FLUSH_DONE_V: u32 = 1;
pub const DPORT_APP_CACHE_FLUSH_DONE_S: u32 = 5;
pub const DPORT_APP_CACHE_FLUSH_ENA_V: u32 = 1;
pub const DPORT_APP_CACHE_FLUSH_ENA_S: u32 = 4;
pub const DPORT_APP_CACHE_ENABLE_V: u32 = 1;
pub const DPORT_APP_CACHE_ENABLE_S: u32 = 3;
pub const DPORT_APP_CACHE_MODE_V: u32 = 1;
pub const DPORT_APP_CACHE_MODE_S: u32 = 2;
pub const DPORT_APP_CACHE_CTRL1_REG: u32 = 1072693340;
pub const DPORT_APP_CACHE_MMU_IA_CLR_V: u32 = 1;
pub const DPORT_APP_CACHE_MMU_IA_CLR_S: u32 = 13;
pub const DPORT_APP_CMMU_PD_V: u32 = 1;
pub const DPORT_APP_CMMU_PD_S: u32 = 12;
pub const DPORT_APP_CMMU_FORCE_ON_V: u32 = 1;
pub const DPORT_APP_CMMU_FORCE_ON_S: u32 = 11;
pub const DPORT_APP_CMMU_FLASH_PAGE_MODE: u32 = 3;
pub const DPORT_APP_CMMU_FLASH_PAGE_MODE_V: u32 = 3;
pub const DPORT_APP_CMMU_FLASH_PAGE_MODE_S: u32 = 9;
pub const DPORT_APP_CMMU_SRAM_PAGE_MODE: u32 = 7;
pub const DPORT_APP_CMMU_SRAM_PAGE_MODE_V: u32 = 7;
pub const DPORT_APP_CMMU_SRAM_PAGE_MODE_S: u32 = 6;
pub const DPORT_APP_CACHE_MASK_OPSDRAM_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_OPSDRAM_S: u32 = 5;
pub const DPORT_APP_CACHE_MASK_DROM0_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_DROM0_S: u32 = 4;
pub const DPORT_APP_CACHE_MASK_DRAM1_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_DRAM1_S: u32 = 3;
pub const DPORT_APP_CACHE_MASK_IROM0_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_IROM0_S: u32 = 2;
pub const DPORT_APP_CACHE_MASK_IRAM1_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_IRAM1_S: u32 = 1;
pub const DPORT_APP_CACHE_MASK_IRAM0_V: u32 = 1;
pub const DPORT_APP_CACHE_MASK_IRAM0_S: u32 = 0;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_REG: u32 = 1072693344;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MAX: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S: u32 = 18;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MIN: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S: u32 = 14;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_PRE: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S: u32 = 0;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_REG: u32 = 1072693348;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MAX: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S: u32 = 18;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MIN: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S: u32 = 14;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_PRE: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S: u32 = 0;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_REG: u32 = 1072693352;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MAX: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S: u32 = 18;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MIN: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S: u32 = 14;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_PRE: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S: u32 = 0;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_REG: u32 = 1072693356;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MAX: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S: u32 = 18;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MIN: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V: u32 = 15;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S: u32 = 14;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_PRE: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V: u32 = 16383;
pub const DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S: u32 = 0;
pub const DPORT_TRACEMEM_MUX_MODE_REG: u32 = 1072693360;
pub const DPORT_TRACEMEM_MUX_MODE: u32 = 3;
pub const DPORT_TRACEMEM_MUX_MODE_V: u32 = 3;
pub const DPORT_TRACEMEM_MUX_MODE_S: u32 = 0;
pub const DPORT_PRO_TRACEMEM_ENA_REG: u32 = 1072693364;
pub const DPORT_PRO_TRACEMEM_ENA_V: u32 = 1;
pub const DPORT_PRO_TRACEMEM_ENA_S: u32 = 0;
pub const DPORT_APP_TRACEMEM_ENA_REG: u32 = 1072693368;
pub const DPORT_APP_TRACEMEM_ENA_V: u32 = 1;
pub const DPORT_APP_TRACEMEM_ENA_S: u32 = 0;
pub const DPORT_CACHE_MUX_MODE_REG: u32 = 1072693372;
pub const DPORT_CACHE_MUX_MODE: u32 = 3;
pub const DPORT_CACHE_MUX_MODE_V: u32 = 3;
pub const DPORT_CACHE_MUX_MODE_S: u32 = 0;
pub const DPORT_IMMU_PAGE_MODE_REG: u32 = 1072693376;
pub const DPORT_IMMU_PAGE_MODE: u32 = 3;
pub const DPORT_IMMU_PAGE_MODE_V: u32 = 3;
pub const DPORT_IMMU_PAGE_MODE_S: u32 = 1;
pub const DPORT_INTERNAL_SRAM_IMMU_ENA_V: u32 = 1;
pub const DPORT_INTERNAL_SRAM_IMMU_ENA_S: u32 = 0;
pub const DPORT_DMMU_PAGE_MODE_REG: u32 = 1072693380;
pub const DPORT_DMMU_PAGE_MODE: u32 = 3;
pub const DPORT_DMMU_PAGE_MODE_V: u32 = 3;
pub const DPORT_DMMU_PAGE_MODE_S: u32 = 1;
pub const DPORT_INTERNAL_SRAM_DMMU_ENA_V: u32 = 1;
pub const DPORT_INTERNAL_SRAM_DMMU_ENA_S: u32 = 0;
pub const DPORT_ROM_MPU_ENA_REG: u32 = 1072693384;
pub const DPORT_APP_ROM_MPU_ENA_V: u32 = 1;
pub const DPORT_APP_ROM_MPU_ENA_S: u32 = 2;
pub const DPORT_PRO_ROM_MPU_ENA_V: u32 = 1;
pub const DPORT_PRO_ROM_MPU_ENA_S: u32 = 1;
pub const DPORT_SHARE_ROM_MPU_ENA_V: u32 = 1;
pub const DPORT_SHARE_ROM_MPU_ENA_S: u32 = 0;
pub const DPORT_MEM_PD_MASK_REG: u32 = 1072693388;
pub const DPORT_LSLP_MEM_PD_MASK_V: u32 = 1;
pub const DPORT_LSLP_MEM_PD_MASK_S: u32 = 0;
pub const DPORT_ROM_PD_CTRL_REG: u32 = 1072693392;
pub const DPORT_SHARE_ROM_PD: u32 = 63;
pub const DPORT_SHARE_ROM_PD_V: u32 = 63;
pub const DPORT_SHARE_ROM_PD_S: u32 = 2;
pub const DPORT_APP_ROM_PD_V: u32 = 1;
pub const DPORT_APP_ROM_PD_S: u32 = 1;
pub const DPORT_PRO_ROM_PD_V: u32 = 1;
pub const DPORT_PRO_ROM_PD_S: u32 = 0;
pub const DPORT_ROM_FO_CTRL_REG: u32 = 1072693396;
pub const DPORT_SHARE_ROM_FO: u32 = 63;
pub const DPORT_SHARE_ROM_FO_V: u32 = 63;
pub const DPORT_SHARE_ROM_FO_S: u32 = 2;
pub const DPORT_APP_ROM_FO_V: u32 = 1;
pub const DPORT_APP_ROM_FO_S: u32 = 1;
pub const DPORT_PRO_ROM_FO_V: u32 = 1;
pub const DPORT_PRO_ROM_FO_S: u32 = 0;
pub const DPORT_SRAM_PD_CTRL_0_REG: u32 = 1072693400;
pub const DPORT_SRAM_PD_0: u32 = 4294967295;
pub const DPORT_SRAM_PD_0_V: u32 = 4294967295;
pub const DPORT_SRAM_PD_0_S: u32 = 0;
pub const DPORT_SRAM_PD_CTRL_1_REG: u32 = 1072693404;
pub const DPORT_SRAM_PD_1_V: u32 = 1;
pub const DPORT_SRAM_PD_1_S: u32 = 0;
pub const DPORT_SRAM_FO_CTRL_0_REG: u32 = 1072693408;
pub const DPORT_SRAM_FO_0: u32 = 4294967295;
pub const DPORT_SRAM_FO_0_V: u32 = 4294967295;
pub const DPORT_SRAM_FO_0_S: u32 = 0;
pub const DPORT_SRAM_FO_CTRL_1_REG: u32 = 1072693412;
pub const DPORT_SRAM_FO_1_V: u32 = 1;
pub const DPORT_SRAM_FO_1_S: u32 = 0;
pub const DPORT_IRAM_DRAM_AHB_SEL_REG: u32 = 1072693416;
pub const DPORT_MAC_DUMP_MODE: u32 = 3;
pub const DPORT_MAC_DUMP_MODE_V: u32 = 3;
pub const DPORT_MAC_DUMP_MODE_S: u32 = 5;
pub const DPORT_MASK_AHB_V: u32 = 1;
pub const DPORT_MASK_AHB_S: u32 = 4;
pub const DPORT_MASK_APP_DRAM_V: u32 = 1;
pub const DPORT_MASK_APP_DRAM_S: u32 = 3;
pub const DPORT_MASK_PRO_DRAM_V: u32 = 1;
pub const DPORT_MASK_PRO_DRAM_S: u32 = 2;
pub const DPORT_MASK_APP_IRAM_V: u32 = 1;
pub const DPORT_MASK_APP_IRAM_S: u32 = 1;
pub const DPORT_MASK_PRO_IRAM_V: u32 = 1;
pub const DPORT_MASK_PRO_IRAM_S: u32 = 0;
pub const DPORT_TAG_FO_CTRL_REG: u32 = 1072693420;
pub const DPORT_APP_CACHE_TAG_PD_V: u32 = 1;
pub const DPORT_APP_CACHE_TAG_PD_S: u32 = 9;
pub const DPORT_APP_CACHE_TAG_FORCE_ON_V: u32 = 1;
pub const DPORT_APP_CACHE_TAG_FORCE_ON_S: u32 = 8;
pub const DPORT_PRO_CACHE_TAG_PD_V: u32 = 1;
pub const DPORT_PRO_CACHE_TAG_PD_S: u32 = 1;
pub const DPORT_PRO_CACHE_TAG_FORCE_ON_V: u32 = 1;
pub const DPORT_PRO_CACHE_TAG_FORCE_ON_S: u32 = 0;
pub const DPORT_AHB_LITE_MASK_REG: u32 = 1072693424;
pub const DPORT_AHB_LITE_SDHOST_PID_REG: u32 = 7;
pub const DPORT_AHB_LITE_SDHOST_PID_REG_V: u32 = 7;
pub const DPORT_AHB_LITE_SDHOST_PID_REG_S: u32 = 11;
pub const DPORT_AHB_LITE_MASK_APPDPORT_V: u32 = 1;
pub const DPORT_AHB_LITE_MASK_APPDPORT_S: u32 = 10;
pub const DPORT_AHB_LITE_MASK_PRODPORT_V: u32 = 1;
pub const DPORT_AHB_LITE_MASK_PRODPORT_S: u32 = 9;
pub const DPORT_AHB_LITE_MASK_SDIO_V: u32 = 1;
pub const DPORT_AHB_LITE_MASK_SDIO_S: u32 = 8;
pub const DPORT_AHB_LITE_MASK_APP_V: u32 = 1;
pub const DPORT_AHB_LITE_MASK_APP_S: u32 = 4;
pub const DPORT_AHB_LITE_MASK_PRO_V: u32 = 1;
pub const DPORT_AHB_LITE_MASK_PRO_S: u32 = 0;
pub const DPORT_AHB_MPU_TABLE_0_REG: u32 = 1072693428;
pub const DPORT_AHB_ACCESS_GRANT_0: u32 = 4294967295;
pub const DPORT_AHB_ACCESS_GRANT_0_V: u32 = 4294967295;
pub const DPORT_AHB_ACCESS_GRANT_0_S: u32 = 0;
pub const DPORT_AHB_MPU_TABLE_1_REG: u32 = 1072693432;
pub const DPORT_AHB_ACCESS_GRANT_1: u32 = 511;
pub const DPORT_AHB_ACCESS_GRANT_1_V: u32 = 511;
pub const DPORT_AHB_ACCESS_GRANT_1_S: u32 = 0;
pub const DPORT_HOST_INF_SEL_REG: u32 = 1072693436;
pub const DPORT_LINK_DEVICE_SEL: u32 = 255;
pub const DPORT_LINK_DEVICE_SEL_V: u32 = 255;
pub const DPORT_LINK_DEVICE_SEL_S: u32 = 8;
pub const DPORT_PERI_IO_SWAP: u32 = 255;
pub const DPORT_PERI_IO_SWAP_V: u32 = 255;
pub const DPORT_PERI_IO_SWAP_S: u32 = 0;
pub const DPORT_PERIP_CLK_EN_REG: u32 = 1072693440;
pub const DPORT_PERIP_CLK_EN: u32 = 4294967295;
pub const DPORT_PERIP_CLK_EN_V: u32 = 4294967295;
pub const DPORT_PERIP_CLK_EN_S: u32 = 0;
pub const DPORT_PERIP_RST_EN_REG: u32 = 1072693444;
pub const DPORT_PERIP_RST: u32 = 4294967295;
pub const DPORT_PERIP_RST_V: u32 = 4294967295;
pub const DPORT_PERIP_RST_S: u32 = 0;
pub const DPORT_SLAVE_SPI_CONFIG_REG: u32 = 1072693448;
pub const DPORT_SPI_DECRYPT_ENABLE_V: u32 = 1;
pub const DPORT_SPI_DECRYPT_ENABLE_S: u32 = 12;
pub const DPORT_SPI_ENCRYPT_ENABLE_V: u32 = 1;
pub const DPORT_SPI_ENCRYPT_ENABLE_S: u32 = 8;
pub const DPORT_SLAVE_SPI_MASK_APP_V: u32 = 1;
pub const DPORT_SLAVE_SPI_MASK_APP_S: u32 = 4;
pub const DPORT_SLAVE_SPI_MASK_PRO_V: u32 = 1;
pub const DPORT_SLAVE_SPI_MASK_PRO_S: u32 = 0;
pub const DPORT_WIFI_CLK_EN_REG: u32 = 1072693452;
pub const DPORT_WIFI_CLK_EN: u32 = 4294967295;
pub const DPORT_WIFI_CLK_EN_V: u32 = 4294967295;
pub const DPORT_WIFI_CLK_EN_S: u32 = 0;
pub const DPORT_WIFI_CLK_WIFI_EN: u32 = 1030;
pub const DPORT_WIFI_CLK_WIFI_EN_V: u32 = 1030;
pub const DPORT_WIFI_CLK_WIFI_EN_S: u32 = 0;
pub const DPORT_WIFI_CLK_BT_EN: u32 = 97;
pub const DPORT_WIFI_CLK_BT_EN_V: u32 = 97;
pub const DPORT_WIFI_CLK_BT_EN_S: u32 = 11;
pub const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 969;
pub const DPORT_CORE_RST_EN_REG: u32 = 1072693456;
pub const DPORT_BT_LPCK_DIV_INT_REG: u32 = 1072693460;
pub const DPORT_BTEXTWAKEUP_REQ_V: u32 = 1;
pub const DPORT_BTEXTWAKEUP_REQ_S: u32 = 12;
pub const DPORT_BT_LPCK_DIV_NUM: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_NUM_V: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_NUM_S: u32 = 0;
pub const DPORT_BT_LPCK_DIV_FRAC_REG: u32 = 1072693464;
pub const DPORT_LPCLK_SEL_XTAL32K_V: u32 = 1;
pub const DPORT_LPCLK_SEL_XTAL32K_S: u32 = 27;
pub const DPORT_LPCLK_SEL_XTAL_V: u32 = 1;
pub const DPORT_LPCLK_SEL_XTAL_S: u32 = 26;
pub const DPORT_LPCLK_SEL_8M_V: u32 = 1;
pub const DPORT_LPCLK_SEL_8M_S: u32 = 25;
pub const DPORT_LPCLK_SEL_RTC_SLOW_V: u32 = 1;
pub const DPORT_LPCLK_SEL_RTC_SLOW_S: u32 = 24;
pub const DPORT_BT_LPCK_DIV_A: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_A_V: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_A_S: u32 = 12;
pub const DPORT_BT_LPCK_DIV_B: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_B_V: u32 = 4095;
pub const DPORT_BT_LPCK_DIV_B_S: u32 = 0;
pub const DPORT_CPU_INTR_FROM_CPU_0_REG: u32 = 1072693468;
pub const DPORT_CPU_INTR_FROM_CPU_0_V: u32 = 1;
pub const DPORT_CPU_INTR_FROM_CPU_0_S: u32 = 0;
pub const DPORT_CPU_INTR_FROM_CPU_1_REG: u32 = 1072693472;
pub const DPORT_CPU_INTR_FROM_CPU_1_V: u32 = 1;
pub const DPORT_CPU_INTR_FROM_CPU_1_S: u32 = 0;
pub const DPORT_CPU_INTR_FROM_CPU_2_REG: u32 = 1072693476;
pub const DPORT_CPU_INTR_FROM_CPU_2_V: u32 = 1;
pub const DPORT_CPU_INTR_FROM_CPU_2_S: u32 = 0;
pub const DPORT_CPU_INTR_FROM_CPU_3_REG: u32 = 1072693480;
pub const DPORT_CPU_INTR_FROM_CPU_3_V: u32 = 1;
pub const DPORT_CPU_INTR_FROM_CPU_3_S: u32 = 0;
pub const DPORT_PRO_INTR_STATUS_0_REG: u32 = 1072693484;
pub const DPORT_PRO_INTR_STATUS_0: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_0_V: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_0_S: u32 = 0;
pub const DPORT_PRO_INTR_STATUS_1_REG: u32 = 1072693488;
pub const DPORT_PRO_INTR_STATUS_1: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_1_V: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_1_S: u32 = 0;
pub const DPORT_PRO_INTR_STATUS_2_REG: u32 = 1072693492;
pub const DPORT_PRO_INTR_STATUS_2: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_2_V: u32 = 4294967295;
pub const DPORT_PRO_INTR_STATUS_2_S: u32 = 0;
pub const DPORT_APP_INTR_STATUS_0_REG: u32 = 1072693496;
pub const DPORT_APP_INTR_STATUS_0: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_0_V: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_0_S: u32 = 0;
pub const DPORT_APP_INTR_STATUS_1_REG: u32 = 1072693500;
pub const DPORT_APP_INTR_STATUS_1: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_1_V: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_1_S: u32 = 0;
pub const DPORT_APP_INTR_STATUS_2_REG: u32 = 1072693504;
pub const DPORT_APP_INTR_STATUS_2: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_2_V: u32 = 4294967295;
pub const DPORT_APP_INTR_STATUS_2_S: u32 = 0;
pub const DPORT_PRO_MAC_INTR_MAP_REG: u32 = 1072693508;
pub const DPORT_PRO_MAC_INTR_MAP: u32 = 31;
pub const DPORT_PRO_MAC_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_MAC_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_MAC_NMI_MAP_REG: u32 = 1072693512;
pub const DPORT_PRO_MAC_NMI_MAP: u32 = 31;
pub const DPORT_PRO_MAC_NMI_MAP_V: u32 = 31;
pub const DPORT_PRO_MAC_NMI_MAP_S: u32 = 0;
pub const DPORT_PRO_BB_INT_MAP_REG: u32 = 1072693516;
pub const DPORT_PRO_BB_INT_MAP: u32 = 31;
pub const DPORT_PRO_BB_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_BB_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_BT_MAC_INT_MAP_REG: u32 = 1072693520;
pub const DPORT_PRO_BT_MAC_INT_MAP: u32 = 31;
pub const DPORT_PRO_BT_MAC_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_BT_MAC_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_BT_BB_INT_MAP_REG: u32 = 1072693524;
pub const DPORT_PRO_BT_BB_INT_MAP: u32 = 31;
pub const DPORT_PRO_BT_BB_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_BT_BB_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_BT_BB_NMI_MAP_REG: u32 = 1072693528;
pub const DPORT_PRO_BT_BB_NMI_MAP: u32 = 31;
pub const DPORT_PRO_BT_BB_NMI_MAP_V: u32 = 31;
pub const DPORT_PRO_BT_BB_NMI_MAP_S: u32 = 0;
pub const DPORT_PRO_RWBT_IRQ_MAP_REG: u32 = 1072693532;
pub const DPORT_PRO_RWBT_IRQ_MAP: u32 = 31;
pub const DPORT_PRO_RWBT_IRQ_MAP_V: u32 = 31;
pub const DPORT_PRO_RWBT_IRQ_MAP_S: u32 = 0;
pub const DPORT_PRO_RWBLE_IRQ_MAP_REG: u32 = 1072693536;
pub const DPORT_PRO_RWBLE_IRQ_MAP: u32 = 31;
pub const DPORT_PRO_RWBLE_IRQ_MAP_V: u32 = 31;
pub const DPORT_PRO_RWBLE_IRQ_MAP_S: u32 = 0;
pub const DPORT_PRO_RWBT_NMI_MAP_REG: u32 = 1072693540;
pub const DPORT_PRO_RWBT_NMI_MAP: u32 = 31;
pub const DPORT_PRO_RWBT_NMI_MAP_V: u32 = 31;
pub const DPORT_PRO_RWBT_NMI_MAP_S: u32 = 0;
pub const DPORT_PRO_RWBLE_NMI_MAP_REG: u32 = 1072693544;
pub const DPORT_PRO_RWBLE_NMI_MAP: u32 = 31;
pub const DPORT_PRO_RWBLE_NMI_MAP_V: u32 = 31;
pub const DPORT_PRO_RWBLE_NMI_MAP_S: u32 = 0;
pub const DPORT_PRO_SLC0_INTR_MAP_REG: u32 = 1072693548;
pub const DPORT_PRO_SLC0_INTR_MAP: u32 = 31;
pub const DPORT_PRO_SLC0_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_SLC0_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_SLC1_INTR_MAP_REG: u32 = 1072693552;
pub const DPORT_PRO_SLC1_INTR_MAP: u32 = 31;
pub const DPORT_PRO_SLC1_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_SLC1_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_UHCI0_INTR_MAP_REG: u32 = 1072693556;
pub const DPORT_PRO_UHCI0_INTR_MAP: u32 = 31;
pub const DPORT_PRO_UHCI0_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_UHCI0_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_UHCI1_INTR_MAP_REG: u32 = 1072693560;
pub const DPORT_PRO_UHCI1_INTR_MAP: u32 = 31;
pub const DPORT_PRO_UHCI1_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_UHCI1_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG: u32 = 1072693564;
pub const DPORT_PRO_TG_T0_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_T0_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_T0_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG: u32 = 1072693568;
pub const DPORT_PRO_TG_T1_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_T1_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_T1_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG: u32 = 1072693572;
pub const DPORT_PRO_TG_WDT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG: u32 = 1072693576;
pub const DPORT_PRO_TG_LACT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG: u32 = 1072693580;
pub const DPORT_PRO_TG1_T0_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG: u32 = 1072693584;
pub const DPORT_PRO_TG1_T1_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG: u32 = 1072693588;
pub const DPORT_PRO_TG1_WDT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG: u32 = 1072693592;
pub const DPORT_PRO_TG1_LACT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_GPIO_INTERRUPT_MAP_REG: u32 = 1072693596;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_MAP: u32 = 31;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V: u32 = 31;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S: u32 = 0;
pub const DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG: u32 = 1072693600;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP: u32 = 31;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V: u32 = 31;
pub const DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S: u32 = 0;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG: u32 = 1072693604;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S: u32 = 0;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG: u32 = 1072693608;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S: u32 = 0;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG: u32 = 1072693612;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S: u32 = 0;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG: u32 = 1072693616;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V: u32 = 31;
pub const DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI_INTR_0_MAP_REG: u32 = 1072693620;
pub const DPORT_PRO_SPI_INTR_0_MAP: u32 = 31;
pub const DPORT_PRO_SPI_INTR_0_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI_INTR_0_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI_INTR_1_MAP_REG: u32 = 1072693624;
pub const DPORT_PRO_SPI_INTR_1_MAP: u32 = 31;
pub const DPORT_PRO_SPI_INTR_1_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI_INTR_1_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI_INTR_2_MAP_REG: u32 = 1072693628;
pub const DPORT_PRO_SPI_INTR_2_MAP: u32 = 31;
pub const DPORT_PRO_SPI_INTR_2_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI_INTR_2_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI_INTR_3_MAP_REG: u32 = 1072693632;
pub const DPORT_PRO_SPI_INTR_3_MAP: u32 = 31;
pub const DPORT_PRO_SPI_INTR_3_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI_INTR_3_MAP_S: u32 = 0;
pub const DPORT_PRO_I2S0_INT_MAP_REG: u32 = 1072693636;
pub const DPORT_PRO_I2S0_INT_MAP: u32 = 31;
pub const DPORT_PRO_I2S0_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_I2S0_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_I2S1_INT_MAP_REG: u32 = 1072693640;
pub const DPORT_PRO_I2S1_INT_MAP: u32 = 31;
pub const DPORT_PRO_I2S1_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_I2S1_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_UART_INTR_MAP_REG: u32 = 1072693644;
pub const DPORT_PRO_UART_INTR_MAP: u32 = 31;
pub const DPORT_PRO_UART_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_UART_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_UART1_INTR_MAP_REG: u32 = 1072693648;
pub const DPORT_PRO_UART1_INTR_MAP: u32 = 31;
pub const DPORT_PRO_UART1_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_UART1_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_UART2_INTR_MAP_REG: u32 = 1072693652;
pub const DPORT_PRO_UART2_INTR_MAP: u32 = 31;
pub const DPORT_PRO_UART2_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_UART2_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG: u32 = 1072693656;
pub const DPORT_PRO_SDIO_HOST_INTERRUPT_MAP: u32 = 31;
pub const DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V: u32 = 31;
pub const DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S: u32 = 0;
pub const DPORT_PRO_EMAC_INT_MAP_REG: u32 = 1072693660;
pub const DPORT_PRO_EMAC_INT_MAP: u32 = 31;
pub const DPORT_PRO_EMAC_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_EMAC_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_PWM0_INTR_MAP_REG: u32 = 1072693664;
pub const DPORT_PRO_PWM0_INTR_MAP: u32 = 31;
pub const DPORT_PRO_PWM0_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_PWM0_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_PWM1_INTR_MAP_REG: u32 = 1072693668;
pub const DPORT_PRO_PWM1_INTR_MAP: u32 = 31;
pub const DPORT_PRO_PWM1_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_PWM1_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_PWM2_INTR_MAP_REG: u32 = 1072693672;
pub const DPORT_PRO_PWM2_INTR_MAP: u32 = 31;
pub const DPORT_PRO_PWM2_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_PWM2_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_PWM3_INTR_MAP_REG: u32 = 1072693676;
pub const DPORT_PRO_PWM3_INTR_MAP: u32 = 31;
pub const DPORT_PRO_PWM3_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_PWM3_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_LEDC_INT_MAP_REG: u32 = 1072693680;
pub const DPORT_PRO_LEDC_INT_MAP: u32 = 31;
pub const DPORT_PRO_LEDC_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_LEDC_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_EFUSE_INT_MAP_REG: u32 = 1072693684;
pub const DPORT_PRO_EFUSE_INT_MAP: u32 = 31;
pub const DPORT_PRO_EFUSE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_EFUSE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_CAN_INT_MAP_REG: u32 = 1072693688;
pub const DPORT_PRO_CAN_INT_MAP: u32 = 31;
pub const DPORT_PRO_CAN_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_CAN_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_RTC_CORE_INTR_MAP_REG: u32 = 1072693692;
pub const DPORT_PRO_RTC_CORE_INTR_MAP: u32 = 31;
pub const DPORT_PRO_RTC_CORE_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_RTC_CORE_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_RMT_INTR_MAP_REG: u32 = 1072693696;
pub const DPORT_PRO_RMT_INTR_MAP: u32 = 31;
pub const DPORT_PRO_RMT_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_RMT_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_PCNT_INTR_MAP_REG: u32 = 1072693700;
pub const DPORT_PRO_PCNT_INTR_MAP: u32 = 31;
pub const DPORT_PRO_PCNT_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_PCNT_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_I2C_EXT0_INTR_MAP_REG: u32 = 1072693704;
pub const DPORT_PRO_I2C_EXT0_INTR_MAP: u32 = 31;
pub const DPORT_PRO_I2C_EXT0_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_I2C_EXT0_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_I2C_EXT1_INTR_MAP_REG: u32 = 1072693708;
pub const DPORT_PRO_I2C_EXT1_INTR_MAP: u32 = 31;
pub const DPORT_PRO_I2C_EXT1_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_I2C_EXT1_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_RSA_INTR_MAP_REG: u32 = 1072693712;
pub const DPORT_PRO_RSA_INTR_MAP: u32 = 31;
pub const DPORT_PRO_RSA_INTR_MAP_V: u32 = 31;
pub const DPORT_PRO_RSA_INTR_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI1_DMA_INT_MAP_REG: u32 = 1072693716;
pub const DPORT_PRO_SPI1_DMA_INT_MAP: u32 = 31;
pub const DPORT_PRO_SPI1_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI1_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI2_DMA_INT_MAP_REG: u32 = 1072693720;
pub const DPORT_PRO_SPI2_DMA_INT_MAP: u32 = 31;
pub const DPORT_PRO_SPI2_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI2_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_SPI3_DMA_INT_MAP_REG: u32 = 1072693724;
pub const DPORT_PRO_SPI3_DMA_INT_MAP: u32 = 31;
pub const DPORT_PRO_SPI3_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_SPI3_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_WDG_INT_MAP_REG: u32 = 1072693728;
pub const DPORT_PRO_WDG_INT_MAP: u32 = 31;
pub const DPORT_PRO_WDG_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_WDG_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TIMER_INT1_MAP_REG: u32 = 1072693732;
pub const DPORT_PRO_TIMER_INT1_MAP: u32 = 31;
pub const DPORT_PRO_TIMER_INT1_MAP_V: u32 = 31;
pub const DPORT_PRO_TIMER_INT1_MAP_S: u32 = 0;
pub const DPORT_PRO_TIMER_INT2_MAP_REG: u32 = 1072693736;
pub const DPORT_PRO_TIMER_INT2_MAP: u32 = 31;
pub const DPORT_PRO_TIMER_INT2_MAP_V: u32 = 31;
pub const DPORT_PRO_TIMER_INT2_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_T0_EDGE_INT_MAP_REG: u32 = 1072693740;
pub const DPORT_PRO_TG_T0_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_T0_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_T0_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_T1_EDGE_INT_MAP_REG: u32 = 1072693744;
pub const DPORT_PRO_TG_T1_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_T1_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_T1_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG: u32 = 1072693748;
pub const DPORT_PRO_TG_WDT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_WDT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_WDT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG: u32 = 1072693752;
pub const DPORT_PRO_TG_LACT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG_LACT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG_LACT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG: u32 = 1072693756;
pub const DPORT_PRO_TG1_T0_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_T0_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_T0_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG: u32 = 1072693760;
pub const DPORT_PRO_TG1_T1_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_T1_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_T1_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG: u32 = 1072693764;
pub const DPORT_PRO_TG1_WDT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG: u32 = 1072693768;
pub const DPORT_PRO_TG1_LACT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_MMU_IA_INT_MAP_REG: u32 = 1072693772;
pub const DPORT_PRO_MMU_IA_INT_MAP: u32 = 31;
pub const DPORT_PRO_MMU_IA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_MMU_IA_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_MPU_IA_INT_MAP_REG: u32 = 1072693776;
pub const DPORT_PRO_MPU_IA_INT_MAP: u32 = 31;
pub const DPORT_PRO_MPU_IA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_MPU_IA_INT_MAP_S: u32 = 0;
pub const DPORT_PRO_CACHE_IA_INT_MAP_REG: u32 = 1072693780;
pub const DPORT_PRO_CACHE_IA_INT_MAP: u32 = 31;
pub const DPORT_PRO_CACHE_IA_INT_MAP_V: u32 = 31;
pub const DPORT_PRO_CACHE_IA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_MAC_INTR_MAP_REG: u32 = 1072693784;
pub const DPORT_APP_MAC_INTR_MAP: u32 = 31;
pub const DPORT_APP_MAC_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_MAC_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_MAC_NMI_MAP_REG: u32 = 1072693788;
pub const DPORT_APP_MAC_NMI_MAP: u32 = 31;
pub const DPORT_APP_MAC_NMI_MAP_V: u32 = 31;
pub const DPORT_APP_MAC_NMI_MAP_S: u32 = 0;
pub const DPORT_APP_BB_INT_MAP_REG: u32 = 1072693792;
pub const DPORT_APP_BB_INT_MAP: u32 = 31;
pub const DPORT_APP_BB_INT_MAP_V: u32 = 31;
pub const DPORT_APP_BB_INT_MAP_S: u32 = 0;
pub const DPORT_APP_BT_MAC_INT_MAP_REG: u32 = 1072693796;
pub const DPORT_APP_BT_MAC_INT_MAP: u32 = 31;
pub const DPORT_APP_BT_MAC_INT_MAP_V: u32 = 31;
pub const DPORT_APP_BT_MAC_INT_MAP_S: u32 = 0;
pub const DPORT_APP_BT_BB_INT_MAP_REG: u32 = 1072693800;
pub const DPORT_APP_BT_BB_INT_MAP: u32 = 31;
pub const DPORT_APP_BT_BB_INT_MAP_V: u32 = 31;
pub const DPORT_APP_BT_BB_INT_MAP_S: u32 = 0;
pub const DPORT_APP_BT_BB_NMI_MAP_REG: u32 = 1072693804;
pub const DPORT_APP_BT_BB_NMI_MAP: u32 = 31;
pub const DPORT_APP_BT_BB_NMI_MAP_V: u32 = 31;
pub const DPORT_APP_BT_BB_NMI_MAP_S: u32 = 0;
pub const DPORT_APP_RWBT_IRQ_MAP_REG: u32 = 1072693808;
pub const DPORT_APP_RWBT_IRQ_MAP: u32 = 31;
pub const DPORT_APP_RWBT_IRQ_MAP_V: u32 = 31;
pub const DPORT_APP_RWBT_IRQ_MAP_S: u32 = 0;
pub const DPORT_APP_RWBLE_IRQ_MAP_REG: u32 = 1072693812;
pub const DPORT_APP_RWBLE_IRQ_MAP: u32 = 31;
pub const DPORT_APP_RWBLE_IRQ_MAP_V: u32 = 31;
pub const DPORT_APP_RWBLE_IRQ_MAP_S: u32 = 0;
pub const DPORT_APP_RWBT_NMI_MAP_REG: u32 = 1072693816;
pub const DPORT_APP_RWBT_NMI_MAP: u32 = 31;
pub const DPORT_APP_RWBT_NMI_MAP_V: u32 = 31;
pub const DPORT_APP_RWBT_NMI_MAP_S: u32 = 0;
pub const DPORT_APP_RWBLE_NMI_MAP_REG: u32 = 1072693820;
pub const DPORT_APP_RWBLE_NMI_MAP: u32 = 31;
pub const DPORT_APP_RWBLE_NMI_MAP_V: u32 = 31;
pub const DPORT_APP_RWBLE_NMI_MAP_S: u32 = 0;
pub const DPORT_APP_SLC0_INTR_MAP_REG: u32 = 1072693824;
pub const DPORT_APP_SLC0_INTR_MAP: u32 = 31;
pub const DPORT_APP_SLC0_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_SLC0_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_SLC1_INTR_MAP_REG: u32 = 1072693828;
pub const DPORT_APP_SLC1_INTR_MAP: u32 = 31;
pub const DPORT_APP_SLC1_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_SLC1_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_UHCI0_INTR_MAP_REG: u32 = 1072693832;
pub const DPORT_APP_UHCI0_INTR_MAP: u32 = 31;
pub const DPORT_APP_UHCI0_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_UHCI0_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_UHCI1_INTR_MAP_REG: u32 = 1072693836;
pub const DPORT_APP_UHCI1_INTR_MAP: u32 = 31;
pub const DPORT_APP_UHCI1_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_UHCI1_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_TG_T0_LEVEL_INT_MAP_REG: u32 = 1072693840;
pub const DPORT_APP_TG_T0_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_T0_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_T0_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_T1_LEVEL_INT_MAP_REG: u32 = 1072693844;
pub const DPORT_APP_TG_T1_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_T1_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_T1_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG: u32 = 1072693848;
pub const DPORT_APP_TG_WDT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_WDT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_WDT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG: u32 = 1072693852;
pub const DPORT_APP_TG_LACT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_LACT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_LACT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG: u32 = 1072693856;
pub const DPORT_APP_TG1_T0_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_T0_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_T0_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG: u32 = 1072693860;
pub const DPORT_APP_TG1_T1_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_T1_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_T1_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG: u32 = 1072693864;
pub const DPORT_APP_TG1_WDT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG: u32 = 1072693868;
pub const DPORT_APP_TG1_LACT_LEVEL_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S: u32 = 0;
pub const DPORT_APP_GPIO_INTERRUPT_MAP_REG: u32 = 1072693872;
pub const DPORT_APP_GPIO_INTERRUPT_APP_MAP: u32 = 31;
pub const DPORT_APP_GPIO_INTERRUPT_APP_MAP_V: u32 = 31;
pub const DPORT_APP_GPIO_INTERRUPT_APP_MAP_S: u32 = 0;
pub const DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG: u32 = 1072693876;
pub const DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP: u32 = 31;
pub const DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V: u32 = 31;
pub const DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S: u32 = 0;
pub const DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG: u32 = 1072693880;
pub const DPORT_APP_CPU_INTR_FROM_CPU_0_MAP: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S: u32 = 0;
pub const DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG: u32 = 1072693884;
pub const DPORT_APP_CPU_INTR_FROM_CPU_1_MAP: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S: u32 = 0;
pub const DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG: u32 = 1072693888;
pub const DPORT_APP_CPU_INTR_FROM_CPU_2_MAP: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S: u32 = 0;
pub const DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG: u32 = 1072693892;
pub const DPORT_APP_CPU_INTR_FROM_CPU_3_MAP: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V: u32 = 31;
pub const DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S: u32 = 0;
pub const DPORT_APP_SPI_INTR_0_MAP_REG: u32 = 1072693896;
pub const DPORT_APP_SPI_INTR_0_MAP: u32 = 31;
pub const DPORT_APP_SPI_INTR_0_MAP_V: u32 = 31;
pub const DPORT_APP_SPI_INTR_0_MAP_S: u32 = 0;
pub const DPORT_APP_SPI_INTR_1_MAP_REG: u32 = 1072693900;
pub const DPORT_APP_SPI_INTR_1_MAP: u32 = 31;
pub const DPORT_APP_SPI_INTR_1_MAP_V: u32 = 31;
pub const DPORT_APP_SPI_INTR_1_MAP_S: u32 = 0;
pub const DPORT_APP_SPI_INTR_2_MAP_REG: u32 = 1072693904;
pub const DPORT_APP_SPI_INTR_2_MAP: u32 = 31;
pub const DPORT_APP_SPI_INTR_2_MAP_V: u32 = 31;
pub const DPORT_APP_SPI_INTR_2_MAP_S: u32 = 0;
pub const DPORT_APP_SPI_INTR_3_MAP_REG: u32 = 1072693908;
pub const DPORT_APP_SPI_INTR_3_MAP: u32 = 31;
pub const DPORT_APP_SPI_INTR_3_MAP_V: u32 = 31;
pub const DPORT_APP_SPI_INTR_3_MAP_S: u32 = 0;
pub const DPORT_APP_I2S0_INT_MAP_REG: u32 = 1072693912;
pub const DPORT_APP_I2S0_INT_MAP: u32 = 31;
pub const DPORT_APP_I2S0_INT_MAP_V: u32 = 31;
pub const DPORT_APP_I2S0_INT_MAP_S: u32 = 0;
pub const DPORT_APP_I2S1_INT_MAP_REG: u32 = 1072693916;
pub const DPORT_APP_I2S1_INT_MAP: u32 = 31;
pub const DPORT_APP_I2S1_INT_MAP_V: u32 = 31;
pub const DPORT_APP_I2S1_INT_MAP_S: u32 = 0;
pub const DPORT_APP_UART_INTR_MAP_REG: u32 = 1072693920;
pub const DPORT_APP_UART_INTR_MAP: u32 = 31;
pub const DPORT_APP_UART_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_UART_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_UART1_INTR_MAP_REG: u32 = 1072693924;
pub const DPORT_APP_UART1_INTR_MAP: u32 = 31;
pub const DPORT_APP_UART1_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_UART1_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_UART2_INTR_MAP_REG: u32 = 1072693928;
pub const DPORT_APP_UART2_INTR_MAP: u32 = 31;
pub const DPORT_APP_UART2_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_UART2_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG: u32 = 1072693932;
pub const DPORT_APP_SDIO_HOST_INTERRUPT_MAP: u32 = 31;
pub const DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V: u32 = 31;
pub const DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S: u32 = 0;
pub const DPORT_APP_EMAC_INT_MAP_REG: u32 = 1072693936;
pub const DPORT_APP_EMAC_INT_MAP: u32 = 31;
pub const DPORT_APP_EMAC_INT_MAP_V: u32 = 31;
pub const DPORT_APP_EMAC_INT_MAP_S: u32 = 0;
pub const DPORT_APP_PWM0_INTR_MAP_REG: u32 = 1072693940;
pub const DPORT_APP_PWM0_INTR_MAP: u32 = 31;
pub const DPORT_APP_PWM0_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_PWM0_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_PWM1_INTR_MAP_REG: u32 = 1072693944;
pub const DPORT_APP_PWM1_INTR_MAP: u32 = 31;
pub const DPORT_APP_PWM1_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_PWM1_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_PWM2_INTR_MAP_REG: u32 = 1072693948;
pub const DPORT_APP_PWM2_INTR_MAP: u32 = 31;
pub const DPORT_APP_PWM2_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_PWM2_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_PWM3_INTR_MAP_REG: u32 = 1072693952;
pub const DPORT_APP_PWM3_INTR_MAP: u32 = 31;
pub const DPORT_APP_PWM3_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_PWM3_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_LEDC_INT_MAP_REG: u32 = 1072693956;
pub const DPORT_APP_LEDC_INT_MAP: u32 = 31;
pub const DPORT_APP_LEDC_INT_MAP_V: u32 = 31;
pub const DPORT_APP_LEDC_INT_MAP_S: u32 = 0;
pub const DPORT_APP_EFUSE_INT_MAP_REG: u32 = 1072693960;
pub const DPORT_APP_EFUSE_INT_MAP: u32 = 31;
pub const DPORT_APP_EFUSE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_EFUSE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_CAN_INT_MAP_REG: u32 = 1072693964;
pub const DPORT_APP_CAN_INT_MAP: u32 = 31;
pub const DPORT_APP_CAN_INT_MAP_V: u32 = 31;
pub const DPORT_APP_CAN_INT_MAP_S: u32 = 0;
pub const DPORT_APP_RTC_CORE_INTR_MAP_REG: u32 = 1072693968;
pub const DPORT_APP_RTC_CORE_INTR_MAP: u32 = 31;
pub const DPORT_APP_RTC_CORE_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_RTC_CORE_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_RMT_INTR_MAP_REG: u32 = 1072693972;
pub const DPORT_APP_RMT_INTR_MAP: u32 = 31;
pub const DPORT_APP_RMT_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_RMT_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_PCNT_INTR_MAP_REG: u32 = 1072693976;
pub const DPORT_APP_PCNT_INTR_MAP: u32 = 31;
pub const DPORT_APP_PCNT_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_PCNT_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_I2C_EXT0_INTR_MAP_REG: u32 = 1072693980;
pub const DPORT_APP_I2C_EXT0_INTR_MAP: u32 = 31;
pub const DPORT_APP_I2C_EXT0_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_I2C_EXT0_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_I2C_EXT1_INTR_MAP_REG: u32 = 1072693984;
pub const DPORT_APP_I2C_EXT1_INTR_MAP: u32 = 31;
pub const DPORT_APP_I2C_EXT1_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_I2C_EXT1_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_RSA_INTR_MAP_REG: u32 = 1072693988;
pub const DPORT_APP_RSA_INTR_MAP: u32 = 31;
pub const DPORT_APP_RSA_INTR_MAP_V: u32 = 31;
pub const DPORT_APP_RSA_INTR_MAP_S: u32 = 0;
pub const DPORT_APP_SPI1_DMA_INT_MAP_REG: u32 = 1072693992;
pub const DPORT_APP_SPI1_DMA_INT_MAP: u32 = 31;
pub const DPORT_APP_SPI1_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_SPI1_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_SPI2_DMA_INT_MAP_REG: u32 = 1072693996;
pub const DPORT_APP_SPI2_DMA_INT_MAP: u32 = 31;
pub const DPORT_APP_SPI2_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_SPI2_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_SPI3_DMA_INT_MAP_REG: u32 = 1072694000;
pub const DPORT_APP_SPI3_DMA_INT_MAP: u32 = 31;
pub const DPORT_APP_SPI3_DMA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_SPI3_DMA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_WDG_INT_MAP_REG: u32 = 1072694004;
pub const DPORT_APP_WDG_INT_MAP: u32 = 31;
pub const DPORT_APP_WDG_INT_MAP_V: u32 = 31;
pub const DPORT_APP_WDG_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TIMER_INT1_MAP_REG: u32 = 1072694008;
pub const DPORT_APP_TIMER_INT1_MAP: u32 = 31;
pub const DPORT_APP_TIMER_INT1_MAP_V: u32 = 31;
pub const DPORT_APP_TIMER_INT1_MAP_S: u32 = 0;
pub const DPORT_APP_TIMER_INT2_MAP_REG: u32 = 1072694012;
pub const DPORT_APP_TIMER_INT2_MAP: u32 = 31;
pub const DPORT_APP_TIMER_INT2_MAP_V: u32 = 31;
pub const DPORT_APP_TIMER_INT2_MAP_S: u32 = 0;
pub const DPORT_APP_TG_T0_EDGE_INT_MAP_REG: u32 = 1072694016;
pub const DPORT_APP_TG_T0_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_T0_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_T0_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_T1_EDGE_INT_MAP_REG: u32 = 1072694020;
pub const DPORT_APP_TG_T1_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_T1_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_T1_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_WDT_EDGE_INT_MAP_REG: u32 = 1072694024;
pub const DPORT_APP_TG_WDT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_WDT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_WDT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG_LACT_EDGE_INT_MAP_REG: u32 = 1072694028;
pub const DPORT_APP_TG_LACT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG_LACT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG_LACT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_T0_EDGE_INT_MAP_REG: u32 = 1072694032;
pub const DPORT_APP_TG1_T0_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_T0_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_T0_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_T1_EDGE_INT_MAP_REG: u32 = 1072694036;
pub const DPORT_APP_TG1_T1_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_T1_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_T1_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG: u32 = 1072694040;
pub const DPORT_APP_TG1_WDT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_WDT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_WDT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG: u32 = 1072694044;
pub const DPORT_APP_TG1_LACT_EDGE_INT_MAP: u32 = 31;
pub const DPORT_APP_TG1_LACT_EDGE_INT_MAP_V: u32 = 31;
pub const DPORT_APP_TG1_LACT_EDGE_INT_MAP_S: u32 = 0;
pub const DPORT_APP_MMU_IA_INT_MAP_REG: u32 = 1072694048;
pub const DPORT_APP_MMU_IA_INT_MAP: u32 = 31;
pub const DPORT_APP_MMU_IA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_MMU_IA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_MPU_IA_INT_MAP_REG: u32 = 1072694052;
pub const DPORT_APP_MPU_IA_INT_MAP: u32 = 31;
pub const DPORT_APP_MPU_IA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_MPU_IA_INT_MAP_S: u32 = 0;
pub const DPORT_APP_CACHE_IA_INT_MAP_REG: u32 = 1072694056;
pub const DPORT_APP_CACHE_IA_INT_MAP: u32 = 31;
pub const DPORT_APP_CACHE_IA_INT_MAP_V: u32 = 31;
pub const DPORT_APP_CACHE_IA_INT_MAP_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_UART_REG: u32 = 1072694060;
pub const DPORT_UART_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_UART_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_UART_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SPI1_REG: u32 = 1072694064;
pub const DPORT_SPI1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SPI1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SPI1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SPI0_REG: u32 = 1072694068;
pub const DPORT_SPI0_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SPI0_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SPI0_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_GPIO_REG: u32 = 1072694072;
pub const DPORT_GPIO_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_GPIO_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_GPIO_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_FE2_REG: u32 = 1072694076;
pub const DPORT_FE2_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_FE2_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_FE2_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_FE_REG: u32 = 1072694080;
pub const DPORT_FE_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_FE_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_FE_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_TIMER_REG: u32 = 1072694084;
pub const DPORT_TIMER_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_TIMER_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_TIMER_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_RTC_REG: u32 = 1072694088;
pub const DPORT_RTC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_RTC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_RTC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG: u32 = 1072694092;
pub const DPORT_IOMUX_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_IOMUX_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_IOMUX_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_WDG_REG: u32 = 1072694096;
pub const DPORT_WDG_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_WDG_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_WDG_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_HINF_REG: u32 = 1072694100;
pub const DPORT_HINF_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_HINF_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_HINF_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_UHCI1_REG: u32 = 1072694104;
pub const DPORT_UHCI1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_UHCI1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_UHCI1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_MISC_REG: u32 = 1072694108;
pub const DPORT_MISC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_MISC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_MISC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_I2C_REG: u32 = 1072694112;
pub const DPORT_I2C_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_I2C_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_I2C_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_I2S0_REG: u32 = 1072694116;
pub const DPORT_I2S0_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_I2S0_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_I2S0_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_UART1_REG: u32 = 1072694120;
pub const DPORT_UART1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_UART1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_UART1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_BT_REG: u32 = 1072694124;
pub const DPORT_BT_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_BT_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_BT_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG: u32 = 1072694128;
pub const DPORT_BTBUFFER_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG: u32 = 1072694132;
pub const DPORT_I2CEXT0_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_UHCI0_REG: u32 = 1072694136;
pub const DPORT_UHCI0_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_UHCI0_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_UHCI0_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG: u32 = 1072694140;
pub const DPORT_SLCHOST_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_RMT_REG: u32 = 1072694144;
pub const DPORT_RMT_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_RMT_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_RMT_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PCNT_REG: u32 = 1072694148;
pub const DPORT_PCNT_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PCNT_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PCNT_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SLC_REG: u32 = 1072694152;
pub const DPORT_SLC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SLC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SLC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_LEDC_REG: u32 = 1072694156;
pub const DPORT_LEDC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_LEDC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_LEDC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_EFUSE_REG: u32 = 1072694160;
pub const DPORT_EFUSE_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_EFUSE_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_EFUSE_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG: u32 = 1072694164;
pub const DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_BB_REG: u32 = 1072694168;
pub const DPORT_BB_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_BB_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_BB_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PWM0_REG: u32 = 1072694172;
pub const DPORT_PWM0_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PWM0_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PWM0_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG: u32 = 1072694176;
pub const DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG: u32 = 1072694180;
pub const DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SPI2_REG: u32 = 1072694184;
pub const DPORT_SPI2_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SPI2_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SPI2_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SPI3_REG: u32 = 1072694188;
pub const DPORT_SPI3_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SPI3_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SPI3_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG: u32 = 1072694192;
pub const DPORT_APBCTRL_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG: u32 = 1072694196;
pub const DPORT_I2CEXT1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG: u32 = 1072694200;
pub const DPORT_SDIOHOST_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_EMAC_REG: u32 = 1072694204;
pub const DPORT_EMAC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_EMAC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_EMAC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_CAN_REG: u32 = 1072694208;
pub const DPORT_CAN_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_CAN_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_CAN_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PWM1_REG: u32 = 1072694212;
pub const DPORT_PWM1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PWM1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PWM1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_I2S1_REG: u32 = 1072694216;
pub const DPORT_I2S1_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_I2S1_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_I2S1_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_UART2_REG: u32 = 1072694220;
pub const DPORT_UART2_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_UART2_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_UART2_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PWM2_REG: u32 = 1072694224;
pub const DPORT_PWM2_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PWM2_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PWM2_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PWM3_REG: u32 = 1072694228;
pub const DPORT_PWM3_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PWM3_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PWM3_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_RWBT_REG: u32 = 1072694232;
pub const DPORT_RWBT_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_RWBT_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_RWBT_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_BTMAC_REG: u32 = 1072694236;
pub const DPORT_BTMAC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_BTMAC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_BTMAC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG: u32 = 1072694240;
pub const DPORT_WIFIMAC_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_AHBLITE_MPU_TABLE_PWR_REG: u32 = 1072694244;
pub const DPORT_PWR_ACCESS_GRANT_CONFIG: u32 = 63;
pub const DPORT_PWR_ACCESS_GRANT_CONFIG_V: u32 = 63;
pub const DPORT_PWR_ACCESS_GRANT_CONFIG_S: u32 = 0;
pub const DPORT_MEM_ACCESS_DBUG0_REG: u32 = 1072694248;
pub const DPORT_INTERNAL_SRAM_MMU_MULTI_HIT: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S: u32 = 26;
pub const DPORT_INTERNAL_SRAM_IA: u32 = 4095;
pub const DPORT_INTERNAL_SRAM_IA_V: u32 = 4095;
pub const DPORT_INTERNAL_SRAM_IA_S: u32 = 14;
pub const DPORT_INTERNAL_SRAM_MMU_AD: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_AD_V: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_AD_S: u32 = 10;
pub const DPORT_SHARE_ROM_IA: u32 = 15;
pub const DPORT_SHARE_ROM_IA_V: u32 = 15;
pub const DPORT_SHARE_ROM_IA_S: u32 = 6;
pub const DPORT_SHARE_ROM_MPU_AD: u32 = 3;
pub const DPORT_SHARE_ROM_MPU_AD_V: u32 = 3;
pub const DPORT_SHARE_ROM_MPU_AD_S: u32 = 4;
pub const DPORT_APP_ROM_IA_V: u32 = 1;
pub const DPORT_APP_ROM_IA_S: u32 = 3;
pub const DPORT_APP_ROM_MPU_AD_V: u32 = 1;
pub const DPORT_APP_ROM_MPU_AD_S: u32 = 2;
pub const DPORT_PRO_ROM_IA_V: u32 = 1;
pub const DPORT_PRO_ROM_IA_S: u32 = 1;
pub const DPORT_PRO_ROM_MPU_AD_V: u32 = 1;
pub const DPORT_PRO_ROM_MPU_AD_S: u32 = 0;
pub const DPORT_MEM_ACCESS_DBUG1_REG: u32 = 1072694252;
pub const DPORT_AHBLITE_IA_V: u32 = 1;
pub const DPORT_AHBLITE_IA_S: u32 = 10;
pub const DPORT_AHBLITE_ACCESS_DENY_V: u32 = 1;
pub const DPORT_AHBLITE_ACCESS_DENY_S: u32 = 9;
pub const DPORT_AHB_ACCESS_DENY_V: u32 = 1;
pub const DPORT_AHB_ACCESS_DENY_S: u32 = 8;
pub const DPORT_PIDGEN_IA: u32 = 3;
pub const DPORT_PIDGEN_IA_V: u32 = 3;
pub const DPORT_PIDGEN_IA_S: u32 = 6;
pub const DPORT_ARB_IA: u32 = 3;
pub const DPORT_ARB_IA_V: u32 = 3;
pub const DPORT_ARB_IA_S: u32 = 4;
pub const DPORT_INTERNAL_SRAM_MMU_MISS: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_MISS_V: u32 = 15;
pub const DPORT_INTERNAL_SRAM_MMU_MISS_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG0_REG: u32 = 1072694256;
pub const DPORT_PRO_RX_END_V: u32 = 1;
pub const DPORT_PRO_RX_END_S: u32 = 23;
pub const DPORT_PRO_SLAVE_WDATA_V_V: u32 = 1;
pub const DPORT_PRO_SLAVE_WDATA_V_S: u32 = 22;
pub const DPORT_PRO_SLAVE_WR_V: u32 = 1;
pub const DPORT_PRO_SLAVE_WR_S: u32 = 21;
pub const DPORT_PRO_TX_END_V: u32 = 1;
pub const DPORT_PRO_TX_END_S: u32 = 20;
pub const DPORT_PRO_WR_BAK_TO_READ_V: u32 = 1;
pub const DPORT_PRO_WR_BAK_TO_READ_S: u32 = 19;
pub const DPORT_PRO_CACHE_STATE: u32 = 4095;
pub const DPORT_PRO_CACHE_STATE_V: u32 = 4095;
pub const DPORT_PRO_CACHE_STATE_S: u32 = 7;
pub const DPORT_PRO_CACHE_IA: u32 = 63;
pub const DPORT_PRO_CACHE_IA_V: u32 = 63;
pub const DPORT_PRO_CACHE_IA_S: u32 = 1;
pub const DPORT_PRO_CACHE_MMU_IA_V: u32 = 1;
pub const DPORT_PRO_CACHE_MMU_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG1_REG: u32 = 1072694260;
pub const DPORT_PRO_CTAG_RAM_RDATA: u32 = 4294967295;
pub const DPORT_PRO_CTAG_RAM_RDATA_V: u32 = 4294967295;
pub const DPORT_PRO_CTAG_RAM_RDATA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG2_REG: u32 = 1072694264;
pub const DPORT_PRO_CACHE_VADDR: u32 = 134217727;
pub const DPORT_PRO_CACHE_VADDR_V: u32 = 134217727;
pub const DPORT_PRO_CACHE_VADDR_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG3_REG: u32 = 1072694268;
pub const DPORT_PRO_CACHE_IRAM0_PID_ERROR_V: u32 = 1;
pub const DPORT_PRO_CACHE_IRAM0_PID_ERROR_S: u32 = 15;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA: u32 = 63;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_V: u32 = 63;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_S: u32 = 9;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S: u32 = 9;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S: u32 = 10;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S: u32 = 11;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S: u32 = 12;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S: u32 = 13;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V: u32 = 1;
pub const DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S: u32 = 14;
pub const DPORT_PRO_MMU_RDATA: u32 = 511;
pub const DPORT_PRO_MMU_RDATA_V: u32 = 511;
pub const DPORT_PRO_MMU_RDATA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG4_REG: u32 = 1072694272;
pub const DPORT_PRO_DRAM1ADDR0_IA: u32 = 1048575;
pub const DPORT_PRO_DRAM1ADDR0_IA_V: u32 = 1048575;
pub const DPORT_PRO_DRAM1ADDR0_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG5_REG: u32 = 1072694276;
pub const DPORT_PRO_DROM0ADDR0_IA: u32 = 1048575;
pub const DPORT_PRO_DROM0ADDR0_IA_V: u32 = 1048575;
pub const DPORT_PRO_DROM0ADDR0_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG6_REG: u32 = 1072694280;
pub const DPORT_PRO_IRAM0ADDR_IA: u32 = 1048575;
pub const DPORT_PRO_IRAM0ADDR_IA_V: u32 = 1048575;
pub const DPORT_PRO_IRAM0ADDR_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG7_REG: u32 = 1072694284;
pub const DPORT_PRO_IRAM1ADDR_IA: u32 = 1048575;
pub const DPORT_PRO_IRAM1ADDR_IA_V: u32 = 1048575;
pub const DPORT_PRO_IRAM1ADDR_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG8_REG: u32 = 1072694288;
pub const DPORT_PRO_IROM0ADDR_IA: u32 = 1048575;
pub const DPORT_PRO_IROM0ADDR_IA_V: u32 = 1048575;
pub const DPORT_PRO_IROM0ADDR_IA_S: u32 = 0;
pub const DPORT_PRO_DCACHE_DBUG9_REG: u32 = 1072694292;
pub const DPORT_PRO_OPSDRAMADDR_IA: u32 = 1048575;
pub const DPORT_PRO_OPSDRAMADDR_IA_V: u32 = 1048575;
pub const DPORT_PRO_OPSDRAMADDR_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG0_REG: u32 = 1072694296;
pub const DPORT_APP_RX_END_V: u32 = 1;
pub const DPORT_APP_RX_END_S: u32 = 23;
pub const DPORT_APP_SLAVE_WDATA_V_V: u32 = 1;
pub const DPORT_APP_SLAVE_WDATA_V_S: u32 = 22;
pub const DPORT_APP_SLAVE_WR_V: u32 = 1;
pub const DPORT_APP_SLAVE_WR_S: u32 = 21;
pub const DPORT_APP_TX_END_V: u32 = 1;
pub const DPORT_APP_TX_END_S: u32 = 20;
pub const DPORT_APP_WR_BAK_TO_READ_V: u32 = 1;
pub const DPORT_APP_WR_BAK_TO_READ_S: u32 = 19;
pub const DPORT_APP_CACHE_STATE: u32 = 4095;
pub const DPORT_APP_CACHE_STATE_V: u32 = 4095;
pub const DPORT_APP_CACHE_STATE_S: u32 = 7;
pub const DPORT_APP_CACHE_IA: u32 = 63;
pub const DPORT_APP_CACHE_IA_V: u32 = 63;
pub const DPORT_APP_CACHE_IA_S: u32 = 1;
pub const DPORT_APP_CACHE_MMU_IA_V: u32 = 1;
pub const DPORT_APP_CACHE_MMU_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG1_REG: u32 = 1072694300;
pub const DPORT_APP_CTAG_RAM_RDATA: u32 = 4294967295;
pub const DPORT_APP_CTAG_RAM_RDATA_V: u32 = 4294967295;
pub const DPORT_APP_CTAG_RAM_RDATA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG2_REG: u32 = 1072694304;
pub const DPORT_APP_CACHE_VADDR: u32 = 134217727;
pub const DPORT_APP_CACHE_VADDR_V: u32 = 134217727;
pub const DPORT_APP_CACHE_VADDR_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG3_REG: u32 = 1072694308;
pub const DPORT_APP_CACHE_IRAM0_PID_ERROR_V: u32 = 1;
pub const DPORT_APP_CACHE_IRAM0_PID_ERROR_S: u32 = 15;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA: u32 = 63;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_V: u32 = 63;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_S: u32 = 9;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S: u32 = 9;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S: u32 = 10;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S: u32 = 11;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S: u32 = 12;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S: u32 = 13;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V: u32 = 1;
pub const DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S: u32 = 14;
pub const DPORT_APP_MMU_RDATA: u32 = 511;
pub const DPORT_APP_MMU_RDATA_V: u32 = 511;
pub const DPORT_APP_MMU_RDATA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG4_REG: u32 = 1072694312;
pub const DPORT_APP_DRAM1ADDR0_IA: u32 = 1048575;
pub const DPORT_APP_DRAM1ADDR0_IA_V: u32 = 1048575;
pub const DPORT_APP_DRAM1ADDR0_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG5_REG: u32 = 1072694316;
pub const DPORT_APP_DROM0ADDR0_IA: u32 = 1048575;
pub const DPORT_APP_DROM0ADDR0_IA_V: u32 = 1048575;
pub const DPORT_APP_DROM0ADDR0_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG6_REG: u32 = 1072694320;
pub const DPORT_APP_IRAM0ADDR_IA: u32 = 1048575;
pub const DPORT_APP_IRAM0ADDR_IA_V: u32 = 1048575;
pub const DPORT_APP_IRAM0ADDR_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG7_REG: u32 = 1072694324;
pub const DPORT_APP_IRAM1ADDR_IA: u32 = 1048575;
pub const DPORT_APP_IRAM1ADDR_IA_V: u32 = 1048575;
pub const DPORT_APP_IRAM1ADDR_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG8_REG: u32 = 1072694328;
pub const DPORT_APP_IROM0ADDR_IA: u32 = 1048575;
pub const DPORT_APP_IROM0ADDR_IA_V: u32 = 1048575;
pub const DPORT_APP_IROM0ADDR_IA_S: u32 = 0;
pub const DPORT_APP_DCACHE_DBUG9_REG: u32 = 1072694332;
pub const DPORT_APP_OPSDRAMADDR_IA: u32 = 1048575;
pub const DPORT_APP_OPSDRAMADDR_IA_V: u32 = 1048575;
pub const DPORT_APP_OPSDRAMADDR_IA_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_CTRL_REG: u32 = 1072694336;
pub const DPORT_PRO_CPU_PDEBUG_ENABLE_V: u32 = 1;
pub const DPORT_PRO_CPU_PDEBUG_ENABLE_S: u32 = 8;
pub const DPORT_PRO_CPU_RECORD_DISABLE_V: u32 = 1;
pub const DPORT_PRO_CPU_RECORD_DISABLE_S: u32 = 4;
pub const DPORT_PRO_CPU_RECORD_ENABLE_V: u32 = 1;
pub const DPORT_PRO_CPU_RECORD_ENABLE_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_STATUS_REG: u32 = 1072694340;
pub const DPORT_PRO_CPU_RECORDING_V: u32 = 1;
pub const DPORT_PRO_CPU_RECORDING_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_PID_REG: u32 = 1072694344;
pub const DPORT_RECORD_PRO_PID: u32 = 7;
pub const DPORT_RECORD_PRO_PID_V: u32 = 7;
pub const DPORT_RECORD_PRO_PID_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_PDEBUGINST_REG: u32 = 1072694348;
pub const DPORT_RECORD_PRO_PDEBUGINST: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGINST_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGINST_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGINST_SZ_V: u32 = 255;
pub const DPORT_RECORD_PDEBUGINST_SZ_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGINST_ISRC_V: u32 = 7;
pub const DPORT_RECORD_PDEBUGINST_ISRC_S: u32 = 12;
pub const DPORT_RECORD_PDEBUGINST_CINTL_V: u32 = 15;
pub const DPORT_RECORD_PDEBUGINST_CINTL_S: u32 = 24;
pub const DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG: u32 = 1072694352;
pub const DPORT_RECORD_PRO_PDEBUGSTATUS: u32 = 255;
pub const DPORT_RECORD_PRO_PDEBUGSTATUS_V: u32 = 255;
pub const DPORT_RECORD_PRO_PDEBUGSTATUS_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V: u32 = 63;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO: u32 = 0;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP: u32 = 2;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL: u32 = 4;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM: u32 = 8;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM: u32 = 12;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0: u32 = 16;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1: u32 = 17;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL: u32 = 20;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB: u32 = 24;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM: u32 = 26;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB: u32 = 28;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM: u32 = 30;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL: u32 = 32;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC: u32 = 36;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI: u32 = 40;
pub const DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER: u32 = 60;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V: u32 = 63;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX: u32 = 0;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX: u32 = 4;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET: u32 = 8;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET: u32 = 12;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B: u32 = 16;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J: u32 = 20;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL: u32 = 24;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN: u32 = 28;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP: u32 = 32;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I: u32 = 36;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB: u32 = 40;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID: u32 = 44;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR: u32 = 48;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER: u32 = 52;
pub const DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF: u32 = 60;
pub const DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG: u32 = 1072694356;
pub const DPORT_RECORD_PRO_PDEBUGDATA: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGDATA_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGDATA_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V: u32 = 63;
pub const DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S: u32 = 16;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_M: u32 = 4128768;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_V: u32 = 31;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE: u32 = 0;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_RST: u32 = 1;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG: u32 = 2;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI: u32 = 3;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_USR: u32 = 4;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL: u32 = 5;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL: u32 = 6;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM: u32 = 7;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4: u32 = 10;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4: u32 = 11;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8: u32 = 12;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8: u32 = 13;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12: u32 = 14;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12: u32 = 15;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2: u32 = 16;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3: u32 = 17;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4: u32 = 18;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5: u32 = 19;
pub const DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6: u32 = 20;
pub const DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V: u32 = 255;
pub const DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V: u32 = 4095;
pub const DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S: u32 = 2;
pub const DPORT_PRO_CPU_RECORD_PDEBUGPC_REG: u32 = 1072694360;
pub const DPORT_RECORD_PRO_PDEBUGPC: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGPC_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGPC_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG: u32 = 1072694364;
pub const DPORT_RECORD_PRO_PDEBUGLS0STAT: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0STAT_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0STAT_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_V: u32 = 15;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_S: u32 = 0;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE: u32 = 0;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR: u32 = 1;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR: u32 = 2;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD: u32 = 5;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR: u32 = 6;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R: u32 = 8;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1: u32 = 10;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI: u32 = 12;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR: u32 = 14;
pub const DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER: u32 = 15;
pub const DPORT_RECORD_PDEBUGLS0STAT_SZ_V: u32 = 15;
pub const DPORT_RECORD_PDEBUGLS0STAT_SZ_S: u32 = 4;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_V: u32 = 3;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_S: u32 = 17;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE: u32 = 0;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED: u32 = 1;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL: u32 = 2;
pub const DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD: u32 = 3;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_V: u32 = 15;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_S: u32 = 20;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT: u32 = 0;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0: u32 = 2;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1: u32 = 3;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0: u32 = 4;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1: u32 = 5;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0: u32 = 10;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1: u32 = 11;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0: u32 = 14;
pub const DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1: u32 = 15;
pub const DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG: u32 = 1072694368;
pub const DPORT_RECORD_PRO_PDEBUGLS0ADDR: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0ADDR_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0ADDR_S: u32 = 0;
pub const DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG: u32 = 1072694372;
pub const DPORT_RECORD_PRO_PDEBUGLS0DATA: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0DATA_V: u32 = 4294967295;
pub const DPORT_RECORD_PRO_PDEBUGLS0DATA_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_CTRL_REG: u32 = 1072694376;
pub const DPORT_APP_CPU_PDEBUG_ENABLE_V: u32 = 1;
pub const DPORT_APP_CPU_PDEBUG_ENABLE_S: u32 = 8;
pub const DPORT_APP_CPU_RECORD_DISABLE_V: u32 = 1;
pub const DPORT_APP_CPU_RECORD_DISABLE_S: u32 = 4;
pub const DPORT_APP_CPU_RECORD_ENABLE_V: u32 = 1;
pub const DPORT_APP_CPU_RECORD_ENABLE_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_STATUS_REG: u32 = 1072694380;
pub const DPORT_APP_CPU_RECORDING_V: u32 = 1;
pub const DPORT_APP_CPU_RECORDING_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PID_REG: u32 = 1072694384;
pub const DPORT_RECORD_APP_PID: u32 = 7;
pub const DPORT_RECORD_APP_PID_V: u32 = 7;
pub const DPORT_RECORD_APP_PID_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGINST_REG: u32 = 1072694388;
pub const DPORT_RECORD_APP_PDEBUGINST: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGINST_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGINST_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG: u32 = 1072694392;
pub const DPORT_RECORD_APP_PDEBUGSTATUS: u32 = 255;
pub const DPORT_RECORD_APP_PDEBUGSTATUS_V: u32 = 255;
pub const DPORT_RECORD_APP_PDEBUGSTATUS_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGDATA_REG: u32 = 1072694396;
pub const DPORT_RECORD_APP_PDEBUGDATA: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGDATA_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGDATA_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGPC_REG: u32 = 1072694400;
pub const DPORT_RECORD_APP_PDEBUGPC: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGPC_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGPC_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG: u32 = 1072694404;
pub const DPORT_RECORD_APP_PDEBUGLS0STAT: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0STAT_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0STAT_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG: u32 = 1072694408;
pub const DPORT_RECORD_APP_PDEBUGLS0ADDR: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0ADDR_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0ADDR_S: u32 = 0;
pub const DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG: u32 = 1072694412;
pub const DPORT_RECORD_APP_PDEBUGLS0DATA: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0DATA_V: u32 = 4294967295;
pub const DPORT_RECORD_APP_PDEBUGLS0DATA_S: u32 = 0;
pub const DPORT_RSA_PD_CTRL_REG: u32 = 1072694416;
pub const DPORT_RSA_PD_V: u32 = 1;
pub const DPORT_RSA_PD_S: u32 = 0;
pub const DPORT_ROM_MPU_TABLE0_REG: u32 = 1072694420;
pub const DPORT_ROM_MPU_TABLE0: u32 = 3;
pub const DPORT_ROM_MPU_TABLE0_V: u32 = 3;
pub const DPORT_ROM_MPU_TABLE0_S: u32 = 0;
pub const DPORT_ROM_MPU_TABLE1_REG: u32 = 1072694424;
pub const DPORT_ROM_MPU_TABLE1: u32 = 3;
pub const DPORT_ROM_MPU_TABLE1_V: u32 = 3;
pub const DPORT_ROM_MPU_TABLE1_S: u32 = 0;
pub const DPORT_ROM_MPU_TABLE2_REG: u32 = 1072694428;
pub const DPORT_ROM_MPU_TABLE2: u32 = 3;
pub const DPORT_ROM_MPU_TABLE2_V: u32 = 3;
pub const DPORT_ROM_MPU_TABLE2_S: u32 = 0;
pub const DPORT_ROM_MPU_TABLE3_REG: u32 = 1072694432;
pub const DPORT_ROM_MPU_TABLE3: u32 = 3;
pub const DPORT_ROM_MPU_TABLE3_V: u32 = 3;
pub const DPORT_ROM_MPU_TABLE3_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE0_REG: u32 = 1072694436;
pub const DPORT_SHROM_MPU_TABLE0: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE0_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE0_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE1_REG: u32 = 1072694440;
pub const DPORT_SHROM_MPU_TABLE1: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE1_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE1_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE2_REG: u32 = 1072694444;
pub const DPORT_SHROM_MPU_TABLE2: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE2_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE2_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE3_REG: u32 = 1072694448;
pub const DPORT_SHROM_MPU_TABLE3: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE3_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE3_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE4_REG: u32 = 1072694452;
pub const DPORT_SHROM_MPU_TABLE4: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE4_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE4_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE5_REG: u32 = 1072694456;
pub const DPORT_SHROM_MPU_TABLE5: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE5_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE5_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE6_REG: u32 = 1072694460;
pub const DPORT_SHROM_MPU_TABLE6: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE6_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE6_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE7_REG: u32 = 1072694464;
pub const DPORT_SHROM_MPU_TABLE7: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE7_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE7_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE8_REG: u32 = 1072694468;
pub const DPORT_SHROM_MPU_TABLE8: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE8_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE8_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE9_REG: u32 = 1072694472;
pub const DPORT_SHROM_MPU_TABLE9: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE9_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE9_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE10_REG: u32 = 1072694476;
pub const DPORT_SHROM_MPU_TABLE10: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE10_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE10_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE11_REG: u32 = 1072694480;
pub const DPORT_SHROM_MPU_TABLE11: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE11_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE11_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE12_REG: u32 = 1072694484;
pub const DPORT_SHROM_MPU_TABLE12: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE12_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE12_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE13_REG: u32 = 1072694488;
pub const DPORT_SHROM_MPU_TABLE13: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE13_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE13_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE14_REG: u32 = 1072694492;
pub const DPORT_SHROM_MPU_TABLE14: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE14_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE14_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE15_REG: u32 = 1072694496;
pub const DPORT_SHROM_MPU_TABLE15: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE15_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE15_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE16_REG: u32 = 1072694500;
pub const DPORT_SHROM_MPU_TABLE16: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE16_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE16_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE17_REG: u32 = 1072694504;
pub const DPORT_SHROM_MPU_TABLE17: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE17_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE17_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE18_REG: u32 = 1072694508;
pub const DPORT_SHROM_MPU_TABLE18: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE18_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE18_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE19_REG: u32 = 1072694512;
pub const DPORT_SHROM_MPU_TABLE19: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE19_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE19_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE20_REG: u32 = 1072694516;
pub const DPORT_SHROM_MPU_TABLE20: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE20_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE20_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE21_REG: u32 = 1072694520;
pub const DPORT_SHROM_MPU_TABLE21: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE21_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE21_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE22_REG: u32 = 1072694524;
pub const DPORT_SHROM_MPU_TABLE22: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE22_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE22_S: u32 = 0;
pub const DPORT_SHROM_MPU_TABLE23_REG: u32 = 1072694528;
pub const DPORT_SHROM_MPU_TABLE23: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE23_V: u32 = 3;
pub const DPORT_SHROM_MPU_TABLE23_S: u32 = 0;
pub const DPORT_IMMU_TABLE0_REG: u32 = 1072694532;
pub const DPORT_IMMU_TABLE0: u32 = 127;
pub const DPORT_IMMU_TABLE0_V: u32 = 127;
pub const DPORT_IMMU_TABLE0_S: u32 = 0;
pub const DPORT_IMMU_TABLE1_REG: u32 = 1072694536;
pub const DPORT_IMMU_TABLE1: u32 = 127;
pub const DPORT_IMMU_TABLE1_V: u32 = 127;
pub const DPORT_IMMU_TABLE1_S: u32 = 0;
pub const DPORT_IMMU_TABLE2_REG: u32 = 1072694540;
pub const DPORT_IMMU_TABLE2: u32 = 127;
pub const DPORT_IMMU_TABLE2_V: u32 = 127;
pub const DPORT_IMMU_TABLE2_S: u32 = 0;
pub const DPORT_IMMU_TABLE3_REG: u32 = 1072694544;
pub const DPORT_IMMU_TABLE3: u32 = 127;
pub const DPORT_IMMU_TABLE3_V: u32 = 127;
pub const DPORT_IMMU_TABLE3_S: u32 = 0;
pub const DPORT_IMMU_TABLE4_REG: u32 = 1072694548;
pub const DPORT_IMMU_TABLE4: u32 = 127;
pub const DPORT_IMMU_TABLE4_V: u32 = 127;
pub const DPORT_IMMU_TABLE4_S: u32 = 0;
pub const DPORT_IMMU_TABLE5_REG: u32 = 1072694552;
pub const DPORT_IMMU_TABLE5: u32 = 127;
pub const DPORT_IMMU_TABLE5_V: u32 = 127;
pub const DPORT_IMMU_TABLE5_S: u32 = 0;
pub const DPORT_IMMU_TABLE6_REG: u32 = 1072694556;
pub const DPORT_IMMU_TABLE6: u32 = 127;
pub const DPORT_IMMU_TABLE6_V: u32 = 127;
pub const DPORT_IMMU_TABLE6_S: u32 = 0;
pub const DPORT_IMMU_TABLE7_REG: u32 = 1072694560;
pub const DPORT_IMMU_TABLE7: u32 = 127;
pub const DPORT_IMMU_TABLE7_V: u32 = 127;
pub const DPORT_IMMU_TABLE7_S: u32 = 0;
pub const DPORT_IMMU_TABLE8_REG: u32 = 1072694564;
pub const DPORT_IMMU_TABLE8: u32 = 127;
pub const DPORT_IMMU_TABLE8_V: u32 = 127;
pub const DPORT_IMMU_TABLE8_S: u32 = 0;
pub const DPORT_IMMU_TABLE9_REG: u32 = 1072694568;
pub const DPORT_IMMU_TABLE9: u32 = 127;
pub const DPORT_IMMU_TABLE9_V: u32 = 127;
pub const DPORT_IMMU_TABLE9_S: u32 = 0;
pub const DPORT_IMMU_TABLE10_REG: u32 = 1072694572;
pub const DPORT_IMMU_TABLE10: u32 = 127;
pub const DPORT_IMMU_TABLE10_V: u32 = 127;
pub const DPORT_IMMU_TABLE10_S: u32 = 0;
pub const DPORT_IMMU_TABLE11_REG: u32 = 1072694576;
pub const DPORT_IMMU_TABLE11: u32 = 127;
pub const DPORT_IMMU_TABLE11_V: u32 = 127;
pub const DPORT_IMMU_TABLE11_S: u32 = 0;
pub const DPORT_IMMU_TABLE12_REG: u32 = 1072694580;
pub const DPORT_IMMU_TABLE12: u32 = 127;
pub const DPORT_IMMU_TABLE12_V: u32 = 127;
pub const DPORT_IMMU_TABLE12_S: u32 = 0;
pub const DPORT_IMMU_TABLE13_REG: u32 = 1072694584;
pub const DPORT_IMMU_TABLE13: u32 = 127;
pub const DPORT_IMMU_TABLE13_V: u32 = 127;
pub const DPORT_IMMU_TABLE13_S: u32 = 0;
pub const DPORT_IMMU_TABLE14_REG: u32 = 1072694588;
pub const DPORT_IMMU_TABLE14: u32 = 127;
pub const DPORT_IMMU_TABLE14_V: u32 = 127;
pub const DPORT_IMMU_TABLE14_S: u32 = 0;
pub const DPORT_IMMU_TABLE15_REG: u32 = 1072694592;
pub const DPORT_IMMU_TABLE15: u32 = 127;
pub const DPORT_IMMU_TABLE15_V: u32 = 127;
pub const DPORT_IMMU_TABLE15_S: u32 = 0;
pub const DPORT_DMMU_TABLE0_REG: u32 = 1072694596;
pub const DPORT_DMMU_TABLE0: u32 = 127;
pub const DPORT_DMMU_TABLE0_V: u32 = 127;
pub const DPORT_DMMU_TABLE0_S: u32 = 0;
pub const DPORT_DMMU_TABLE1_REG: u32 = 1072694600;
pub const DPORT_DMMU_TABLE1: u32 = 127;
pub const DPORT_DMMU_TABLE1_V: u32 = 127;
pub const DPORT_DMMU_TABLE1_S: u32 = 0;
pub const DPORT_DMMU_TABLE2_REG: u32 = 1072694604;
pub const DPORT_DMMU_TABLE2: u32 = 127;
pub const DPORT_DMMU_TABLE2_V: u32 = 127;
pub const DPORT_DMMU_TABLE2_S: u32 = 0;
pub const DPORT_DMMU_TABLE3_REG: u32 = 1072694608;
pub const DPORT_DMMU_TABLE3: u32 = 127;
pub const DPORT_DMMU_TABLE3_V: u32 = 127;
pub const DPORT_DMMU_TABLE3_S: u32 = 0;
pub const DPORT_DMMU_TABLE4_REG: u32 = 1072694612;
pub const DPORT_DMMU_TABLE4: u32 = 127;
pub const DPORT_DMMU_TABLE4_V: u32 = 127;
pub const DPORT_DMMU_TABLE4_S: u32 = 0;
pub const DPORT_DMMU_TABLE5_REG: u32 = 1072694616;
pub const DPORT_DMMU_TABLE5: u32 = 127;
pub const DPORT_DMMU_TABLE5_V: u32 = 127;
pub const DPORT_DMMU_TABLE5_S: u32 = 0;
pub const DPORT_DMMU_TABLE6_REG: u32 = 1072694620;
pub const DPORT_DMMU_TABLE6: u32 = 127;
pub const DPORT_DMMU_TABLE6_V: u32 = 127;
pub const DPORT_DMMU_TABLE6_S: u32 = 0;
pub const DPORT_DMMU_TABLE7_REG: u32 = 1072694624;
pub const DPORT_DMMU_TABLE7: u32 = 127;
pub const DPORT_DMMU_TABLE7_V: u32 = 127;
pub const DPORT_DMMU_TABLE7_S: u32 = 0;
pub const DPORT_DMMU_TABLE8_REG: u32 = 1072694628;
pub const DPORT_DMMU_TABLE8: u32 = 127;
pub const DPORT_DMMU_TABLE8_V: u32 = 127;
pub const DPORT_DMMU_TABLE8_S: u32 = 0;
pub const DPORT_DMMU_TABLE9_REG: u32 = 1072694632;
pub const DPORT_DMMU_TABLE9: u32 = 127;
pub const DPORT_DMMU_TABLE9_V: u32 = 127;
pub const DPORT_DMMU_TABLE9_S: u32 = 0;
pub const DPORT_DMMU_TABLE10_REG: u32 = 1072694636;
pub const DPORT_DMMU_TABLE10: u32 = 127;
pub const DPORT_DMMU_TABLE10_V: u32 = 127;
pub const DPORT_DMMU_TABLE10_S: u32 = 0;
pub const DPORT_DMMU_TABLE11_REG: u32 = 1072694640;
pub const DPORT_DMMU_TABLE11: u32 = 127;
pub const DPORT_DMMU_TABLE11_V: u32 = 127;
pub const DPORT_DMMU_TABLE11_S: u32 = 0;
pub const DPORT_DMMU_TABLE12_REG: u32 = 1072694644;
pub const DPORT_DMMU_TABLE12: u32 = 127;
pub const DPORT_DMMU_TABLE12_V: u32 = 127;
pub const DPORT_DMMU_TABLE12_S: u32 = 0;
pub const DPORT_DMMU_TABLE13_REG: u32 = 1072694648;
pub const DPORT_DMMU_TABLE13: u32 = 127;
pub const DPORT_DMMU_TABLE13_V: u32 = 127;
pub const DPORT_DMMU_TABLE13_S: u32 = 0;
pub const DPORT_DMMU_TABLE14_REG: u32 = 1072694652;
pub const DPORT_DMMU_TABLE14: u32 = 127;
pub const DPORT_DMMU_TABLE14_V: u32 = 127;
pub const DPORT_DMMU_TABLE14_S: u32 = 0;
pub const DPORT_DMMU_TABLE15_REG: u32 = 1072694656;
pub const DPORT_DMMU_TABLE15: u32 = 127;
pub const DPORT_DMMU_TABLE15_V: u32 = 127;
pub const DPORT_DMMU_TABLE15_S: u32 = 0;
pub const DPORT_PRO_INTRUSION_CTRL_REG: u32 = 1072694660;
pub const DPORT_PRO_INTRUSION_RECORD_RESET_N_V: u32 = 1;
pub const DPORT_PRO_INTRUSION_RECORD_RESET_N_S: u32 = 0;
pub const DPORT_PRO_INTRUSION_STATUS_REG: u32 = 1072694664;
pub const DPORT_PRO_INTRUSION_RECORD: u32 = 15;
pub const DPORT_PRO_INTRUSION_RECORD_V: u32 = 15;
pub const DPORT_PRO_INTRUSION_RECORD_S: u32 = 0;
pub const DPORT_APP_INTRUSION_CTRL_REG: u32 = 1072694668;
pub const DPORT_APP_INTRUSION_RECORD_RESET_N_V: u32 = 1;
pub const DPORT_APP_INTRUSION_RECORD_RESET_N_S: u32 = 0;
pub const DPORT_APP_INTRUSION_STATUS_REG: u32 = 1072694672;
pub const DPORT_APP_INTRUSION_RECORD: u32 = 15;
pub const DPORT_APP_INTRUSION_RECORD_V: u32 = 15;
pub const DPORT_APP_INTRUSION_RECORD_S: u32 = 0;
pub const DPORT_FRONT_END_MEM_PD_REG: u32 = 1072694676;
pub const DPORT_PBUS_MEM_FORCE_PD_V: u32 = 1;
pub const DPORT_PBUS_MEM_FORCE_PD_S: u32 = 3;
pub const DPORT_PBUS_MEM_FORCE_PU_V: u32 = 1;
pub const DPORT_PBUS_MEM_FORCE_PU_S: u32 = 2;
pub const DPORT_AGC_MEM_FORCE_PD_V: u32 = 1;
pub const DPORT_AGC_MEM_FORCE_PD_S: u32 = 1;
pub const DPORT_AGC_MEM_FORCE_PU_V: u32 = 1;
pub const DPORT_AGC_MEM_FORCE_PU_S: u32 = 0;
pub const DPORT_MMU_IA_INT_EN_REG: u32 = 1072694680;
pub const DPORT_MMU_IA_INT_EN: u32 = 16777215;
pub const DPORT_MMU_IA_INT_EN_V: u32 = 16777215;
pub const DPORT_MMU_IA_INT_EN_S: u32 = 0;
pub const DPORT_MPU_IA_INT_EN_REG: u32 = 1072694684;
pub const DPORT_MPU_IA_INT_EN: u32 = 131071;
pub const DPORT_MPU_IA_INT_EN_V: u32 = 131071;
pub const DPORT_MPU_IA_INT_EN_S: u32 = 0;
pub const DPORT_CACHE_IA_INT_EN_REG: u32 = 1072694688;
pub const DPORT_CACHE_IA_INT_EN: u32 = 268435455;
pub const DPORT_CACHE_IA_INT_EN_V: u32 = 268435455;
pub const DPORT_CACHE_IA_INT_EN_S: u32 = 0;
pub const DPORT_CACHE_IA_INT_PRO_OPPOSITE_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_OPPOSITE_S: u32 = 19;
pub const DPORT_CACHE_IA_INT_PRO_DRAM1_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_DRAM1_S: u32 = 18;
pub const DPORT_CACHE_IA_INT_PRO_IROM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_IROM0_S: u32 = 17;
pub const DPORT_CACHE_IA_INT_PRO_IRAM1_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_IRAM1_S: u32 = 16;
pub const DPORT_CACHE_IA_INT_PRO_IRAM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_IRAM0_S: u32 = 15;
pub const DPORT_CACHE_IA_INT_PRO_DROM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_PRO_DROM0_S: u32 = 14;
pub const DPORT_CACHE_IA_INT_APP_OPPOSITE_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_OPPOSITE_S: u32 = 5;
pub const DPORT_CACHE_IA_INT_APP_DRAM1_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_DRAM1_S: u32 = 4;
pub const DPORT_CACHE_IA_INT_APP_IROM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_IROM0_S: u32 = 3;
pub const DPORT_CACHE_IA_INT_APP_IRAM1_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_IRAM1_S: u32 = 2;
pub const DPORT_CACHE_IA_INT_APP_IRAM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_IRAM0_S: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_DROM0_V: u32 = 1;
pub const DPORT_CACHE_IA_INT_APP_DROM0_S: u32 = 0;
pub const DPORT_SECURE_BOOT_CTRL_REG: u32 = 1072694692;
pub const DPORT_SW_BOOTLOADER_SEL_V: u32 = 1;
pub const DPORT_SW_BOOTLOADER_SEL_S: u32 = 0;
pub const DPORT_SPI_DMA_CHAN_SEL_REG: u32 = 1072694696;
pub const DPORT_SPI3_DMA_CHAN_SEL: u32 = 3;
pub const DPORT_SPI3_DMA_CHAN_SEL_V: u32 = 3;
pub const DPORT_SPI3_DMA_CHAN_SEL_S: u32 = 4;
pub const DPORT_SPI2_DMA_CHAN_SEL: u32 = 3;
pub const DPORT_SPI2_DMA_CHAN_SEL_V: u32 = 3;
pub const DPORT_SPI2_DMA_CHAN_SEL_S: u32 = 2;
pub const DPORT_SPI1_DMA_CHAN_SEL: u32 = 3;
pub const DPORT_SPI1_DMA_CHAN_SEL_V: u32 = 3;
pub const DPORT_SPI1_DMA_CHAN_SEL_S: u32 = 0;
pub const DPORT_PRO_VECBASE_CTRL_REG: u32 = 1072694700;
pub const DPORT_PRO_OUT_VECBASE_SEL: u32 = 3;
pub const DPORT_PRO_OUT_VECBASE_SEL_V: u32 = 3;
pub const DPORT_PRO_OUT_VECBASE_SEL_S: u32 = 0;
pub const DPORT_PRO_VECBASE_SET_REG: u32 = 1072694704;
pub const DPORT_PRO_OUT_VECBASE_REG: u32 = 4194303;
pub const DPORT_PRO_OUT_VECBASE_REG_V: u32 = 4194303;
pub const DPORT_PRO_OUT_VECBASE_REG_S: u32 = 0;
pub const DPORT_APP_VECBASE_CTRL_REG: u32 = 1072694708;
pub const DPORT_APP_OUT_VECBASE_SEL: u32 = 3;
pub const DPORT_APP_OUT_VECBASE_SEL_V: u32 = 3;
pub const DPORT_APP_OUT_VECBASE_SEL_S: u32 = 0;
pub const DPORT_APP_VECBASE_SET_REG: u32 = 1072694712;
pub const DPORT_APP_OUT_VECBASE_REG: u32 = 4194303;
pub const DPORT_APP_OUT_VECBASE_REG_V: u32 = 4194303;
pub const DPORT_APP_OUT_VECBASE_REG_S: u32 = 0;
pub const DPORT_DATE_REG: u32 = 1072697340;
pub const DPORT_DATE: u32 = 268435455;
pub const DPORT_DATE_V: u32 = 268435455;
pub const DPORT_DATE_S: u32 = 0;
pub const DPORT_DPORT_DATE_VERSION: u32 = 23089552;
pub const DPORT_FLASH_MMU_TABLE_SIZE: u32 = 256;
pub const DPORT_FLASH_MMU_TABLE_INVALID_VAL: u32 = 256;
pub const I2S_PIN_NO_CHANGE: i32 = -1;
pub const LEDC_APB_CLK_HZ: u32 = 80000000;
pub const LEDC_REF_CLK_HZ: u32 = 1000000;
pub const LEDC_ERR_DUTY: u32 = 4294967295;
pub const LEDC_ERR_VAL: i32 = -1;
pub const LLDESC_TX_MBLK_SIZE: u32 = 268;
pub const LLDESC_RX_SMBLK_SIZE: u32 = 64;
pub const LLDESC_RX_MBLK_SIZE: u32 = 524;
pub const LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE: u32 = 64;
pub const LLDESC_RX_AMPDU_LEN_MBLK_SIZE: u32 = 256;
pub const LLDESC_TX_MBLK_NUM: u32 = 10;
pub const LLDESC_RX_MBLK_NUM: u32 = 10;
pub const LLDESC_RX_AMPDU_ENTRY_MBLK_NUM: u32 = 4;
pub const LLDESC_RX_AMPDU_LEN_MLBK_NUM: u32 = 8;
pub const LLDESC_OWNER_MASK: u32 = 2147483648;
pub const LLDESC_OWNER_SHIFT: u32 = 31;
pub const LLDESC_SW_OWNED: u32 = 0;
pub const LLDESC_HW_OWNED: u32 = 1;
pub const LLDESC_EOF_MASK: u32 = 1073741824;
pub const LLDESC_EOF_SHIFT: u32 = 30;
pub const LLDESC_SOSF_MASK: u32 = 536870912;
pub const LLDESC_SOSF_SHIFT: u32 = 29;
pub const LLDESC_LENGTH_MASK: u32 = 16773120;
pub const LLDESC_LENGTH_SHIFT: u32 = 12;
pub const LLDESC_SIZE_MASK: u32 = 4095;
pub const LLDESC_SIZE_SHIFT: u32 = 0;
pub const LLDESC_ADDR_MASK: u32 = 1048575;
pub const SPI_IOMUX_PIN_NUM_MISO: u32 = 7;
pub const SPI_IOMUX_PIN_NUM_MOSI: u32 = 8;
pub const SPI_IOMUX_PIN_NUM_CLK: u32 = 6;
pub const SPI_IOMUX_PIN_NUM_CS: u32 = 11;
pub const SPI_IOMUX_PIN_NUM_WP: u32 = 10;
pub const SPI_IOMUX_PIN_NUM_HD: u32 = 9;
pub const HSPI_IOMUX_PIN_NUM_MISO: u32 = 12;
pub const HSPI_IOMUX_PIN_NUM_MOSI: u32 = 13;
pub const HSPI_IOMUX_PIN_NUM_CLK: u32 = 14;
pub const HSPI_IOMUX_PIN_NUM_CS: u32 = 15;
pub const HSPI_IOMUX_PIN_NUM_WP: u32 = 2;
pub const HSPI_IOMUX_PIN_NUM_HD: u32 = 4;
pub const VSPI_IOMUX_PIN_NUM_MISO: u32 = 19;
pub const VSPI_IOMUX_PIN_NUM_MOSI: u32 = 23;
pub const VSPI_IOMUX_PIN_NUM_CLK: u32 = 18;
pub const VSPI_IOMUX_PIN_NUM_CS: u32 = 5;
pub const VSPI_IOMUX_PIN_NUM_WP: u32 = 22;
pub const VSPI_IOMUX_PIN_NUM_HD: u32 = 21;
pub const SPI_FLASH_READ_V: u32 = 1;
pub const SPI_FLASH_READ_S: u32 = 31;
pub const SPI_FLASH_WREN_V: u32 = 1;
pub const SPI_FLASH_WREN_S: u32 = 30;
pub const SPI_FLASH_WRDI_V: u32 = 1;
pub const SPI_FLASH_WRDI_S: u32 = 29;
pub const SPI_FLASH_RDID_V: u32 = 1;
pub const SPI_FLASH_RDID_S: u32 = 28;
pub const SPI_FLASH_RDSR_V: u32 = 1;
pub const SPI_FLASH_RDSR_S: u32 = 27;
pub const SPI_FLASH_WRSR_V: u32 = 1;
pub const SPI_FLASH_WRSR_S: u32 = 26;
pub const SPI_FLASH_PP_V: u32 = 1;
pub const SPI_FLASH_PP_S: u32 = 25;
pub const SPI_FLASH_SE_V: u32 = 1;
pub const SPI_FLASH_SE_S: u32 = 24;
pub const SPI_FLASH_BE_V: u32 = 1;
pub const SPI_FLASH_BE_S: u32 = 23;
pub const SPI_FLASH_CE_V: u32 = 1;
pub const SPI_FLASH_CE_S: u32 = 22;
pub const SPI_FLASH_DP_V: u32 = 1;
pub const SPI_FLASH_DP_S: u32 = 21;
pub const SPI_FLASH_RES_V: u32 = 1;
pub const SPI_FLASH_RES_S: u32 = 20;
pub const SPI_FLASH_HPM_V: u32 = 1;
pub const SPI_FLASH_HPM_S: u32 = 19;
pub const SPI_USR_V: u32 = 1;
pub const SPI_USR_S: u32 = 18;
pub const SPI_FLASH_PES_V: u32 = 1;
pub const SPI_FLASH_PES_S: u32 = 17;
pub const SPI_FLASH_PER_V: u32 = 1;
pub const SPI_FLASH_PER_S: u32 = 16;
pub const SPI_WR_BIT_ORDER_V: u32 = 1;
pub const SPI_WR_BIT_ORDER_S: u32 = 26;
pub const SPI_RD_BIT_ORDER_V: u32 = 1;
pub const SPI_RD_BIT_ORDER_S: u32 = 25;
pub const SPI_FREAD_QIO_V: u32 = 1;
pub const SPI_FREAD_QIO_S: u32 = 24;
pub const SPI_FREAD_DIO_V: u32 = 1;
pub const SPI_FREAD_DIO_S: u32 = 23;
pub const SPI_WRSR_2B_V: u32 = 1;
pub const SPI_WRSR_2B_S: u32 = 22;
pub const SPI_WP_REG_V: u32 = 1;
pub const SPI_WP_REG_S: u32 = 21;
pub const SPI_FREAD_QUAD_V: u32 = 1;
pub const SPI_FREAD_QUAD_S: u32 = 20;
pub const SPI_RESANDRES_V: u32 = 1;
pub const SPI_RESANDRES_S: u32 = 15;
pub const SPI_FREAD_DUAL_V: u32 = 1;
pub const SPI_FREAD_DUAL_S: u32 = 14;
pub const SPI_FASTRD_MODE_V: u32 = 1;
pub const SPI_FASTRD_MODE_S: u32 = 13;
pub const SPI_WAIT_FLASH_IDLE_EN_V: u32 = 1;
pub const SPI_WAIT_FLASH_IDLE_EN_S: u32 = 12;
pub const SPI_TX_CRC_EN_V: u32 = 1;
pub const SPI_TX_CRC_EN_S: u32 = 11;
pub const SPI_FCS_CRC_EN_V: u32 = 1;
pub const SPI_FCS_CRC_EN_S: u32 = 10;
pub const SPI_CS_HOLD_DELAY: u32 = 15;
pub const SPI_CS_HOLD_DELAY_V: u32 = 15;
pub const SPI_CS_HOLD_DELAY_S: u32 = 28;
pub const SPI_CS_HOLD_DELAY_RES: u32 = 4095;
pub const SPI_CS_HOLD_DELAY_RES_V: u32 = 4095;
pub const SPI_CS_HOLD_DELAY_RES_S: u32 = 16;
pub const SPI_STATUS_EXT: u32 = 255;
pub const SPI_STATUS_EXT_V: u32 = 255;
pub const SPI_STATUS_EXT_S: u32 = 24;
pub const SPI_WB_MODE: u32 = 255;
pub const SPI_WB_MODE_V: u32 = 255;
pub const SPI_WB_MODE_S: u32 = 16;
pub const SPI_STATUS: u32 = 65535;
pub const SPI_STATUS_V: u32 = 65535;
pub const SPI_STATUS_S: u32 = 0;
pub const SPI_CS_DELAY_NUM: u32 = 15;
pub const SPI_CS_DELAY_NUM_V: u32 = 15;
pub const SPI_CS_DELAY_NUM_S: u32 = 28;
pub const SPI_CS_DELAY_MODE: u32 = 3;
pub const SPI_CS_DELAY_MODE_V: u32 = 3;
pub const SPI_CS_DELAY_MODE_S: u32 = 26;
pub const SPI_MOSI_DELAY_NUM: u32 = 7;
pub const SPI_MOSI_DELAY_NUM_V: u32 = 7;
pub const SPI_MOSI_DELAY_NUM_S: u32 = 23;
pub const SPI_MOSI_DELAY_MODE: u32 = 3;
pub const SPI_MOSI_DELAY_MODE_V: u32 = 3;
pub const SPI_MOSI_DELAY_MODE_S: u32 = 21;
pub const SPI_MISO_DELAY_NUM: u32 = 7;
pub const SPI_MISO_DELAY_NUM_V: u32 = 7;
pub const SPI_MISO_DELAY_NUM_S: u32 = 18;
pub const SPI_MISO_DELAY_MODE: u32 = 3;
pub const SPI_MISO_DELAY_MODE_V: u32 = 3;
pub const SPI_MISO_DELAY_MODE_S: u32 = 16;
pub const SPI_CK_OUT_HIGH_MODE: u32 = 15;
pub const SPI_CK_OUT_HIGH_MODE_V: u32 = 15;
pub const SPI_CK_OUT_HIGH_MODE_S: u32 = 12;
pub const SPI_CK_OUT_LOW_MODE: u32 = 15;
pub const SPI_CK_OUT_LOW_MODE_V: u32 = 15;
pub const SPI_CK_OUT_LOW_MODE_S: u32 = 8;
pub const SPI_HOLD_TIME: u32 = 15;
pub const SPI_HOLD_TIME_V: u32 = 15;
pub const SPI_HOLD_TIME_S: u32 = 4;
pub const SPI_SETUP_TIME: u32 = 15;
pub const SPI_SETUP_TIME_V: u32 = 15;
pub const SPI_SETUP_TIME_S: u32 = 0;
pub const SPI_CLK_EQU_SYSCLK_V: u32 = 1;
pub const SPI_CLK_EQU_SYSCLK_S: u32 = 31;
pub const SPI_CLKDIV_PRE: u32 = 8191;
pub const SPI_CLKDIV_PRE_V: u32 = 8191;
pub const SPI_CLKDIV_PRE_S: u32 = 18;
pub const SPI_CLKCNT_N: u32 = 63;
pub const SPI_CLKCNT_N_V: u32 = 63;
pub const SPI_CLKCNT_N_S: u32 = 12;
pub const SPI_CLKCNT_H: u32 = 63;
pub const SPI_CLKCNT_H_V: u32 = 63;
pub const SPI_CLKCNT_H_S: u32 = 6;
pub const SPI_CLKCNT_L: u32 = 63;
pub const SPI_CLKCNT_L_V: u32 = 63;
pub const SPI_CLKCNT_L_S: u32 = 0;
pub const SPI_USR_COMMAND_V: u32 = 1;
pub const SPI_USR_COMMAND_S: u32 = 31;
pub const SPI_USR_ADDR_V: u32 = 1;
pub const SPI_USR_ADDR_S: u32 = 30;
pub const SPI_USR_DUMMY_V: u32 = 1;
pub const SPI_USR_DUMMY_S: u32 = 29;
pub const SPI_USR_MISO_V: u32 = 1;
pub const SPI_USR_MISO_S: u32 = 28;
pub const SPI_USR_MOSI_V: u32 = 1;
pub const SPI_USR_MOSI_S: u32 = 27;
pub const SPI_USR_DUMMY_IDLE_V: u32 = 1;
pub const SPI_USR_DUMMY_IDLE_S: u32 = 26;
pub const SPI_USR_MOSI_HIGHPART_V: u32 = 1;
pub const SPI_USR_MOSI_HIGHPART_S: u32 = 25;
pub const SPI_USR_MISO_HIGHPART_V: u32 = 1;
pub const SPI_USR_MISO_HIGHPART_S: u32 = 24;
pub const SPI_USR_PREP_HOLD_V: u32 = 1;
pub const SPI_USR_PREP_HOLD_S: u32 = 23;
pub const SPI_USR_CMD_HOLD_V: u32 = 1;
pub const SPI_USR_CMD_HOLD_S: u32 = 22;
pub const SPI_USR_ADDR_HOLD_V: u32 = 1;
pub const SPI_USR_ADDR_HOLD_S: u32 = 21;
pub const SPI_USR_DUMMY_HOLD_V: u32 = 1;
pub const SPI_USR_DUMMY_HOLD_S: u32 = 20;
pub const SPI_USR_DIN_HOLD_V: u32 = 1;
pub const SPI_USR_DIN_HOLD_S: u32 = 19;
pub const SPI_USR_DOUT_HOLD_V: u32 = 1;
pub const SPI_USR_DOUT_HOLD_S: u32 = 18;
pub const SPI_USR_HOLD_POL_V: u32 = 1;
pub const SPI_USR_HOLD_POL_S: u32 = 17;
pub const SPI_SIO_V: u32 = 1;
pub const SPI_SIO_S: u32 = 16;
pub const SPI_FWRITE_QIO_V: u32 = 1;
pub const SPI_FWRITE_QIO_S: u32 = 15;
pub const SPI_FWRITE_DIO_V: u32 = 1;
pub const SPI_FWRITE_DIO_S: u32 = 14;
pub const SPI_FWRITE_QUAD_V: u32 = 1;
pub const SPI_FWRITE_QUAD_S: u32 = 13;
pub const SPI_FWRITE_DUAL_V: u32 = 1;
pub const SPI_FWRITE_DUAL_S: u32 = 12;
pub const SPI_WR_BYTE_ORDER_V: u32 = 1;
pub const SPI_WR_BYTE_ORDER_S: u32 = 11;
pub const SPI_RD_BYTE_ORDER_V: u32 = 1;
pub const SPI_RD_BYTE_ORDER_S: u32 = 10;
pub const SPI_CK_OUT_EDGE_V: u32 = 1;
pub const SPI_CK_OUT_EDGE_S: u32 = 7;
pub const SPI_CK_I_EDGE_V: u32 = 1;
pub const SPI_CK_I_EDGE_S: u32 = 6;
pub const SPI_CS_SETUP_V: u32 = 1;
pub const SPI_CS_SETUP_S: u32 = 5;
pub const SPI_CS_HOLD_V: u32 = 1;
pub const SPI_CS_HOLD_S: u32 = 4;
pub const SPI_DOUTDIN_V: u32 = 1;
pub const SPI_DOUTDIN_S: u32 = 0;
pub const SPI_USR_ADDR_BITLEN: u32 = 63;
pub const SPI_USR_ADDR_BITLEN_V: u32 = 63;
pub const SPI_USR_ADDR_BITLEN_S: u32 = 26;
pub const SPI_USR_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_USR_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_USR_DUMMY_CYCLELEN_S: u32 = 0;
pub const SPI_USR_COMMAND_BITLEN: u32 = 15;
pub const SPI_USR_COMMAND_BITLEN_V: u32 = 15;
pub const SPI_USR_COMMAND_BITLEN_S: u32 = 28;
pub const SPI_USR_COMMAND_VALUE: u32 = 65535;
pub const SPI_USR_COMMAND_VALUE_V: u32 = 65535;
pub const SPI_USR_COMMAND_VALUE_S: u32 = 0;
pub const SPI_USR_MOSI_DBITLEN: u32 = 16777215;
pub const SPI_USR_MOSI_DBITLEN_V: u32 = 16777215;
pub const SPI_USR_MOSI_DBITLEN_S: u32 = 0;
pub const SPI_USR_MISO_DBITLEN: u32 = 16777215;
pub const SPI_USR_MISO_DBITLEN_V: u32 = 16777215;
pub const SPI_USR_MISO_DBITLEN_S: u32 = 0;
pub const SPI_SLV_WR_ST: u32 = 4294967295;
pub const SPI_SLV_WR_ST_V: u32 = 4294967295;
pub const SPI_SLV_WR_ST_S: u32 = 0;
pub const SPI_CS_KEEP_ACTIVE_V: u32 = 1;
pub const SPI_CS_KEEP_ACTIVE_S: u32 = 30;
pub const SPI_CK_IDLE_EDGE_V: u32 = 1;
pub const SPI_CK_IDLE_EDGE_S: u32 = 29;
pub const SPI_MASTER_CK_SEL: u32 = 7;
pub const SPI_MASTER_CK_SEL_V: u32 = 7;
pub const SPI_MASTER_CK_SEL_S: u32 = 11;
pub const SPI_MASTER_CS_POL: u32 = 7;
pub const SPI_MASTER_CS_POL_V: u32 = 7;
pub const SPI_MASTER_CS_POL_S: u32 = 6;
pub const SPI_CK_DIS_V: u32 = 1;
pub const SPI_CK_DIS_S: u32 = 5;
pub const SPI_CS2_DIS_V: u32 = 1;
pub const SPI_CS2_DIS_S: u32 = 2;
pub const SPI_CS1_DIS_V: u32 = 1;
pub const SPI_CS1_DIS_S: u32 = 1;
pub const SPI_CS0_DIS_V: u32 = 1;
pub const SPI_CS0_DIS_S: u32 = 0;
pub const SPI_SYNC_RESET_V: u32 = 1;
pub const SPI_SYNC_RESET_S: u32 = 31;
pub const SPI_SLAVE_MODE_V: u32 = 1;
pub const SPI_SLAVE_MODE_S: u32 = 30;
pub const SPI_SLV_WR_RD_BUF_EN_V: u32 = 1;
pub const SPI_SLV_WR_RD_BUF_EN_S: u32 = 29;
pub const SPI_SLV_WR_RD_STA_EN_V: u32 = 1;
pub const SPI_SLV_WR_RD_STA_EN_S: u32 = 28;
pub const SPI_SLV_CMD_DEFINE_V: u32 = 1;
pub const SPI_SLV_CMD_DEFINE_S: u32 = 27;
pub const SPI_TRANS_CNT: u32 = 15;
pub const SPI_TRANS_CNT_V: u32 = 15;
pub const SPI_TRANS_CNT_S: u32 = 23;
pub const SPI_SLV_LAST_STATE: u32 = 7;
pub const SPI_SLV_LAST_STATE_V: u32 = 7;
pub const SPI_SLV_LAST_STATE_S: u32 = 20;
pub const SPI_SLV_LAST_COMMAND: u32 = 7;
pub const SPI_SLV_LAST_COMMAND_V: u32 = 7;
pub const SPI_SLV_LAST_COMMAND_S: u32 = 17;
pub const SPI_CS_I_MODE: u32 = 3;
pub const SPI_CS_I_MODE_V: u32 = 3;
pub const SPI_CS_I_MODE_S: u32 = 10;
pub const SPI_INT_EN: u32 = 31;
pub const SPI_INT_EN_V: u32 = 31;
pub const SPI_INT_EN_S: u32 = 5;
pub const SPI_TRANS_DONE_V: u32 = 1;
pub const SPI_TRANS_DONE_S: u32 = 4;
pub const SPI_SLV_WR_STA_DONE_V: u32 = 1;
pub const SPI_SLV_WR_STA_DONE_S: u32 = 3;
pub const SPI_SLV_RD_STA_DONE_V: u32 = 1;
pub const SPI_SLV_RD_STA_DONE_S: u32 = 2;
pub const SPI_SLV_WR_BUF_DONE_V: u32 = 1;
pub const SPI_SLV_WR_BUF_DONE_S: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_V: u32 = 1;
pub const SPI_SLV_RD_BUF_DONE_S: u32 = 0;
pub const SPI_SLV_STATUS_BITLEN: u32 = 31;
pub const SPI_SLV_STATUS_BITLEN_V: u32 = 31;
pub const SPI_SLV_STATUS_BITLEN_S: u32 = 27;
pub const SPI_SLV_STATUS_FAST_EN_V: u32 = 1;
pub const SPI_SLV_STATUS_FAST_EN_S: u32 = 26;
pub const SPI_SLV_STATUS_READBACK_V: u32 = 1;
pub const SPI_SLV_STATUS_READBACK_S: u32 = 25;
pub const SPI_SLV_RD_ADDR_BITLEN: u32 = 63;
pub const SPI_SLV_RD_ADDR_BITLEN_V: u32 = 63;
pub const SPI_SLV_RD_ADDR_BITLEN_S: u32 = 10;
pub const SPI_SLV_WR_ADDR_BITLEN: u32 = 63;
pub const SPI_SLV_WR_ADDR_BITLEN_V: u32 = 63;
pub const SPI_SLV_WR_ADDR_BITLEN_S: u32 = 4;
pub const SPI_SLV_WRSTA_DUMMY_EN_V: u32 = 1;
pub const SPI_SLV_WRSTA_DUMMY_EN_S: u32 = 3;
pub const SPI_SLV_RDSTA_DUMMY_EN_V: u32 = 1;
pub const SPI_SLV_RDSTA_DUMMY_EN_S: u32 = 2;
pub const SPI_SLV_WRBUF_DUMMY_EN_V: u32 = 1;
pub const SPI_SLV_WRBUF_DUMMY_EN_S: u32 = 1;
pub const SPI_SLV_RDBUF_DUMMY_EN_V: u32 = 1;
pub const SPI_SLV_RDBUF_DUMMY_EN_S: u32 = 0;
pub const SPI_SLV_WRBUF_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_SLV_WRBUF_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_SLV_WRBUF_DUMMY_CYCLELEN_S: u32 = 24;
pub const SPI_SLV_RDBUF_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_SLV_RDBUF_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_SLV_RDBUF_DUMMY_CYCLELEN_S: u32 = 16;
pub const SPI_SLV_WRSTA_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_SLV_WRSTA_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_SLV_WRSTA_DUMMY_CYCLELEN_S: u32 = 8;
pub const SPI_SLV_RDSTA_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_SLV_RDSTA_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_SLV_RDSTA_DUMMY_CYCLELEN_S: u32 = 0;
pub const SPI_SLV_WRSTA_CMD_VALUE: u32 = 255;
pub const SPI_SLV_WRSTA_CMD_VALUE_V: u32 = 255;
pub const SPI_SLV_WRSTA_CMD_VALUE_S: u32 = 24;
pub const SPI_SLV_RDSTA_CMD_VALUE: u32 = 255;
pub const SPI_SLV_RDSTA_CMD_VALUE_V: u32 = 255;
pub const SPI_SLV_RDSTA_CMD_VALUE_S: u32 = 16;
pub const SPI_SLV_WRBUF_CMD_VALUE: u32 = 255;
pub const SPI_SLV_WRBUF_CMD_VALUE_V: u32 = 255;
pub const SPI_SLV_WRBUF_CMD_VALUE_S: u32 = 8;
pub const SPI_SLV_RDBUF_CMD_VALUE: u32 = 255;
pub const SPI_SLV_RDBUF_CMD_VALUE_V: u32 = 255;
pub const SPI_SLV_RDBUF_CMD_VALUE_S: u32 = 0;
pub const SPI_SLV_WRBUF_DBITLEN: u32 = 16777215;
pub const SPI_SLV_WRBUF_DBITLEN_V: u32 = 16777215;
pub const SPI_SLV_WRBUF_DBITLEN_S: u32 = 0;
pub const SPI_SLV_RDBUF_DBITLEN: u32 = 16777215;
pub const SPI_SLV_RDBUF_DBITLEN_V: u32 = 16777215;
pub const SPI_SLV_RDBUF_DBITLEN_S: u32 = 0;
pub const SPI_CACHE_FLASH_PES_EN_V: u32 = 1;
pub const SPI_CACHE_FLASH_PES_EN_S: u32 = 3;
pub const SPI_CACHE_FLASH_USR_CMD_V: u32 = 1;
pub const SPI_CACHE_FLASH_USR_CMD_S: u32 = 2;
pub const SPI_CACHE_USR_CMD_4BYTE_V: u32 = 1;
pub const SPI_CACHE_USR_CMD_4BYTE_S: u32 = 1;
pub const SPI_CACHE_REQ_EN_V: u32 = 1;
pub const SPI_CACHE_REQ_EN_S: u32 = 0;
pub const SPI_CACHE_SRAM_USR_WCMD_V: u32 = 1;
pub const SPI_CACHE_SRAM_USR_WCMD_S: u32 = 28;
pub const SPI_SRAM_ADDR_BITLEN: u32 = 63;
pub const SPI_SRAM_ADDR_BITLEN_V: u32 = 63;
pub const SPI_SRAM_ADDR_BITLEN_S: u32 = 22;
pub const SPI_SRAM_DUMMY_CYCLELEN: u32 = 255;
pub const SPI_SRAM_DUMMY_CYCLELEN_V: u32 = 255;
pub const SPI_SRAM_DUMMY_CYCLELEN_S: u32 = 14;
pub const SPI_SRAM_BYTES_LEN: u32 = 255;
pub const SPI_SRAM_BYTES_LEN_V: u32 = 255;
pub const SPI_SRAM_BYTES_LEN_S: u32 = 6;
pub const SPI_CACHE_SRAM_USR_RCMD_V: u32 = 1;
pub const SPI_CACHE_SRAM_USR_RCMD_S: u32 = 5;
pub const SPI_USR_RD_SRAM_DUMMY_V: u32 = 1;
pub const SPI_USR_RD_SRAM_DUMMY_S: u32 = 4;
pub const SPI_USR_WR_SRAM_DUMMY_V: u32 = 1;
pub const SPI_USR_WR_SRAM_DUMMY_S: u32 = 3;
pub const SPI_USR_SRAM_QIO_V: u32 = 1;
pub const SPI_USR_SRAM_QIO_S: u32 = 2;
pub const SPI_USR_SRAM_DIO_V: u32 = 1;
pub const SPI_USR_SRAM_DIO_S: u32 = 1;
pub const SPI_SRAM_RSTIO_V: u32 = 1;
pub const SPI_SRAM_RSTIO_S: u32 = 4;
pub const SPI_SRAM_QIO_V: u32 = 1;
pub const SPI_SRAM_QIO_S: u32 = 1;
pub const SPI_SRAM_DIO_V: u32 = 1;
pub const SPI_SRAM_DIO_S: u32 = 0;
pub const SPI_CACHE_SRAM_USR_RD_CMD_BITLEN: u32 = 15;
pub const SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V: u32 = 15;
pub const SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S: u32 = 28;
pub const SPI_CACHE_SRAM_USR_RD_CMD_VALUE: u32 = 65535;
pub const SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V: u32 = 65535;
pub const SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S: u32 = 0;
pub const SPI_CACHE_SRAM_USR_WR_CMD_BITLEN: u32 = 15;
pub const SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V: u32 = 15;
pub const SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S: u32 = 28;
pub const SPI_CACHE_SRAM_USR_WR_CMD_VALUE: u32 = 65535;
pub const SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V: u32 = 65535;
pub const SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S: u32 = 0;
pub const SPI_SLV_RDATA_BIT: u32 = 16777215;
pub const SPI_SLV_RDATA_BIT_V: u32 = 16777215;
pub const SPI_SLV_RDATA_BIT_S: u32 = 0;
pub const SPI_BUF0: u32 = 4294967295;
pub const SPI_BUF0_V: u32 = 4294967295;
pub const SPI_BUF0_S: u32 = 0;
pub const SPI_BUF1: u32 = 4294967295;
pub const SPI_BUF1_V: u32 = 4294967295;
pub const SPI_BUF1_S: u32 = 0;
pub const SPI_BUF2: u32 = 4294967295;
pub const SPI_BUF2_V: u32 = 4294967295;
pub const SPI_BUF2_S: u32 = 0;
pub const SPI_BUF3: u32 = 4294967295;
pub const SPI_BUF3_V: u32 = 4294967295;
pub const SPI_BUF3_S: u32 = 0;
pub const SPI_BUF4: u32 = 4294967295;
pub const SPI_BUF4_V: u32 = 4294967295;
pub const SPI_BUF4_S: u32 = 0;
pub const SPI_BUF5: u32 = 4294967295;
pub const SPI_BUF5_V: u32 = 4294967295;
pub const SPI_BUF5_S: u32 = 0;
pub const SPI_BUF6: u32 = 4294967295;
pub const SPI_BUF6_V: u32 = 4294967295;
pub const SPI_BUF6_S: u32 = 0;
pub const SPI_BUF7: u32 = 4294967295;
pub const SPI_BUF7_V: u32 = 4294967295;
pub const SPI_BUF7_S: u32 = 0;
pub const SPI_BUF8: u32 = 4294967295;
pub const SPI_BUF8_V: u32 = 4294967295;
pub const SPI_BUF8_S: u32 = 0;
pub const SPI_BUF9: u32 = 4294967295;
pub const SPI_BUF9_V: u32 = 4294967295;
pub const SPI_BUF9_S: u32 = 0;
pub const SPI_BUF10: u32 = 4294967295;
pub const SPI_BUF10_V: u32 = 4294967295;
pub const SPI_BUF10_S: u32 = 0;
pub const SPI_BUF11: u32 = 4294967295;
pub const SPI_BUF11_V: u32 = 4294967295;
pub const SPI_BUF11_S: u32 = 0;
pub const SPI_BUF12: u32 = 4294967295;
pub const SPI_BUF12_V: u32 = 4294967295;
pub const SPI_BUF12_S: u32 = 0;
pub const SPI_BUF13: u32 = 4294967295;
pub const SPI_BUF13_V: u32 = 4294967295;
pub const SPI_BUF13_S: u32 = 0;
pub const SPI_BUF14: u32 = 4294967295;
pub const SPI_BUF14_V: u32 = 4294967295;
pub const SPI_BUF14_S: u32 = 0;
pub const SPI_BUF15: u32 = 4294967295;
pub const SPI_BUF15_V: u32 = 4294967295;
pub const SPI_BUF15_S: u32 = 0;
pub const SPI_TX_CRC_DATA: u32 = 4294967295;
pub const SPI_TX_CRC_DATA_V: u32 = 4294967295;
pub const SPI_TX_CRC_DATA_S: u32 = 0;
pub const SPI_T_PP_ENA_V: u32 = 1;
pub const SPI_T_PP_ENA_S: u32 = 31;
pub const SPI_T_PP_SHIFT: u32 = 15;
pub const SPI_T_PP_SHIFT_V: u32 = 15;
pub const SPI_T_PP_SHIFT_S: u32 = 16;
pub const SPI_T_PP_TIME: u32 = 4095;
pub const SPI_T_PP_TIME_V: u32 = 4095;
pub const SPI_T_PP_TIME_S: u32 = 0;
pub const SPI_T_ERASE_ENA_V: u32 = 1;
pub const SPI_T_ERASE_ENA_S: u32 = 31;
pub const SPI_T_ERASE_SHIFT: u32 = 15;
pub const SPI_T_ERASE_SHIFT_V: u32 = 15;
pub const SPI_T_ERASE_SHIFT_S: u32 = 16;
pub const SPI_T_ERASE_TIME: u32 = 4095;
pub const SPI_T_ERASE_TIME_V: u32 = 4095;
pub const SPI_T_ERASE_TIME_S: u32 = 0;
pub const SPI_ST: u32 = 7;
pub const SPI_ST_V: u32 = 7;
pub const SPI_ST_S: u32 = 0;
pub const SPI_INT_HOLD_ENA: u32 = 3;
pub const SPI_INT_HOLD_ENA_V: u32 = 3;
pub const SPI_INT_HOLD_ENA_S: u32 = 0;
pub const SPI_DMA_CONTINUE_V: u32 = 1;
pub const SPI_DMA_CONTINUE_S: u32 = 16;
pub const SPI_DMA_TX_STOP_V: u32 = 1;
pub const SPI_DMA_TX_STOP_S: u32 = 15;
pub const SPI_DMA_RX_STOP_V: u32 = 1;
pub const SPI_DMA_RX_STOP_S: u32 = 14;
pub const SPI_OUT_DATA_BURST_EN_V: u32 = 1;
pub const SPI_OUT_DATA_BURST_EN_S: u32 = 12;
pub const SPI_INDSCR_BURST_EN_V: u32 = 1;
pub const SPI_INDSCR_BURST_EN_S: u32 = 11;
pub const SPI_OUTDSCR_BURST_EN_V: u32 = 1;
pub const SPI_OUTDSCR_BURST_EN_S: u32 = 10;
pub const SPI_OUT_EOF_MODE_V: u32 = 1;
pub const SPI_OUT_EOF_MODE_S: u32 = 9;
pub const SPI_OUT_AUTO_WRBACK_V: u32 = 1;
pub const SPI_OUT_AUTO_WRBACK_S: u32 = 8;
pub const SPI_OUT_LOOP_TEST_V: u32 = 1;
pub const SPI_OUT_LOOP_TEST_S: u32 = 7;
pub const SPI_IN_LOOP_TEST_V: u32 = 1;
pub const SPI_IN_LOOP_TEST_S: u32 = 6;
pub const SPI_AHBM_RST_V: u32 = 1;
pub const SPI_AHBM_RST_S: u32 = 5;
pub const SPI_AHBM_FIFO_RST_V: u32 = 1;
pub const SPI_AHBM_FIFO_RST_S: u32 = 4;
pub const SPI_OUT_RST_V: u32 = 1;
pub const SPI_OUT_RST_S: u32 = 3;
pub const SPI_IN_RST_V: u32 = 1;
pub const SPI_IN_RST_S: u32 = 2;
pub const SPI_OUTLINK_RESTART_V: u32 = 1;
pub const SPI_OUTLINK_RESTART_S: u32 = 30;
pub const SPI_OUTLINK_START_V: u32 = 1;
pub const SPI_OUTLINK_START_S: u32 = 29;
pub const SPI_OUTLINK_STOP_V: u32 = 1;
pub const SPI_OUTLINK_STOP_S: u32 = 28;
pub const SPI_OUTLINK_ADDR: u32 = 1048575;
pub const SPI_OUTLINK_ADDR_V: u32 = 1048575;
pub const SPI_OUTLINK_ADDR_S: u32 = 0;
pub const SPI_INLINK_RESTART_V: u32 = 1;
pub const SPI_INLINK_RESTART_S: u32 = 30;
pub const SPI_INLINK_START_V: u32 = 1;
pub const SPI_INLINK_START_S: u32 = 29;
pub const SPI_INLINK_STOP_V: u32 = 1;
pub const SPI_INLINK_STOP_S: u32 = 28;
pub const SPI_INLINK_AUTO_RET_V: u32 = 1;
pub const SPI_INLINK_AUTO_RET_S: u32 = 20;
pub const SPI_INLINK_ADDR: u32 = 1048575;
pub const SPI_INLINK_ADDR_V: u32 = 1048575;
pub const SPI_INLINK_ADDR_S: u32 = 0;
pub const SPI_DMA_TX_EN_V: u32 = 1;
pub const SPI_DMA_TX_EN_S: u32 = 1;
pub const SPI_DMA_RX_EN_V: u32 = 1;
pub const SPI_DMA_RX_EN_S: u32 = 0;
pub const SPI_OUT_TOTAL_EOF_INT_ENA_V: u32 = 1;
pub const SPI_OUT_TOTAL_EOF_INT_ENA_S: u32 = 8;
pub const SPI_OUT_EOF_INT_ENA_V: u32 = 1;
pub const SPI_OUT_EOF_INT_ENA_S: u32 = 7;
pub const SPI_OUT_DONE_INT_ENA_V: u32 = 1;
pub const SPI_OUT_DONE_INT_ENA_S: u32 = 6;
pub const SPI_IN_SUC_EOF_INT_ENA_V: u32 = 1;
pub const SPI_IN_SUC_EOF_INT_ENA_S: u32 = 5;
pub const SPI_IN_ERR_EOF_INT_ENA_V: u32 = 1;
pub const SPI_IN_ERR_EOF_INT_ENA_S: u32 = 4;
pub const SPI_IN_DONE_INT_ENA_V: u32 = 1;
pub const SPI_IN_DONE_INT_ENA_S: u32 = 3;
pub const SPI_INLINK_DSCR_ERROR_INT_ENA_V: u32 = 1;
pub const SPI_INLINK_DSCR_ERROR_INT_ENA_S: u32 = 2;
pub const SPI_OUTLINK_DSCR_ERROR_INT_ENA_V: u32 = 1;
pub const SPI_OUTLINK_DSCR_ERROR_INT_ENA_S: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_ENA_V: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_ENA_S: u32 = 0;
pub const SPI_OUT_TOTAL_EOF_INT_RAW_V: u32 = 1;
pub const SPI_OUT_TOTAL_EOF_INT_RAW_S: u32 = 8;
pub const SPI_OUT_EOF_INT_RAW_V: u32 = 1;
pub const SPI_OUT_EOF_INT_RAW_S: u32 = 7;
pub const SPI_OUT_DONE_INT_RAW_V: u32 = 1;
pub const SPI_OUT_DONE_INT_RAW_S: u32 = 6;
pub const SPI_IN_SUC_EOF_INT_RAW_V: u32 = 1;
pub const SPI_IN_SUC_EOF_INT_RAW_S: u32 = 5;
pub const SPI_IN_ERR_EOF_INT_RAW_V: u32 = 1;
pub const SPI_IN_ERR_EOF_INT_RAW_S: u32 = 4;
pub const SPI_IN_DONE_INT_RAW_V: u32 = 1;
pub const SPI_IN_DONE_INT_RAW_S: u32 = 3;
pub const SPI_INLINK_DSCR_ERROR_INT_RAW_V: u32 = 1;
pub const SPI_INLINK_DSCR_ERROR_INT_RAW_S: u32 = 2;
pub const SPI_OUTLINK_DSCR_ERROR_INT_RAW_V: u32 = 1;
pub const SPI_OUTLINK_DSCR_ERROR_INT_RAW_S: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_RAW_V: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_RAW_S: u32 = 0;
pub const SPI_OUT_TOTAL_EOF_INT_ST_V: u32 = 1;
pub const SPI_OUT_TOTAL_EOF_INT_ST_S: u32 = 8;
pub const SPI_OUT_EOF_INT_ST_V: u32 = 1;
pub const SPI_OUT_EOF_INT_ST_S: u32 = 7;
pub const SPI_OUT_DONE_INT_ST_V: u32 = 1;
pub const SPI_OUT_DONE_INT_ST_S: u32 = 6;
pub const SPI_IN_SUC_EOF_INT_ST_V: u32 = 1;
pub const SPI_IN_SUC_EOF_INT_ST_S: u32 = 5;
pub const SPI_IN_ERR_EOF_INT_ST_V: u32 = 1;
pub const SPI_IN_ERR_EOF_INT_ST_S: u32 = 4;
pub const SPI_IN_DONE_INT_ST_V: u32 = 1;
pub const SPI_IN_DONE_INT_ST_S: u32 = 3;
pub const SPI_INLINK_DSCR_ERROR_INT_ST_V: u32 = 1;
pub const SPI_INLINK_DSCR_ERROR_INT_ST_S: u32 = 2;
pub const SPI_OUTLINK_DSCR_ERROR_INT_ST_V: u32 = 1;
pub const SPI_OUTLINK_DSCR_ERROR_INT_ST_S: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_ST_V: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_ST_S: u32 = 0;
pub const SPI_OUT_TOTAL_EOF_INT_CLR_V: u32 = 1;
pub const SPI_OUT_TOTAL_EOF_INT_CLR_S: u32 = 8;
pub const SPI_OUT_EOF_INT_CLR_V: u32 = 1;
pub const SPI_OUT_EOF_INT_CLR_S: u32 = 7;
pub const SPI_OUT_DONE_INT_CLR_V: u32 = 1;
pub const SPI_OUT_DONE_INT_CLR_S: u32 = 6;
pub const SPI_IN_SUC_EOF_INT_CLR_V: u32 = 1;
pub const SPI_IN_SUC_EOF_INT_CLR_S: u32 = 5;
pub const SPI_IN_ERR_EOF_INT_CLR_V: u32 = 1;
pub const SPI_IN_ERR_EOF_INT_CLR_S: u32 = 4;
pub const SPI_IN_DONE_INT_CLR_V: u32 = 1;
pub const SPI_IN_DONE_INT_CLR_S: u32 = 3;
pub const SPI_INLINK_DSCR_ERROR_INT_CLR_V: u32 = 1;
pub const SPI_INLINK_DSCR_ERROR_INT_CLR_S: u32 = 2;
pub const SPI_OUTLINK_DSCR_ERROR_INT_CLR_V: u32 = 1;
pub const SPI_OUTLINK_DSCR_ERROR_INT_CLR_S: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_CLR_V: u32 = 1;
pub const SPI_INLINK_DSCR_EMPTY_INT_CLR_S: u32 = 0;
pub const SPI_DMA_IN_ERR_EOF_DES_ADDR: u32 = 4294967295;
pub const SPI_DMA_IN_ERR_EOF_DES_ADDR_V: u32 = 4294967295;
pub const SPI_DMA_IN_ERR_EOF_DES_ADDR_S: u32 = 0;
pub const SPI_DMA_IN_SUC_EOF_DES_ADDR: u32 = 4294967295;
pub const SPI_DMA_IN_SUC_EOF_DES_ADDR_V: u32 = 4294967295;
pub const SPI_DMA_IN_SUC_EOF_DES_ADDR_S: u32 = 0;
pub const SPI_DMA_INLINK_DSCR: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_V: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_S: u32 = 0;
pub const SPI_DMA_INLINK_DSCR_BF0: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_BF0_V: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_BF0_S: u32 = 0;
pub const SPI_DMA_INLINK_DSCR_BF1: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_BF1_V: u32 = 4294967295;
pub const SPI_DMA_INLINK_DSCR_BF1_S: u32 = 0;
pub const SPI_DMA_OUT_EOF_BFR_DES_ADDR: u32 = 4294967295;
pub const SPI_DMA_OUT_EOF_BFR_DES_ADDR_V: u32 = 4294967295;
pub const SPI_DMA_OUT_EOF_BFR_DES_ADDR_S: u32 = 0;
pub const SPI_DMA_OUT_EOF_DES_ADDR: u32 = 4294967295;
pub const SPI_DMA_OUT_EOF_DES_ADDR_V: u32 = 4294967295;
pub const SPI_DMA_OUT_EOF_DES_ADDR_S: u32 = 0;
pub const SPI_DMA_OUTLINK_DSCR: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_V: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_S: u32 = 0;
pub const SPI_DMA_OUTLINK_DSCR_BF0: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_BF0_V: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_BF0_S: u32 = 0;
pub const SPI_DMA_OUTLINK_DSCR_BF1: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_BF1_V: u32 = 4294967295;
pub const SPI_DMA_OUTLINK_DSCR_BF1_S: u32 = 0;
pub const SPI_DMA_OUT_STATUS: u32 = 4294967295;
pub const SPI_DMA_OUT_STATUS_V: u32 = 4294967295;
pub const SPI_DMA_OUT_STATUS_S: u32 = 0;
pub const SPI_DMA_IN_STATUS: u32 = 4294967295;
pub const SPI_DMA_IN_STATUS_V: u32 = 4294967295;
pub const SPI_DMA_IN_STATUS_S: u32 = 0;
pub const SPI_DATE: u32 = 268435455;
pub const SPI_DATE_V: u32 = 268435455;
pub const SPI_DATE_S: u32 = 0;
pub const SPI_MAX_DMA_LEN: u32 = 4092;
pub const SPICOMMON_BUSFLAG_SLAVE: u32 = 0;
pub const SPICOMMON_BUSFLAG_MASTER: u32 = 1;
pub const SPICOMMON_BUSFLAG_NATIVE_PINS: u32 = 2;
pub const SPICOMMON_BUSFLAG_SCLK: u32 = 4;
pub const SPICOMMON_BUSFLAG_MISO: u32 = 8;
pub const SPICOMMON_BUSFLAG_MOSI: u32 = 16;
pub const SPICOMMON_BUSFLAG_DUAL: u32 = 32;
pub const SPICOMMON_BUSFLAG_WPHD: u32 = 64;
pub const SPICOMMON_BUSFLAG_QUAD: u32 = 96;
pub const SPI_MASTER_FREQ_8M: u32 = 8000000;
pub const SPI_MASTER_FREQ_9M: u32 = 8888888;
pub const SPI_MASTER_FREQ_10M: u32 = 10000000;
pub const SPI_MASTER_FREQ_11M: u32 = 11428571;
pub const SPI_MASTER_FREQ_13M: u32 = 13333333;
pub const SPI_MASTER_FREQ_16M: u32 = 16000000;
pub const SPI_MASTER_FREQ_20M: u32 = 20000000;
pub const SPI_MASTER_FREQ_26M: u32 = 26666666;
pub const SPI_MASTER_FREQ_40M: u32 = 40000000;
pub const SPI_MASTER_FREQ_80M: u32 = 80000000;
pub const SPI_DEVICE_TXBIT_LSBFIRST: u32 = 1;
pub const SPI_DEVICE_RXBIT_LSBFIRST: u32 = 2;
pub const SPI_DEVICE_BIT_LSBFIRST: u32 = 3;
pub const SPI_DEVICE_3WIRE: u32 = 4;
pub const SPI_DEVICE_POSITIVE_CS: u32 = 8;
pub const SPI_DEVICE_HALFDUPLEX: u32 = 16;
pub const SPI_DEVICE_CLK_AS_CS: u32 = 32;
pub const SPI_DEVICE_NO_DUMMY: u32 = 64;
pub const SPI_TRANS_MODE_DIO: u32 = 1;
pub const SPI_TRANS_MODE_QIO: u32 = 2;
pub const SPI_TRANS_USE_RXDATA: u32 = 4;
pub const SPI_TRANS_USE_TXDATA: u32 = 8;
pub const SPI_TRANS_MODE_DIOQIO_ADDR: u32 = 16;
pub const SPI_TRANS_VARIABLE_CMD: u32 = 32;
pub const SPI_TRANS_VARIABLE_ADDR: u32 = 64;
pub const SPI_SLAVE_TXBIT_LSBFIRST: u32 = 1;
pub const SPI_SLAVE_RXBIT_LSBFIRST: u32 = 2;
pub const SPI_SLAVE_BIT_LSBFIRST: u32 = 3;
pub const TIMG_WDT_WKEY_VALUE: u32 = 1356348065;
pub const TIMG_WDT_STG_SEL_OFF: u32 = 0;
pub const TIMG_WDT_STG_SEL_INT: u32 = 1;
pub const TIMG_WDT_STG_SEL_RESET_CPU: u32 = 2;
pub const TIMG_WDT_STG_SEL_RESET_SYSTEM: u32 = 3;
pub const TIMG_T0_EN_V: u32 = 1;
pub const TIMG_T0_EN_S: u32 = 31;
pub const TIMG_T0_INCREASE_V: u32 = 1;
pub const TIMG_T0_INCREASE_S: u32 = 30;
pub const TIMG_T0_AUTORELOAD_V: u32 = 1;
pub const TIMG_T0_AUTORELOAD_S: u32 = 29;
pub const TIMG_T0_DIVIDER: u32 = 65535;
pub const TIMG_T0_DIVIDER_V: u32 = 65535;
pub const TIMG_T0_DIVIDER_S: u32 = 13;
pub const TIMG_T0_EDGE_INT_EN_V: u32 = 1;
pub const TIMG_T0_EDGE_INT_EN_S: u32 = 12;
pub const TIMG_T0_LEVEL_INT_EN_V: u32 = 1;
pub const TIMG_T0_LEVEL_INT_EN_S: u32 = 11;
pub const TIMG_T0_ALARM_EN_V: u32 = 1;
pub const TIMG_T0_ALARM_EN_S: u32 = 10;
pub const TIMG_T0_LO: u32 = 4294967295;
pub const TIMG_T0_LO_V: u32 = 4294967295;
pub const TIMG_T0_LO_S: u32 = 0;
pub const TIMG_T0_HI: u32 = 4294967295;
pub const TIMG_T0_HI_V: u32 = 4294967295;
pub const TIMG_T0_HI_S: u32 = 0;
pub const TIMG_T0_UPDATE: u32 = 4294967295;
pub const TIMG_T0_UPDATE_V: u32 = 4294967295;
pub const TIMG_T0_UPDATE_S: u32 = 0;
pub const TIMG_T0_ALARM_LO: u32 = 4294967295;
pub const TIMG_T0_ALARM_LO_V: u32 = 4294967295;
pub const TIMG_T0_ALARM_LO_S: u32 = 0;
pub const TIMG_T0_ALARM_HI: u32 = 4294967295;
pub const TIMG_T0_ALARM_HI_V: u32 = 4294967295;
pub const TIMG_T0_ALARM_HI_S: u32 = 0;
pub const TIMG_T0_LOAD_LO: u32 = 4294967295;
pub const TIMG_T0_LOAD_LO_V: u32 = 4294967295;
pub const TIMG_T0_LOAD_LO_S: u32 = 0;
pub const TIMG_T0_LOAD_HI: u32 = 4294967295;
pub const TIMG_T0_LOAD_HI_V: u32 = 4294967295;
pub const TIMG_T0_LOAD_HI_S: u32 = 0;
pub const TIMG_T0_LOAD: u32 = 4294967295;
pub const TIMG_T0_LOAD_V: u32 = 4294967295;
pub const TIMG_T0_LOAD_S: u32 = 0;
pub const TIMG_T1_EN_V: u32 = 1;
pub const TIMG_T1_EN_S: u32 = 31;
pub const TIMG_T1_INCREASE_V: u32 = 1;
pub const TIMG_T1_INCREASE_S: u32 = 30;
pub const TIMG_T1_AUTORELOAD_V: u32 = 1;
pub const TIMG_T1_AUTORELOAD_S: u32 = 29;
pub const TIMG_T1_DIVIDER: u32 = 65535;
pub const TIMG_T1_DIVIDER_V: u32 = 65535;
pub const TIMG_T1_DIVIDER_S: u32 = 13;
pub const TIMG_T1_EDGE_INT_EN_V: u32 = 1;
pub const TIMG_T1_EDGE_INT_EN_S: u32 = 12;
pub const TIMG_T1_LEVEL_INT_EN_V: u32 = 1;
pub const TIMG_T1_LEVEL_INT_EN_S: u32 = 11;
pub const TIMG_T1_ALARM_EN_V: u32 = 1;
pub const TIMG_T1_ALARM_EN_S: u32 = 10;
pub const TIMG_T1_LO: u32 = 4294967295;
pub const TIMG_T1_LO_V: u32 = 4294967295;
pub const TIMG_T1_LO_S: u32 = 0;
pub const TIMG_T1_HI: u32 = 4294967295;
pub const TIMG_T1_HI_V: u32 = 4294967295;
pub const TIMG_T1_HI_S: u32 = 0;
pub const TIMG_T1_UPDATE: u32 = 4294967295;
pub const TIMG_T1_UPDATE_V: u32 = 4294967295;
pub const TIMG_T1_UPDATE_S: u32 = 0;
pub const TIMG_T1_ALARM_LO: u32 = 4294967295;
pub const TIMG_T1_ALARM_LO_V: u32 = 4294967295;
pub const TIMG_T1_ALARM_LO_S: u32 = 0;
pub const TIMG_T1_ALARM_HI: u32 = 4294967295;
pub const TIMG_T1_ALARM_HI_V: u32 = 4294967295;
pub const TIMG_T1_ALARM_HI_S: u32 = 0;
pub const TIMG_T1_LOAD_LO: u32 = 4294967295;
pub const TIMG_T1_LOAD_LO_V: u32 = 4294967295;
pub const TIMG_T1_LOAD_LO_S: u32 = 0;
pub const TIMG_T1_LOAD_HI: u32 = 4294967295;
pub const TIMG_T1_LOAD_HI_V: u32 = 4294967295;
pub const TIMG_T1_LOAD_HI_S: u32 = 0;
pub const TIMG_T1_LOAD: u32 = 4294967295;
pub const TIMG_T1_LOAD_V: u32 = 4294967295;
pub const TIMG_T1_LOAD_S: u32 = 0;
pub const TIMG_WDT_EN_V: u32 = 1;
pub const TIMG_WDT_EN_S: u32 = 31;
pub const TIMG_WDT_STG0: u32 = 3;
pub const TIMG_WDT_STG0_V: u32 = 3;
pub const TIMG_WDT_STG0_S: u32 = 29;
pub const TIMG_WDT_STG1: u32 = 3;
pub const TIMG_WDT_STG1_V: u32 = 3;
pub const TIMG_WDT_STG1_S: u32 = 27;
pub const TIMG_WDT_STG2: u32 = 3;
pub const TIMG_WDT_STG2_V: u32 = 3;
pub const TIMG_WDT_STG2_S: u32 = 25;
pub const TIMG_WDT_STG3: u32 = 3;
pub const TIMG_WDT_STG3_V: u32 = 3;
pub const TIMG_WDT_STG3_S: u32 = 23;
pub const TIMG_WDT_EDGE_INT_EN_V: u32 = 1;
pub const TIMG_WDT_EDGE_INT_EN_S: u32 = 22;
pub const TIMG_WDT_LEVEL_INT_EN_V: u32 = 1;
pub const TIMG_WDT_LEVEL_INT_EN_S: u32 = 21;
pub const TIMG_WDT_CPU_RESET_LENGTH: u32 = 7;
pub const TIMG_WDT_CPU_RESET_LENGTH_V: u32 = 7;
pub const TIMG_WDT_CPU_RESET_LENGTH_S: u32 = 18;
pub const TIMG_WDT_SYS_RESET_LENGTH: u32 = 7;
pub const TIMG_WDT_SYS_RESET_LENGTH_V: u32 = 7;
pub const TIMG_WDT_SYS_RESET_LENGTH_S: u32 = 15;
pub const TIMG_WDT_FLASHBOOT_MOD_EN_V: u32 = 1;
pub const TIMG_WDT_FLASHBOOT_MOD_EN_S: u32 = 14;
pub const TIMG_WDT_CLK_PRESCALE: u32 = 65535;
pub const TIMG_WDT_CLK_PRESCALE_V: u32 = 65535;
pub const TIMG_WDT_CLK_PRESCALE_S: u32 = 16;
pub const TIMG_WDT_STG0_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG0_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG0_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG1_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG1_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG1_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG2_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG2_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG2_HOLD_S: u32 = 0;
pub const TIMG_WDT_STG3_HOLD: u32 = 4294967295;
pub const TIMG_WDT_STG3_HOLD_V: u32 = 4294967295;
pub const TIMG_WDT_STG3_HOLD_S: u32 = 0;
pub const TIMG_WDT_FEED: u32 = 4294967295;
pub const TIMG_WDT_FEED_V: u32 = 4294967295;
pub const TIMG_WDT_FEED_S: u32 = 0;
pub const TIMG_WDT_WKEY: u32 = 4294967295;
pub const TIMG_WDT_WKEY_V: u32 = 4294967295;
pub const TIMG_WDT_WKEY_S: u32 = 0;
pub const TIMG_RTC_CALI_START_V: u32 = 1;
pub const TIMG_RTC_CALI_START_S: u32 = 31;
pub const TIMG_RTC_CALI_MAX: u32 = 32767;
pub const TIMG_RTC_CALI_MAX_V: u32 = 32767;
pub const TIMG_RTC_CALI_MAX_S: u32 = 16;
pub const TIMG_RTC_CALI_RDY_V: u32 = 1;
pub const TIMG_RTC_CALI_RDY_S: u32 = 15;
pub const TIMG_RTC_CALI_CLK_SEL: u32 = 3;
pub const TIMG_RTC_CALI_CLK_SEL_V: u32 = 3;
pub const TIMG_RTC_CALI_CLK_SEL_S: u32 = 13;
pub const TIMG_RTC_CALI_START_CYCLING_V: u32 = 1;
pub const TIMG_RTC_CALI_START_CYCLING_S: u32 = 12;
pub const TIMG_RTC_CALI_VALUE: u32 = 33554431;
pub const TIMG_RTC_CALI_VALUE_V: u32 = 33554431;
pub const TIMG_RTC_CALI_VALUE_S: u32 = 7;
pub const TIMG_LACT_EN_V: u32 = 1;
pub const TIMG_LACT_EN_S: u32 = 31;
pub const TIMG_LACT_INCREASE_V: u32 = 1;
pub const TIMG_LACT_INCREASE_S: u32 = 30;
pub const TIMG_LACT_AUTORELOAD_V: u32 = 1;
pub const TIMG_LACT_AUTORELOAD_S: u32 = 29;
pub const TIMG_LACT_DIVIDER: u32 = 65535;
pub const TIMG_LACT_DIVIDER_V: u32 = 65535;
pub const TIMG_LACT_DIVIDER_S: u32 = 13;
pub const TIMG_LACT_EDGE_INT_EN_V: u32 = 1;
pub const TIMG_LACT_EDGE_INT_EN_S: u32 = 12;
pub const TIMG_LACT_LEVEL_INT_EN_V: u32 = 1;
pub const TIMG_LACT_LEVEL_INT_EN_S: u32 = 11;
pub const TIMG_LACT_ALARM_EN_V: u32 = 1;
pub const TIMG_LACT_ALARM_EN_S: u32 = 10;
pub const TIMG_LACT_LAC_EN_V: u32 = 1;
pub const TIMG_LACT_LAC_EN_S: u32 = 9;
pub const TIMG_LACT_CPST_EN_V: u32 = 1;
pub const TIMG_LACT_CPST_EN_S: u32 = 8;
pub const TIMG_LACT_RTC_ONLY_V: u32 = 1;
pub const TIMG_LACT_RTC_ONLY_S: u32 = 7;
pub const TIMG_LACT_RTC_STEP_LEN: u32 = 67108863;
pub const TIMG_LACT_RTC_STEP_LEN_V: u32 = 67108863;
pub const TIMG_LACT_RTC_STEP_LEN_S: u32 = 6;
pub const TIMG_LACT_LO: u32 = 4294967295;
pub const TIMG_LACT_LO_V: u32 = 4294967295;
pub const TIMG_LACT_LO_S: u32 = 0;
pub const TIMG_LACT_HI: u32 = 4294967295;
pub const TIMG_LACT_HI_V: u32 = 4294967295;
pub const TIMG_LACT_HI_S: u32 = 0;
pub const TIMG_LACT_UPDATE: u32 = 4294967295;
pub const TIMG_LACT_UPDATE_V: u32 = 4294967295;
pub const TIMG_LACT_UPDATE_S: u32 = 0;
pub const TIMG_LACT_ALARM_LO: u32 = 4294967295;
pub const TIMG_LACT_ALARM_LO_V: u32 = 4294967295;
pub const TIMG_LACT_ALARM_LO_S: u32 = 0;
pub const TIMG_LACT_ALARM_HI: u32 = 4294967295;
pub const TIMG_LACT_ALARM_HI_V: u32 = 4294967295;
pub const TIMG_LACT_ALARM_HI_S: u32 = 0;
pub const TIMG_LACT_LOAD_LO: u32 = 4294967295;
pub const TIMG_LACT_LOAD_LO_V: u32 = 4294967295;
pub const TIMG_LACT_LOAD_LO_S: u32 = 0;
pub const TIMG_LACT_LOAD_HI: u32 = 4294967295;
pub const TIMG_LACT_LOAD_HI_V: u32 = 4294967295;
pub const TIMG_LACT_LOAD_HI_S: u32 = 0;
pub const TIMG_LACT_LOAD: u32 = 4294967295;
pub const TIMG_LACT_LOAD_V: u32 = 4294967295;
pub const TIMG_LACT_LOAD_S: u32 = 0;
pub const TIMG_LACT_INT_ENA_V: u32 = 1;
pub const TIMG_LACT_INT_ENA_S: u32 = 3;
pub const TIMG_WDT_INT_ENA_V: u32 = 1;
pub const TIMG_WDT_INT_ENA_S: u32 = 2;
pub const TIMG_T1_INT_ENA_V: u32 = 1;
pub const TIMG_T1_INT_ENA_S: u32 = 1;
pub const TIMG_T0_INT_ENA_V: u32 = 1;
pub const TIMG_T0_INT_ENA_S: u32 = 0;
pub const TIMG_LACT_INT_RAW_V: u32 = 1;
pub const TIMG_LACT_INT_RAW_S: u32 = 3;
pub const TIMG_WDT_INT_RAW_V: u32 = 1;
pub const TIMG_WDT_INT_RAW_S: u32 = 2;
pub const TIMG_T1_INT_RAW_V: u32 = 1;
pub const TIMG_T1_INT_RAW_S: u32 = 1;
pub const TIMG_T0_INT_RAW_V: u32 = 1;
pub const TIMG_T0_INT_RAW_S: u32 = 0;
pub const TIMG_LACT_INT_ST_V: u32 = 1;
pub const TIMG_LACT_INT_ST_S: u32 = 3;
pub const TIMG_WDT_INT_ST_V: u32 = 1;
pub const TIMG_WDT_INT_ST_S: u32 = 2;
pub const TIMG_T1_INT_ST_V: u32 = 1;
pub const TIMG_T1_INT_ST_S: u32 = 1;
pub const TIMG_T0_INT_ST_V: u32 = 1;
pub const TIMG_T0_INT_ST_S: u32 = 0;
pub const TIMG_LACT_INT_CLR_V: u32 = 1;
pub const TIMG_LACT_INT_CLR_S: u32 = 3;
pub const TIMG_WDT_INT_CLR_V: u32 = 1;
pub const TIMG_WDT_INT_CLR_S: u32 = 2;
pub const TIMG_T1_INT_CLR_V: u32 = 1;
pub const TIMG_T1_INT_CLR_S: u32 = 1;
pub const TIMG_T0_INT_CLR_V: u32 = 1;
pub const TIMG_T0_INT_CLR_S: u32 = 0;
pub const TIMG_NTIMERS_DATE: u32 = 268435455;
pub const TIMG_NTIMERS_DATE_V: u32 = 268435455;
pub const TIMG_NTIMERS_DATE_S: u32 = 0;
pub const TIMG_CLK_EN_V: u32 = 1;
pub const TIMG_CLK_EN_S: u32 = 31;
pub const TIMER_BASE_CLK: u32 = 80000000;
pub const UART_NUM_0_TXD_DIRECT_GPIO_NUM: u32 = 1;
pub const UART_NUM_0_RXD_DIRECT_GPIO_NUM: u32 = 3;
pub const UART_NUM_0_CTS_DIRECT_GPIO_NUM: u32 = 19;
pub const UART_NUM_0_RTS_DIRECT_GPIO_NUM: u32 = 22;
pub const UART_NUM_1_TXD_DIRECT_GPIO_NUM: u32 = 10;
pub const UART_NUM_1_RXD_DIRECT_GPIO_NUM: u32 = 9;
pub const UART_NUM_1_CTS_DIRECT_GPIO_NUM: u32 = 6;
pub const UART_NUM_1_RTS_DIRECT_GPIO_NUM: u32 = 11;
pub const UART_NUM_2_TXD_DIRECT_GPIO_NUM: u32 = 17;
pub const UART_NUM_2_RXD_DIRECT_GPIO_NUM: u32 = 16;
pub const UART_NUM_2_CTS_DIRECT_GPIO_NUM: u32 = 8;
pub const UART_NUM_2_RTS_DIRECT_GPIO_NUM: u32 = 7;
pub const UART_FIFO_LEN: u32 = 128;
pub const UART_INTR_MASK: u32 = 511;
pub const UART_LINE_INV_MASK: u32 = 33030144;
pub const UART_BITRATE_MAX: u32 = 5000000;
pub const UART_PIN_NO_CHANGE: i32 = -1;
pub const UART_INVERSE_DISABLE: u32 = 0;
pub type wchar_t = ::std::os::raw::c_uchar;
#[repr(C)]
#[repr(align(8))]
#[derive(Debug, Copy, Clone)]
pub struct max_align_t {
pub __clang_max_align_nonce1: ::std::os::raw::c_longlong,
pub __clang_max_align_nonce2: f64,
}
pub type __int8_t = ::std::os::raw::c_schar;
pub type __uint8_t = ::std::os::raw::c_uchar;
pub type __int16_t = ::std::os::raw::c_short;
pub type __uint16_t = ::std::os::raw::c_ushort;
pub type __int32_t = ::std::os::raw::c_int;
pub type __uint32_t = ::std::os::raw::c_uint;
pub type __int64_t = ::std::os::raw::c_longlong;
pub type __uint64_t = ::std::os::raw::c_ulonglong;
pub type __int_least8_t = __int8_t;
pub type __uint_least8_t = __uint8_t;
pub type __int_least16_t = __int16_t;
pub type __uint_least16_t = __uint16_t;
pub type __int_least32_t = __int32_t;
pub type __uint_least32_t = __uint32_t;
pub type __int_least64_t = __int64_t;
pub type __uint_least64_t = __uint64_t;
pub type __intptr_t = ::std::os::raw::c_int;
pub type __uintptr_t = ::std::os::raw::c_uint;
pub type _lock_t = ::std::os::raw::c_int;
pub type _LOCK_RECURSIVE_T = _lock_t;
pub type _LOCK_T = _lock_t;
extern "C" {
pub fn _lock_init(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_init_recursive(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_close(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_close_recursive(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_acquire(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_acquire_recursive(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_try_acquire(lock: *mut _lock_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _lock_try_acquire_recursive(lock: *mut _lock_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _lock_release(lock: *mut _lock_t);
}
extern "C" {
pub fn _lock_release_recursive(lock: *mut _lock_t);
}
pub type _off_t = ::std::os::raw::c_long;
pub type __dev_t = ::std::os::raw::c_short;
pub type __uid_t = ::std::os::raw::c_ushort;
pub type __gid_t = ::std::os::raw::c_ushort;
pub type _off64_t = ::std::os::raw::c_longlong;
pub type _fpos_t = ::std::os::raw::c_long;
pub type _ssize_t = ::std::os::raw::c_int;
pub type wint_t = ::std::os::raw::c_uint;
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _mbstate_t {
pub __count: ::std::os::raw::c_int,
pub __value: _mbstate_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _mbstate_t__bindgen_ty_1 {
pub __wch: wint_t,
pub __wchb: [::std::os::raw::c_uchar; 4usize],
_bindgen_union_align: u32,
}
pub type _flock_t = _LOCK_RECURSIVE_T;
pub type _iconv_t = *mut ::std::os::raw::c_void;
pub type __ULong = ::std::os::raw::c_ulong;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _Bigint {
pub _next: *mut _Bigint,
pub _k: ::std::os::raw::c_int,
pub _maxwds: ::std::os::raw::c_int,
pub _sign: ::std::os::raw::c_int,
pub _wds: ::std::os::raw::c_int,
pub _x: [__ULong; 1usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __tm {
pub __tm_sec: ::std::os::raw::c_int,
pub __tm_min: ::std::os::raw::c_int,
pub __tm_hour: ::std::os::raw::c_int,
pub __tm_mday: ::std::os::raw::c_int,
pub __tm_mon: ::std::os::raw::c_int,
pub __tm_year: ::std::os::raw::c_int,
pub __tm_wday: ::std::os::raw::c_int,
pub __tm_yday: ::std::os::raw::c_int,
pub __tm_isdst: ::std::os::raw::c_int,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _on_exit_args {
pub _fnargs: [*mut ::std::os::raw::c_void; 32usize],
pub _dso_handle: [*mut ::std::os::raw::c_void; 32usize],
pub _fntypes: __ULong,
pub _is_cxa: __ULong,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _atexit {
pub _next: *mut _atexit,
pub _ind: ::std::os::raw::c_int,
pub _fns: [::core::option::Option<unsafe extern "C" fn()>; 32usize],
pub _on_exit_args_ptr: *mut _on_exit_args,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __sbuf {
pub _base: *mut ::std::os::raw::c_uchar,
pub _size: ::std::os::raw::c_int,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __sFILE_fake {
pub _p: *mut ::std::os::raw::c_uchar,
pub _r: ::std::os::raw::c_int,
pub _w: ::std::os::raw::c_int,
pub _flags: ::std::os::raw::c_short,
pub _file: ::std::os::raw::c_short,
pub _bf: __sbuf,
pub _lbfsize: ::std::os::raw::c_int,
pub _data: *mut _reent,
}
extern "C" {
pub fn __sinit(arg1: *mut _reent);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct __sFILE {
pub _p: *mut ::std::os::raw::c_uchar,
pub _r: ::std::os::raw::c_int,
pub _w: ::std::os::raw::c_int,
pub _flags: ::std::os::raw::c_short,
pub _file: ::std::os::raw::c_short,
pub _bf: __sbuf,
pub _lbfsize: ::std::os::raw::c_int,
pub _data: *mut _reent,
pub _cookie: *mut ::std::os::raw::c_void,
pub _read: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: *mut ::std::os::raw::c_char,
arg4: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
pub _write: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: *const ::std::os::raw::c_char,
arg4: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
pub _seek: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: _fpos_t,
arg4: ::std::os::raw::c_int,
) -> _fpos_t,
>,
pub _close: ::core::option::Option<
unsafe extern "C" fn(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
) -> ::std::os::raw::c_int,
>,
pub _ub: __sbuf,
pub _up: *mut ::std::os::raw::c_uchar,
pub _ur: ::std::os::raw::c_int,
pub _ubuf: [::std::os::raw::c_uchar; 3usize],
pub _nbuf: [::std::os::raw::c_uchar; 1usize],
pub _lb: __sbuf,
pub _blksize: ::std::os::raw::c_int,
pub _offset: _off_t,
pub _lock: _flock_t,
pub _mbstate: _mbstate_t,
pub _flags2: ::std::os::raw::c_int,
}
pub type __FILE = __sFILE;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _glue {
pub _next: *mut _glue,
pub _niobs: ::std::os::raw::c_int,
pub _iobs: *mut __FILE,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _rand48 {
pub _seed: [::std::os::raw::c_ushort; 3usize],
pub _mult: [::std::os::raw::c_ushort; 3usize],
pub _add: ::std::os::raw::c_ushort,
pub _rand_next: ::std::os::raw::c_ulonglong,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _mprec {
pub _result: *mut _Bigint,
pub _result_k: ::std::os::raw::c_int,
pub _p5s: *mut _Bigint,
pub _freelist: *mut *mut _Bigint,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _misc_reent {
pub _strtok_last: *mut ::std::os::raw::c_char,
pub _mblen_state: _mbstate_t,
pub _wctomb_state: _mbstate_t,
pub _mbtowc_state: _mbstate_t,
pub _l64a_buf: [::std::os::raw::c_char; 8usize],
pub _getdate_err: ::std::os::raw::c_int,
pub _mbrlen_state: _mbstate_t,
pub _mbrtowc_state: _mbstate_t,
pub _mbsrtowcs_state: _mbstate_t,
pub _wcrtomb_state: _mbstate_t,
pub _wcsrtombs_state: _mbstate_t,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _reent {
pub _errno: ::std::os::raw::c_int,
pub _stdin: *mut __FILE,
pub _stdout: *mut __FILE,
pub _stderr: *mut __FILE,
pub _inc: ::std::os::raw::c_int,
pub _emergency: *mut ::std::os::raw::c_char,
pub __sdidinit: ::std::os::raw::c_int,
pub _current_category: ::std::os::raw::c_int,
pub _current_locale: *const ::std::os::raw::c_char,
pub _mp: *mut _mprec,
pub __cleanup: ::core::option::Option<unsafe extern "C" fn(arg1: *mut _reent)>,
pub _gamma_signgam: ::std::os::raw::c_int,
pub _cvtlen: ::std::os::raw::c_int,
pub _cvtbuf: *mut ::std::os::raw::c_char,
pub _r48: *mut _rand48,
pub _localtime_buf: *mut __tm,
pub _asctime_buf: *mut ::std::os::raw::c_char,
pub _sig_func: *mut ::core::option::Option<unsafe extern "C" fn(arg1: ::std::os::raw::c_int)>,
pub _atexit: *mut _atexit,
pub _atexit0: _atexit,
pub __sglue: _glue,
pub __sf: *mut __FILE,
pub _misc: *mut _misc_reent,
pub _signal_buf: *mut ::std::os::raw::c_char,
}
extern "C" {
pub static __sf_fake_stdin: __sFILE_fake;
}
extern "C" {
pub static __sf_fake_stdout: __sFILE_fake;
}
extern "C" {
pub static __sf_fake_stderr: __sFILE_fake;
}
extern "C" {
pub static mut _global_impure_ptr: *mut _reent;
}
extern "C" {
pub fn _reclaim_reent(arg1: *mut _reent);
}
extern "C" {
pub fn __getreent() -> *mut _reent;
}
pub type int_least8_t = __int_least8_t;
pub type uint_least8_t = __uint_least8_t;
pub type int_least16_t = __int_least16_t;
pub type uint_least16_t = __uint_least16_t;
pub type int_least32_t = __int_least32_t;
pub type uint_least32_t = __uint_least32_t;
pub type int_least64_t = __int_least64_t;
pub type uint_least64_t = __uint_least64_t;
pub type int_fast8_t = ::std::os::raw::c_schar;
pub type uint_fast8_t = ::std::os::raw::c_uchar;
pub type int_fast16_t = ::std::os::raw::c_short;
pub type uint_fast16_t = ::std::os::raw::c_ushort;
pub type int_fast32_t = ::std::os::raw::c_int;
pub type uint_fast32_t = ::std::os::raw::c_uint;
pub type int_fast64_t = ::std::os::raw::c_longlong;
pub type uint_fast64_t = ::std::os::raw::c_ulonglong;
pub type intmax_t = ::std::os::raw::c_longlong;
pub type uintmax_t = ::std::os::raw::c_ulonglong;
extern "C" {
#[doc = " This function is defined to provide a deprecation warning whenever"]
#[doc = " XT_CLOCK_FREQ macro is used."]
#[doc = " Update the code to use esp_clk_cpu_freq function instead."]
#[doc = " @return current CPU clock frequency, in Hz"]
pub fn xt_clock_freq() -> ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_rev_no: ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_save_extra(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_extra(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cpregs(base: *mut ::std::os::raw::c_void, arg1: ::std::os::raw::c_int);
}
extern "C" {
pub fn xthal_restore_cpregs(base: *mut ::std::os::raw::c_void, arg1: ::std::os::raw::c_int);
}
extern "C" {
pub fn xthal_save_cp0(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp1(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp2(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp3(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp4(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp5(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp6(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_save_cp7(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp0(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp1(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp2(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp3(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp4(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp5(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp6(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_restore_cp7(base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub static mut Xthal_cpregs_save_fn: [*mut ::std::os::raw::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_restore_fn: [*mut ::std::os::raw::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_save_nw_fn: [*mut ::std::os::raw::c_void; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_restore_nw_fn: [*mut ::std::os::raw::c_void; 8usize];
}
extern "C" {
pub static Xthal_extra_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_extra_align: ::std::os::raw::c_uint;
}
extern "C" {
pub static mut Xthal_cpregs_size: [::std::os::raw::c_uint; 8usize];
}
extern "C" {
pub static mut Xthal_cpregs_align: [::std::os::raw::c_uint; 8usize];
}
extern "C" {
pub static Xthal_all_extra_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_all_extra_align: ::std::os::raw::c_uint;
}
extern "C" {
pub static mut Xthal_cp_names: [*const ::std::os::raw::c_char; 8usize];
}
extern "C" {
pub fn xthal_init_mem_extra(arg1: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_init_mem_cp(arg1: *mut ::std::os::raw::c_void, arg2: ::std::os::raw::c_int);
}
extern "C" {
pub static Xthal_num_coprocessors: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_num: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_max: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_num_aregs: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_num_aregs_log2: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_icache_linewidth: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dcache_linewidth: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_icache_linesize: ::std::os::raw::c_ushort;
}
extern "C" {
pub static Xthal_dcache_linesize: ::std::os::raw::c_ushort;
}
extern "C" {
pub static Xthal_icache_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_dcache_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_dcache_is_writeback: ::std::os::raw::c_uchar;
}
extern "C" {
pub fn xthal_icache_region_invalidate(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_dcache_region_invalidate(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_icache_line_invalidate(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_dcache_line_invalidate(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_dcache_region_writeback(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_dcache_line_writeback(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_dcache_region_writeback_inv(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_dcache_line_writeback_inv(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_icache_sync();
}
extern "C" {
pub fn xthal_dcache_sync();
}
extern "C" {
pub fn xthal_icache_get_ways() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_icache_set_ways(ways: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_dcache_get_ways() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_dcache_set_ways(ways: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_cache_coherence_on();
}
extern "C" {
pub fn xthal_cache_coherence_off();
}
extern "C" {
pub fn xthal_cache_coherence_optin();
}
extern "C" {
pub fn xthal_cache_coherence_optout();
}
extern "C" {
pub fn xthal_get_cache_prefetch() -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_cache_prefetch(arg1: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_cache_prefetch_long(
arg1: ::std::os::raw::c_ulonglong,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_debug_configured: ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_soft_break(addr: *mut ::std::os::raw::c_void) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_remove_soft_break(addr: *mut ::std::os::raw::c_void, arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_disassemble(
instr_buf: *mut ::std::os::raw::c_uchar,
tgt_addr: *mut ::std::os::raw::c_void,
buffer: *mut ::std::os::raw::c_char,
buflen: ::std::os::raw::c_uint,
options: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_disassemble_size(instr_buf: *mut ::std::os::raw::c_uchar)
-> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_memcpy(
dst: *mut ::std::os::raw::c_void,
src: *const ::std::os::raw::c_void,
len: ::std::os::raw::c_uint,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn xthal_bcopy(
src: *const ::std::os::raw::c_void,
dst: *mut ::std::os::raw::c_void,
len: ::std::os::raw::c_uint,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn xthal_compare_and_set(
addr: *mut ::std::os::raw::c_int,
test_val: ::std::os::raw::c_int,
compare_val: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_release_major: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_release_minor: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_release_name: *const ::std::os::raw::c_char;
}
extern "C" {
pub static Xthal_release_internal: *const ::std::os::raw::c_char;
}
extern "C" {
pub static Xthal_memory_order: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_windowed: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_density: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_booleans: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_loops: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_nsa: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_minmax: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_sext: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_clamps: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_mac16: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_mul16: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_fp: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_speculation: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_threadptr: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_pif: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_writebuffer_entries: ::std::os::raw::c_ushort;
}
extern "C" {
pub static Xthal_build_unique_id: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_hw_configid0: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_hw_configid1: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_hw_release_major: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_hw_release_minor: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_hw_release_name: *const ::std::os::raw::c_char;
}
extern "C" {
pub static Xthal_hw_release_internal: *const ::std::os::raw::c_char;
}
extern "C" {
pub fn xthal_clear_regcached_code();
}
extern "C" {
pub fn xthal_window_spill();
}
extern "C" {
pub fn xthal_validate_cp(arg1: ::std::os::raw::c_int);
}
extern "C" {
pub fn xthal_invalidate_cp(arg1: ::std::os::raw::c_int);
}
extern "C" {
pub fn xthal_set_cpenable(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_get_cpenable() -> ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_num_intlevels: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_interrupts: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_excm_level: ::std::os::raw::c_uchar;
}
extern "C" {
pub static mut Xthal_intlevel_mask: [::std::os::raw::c_uint; 16usize];
}
extern "C" {
pub static mut Xthal_intlevel_andbelow_mask: [::std::os::raw::c_uint; 16usize];
}
extern "C" {
pub static mut Xthal_intlevel: [::std::os::raw::c_uchar; 32usize];
}
extern "C" {
pub static mut Xthal_inttype: [::std::os::raw::c_uchar; 32usize];
}
extern "C" {
pub static mut Xthal_inttype_mask: [::std::os::raw::c_uint; 8usize];
}
extern "C" {
pub static mut Xthal_timer_interrupt: [::std::os::raw::c_int; 4usize];
}
extern "C" {
pub fn xthal_get_intenable() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_intenable(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_get_interrupt() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_intset(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_set_intclear(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub static Xthal_num_ibreak: ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_num_dbreak: ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_have_ccount: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_ccompare: ::std::os::raw::c_uchar;
}
extern "C" {
pub fn xthal_get_ccount() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_ccompare(arg1: ::std::os::raw::c_int, arg2: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_get_ccompare(arg1: ::std::os::raw::c_int) -> ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_have_prid: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_exceptions: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_xea_version: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_interrupts: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_highlevel_interrupts: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_nmi: ::std::os::raw::c_uchar;
}
extern "C" {
pub fn xthal_get_prid() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_vpri_to_intlevel(vpri: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_intlevel_to_vpri(intlevel: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_int_enable(arg1: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_int_disable(arg1: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_int_vpri(
intnum: ::std::os::raw::c_int,
vpri: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_get_int_vpri(intnum: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_vpri_locklevel(intlevel: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_get_vpri_locklevel() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_vpri(vpri: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_get_vpri() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_vpri_intlevel(intlevel: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_vpri_lock() -> ::std::os::raw::c_uint;
}
pub type XtHalVoidFunc = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
pub static mut Xthal_tram_pending: ::std::os::raw::c_uint;
}
extern "C" {
pub static mut Xthal_tram_enabled: ::std::os::raw::c_uint;
}
extern "C" {
pub static mut Xthal_tram_sync: ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_tram_pending_to_service() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_tram_done(serviced_mask: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_tram_set_sync(
intnum: ::std::os::raw::c_int,
sync: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_tram_trigger_func(trigger_fn: XtHalVoidFunc) -> XtHalVoidFunc;
}
extern "C" {
pub static Xthal_num_instrom: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_instram: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_datarom: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_dataram: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_num_xlmi: ::std::os::raw::c_uchar;
}
extern "C" {
pub static mut Xthal_instrom_vaddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instrom_paddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instrom_size: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_vaddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_paddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_instram_size: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_vaddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_paddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_datarom_size: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_vaddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_paddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_dataram_size: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_vaddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_paddr: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static mut Xthal_xlmi_size: [::std::os::raw::c_uint; 0usize];
}
extern "C" {
pub static Xthal_icache_setwidth: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dcache_setwidth: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_icache_ways: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_dcache_ways: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_icache_line_lockable: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dcache_line_lockable: ::std::os::raw::c_uchar;
}
extern "C" {
pub fn xthal_get_cacheattr() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_get_icacheattr() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_get_dcacheattr() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn xthal_set_cacheattr(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_set_icacheattr(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_set_dcacheattr(arg1: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xthal_set_region_attribute(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
cattr: ::std::os::raw::c_uint,
flags: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_icache_enable();
}
extern "C" {
pub fn xthal_dcache_enable();
}
extern "C" {
pub fn xthal_icache_disable();
}
extern "C" {
pub fn xthal_dcache_disable();
}
extern "C" {
pub fn xthal_icache_all_invalidate();
}
extern "C" {
pub fn xthal_dcache_all_invalidate();
}
extern "C" {
pub fn xthal_dcache_all_writeback();
}
extern "C" {
pub fn xthal_dcache_all_writeback_inv();
}
extern "C" {
pub fn xthal_icache_region_lock(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_dcache_region_lock(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_icache_line_lock(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_dcache_line_lock(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_icache_all_unlock();
}
extern "C" {
pub fn xthal_dcache_all_unlock();
}
extern "C" {
pub fn xthal_icache_region_unlock(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_dcache_region_unlock(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
);
}
extern "C" {
pub fn xthal_icache_line_unlock(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_dcache_line_unlock(addr: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xthal_memep_inject_error(
addr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_int,
flags: ::std::os::raw::c_int,
);
}
extern "C" {
pub static Xthal_have_spanning_way: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_identity_map: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_mimic_cacheattr: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_xlt_cacheattr: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_cacheattr: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_have_tlbs: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_asid_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_asid_kernel: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_rings: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_ring_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_sr_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_ca_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_mmu_max_pte_page_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_mmu_min_pte_page_size: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_itlb_way_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_itlb_ways: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_itlb_arf_ways: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_way_bits: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_ways: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_dtlb_arf_ways: ::std::os::raw::c_uchar;
}
extern "C" {
#[doc = " WARNING: these two functions may go away in a future release; don't depend on them!"]
pub fn xthal_static_v2p(
vaddr: ::std::os::raw::c_uint,
paddrp: *mut ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_static_p2v(
paddr: ::std::os::raw::c_uint,
vaddrp: *mut ::std::os::raw::c_uint,
cached: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_region_translation(
vaddr: *mut ::std::os::raw::c_void,
paddr: *mut ::std::os::raw::c_void,
size: ::std::os::raw::c_uint,
cache_atr: ::std::os::raw::c_uint,
flags: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_v2p(
arg1: *mut ::std::os::raw::c_void,
arg2: *mut *mut ::std::os::raw::c_void,
arg3: *mut ::std::os::raw::c_uint,
arg4: *mut ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_invalidate_region(addr: *mut ::std::os::raw::c_void) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn xthal_set_region_translation_raw(
vaddr: *mut ::std::os::raw::c_void,
paddr: *mut ::std::os::raw::c_void,
cattr: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub static Xthal_cp_id_FPU: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_FPU: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP1_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP1_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP2_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP2_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP3_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP3_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP4_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP4_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP5_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP5_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP6_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP6_IDENT: ::std::os::raw::c_uint;
}
extern "C" {
pub static Xthal_cp_id_XCHAL_CP7_IDENT: ::std::os::raw::c_uchar;
}
extern "C" {
pub static Xthal_cp_mask_XCHAL_CP7_IDENT: ::std::os::raw::c_uint;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct KernelFrame {
pub pc: ::std::os::raw::c_long,
pub ps: ::std::os::raw::c_long,
pub areg: [::std::os::raw::c_long; 4usize],
pub sar: ::std::os::raw::c_long,
pub lcount: ::std::os::raw::c_long,
pub lbeg: ::std::os::raw::c_long,
pub lend: ::std::os::raw::c_long,
pub acclo: ::std::os::raw::c_long,
pub acchi: ::std::os::raw::c_long,
pub mr: [::std::os::raw::c_long; 4usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct UserFrame {
pub pc: ::std::os::raw::c_long,
pub ps: ::std::os::raw::c_long,
pub sar: ::std::os::raw::c_long,
pub vpri: ::std::os::raw::c_long,
pub a2: ::std::os::raw::c_long,
pub a3: ::std::os::raw::c_long,
pub a4: ::std::os::raw::c_long,
pub a5: ::std::os::raw::c_long,
pub exccause: ::std::os::raw::c_long,
pub lcount: ::std::os::raw::c_long,
pub lbeg: ::std::os::raw::c_long,
pub lend: ::std::os::raw::c_long,
pub acclo: ::std::os::raw::c_long,
pub acchi: ::std::os::raw::c_long,
pub mr: [::std::os::raw::c_long; 4usize],
pub pad: [::std::os::raw::c_long; 2usize],
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct XtExcFrame {
pub exit: ::std::os::raw::c_long,
pub pc: ::std::os::raw::c_long,
pub ps: ::std::os::raw::c_long,
pub a0: ::std::os::raw::c_long,
pub a1: ::std::os::raw::c_long,
pub a2: ::std::os::raw::c_long,
pub a3: ::std::os::raw::c_long,
pub a4: ::std::os::raw::c_long,
pub a5: ::std::os::raw::c_long,
pub a6: ::std::os::raw::c_long,
pub a7: ::std::os::raw::c_long,
pub a8: ::std::os::raw::c_long,
pub a9: ::std::os::raw::c_long,
pub a10: ::std::os::raw::c_long,
pub a11: ::std::os::raw::c_long,
pub a12: ::std::os::raw::c_long,
pub a13: ::std::os::raw::c_long,
pub a14: ::std::os::raw::c_long,
pub a15: ::std::os::raw::c_long,
pub sar: ::std::os::raw::c_long,
pub exccause: ::std::os::raw::c_long,
pub excvaddr: ::std::os::raw::c_long,
pub lbeg: ::std::os::raw::c_long,
pub lend: ::std::os::raw::c_long,
pub lcount: ::std::os::raw::c_long,
pub tmp0: ::std::os::raw::c_long,
pub tmp1: ::std::os::raw::c_long,
pub tmp2: ::std::os::raw::c_long,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct XtSolFrame {
pub exit: ::std::os::raw::c_long,
pub pc: ::std::os::raw::c_long,
pub ps: ::std::os::raw::c_long,
pub next: ::std::os::raw::c_long,
pub a0: ::std::os::raw::c_long,
pub a1: ::std::os::raw::c_long,
pub a2: ::std::os::raw::c_long,
pub a3: ::std::os::raw::c_long,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct div_t {
pub quot: ::std::os::raw::c_int,
pub rem: ::std::os::raw::c_int,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct ldiv_t {
pub quot: ::std::os::raw::c_long,
pub rem: ::std::os::raw::c_long,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct lldiv_t {
pub quot: ::std::os::raw::c_longlong,
pub rem: ::std::os::raw::c_longlong,
}
pub type __compar_fn_t = ::core::option::Option<
unsafe extern "C" fn(
arg1: *const ::std::os::raw::c_void,
arg2: *const ::std::os::raw::c_void,
) -> ::std::os::raw::c_int,
>;
extern "C" {
pub fn __locale_mb_cur_max() -> ::std::os::raw::c_int;
}
extern "C" {
pub fn abort();
}
extern "C" {
pub fn abs(arg1: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn atexit(__func: ::core::option::Option<unsafe extern "C" fn()>) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn atof(__nptr: *const ::std::os::raw::c_char) -> f64;
}
extern "C" {
pub fn atoff(__nptr: *const ::std::os::raw::c_char) -> f32;
}
extern "C" {
pub fn atoi(__nptr: *const ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _atoi_r(
arg1: *mut _reent,
__nptr: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn atol(__nptr: *const ::std::os::raw::c_char) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _atol_r(
arg1: *mut _reent,
__nptr: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn bsearch(
__key: *const ::std::os::raw::c_void,
__base: *const ::std::os::raw::c_void,
__nmemb: usize,
__size: usize,
_compar: __compar_fn_t,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn calloc(
__nmemb: ::std::os::raw::c_uint,
__size: ::std::os::raw::c_uint,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn div(__numer: ::std::os::raw::c_int, __denom: ::std::os::raw::c_int) -> div_t;
}
extern "C" {
pub fn exit(__status: ::std::os::raw::c_int);
}
extern "C" {
pub fn free(arg1: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn getenv(__string: *const ::std::os::raw::c_char) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _getenv_r(
arg1: *mut _reent,
__string: *const ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _findenv(
arg1: *const ::std::os::raw::c_char,
arg2: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _findenv_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub static mut suboptarg: *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn getsubopt(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *const *mut ::std::os::raw::c_char,
arg3: *mut *mut ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn labs(arg1: ::std::os::raw::c_long) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn ldiv(__numer: ::std::os::raw::c_long, __denom: ::std::os::raw::c_long) -> ldiv_t;
}
extern "C" {
pub fn malloc(__size: ::std::os::raw::c_uint) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn mblen(arg1: *const ::std::os::raw::c_char, arg2: usize) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mblen_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: usize,
arg4: *mut _mbstate_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mbtowc(
arg1: *mut wchar_t,
arg2: *const ::std::os::raw::c_char,
arg3: usize,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mbtowc_r(
arg1: *mut _reent,
arg2: *mut wchar_t,
arg3: *const ::std::os::raw::c_char,
arg4: usize,
arg5: *mut _mbstate_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn wctomb(arg1: *mut ::std::os::raw::c_char, arg2: wchar_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _wctomb_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: wchar_t,
arg4: *mut _mbstate_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mbstowcs(arg1: *mut wchar_t, arg2: *const ::std::os::raw::c_char, arg3: usize) -> usize;
}
extern "C" {
pub fn _mbstowcs_r(
arg1: *mut _reent,
arg2: *mut wchar_t,
arg3: *const ::std::os::raw::c_char,
arg4: usize,
arg5: *mut _mbstate_t,
) -> usize;
}
extern "C" {
pub fn wcstombs(arg1: *mut ::std::os::raw::c_char, arg2: *const wchar_t, arg3: usize) -> usize;
}
extern "C" {
pub fn _wcstombs_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *const wchar_t,
arg4: usize,
arg5: *mut _mbstate_t,
) -> usize;
}
extern "C" {
pub fn mkdtemp(arg1: *mut ::std::os::raw::c_char) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn mkostemp(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mkostemps(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
arg3: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mkstemp(arg1: *mut ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mkstemps(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn mktemp(arg1: *mut ::std::os::raw::c_char) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _mkdtemp_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _mkostemp_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mkostemps_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
arg4: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mkstemp_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mkstemps_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _mktemp_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn qsort(
__base: *mut ::std::os::raw::c_void,
__nmemb: usize,
__size: usize,
_compar: __compar_fn_t,
);
}
extern "C" {
pub fn rand() -> ::std::os::raw::c_int;
}
extern "C" {
pub fn realloc(
__r: *mut ::std::os::raw::c_void,
__size: ::std::os::raw::c_uint,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn reallocf(__r: *mut ::std::os::raw::c_void, __size: usize)
-> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn realpath(
path: *const ::std::os::raw::c_char,
resolved_path: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn srand(__seed: ::std::os::raw::c_uint);
}
extern "C" {
pub fn strtod(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
) -> f64;
}
extern "C" {
pub fn _strtod_r(
arg1: *mut _reent,
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
) -> f64;
}
extern "C" {
pub fn strtof(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
) -> f32;
}
extern "C" {
pub fn strtol(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _strtol_r(
arg1: *mut _reent,
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn strtoul(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_ulong;
}
extern "C" {
pub fn _strtoul_r(
arg1: *mut _reent,
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_ulong;
}
extern "C" {
pub fn system(__string: *const ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn a64l(__input: *const ::std::os::raw::c_char) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn l64a(__input: ::std::os::raw::c_long) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _l64a_r(
arg1: *mut _reent,
__input: ::std::os::raw::c_long,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn on_exit(
__func: ::core::option::Option<
unsafe extern "C" fn(arg1: ::std::os::raw::c_int, arg2: *mut ::std::os::raw::c_void),
>,
__arg: *mut ::std::os::raw::c_void,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _Exit(__status: ::std::os::raw::c_int);
}
extern "C" {
pub fn putenv(__string: *mut ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _putenv_r(
arg1: *mut _reent,
__string: *mut ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _reallocf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn setenv(
__string: *const ::std::os::raw::c_char,
__value: *const ::std::os::raw::c_char,
__overwrite: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _setenv_r(
arg1: *mut _reent,
__string: *const ::std::os::raw::c_char,
__value: *const ::std::os::raw::c_char,
__overwrite: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn gcvt(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn gcvtf(
arg1: f32,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn fcvt(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn fcvtf(
arg1: f32,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn ecvt(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn ecvtbuf(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
arg5: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn fcvtbuf(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
arg5: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn ecvtf(
arg1: f32,
arg2: ::std::os::raw::c_int,
arg3: *mut ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn dtoa(
arg1: f64,
arg2: ::std::os::raw::c_int,
arg3: ::std::os::raw::c_int,
arg4: *mut ::std::os::raw::c_int,
arg5: *mut ::std::os::raw::c_int,
arg6: *mut *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn __itoa(
arg1: ::std::os::raw::c_int,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn __utoa(
arg1: ::std::os::raw::c_uint,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn itoa(
arg1: ::std::os::raw::c_int,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn utoa(
arg1: ::std::os::raw::c_uint,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn rand_r(__seed: *mut ::std::os::raw::c_uint) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn drand48() -> f64;
}
extern "C" {
pub fn _drand48_r(arg1: *mut _reent) -> f64;
}
extern "C" {
pub fn erand48(arg1: *mut ::std::os::raw::c_ushort) -> f64;
}
extern "C" {
pub fn _erand48_r(arg1: *mut _reent, arg2: *mut ::std::os::raw::c_ushort) -> f64;
}
extern "C" {
pub fn jrand48(arg1: *mut ::std::os::raw::c_ushort) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _jrand48_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_ushort,
) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn lcong48(arg1: *mut ::std::os::raw::c_ushort);
}
extern "C" {
pub fn _lcong48_r(arg1: *mut _reent, arg2: *mut ::std::os::raw::c_ushort);
}
extern "C" {
pub fn lrand48() -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _lrand48_r(arg1: *mut _reent) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn mrand48() -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _mrand48_r(arg1: *mut _reent) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn nrand48(arg1: *mut ::std::os::raw::c_ushort) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _nrand48_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_ushort,
) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn seed48(arg1: *mut ::std::os::raw::c_ushort) -> *mut ::std::os::raw::c_ushort;
}
extern "C" {
pub fn _seed48_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_ushort,
) -> *mut ::std::os::raw::c_ushort;
}
extern "C" {
pub fn srand48(arg1: ::std::os::raw::c_long);
}
extern "C" {
pub fn _srand48_r(arg1: *mut _reent, arg2: ::std::os::raw::c_long);
}
extern "C" {
pub fn atoll(__nptr: *const ::std::os::raw::c_char) -> ::std::os::raw::c_longlong;
}
extern "C" {
pub fn _atoll_r(
arg1: *mut _reent,
__nptr: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_longlong;
}
extern "C" {
pub fn llabs(arg1: ::std::os::raw::c_longlong) -> ::std::os::raw::c_longlong;
}
extern "C" {
pub fn lldiv(
__numer: ::std::os::raw::c_longlong,
__denom: ::std::os::raw::c_longlong,
) -> lldiv_t;
}
extern "C" {
pub fn strtoll(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_longlong;
}
extern "C" {
pub fn _strtoll_r(
arg1: *mut _reent,
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_longlong;
}
extern "C" {
pub fn strtoull(
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_ulonglong;
}
extern "C" {
pub fn _strtoull_r(
arg1: *mut _reent,
__n: *const ::std::os::raw::c_char,
__end_PTR: *mut *mut ::std::os::raw::c_char,
__base: ::std::os::raw::c_int,
) -> ::std::os::raw::c_ulonglong;
}
extern "C" {
pub fn cfree(arg1: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn unsetenv(__string: *const ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _unsetenv_r(
arg1: *mut _reent,
__string: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _dtoa_r(
arg1: *mut _reent,
arg2: f64,
arg3: ::std::os::raw::c_int,
arg4: ::std::os::raw::c_int,
arg5: *mut ::std::os::raw::c_int,
arg6: *mut ::std::os::raw::c_int,
arg7: *mut *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _malloc_r(arg1: *mut _reent, arg2: usize) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn _calloc_r(arg1: *mut _reent, arg2: usize, arg3: usize) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn _free_r(arg1: *mut _reent, arg2: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn _realloc_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn _mstats_r(arg1: *mut _reent, arg2: *mut ::std::os::raw::c_char);
}
extern "C" {
pub fn _system_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn __eprintf(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: ::std::os::raw::c_uint,
arg4: *const ::std::os::raw::c_char,
);
}
extern "C" {
pub fn strtold(
arg1: *const ::std::os::raw::c_char,
arg2: *mut *mut ::std::os::raw::c_char,
) -> f64;
}
extern "C" {
pub fn __assert(
arg1: *const ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
);
}
extern "C" {
pub fn __assert_func(
arg1: *const ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
arg4: *const ::std::os::raw::c_char,
);
}
#[doc = "< return successful in ets"]
pub const ETS_STATUS_ETS_OK: ETS_STATUS = 0;
#[doc = "< return failed in ets"]
pub const ETS_STATUS_ETS_FAILED: ETS_STATUS = 1;
#[doc = " @addtogroup ets_apis"]
#[doc = " @{"]
pub type ETS_STATUS = u32;
pub type ETSSignal = u32;
pub type ETSParam = u32;
pub type ETSEvent = ETSEventTag;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct ETSEventTag {
#[doc = "< Event signal, in same task, different Event with different signal"]
pub sig: ETSSignal,
#[doc = "< Event parameter, sometimes without usage, then will be set as 0"]
pub par: ETSParam,
}
pub type ETSTask = ::core::option::Option<unsafe extern "C" fn(e: *mut ETSEvent)>;
pub type ets_idle_cb_t =
::core::option::Option<unsafe extern "C" fn(arg: *mut ::std::os::raw::c_void)>;
extern "C" {
#[doc = " @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it."]
#[doc = ""]
#[doc = " @param none"]
#[doc = ""]
#[doc = " @return none"]
pub fn ets_run();
}
extern "C" {
#[doc = " @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep."]
#[doc = ""]
#[doc = " @param ets_idle_cb_t func : The callback function."]
#[doc = ""]
#[doc = " @param void *arg : Argument of the callback."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_idle_cb(func: ets_idle_cb_t, arg: *mut ::std::os::raw::c_void);
}
extern "C" {
#[doc = " @brief Init a task with processer, priority, queue to receive Event, queue length."]
#[doc = ""]
#[doc = " @param ETSTask task : The task processer."]
#[doc = ""]
#[doc = " @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task."]
#[doc = ""]
#[doc = " @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used."]
#[doc = ""]
#[doc = " @param uint8_t qlen : Queue length."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_task(task: ETSTask, prio: u8, queue: *mut ETSEvent, qlen: u8);
}
extern "C" {
#[doc = " @brief Post an event to an Task."]
#[doc = ""]
#[doc = " @param uint8_t prio : Priority of the Task."]
#[doc = ""]
#[doc = " @param ETSSignal sig : Event signal."]
#[doc = ""]
#[doc = " @param ETSParam par : Event parameter"]
#[doc = ""]
#[doc = " @return ETS_OK : post successful"]
#[doc = " @return ETS_FAILED : post failed"]
pub fn ets_post(prio: u8, sig: ETSSignal, par: ETSParam) -> ETS_STATUS;
}
extern "C" {
pub static mut exc_cause_table: [*const ::std::os::raw::c_char; 40usize];
}
extern "C" {
#[doc = " @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed."]
#[doc = " When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL."]
#[doc = ""]
#[doc = " @param uint32_t start : the PRO Entry code address value in uint32_t"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_user_start(start: u32);
}
extern "C" {
#[doc = " @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code."]
#[doc = " When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run."]
#[doc = ""]
#[doc = " @param uint32_t callback : the Startup code address value in uint32_t"]
#[doc = ""]
#[doc = " @return None : post successful"]
pub fn ets_set_startup_callback(callback: u32);
}
extern "C" {
#[doc = " @brief Set App cpu Entry code, code can be called in PRO CPU."]
#[doc = " When APP booting is completed, APP CPU will call the Entry code if not NULL."]
#[doc = ""]
#[doc = " @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_set_appcpu_boot_addr(start: u32);
}
extern "C" {
#[doc = " @brief unpack the image in flash to iram and dram, no using cache."]
#[doc = ""]
#[doc = " @param uint32_t pos : Flash physical address."]
#[doc = ""]
#[doc = " @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address."]
#[doc = ""]
#[doc = " @param bool jump : Jump into the code in the function or not."]
#[doc = ""]
#[doc = " @param bool config : Config the flash when unpacking the image, config should be done only once."]
#[doc = ""]
#[doc = " @return ETS_OK : unpack successful"]
#[doc = " @return ETS_FAILED : unpack failed"]
pub fn ets_unpack_flash_code_legacy(
pos: u32,
entry_addr: *mut u32,
jump: bool,
config: bool,
) -> ETS_STATUS;
}
extern "C" {
#[doc = " @brief unpack the image in flash to iram and dram, using cache, maybe decrypting."]
#[doc = ""]
#[doc = " @param uint32_t pos : Flash physical address."]
#[doc = ""]
#[doc = " @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address."]
#[doc = ""]
#[doc = " @param bool jump : Jump into the code in the function or not."]
#[doc = ""]
#[doc = " @param bool sb_need_check : Do security boot check or not."]
#[doc = ""]
#[doc = " @param bool config : Config the flash when unpacking the image, config should be done only once."]
#[doc = ""]
#[doc = " @return ETS_OK : unpack successful"]
#[doc = " @return ETS_FAILED : unpack failed"]
pub fn ets_unpack_flash_code(
pos: u32,
entry_addr: *mut u32,
jump: bool,
sb_need_check: bool,
config: bool,
) -> ETS_STATUS;
}
extern "C" {
#[doc = " @brief Printf the strings to uart or other devices, similar with printf, simple than printf."]
#[doc = " Can not print float point data format, or longlong data format."]
#[doc = " So we maybe only use this in ROM."]
#[doc = ""]
#[doc = " @param const char *fmt : See printf."]
#[doc = ""]
#[doc = " @param ... : See printf."]
#[doc = ""]
#[doc = " @return int : the length printed to the output device."]
pub fn ets_printf(fmt: *const ::std::os::raw::c_char, ...) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function."]
#[doc = " Can not print float point data format, or longlong data format"]
#[doc = ""]
#[doc = " @param char c : char to output."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_write_char_uart(c: ::std::os::raw::c_char);
}
extern "C" {
#[doc = " @brief Ets_printf have two output functions\u{ff1a} putc1 and putc2, both of which will be called if need ouput."]
#[doc = " To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode."]
#[doc = ""]
#[doc = " @param void (*)(char) p: Output function to install."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_putc1(
p: ::core::option::Option<unsafe extern "C" fn(c: ::std::os::raw::c_char)>,
);
}
extern "C" {
#[doc = " @brief Ets_printf have two output functions\u{ff1a} putc1 and putc2, both of which will be called if need ouput."]
#[doc = " To install putc2, which is defaulted installed as NULL."]
#[doc = ""]
#[doc = " @param void (*)(char) p: Output function to install."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_putc2(
p: ::core::option::Option<unsafe extern "C" fn(c: ::std::os::raw::c_char)>,
);
}
extern "C" {
#[doc = " @brief Install putc1 as ets_write_char_uart."]
#[doc = " In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_install_uart_printf();
}
#[doc = " @addtogroup ets_timer_apis"]
#[doc = " @{"]
pub type ETSTimerFunc =
::core::option::Option<unsafe extern "C" fn(timer_arg: *mut ::std::os::raw::c_void)>;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _ETSTIMER_ {
#[doc = "< timer linker"]
pub timer_next: *mut _ETSTIMER_,
#[doc = "< abstruct time when timer expire"]
pub timer_expire: u32,
#[doc = "< timer period, 0 means timer is not periodic repeated"]
pub timer_period: u32,
#[doc = "< timer handler"]
pub timer_func: ETSTimerFunc,
#[doc = "< timer handler argument"]
pub timer_arg: *mut ::std::os::raw::c_void,
}
pub type ETSTimer = _ETSTIMER_;
extern "C" {
#[doc = " @brief Init ets timer, this timer range is 640 us to 429496 ms"]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_init();
}
extern "C" {
#[doc = " @brief In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_deinit();
}
extern "C" {
#[doc = " @brief Arm an ets timer, this timer range is 640 us to 429496 ms."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param uint32_t tmout : Timer value in ms, range is 1 to 429496."]
#[doc = ""]
#[doc = " @param bool repeat : Timer is periodic repeated."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_arm(timer: *mut ETSTimer, tmout: u32, repeat: bool);
}
extern "C" {
#[doc = " @brief Arm an ets timer, this timer range is 640 us to 429496 ms."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param uint32_t tmout : Timer value in us, range is 1 to 429496729."]
#[doc = ""]
#[doc = " @param bool repeat : Timer is periodic repeated."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_arm_us(ptimer: *mut ETSTimer, us: u32, repeat: bool);
}
extern "C" {
#[doc = " @brief Disarm an ets timer."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_disarm(timer: *mut ETSTimer);
}
extern "C" {
#[doc = " @brief Set timer callback and argument."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @param ETSTimerFunc *pfunction : Timer callback."]
#[doc = ""]
#[doc = " @param void *parg : Timer callback argument."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_setfn(
ptimer: *mut ETSTimer,
pfunction: ETSTimerFunc,
parg: *mut ::std::os::raw::c_void,
);
}
extern "C" {
#[doc = " @brief Unset timer callback and argument to NULL."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param ETSTimer *timer : Timer struct pointer."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_timer_done(ptimer: *mut ETSTimer);
}
extern "C" {
#[doc = " @brief CPU do while loop for some time."]
#[doc = " In FreeRTOS task, please call FreeRTOS apis."]
#[doc = ""]
#[doc = " @param uint32_t us : Delay time in us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_delay_us(us: u32);
}
extern "C" {
#[doc = " @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate."]
#[doc = " Call this function when CPU frequency is changed."]
#[doc = ""]
#[doc = " @param uint32_t ticks_per_us : CPU ticks per us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_update_cpu_frequency(ticks_per_us: u32);
}
extern "C" {
#[doc = " @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate."]
#[doc = ""]
#[doc = " @note This function only sets the tick rate for the current CPU. It is located in ROM,"]
#[doc = " so the deep sleep stub can use it even if IRAM is not initialized yet."]
#[doc = ""]
#[doc = " @param uint32_t ticks_per_us : CPU ticks per us."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_update_cpu_frequency_rom(ticks_per_us: u32);
}
extern "C" {
#[doc = " @brief Get the real CPU ticks per us to the ets."]
#[doc = " This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : CPU ticks per us record in ets."]
pub fn ets_get_cpu_frequency() -> u32;
}
extern "C" {
#[doc = " @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : xtal_freq/analog_8M*256."]
pub fn ets_get_xtal_scale() -> u32;
}
extern "C" {
#[doc = " @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register."]
#[doc = " clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;"]
#[doc = " else if analog_8M in efuse"]
#[doc = " clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;"]
#[doc = " else clock = 26M."]
pub fn ets_get_detected_xtal_freq() -> u32;
}
#[doc = " @addtogroup ets_intr_apis"]
#[doc = " @{"]
pub type ets_isr_t =
::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>;
extern "C" {
#[doc = " @brief Attach a interrupt handler to a CPU interrupt number."]
#[doc = " This function equals to _xtos_set_interrupt_handler_arg(i, func, arg)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param int i : CPU interrupt number."]
#[doc = ""]
#[doc = " @param ets_isr_t func : Interrupt handler."]
#[doc = ""]
#[doc = " @param void *arg : argument of the handler."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_attach(
i: ::std::os::raw::c_int,
func: ets_isr_t,
arg: *mut ::std::os::raw::c_void,
);
}
extern "C" {
#[doc = " @brief Mask the interrupts which show in mask bits."]
#[doc = " This function equals to _xtos_ints_off(mask)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param uint32_t mask : BIT(i) means mask CPU interrupt number i."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_mask(mask: u32);
}
extern "C" {
#[doc = " @brief Unmask the interrupts which show in mask bits."]
#[doc = " This function equals to _xtos_ints_on(mask)."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param uint32_t mask : BIT(i) means mask CPU interrupt number i."]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_isr_unmask(unmask: u32);
}
extern "C" {
#[doc = " @brief Lock the interrupt to level 2."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_intr_lock();
}
extern "C" {
#[doc = " @brief Unlock the interrupt to level 0."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_intr_unlock();
}
extern "C" {
#[doc = " @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt)."]
#[doc = " This function direct set the CPU registers."]
#[doc = " In FreeRTOS, please call FreeRTOS apis, never call this api."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn ets_waiti0();
}
extern "C" {
#[doc = " @brief Attach an CPU interrupt to a hardware source."]
#[doc = " We have 4 steps to use an interrupt:"]
#[doc = " 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);"]
#[doc = " 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);"]
#[doc = " 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);"]
#[doc = " 4.Enable interrupt in the module."]
#[doc = ""]
#[doc = " @param int cpu_no : The CPU which the interrupt number belongs."]
#[doc = ""]
#[doc = " @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table."]
#[doc = ""]
#[doc = " @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table."]
#[doc = ""]
#[doc = " @return None"]
pub fn intr_matrix_set(cpu_no: ::std::os::raw::c_int, model_num: u32, intr_num: u32);
}
pub const STATUS_OK: STATUS = 0;
pub const STATUS_FAIL: STATUS = 1;
pub const STATUS_PENDING: STATUS = 2;
pub const STATUS_BUSY: STATUS = 3;
pub const STATUS_CANCEL: STATUS = 4;
pub type STATUS = u32;
pub type TaskFunction_t =
::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>;
#[repr(C)]
pub struct XtosCoreState {
pub signature: ::std::os::raw::c_long,
pub restore_label: ::std::os::raw::c_long,
pub aftersave_label: ::std::os::raw::c_long,
pub areg: [::std::os::raw::c_long; 64usize],
pub caller_regs: [::std::os::raw::c_long; 16usize],
pub caller_regs_saved: ::std::os::raw::c_long,
pub windowbase: ::std::os::raw::c_long,
pub windowstart: ::std::os::raw::c_long,
pub sar: ::std::os::raw::c_long,
pub epc1: ::std::os::raw::c_long,
pub ps: ::std::os::raw::c_long,
pub excsave1: ::std::os::raw::c_long,
pub depc: ::std::os::raw::c_long,
pub epc: [::std::os::raw::c_long; 6usize],
pub eps: [::std::os::raw::c_long; 6usize],
pub excsave: [::std::os::raw::c_long; 6usize],
pub lcount: ::std::os::raw::c_long,
pub lbeg: ::std::os::raw::c_long,
pub lend: ::std::os::raw::c_long,
pub vecbase: ::std::os::raw::c_long,
pub atomctl: ::std::os::raw::c_long,
pub memctl: ::std::os::raw::c_long,
pub ccount: ::std::os::raw::c_long,
pub ccompare: [::std::os::raw::c_long; 3usize],
pub intenable: ::std::os::raw::c_long,
pub interrupt: ::std::os::raw::c_long,
pub icount: ::std::os::raw::c_long,
pub icountlevel: ::std::os::raw::c_long,
pub debugcause: ::std::os::raw::c_long,
pub dbreakc: [::std::os::raw::c_long; 2usize],
pub dbreaka: [::std::os::raw::c_long; 2usize],
pub ibreaka: [::std::os::raw::c_long; 2usize],
pub ibreakenable: ::std::os::raw::c_long,
pub misc: [::std::os::raw::c_long; 4usize],
pub cpenable: ::std::os::raw::c_long,
pub tlbs: [::std::os::raw::c_long; 16usize],
pub ncp: [::std::os::raw::c_char; 48usize],
pub cp0: [::std::os::raw::c_char; 72usize],
pub cp1: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp2: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp3: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp4: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp5: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp6: __IncompleteArrayField<::std::os::raw::c_char>,
pub cp7: __IncompleteArrayField<::std::os::raw::c_char>,
}
pub type _xtos_handler_func = ::core::option::Option<unsafe extern "C" fn()>;
pub type _xtos_handler = _xtos_handler_func;
extern "C" {
pub fn _xtos_ints_off(mask: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_ints_on(mask: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_set_intlevel(intlevel: ::std::os::raw::c_int) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_set_min_intlevel(intlevel: ::std::os::raw::c_int) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_restore_intlevel(restoreval: ::std::os::raw::c_uint) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_restore_just_intlevel(
restoreval: ::std::os::raw::c_uint,
) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_set_interrupt_handler(n: ::std::os::raw::c_int, f: _xtos_handler)
-> _xtos_handler;
}
extern "C" {
pub fn _xtos_set_interrupt_handler_arg(
n: ::std::os::raw::c_int,
f: _xtos_handler,
arg: *mut ::std::os::raw::c_void,
) -> _xtos_handler;
}
extern "C" {
pub fn _xtos_set_exception_handler(n: ::std::os::raw::c_int, f: _xtos_handler)
-> _xtos_handler;
}
extern "C" {
pub fn _xtos_memep_initrams();
}
extern "C" {
pub fn _xtos_memep_enable(flags: ::std::os::raw::c_int);
}
extern "C" {
pub fn _xtos_dispatch_level1_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level2_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level3_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level4_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level5_interrupts();
}
extern "C" {
pub fn _xtos_dispatch_level6_interrupts();
}
extern "C" {
pub fn _xtos_read_ints() -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn _xtos_clear_ints(mask: ::std::os::raw::c_uint);
}
extern "C" {
pub fn _xtos_core_shutoff(flags: ::std::os::raw::c_uint) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _xtos_core_save(
flags: ::std::os::raw::c_uint,
savearea: *mut XtosCoreState,
code: *mut ::std::os::raw::c_void,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _xtos_core_restore(retvalue: ::std::os::raw::c_uint, savearea: *mut XtosCoreState);
}
extern "C" {
pub fn _xtos_timer_0_delta(cycles: ::std::os::raw::c_int);
}
extern "C" {
pub fn _xtos_timer_1_delta(cycles: ::std::os::raw::c_int);
}
extern "C" {
pub fn _xtos_timer_2_delta(cycles: ::std::os::raw::c_int);
}
extern "C" {
#[doc = " Initialize the crosscore interrupt system for this CPU."]
#[doc = " This needs to be called once on every CPU that is used"]
#[doc = " by FreeRTOS."]
#[doc = ""]
#[doc = " If multicore FreeRTOS support is enabled, this will be"]
#[doc = " called automatically by the startup code and should not"]
#[doc = " be called manually."]
pub fn esp_crosscore_int_init();
}
extern "C" {
#[doc = " Send an interrupt to a CPU indicating it should yield its"]
#[doc = " currently running task in favour of a higher-priority task"]
#[doc = " that presumably just woke up."]
#[doc = ""]
#[doc = " This is used internally by FreeRTOS in multicore mode"]
#[doc = " and should not be called by the user."]
#[doc = ""]
#[doc = " @param core_id Core that should do the yielding"]
pub fn esp_crosscore_int_send_yield(core_id: ::std::os::raw::c_int);
}
extern "C" {
#[doc = " Send an interrupt to a CPU indicating it should update its"]
#[doc = " CCOMPARE1 value due to a frequency switch."]
#[doc = ""]
#[doc = " This is used internally when dynamic frequency switching is"]
#[doc = " enabled, and should not be called from application code."]
#[doc = ""]
#[doc = " @param core_id Core that should update its CCOMPARE1 value"]
pub fn esp_crosscore_int_send_freq_switch(core_id: ::std::os::raw::c_int);
}
pub type va_list = __builtin_va_list;
pub type __gnuc_va_list = __builtin_va_list;
pub type __off_t = ::std::os::raw::c_long;
pub type __pid_t = ::std::os::raw::c_int;
pub type __loff_t = ::std::os::raw::c_longlong;
pub type u_char = ::std::os::raw::c_uchar;
pub type u_short = ::std::os::raw::c_ushort;
pub type u_int = ::std::os::raw::c_uint;
pub type u_long = ::std::os::raw::c_ulong;
pub type ushort = ::std::os::raw::c_ushort;
pub type uint = ::std::os::raw::c_uint;
pub type ulong = ::std::os::raw::c_ulong;
pub type clock_t = ::std::os::raw::c_ulong;
pub type time_t = ::std::os::raw::c_long;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct timespec {
pub tv_sec: time_t,
pub tv_nsec: ::std::os::raw::c_long,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct itimerspec {
pub it_interval: timespec,
pub it_value: timespec,
}
pub type daddr_t = ::std::os::raw::c_long;
pub type caddr_t = *mut ::std::os::raw::c_char;
pub type ino_t = ::std::os::raw::c_ushort;
pub type off_t = _off_t;
pub type dev_t = __dev_t;
pub type uid_t = __uid_t;
pub type gid_t = __gid_t;
pub type pid_t = ::std::os::raw::c_int;
pub type key_t = ::std::os::raw::c_long;
pub type mode_t = ::std::os::raw::c_uint;
pub type nlink_t = ::std::os::raw::c_ushort;
pub type fd_mask = ::std::os::raw::c_long;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _types_fd_set {
pub fds_bits: [fd_mask; 2usize],
}
pub type clockid_t = ::std::os::raw::c_ulong;
pub type timer_t = ::std::os::raw::c_ulong;
pub type useconds_t = ::std::os::raw::c_ulong;
pub type suseconds_t = ::std::os::raw::c_long;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct sched_param {
pub sched_priority: ::std::os::raw::c_int,
}
extern "C" {
pub fn sched_yield() -> ::std::os::raw::c_int;
}
pub type pthread_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct pthread_attr_t {
pub is_initialized: ::std::os::raw::c_int,
pub stackaddr: *mut ::std::os::raw::c_void,
pub stacksize: ::std::os::raw::c_int,
pub contentionscope: ::std::os::raw::c_int,
pub inheritsched: ::std::os::raw::c_int,
pub schedpolicy: ::std::os::raw::c_int,
pub schedparam: sched_param,
pub detachstate: ::std::os::raw::c_int,
}
pub type pthread_mutex_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct pthread_mutexattr_t {
pub is_initialized: ::std::os::raw::c_int,
pub type_: ::std::os::raw::c_int,
pub recursive: ::std::os::raw::c_int,
}
pub type pthread_cond_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct pthread_condattr_t {
pub is_initialized: ::std::os::raw::c_int,
}
pub type pthread_key_t = __uint32_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct pthread_once_t {
pub is_initialized: ::std::os::raw::c_int,
pub init_executed: ::std::os::raw::c_int,
}
pub type FILE = __FILE;
pub type fpos_t = _fpos_t;
extern "C" {
pub fn tmpfile() -> *mut FILE;
}
extern "C" {
pub fn tmpnam(arg1: *mut ::std::os::raw::c_char) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn tempnam(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn fclose(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fflush(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn freopen(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: *mut FILE,
) -> *mut FILE;
}
extern "C" {
pub fn setbuf(arg1: *mut FILE, arg2: *mut ::std::os::raw::c_char);
}
extern "C" {
pub fn setvbuf(
arg1: *mut FILE,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
arg4: usize,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fprintf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fscanf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn printf(arg1: *const ::std::os::raw::c_char, ...) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn scanf(arg1: *const ::std::os::raw::c_char, ...) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn sscanf(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vfprintf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
arg3: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vprintf(
arg1: *const ::std::os::raw::c_char,
arg2: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fgetc(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fgets(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn fputc(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fputs(arg1: *const ::std::os::raw::c_char, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn getc(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn getchar() -> ::std::os::raw::c_int;
}
extern "C" {
pub fn gets(arg1: *mut ::std::os::raw::c_char) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn putc(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn putchar(arg1: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn puts(arg1: *const ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn ungetc(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fread(
arg1: *mut ::std::os::raw::c_void,
_size: ::std::os::raw::c_uint,
_n: ::std::os::raw::c_uint,
arg2: *mut FILE,
) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn fwrite(
arg1: *const ::std::os::raw::c_void,
_size: ::std::os::raw::c_uint,
_n: ::std::os::raw::c_uint,
arg2: *mut FILE,
) -> ::std::os::raw::c_uint;
}
extern "C" {
pub fn fgetpos(arg1: *mut FILE, arg2: *mut fpos_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fseek(
arg1: *mut FILE,
arg2: ::std::os::raw::c_long,
arg3: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fsetpos(arg1: *mut FILE, arg2: *const fpos_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn ftell(arg1: *mut FILE) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn rewind(arg1: *mut FILE);
}
extern "C" {
pub fn clearerr(arg1: *mut FILE);
}
extern "C" {
pub fn feof(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn ferror(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn perror(arg1: *const ::std::os::raw::c_char);
}
extern "C" {
pub fn fopen(
_name: *const ::std::os::raw::c_char,
_type: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn sprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn remove(arg1: *const ::std::os::raw::c_char) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn rename(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fseeko(
arg1: *mut FILE,
arg2: off_t,
arg3: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn ftello(arg1: *mut FILE) -> off_t;
}
extern "C" {
pub fn asiprintf(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn asniprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: *const ::std::os::raw::c_char,
...
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn asnprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: *const ::std::os::raw::c_char,
...
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn asprintf(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn diprintf(
arg1: ::std::os::raw::c_int,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fiprintf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fiscanf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn iprintf(arg1: *const ::std::os::raw::c_char, ...) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn iscanf(arg1: *const ::std::os::raw::c_char, ...) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn siprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn siscanf(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn snprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_uint,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn sniprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: usize,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vasiprintf(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vasniprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn vasnprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn vasprintf(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vdiprintf(
arg1: ::std::os::raw::c_int,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vfiprintf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vfiscanf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vfscanf(
arg1: *mut FILE,
arg2: *const ::std::os::raw::c_char,
arg3: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn viprintf(
arg1: *const ::std::os::raw::c_char,
arg2: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn viscanf(
arg1: *const ::std::os::raw::c_char,
arg2: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vscanf(
arg1: *const ::std::os::raw::c_char,
arg2: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsiprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsiscanf(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsniprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: usize,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsnprintf(
arg1: *mut ::std::os::raw::c_char,
arg2: ::std::os::raw::c_uint,
arg3: *const ::std::os::raw::c_char,
arg4: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vsscanf(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
arg3: __builtin_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fdopen(arg1: ::std::os::raw::c_int, arg2: *const ::std::os::raw::c_char) -> *mut FILE;
}
extern "C" {
pub fn fileno(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn getw(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn pclose(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn popen(
arg1: *const ::std::os::raw::c_char,
arg2: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn putw(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn setbuffer(
arg1: *mut FILE,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
);
}
extern "C" {
pub fn setlinebuf(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn getc_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn getchar_unlocked() -> ::std::os::raw::c_int;
}
extern "C" {
pub fn flockfile(arg1: *mut FILE);
}
extern "C" {
pub fn ftrylockfile(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn funlockfile(arg1: *mut FILE);
}
extern "C" {
pub fn putc_unlocked(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn putchar_unlocked(arg1: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn dprintf(
arg1: ::std::os::raw::c_int,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fmemopen(
arg1: *mut ::std::os::raw::c_void,
arg2: usize,
arg3: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn open_memstream(arg1: *mut *mut ::std::os::raw::c_char, arg2: *mut usize) -> *mut FILE;
}
extern "C" {
pub fn renameat(
arg1: ::std::os::raw::c_int,
arg2: *const ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
arg4: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn vdprintf(
arg1: ::std::os::raw::c_int,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _asiprintf_r(
arg1: *mut _reent,
arg2: *mut *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _asniprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *mut usize,
arg4: *const ::std::os::raw::c_char,
...
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _asnprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *mut usize,
arg4: *const ::std::os::raw::c_char,
...
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _asprintf_r(
arg1: *mut _reent,
arg2: *mut *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _diprintf_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _dprintf_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fclose_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fcloseall_r(arg1: *mut _reent) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fdopen_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _fflush_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fgetc_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fgetc_unlocked_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fgets_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
arg4: *mut FILE,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _fgets_unlocked_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: ::std::os::raw::c_int,
arg4: *mut FILE,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _fgetpos_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *mut fpos_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fsetpos_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const fpos_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fiprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fiscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fmemopen_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
arg3: usize,
arg4: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _fopen_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
) -> *mut FILE;
}
extern "C" {
pub fn _freopen_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: *mut FILE,
) -> *mut FILE;
}
extern "C" {
pub fn _fprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fpurge_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fputc_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fputc_unlocked_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fputs_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fputs_unlocked_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fread_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg3: *mut FILE,
) -> usize;
}
extern "C" {
pub fn _fread_unlocked_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg3: *mut FILE,
) -> usize;
}
extern "C" {
pub fn _fscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fseek_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: ::std::os::raw::c_long,
arg4: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _fseeko_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: _off_t,
arg4: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _ftell_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_long;
}
extern "C" {
pub fn _ftello_r(arg1: *mut _reent, arg2: *mut FILE) -> _off_t;
}
extern "C" {
pub fn _rewind_r(arg1: *mut _reent, arg2: *mut FILE);
}
extern "C" {
pub fn _fwrite_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg3: *mut FILE,
) -> usize;
}
extern "C" {
pub fn _fwrite_unlocked_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg3: *mut FILE,
) -> usize;
}
extern "C" {
pub fn _getc_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _getc_unlocked_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _getchar_r(arg1: *mut _reent) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _getchar_unlocked_r(arg1: *mut _reent) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _gets_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _iprintf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _iscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _open_memstream_r(
arg1: *mut _reent,
arg2: *mut *mut ::std::os::raw::c_char,
arg3: *mut usize,
) -> *mut FILE;
}
extern "C" {
pub fn _perror_r(arg1: *mut _reent, arg2: *const ::std::os::raw::c_char);
}
extern "C" {
pub fn _printf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _putc_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _putc_unlocked_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _putchar_unlocked_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _putchar_r(arg1: *mut _reent, arg2: ::std::os::raw::c_int) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _puts_r(arg1: *mut _reent, arg2: *const ::std::os::raw::c_char)
-> ::std::os::raw::c_int;
}
extern "C" {
pub fn _remove_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _rename_r(
arg1: *mut _reent,
_old: *const ::std::os::raw::c_char,
_new: *const ::std::os::raw::c_char,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _scanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _siprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _siscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _sniprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: usize,
arg4: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _snprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: usize,
arg4: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _sprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _sscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
...
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _tempnam_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _tmpfile_r(arg1: *mut _reent) -> *mut FILE;
}
extern "C" {
pub fn _tmpnam_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _ungetc_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vasiprintf_r(
arg1: *mut _reent,
arg2: *mut *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vasniprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *mut usize,
arg4: *const ::std::os::raw::c_char,
arg5: __gnuc_va_list,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _vasnprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *mut usize,
arg4: *const ::std::os::raw::c_char,
arg5: __gnuc_va_list,
) -> *mut ::std::os::raw::c_char;
}
extern "C" {
pub fn _vasprintf_r(
arg1: *mut _reent,
arg2: *mut *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vdiprintf_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vdprintf_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vfiprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vfiscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vfprintf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vfscanf_r(
arg1: *mut _reent,
arg2: *mut FILE,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _viprintf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _viscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vprintf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsiprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsiscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsniprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: usize,
arg4: *const ::std::os::raw::c_char,
arg5: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsnprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: usize,
arg4: *const ::std::os::raw::c_char,
arg5: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsprintf_r(
arg1: *mut _reent,
arg2: *mut ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn _vsscanf_r(
arg1: *mut _reent,
arg2: *const ::std::os::raw::c_char,
arg3: *const ::std::os::raw::c_char,
arg4: __gnuc_va_list,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fpurge(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn __getdelim(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: ::std::os::raw::c_int,
arg4: *mut FILE,
) -> isize;
}
extern "C" {
pub fn __getline(
arg1: *mut *mut ::std::os::raw::c_char,
arg2: *mut usize,
arg3: *mut FILE,
) -> isize;
}
extern "C" {
pub fn clearerr_unlocked(arg1: *mut FILE);
}
extern "C" {
pub fn feof_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn ferror_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fileno_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fflush_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fgetc_unlocked(arg1: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fputc_unlocked(arg1: ::std::os::raw::c_int, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn fread_unlocked(
arg1: *mut ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg2: *mut FILE,
) -> usize;
}
extern "C" {
pub fn fwrite_unlocked(
arg1: *const ::std::os::raw::c_void,
_size: usize,
_n: usize,
arg2: *mut FILE,
) -> usize;
}
extern "C" {
pub fn __srget_r(arg1: *mut _reent, arg2: *mut FILE) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn __swbuf_r(
arg1: *mut _reent,
arg2: ::std::os::raw::c_int,
arg3: *mut FILE,
) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn funopen(
__cookie: *const ::std::os::raw::c_void,
__readfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *mut ::std::os::raw::c_char,
__n: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
__writefn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *const ::std::os::raw::c_char,
__n: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
__seekfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__off: fpos_t,
__whence: ::std::os::raw::c_int,
) -> fpos_t,
>,
__closefn: ::core::option::Option<
unsafe extern "C" fn(__cookie: *mut ::std::os::raw::c_void) -> ::std::os::raw::c_int,
>,
) -> *mut FILE;
}
extern "C" {
pub fn _funopen_r(
arg1: *mut _reent,
__cookie: *const ::std::os::raw::c_void,
__readfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *mut ::std::os::raw::c_char,
__n: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
__writefn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *const ::std::os::raw::c_char,
__n: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>,
__seekfn: ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__off: fpos_t,
__whence: ::std::os::raw::c_int,
) -> fpos_t,
>,
__closefn: ::core::option::Option<
unsafe extern "C" fn(__cookie: *mut ::std::os::raw::c_void) -> ::std::os::raw::c_int,
>,
) -> *mut FILE;
}
pub type cookie_read_function_t = ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *mut ::std::os::raw::c_char,
__n: usize,
) -> isize,
>;
pub type cookie_write_function_t = ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__buf: *const ::std::os::raw::c_char,
__n: usize,
) -> isize,
>;
pub type cookie_seek_function_t = ::core::option::Option<
unsafe extern "C" fn(
__cookie: *mut ::std::os::raw::c_void,
__off: *mut off_t,
__whence: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int,
>;
pub type cookie_close_function_t = ::core::option::Option<
unsafe extern "C" fn(__cookie: *mut ::std::os::raw::c_void) -> ::std::os::raw::c_int,
>;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct cookie_io_functions_t {
pub read: cookie_read_function_t,
pub write: cookie_write_function_t,
pub seek: cookie_seek_function_t,
pub close: cookie_close_function_t,
}
extern "C" {
pub fn fopencookie(
__cookie: *mut ::std::os::raw::c_void,
__mode: *const ::std::os::raw::c_char,
__functions: cookie_io_functions_t,
) -> *mut FILE;
}
extern "C" {
pub fn _fopencookie_r(
arg1: *mut _reent,
__cookie: *mut ::std::os::raw::c_void,
__mode: *const ::std::os::raw::c_char,
__functions: cookie_io_functions_t,
) -> *mut FILE;
}
pub type esp_err_t = i32;
extern "C" {
#[doc = " @brief Returns string for esp_err_t error codes"]
#[doc = ""]
#[doc = " This function finds the error code in a pre-generated lookup-table and"]
#[doc = " returns its string representation."]
#[doc = ""]
#[doc = " The function is generated by the Python script"]
#[doc = " tools/gen_esp_err_to_name.py which should be run each time an esp_err_t"]
#[doc = " error is modified, created or removed from the IDF project."]
#[doc = ""]
#[doc = " @param code esp_err_t error code"]
#[doc = " @return string error message"]
pub fn esp_err_to_name(code: esp_err_t) -> *const ::std::os::raw::c_char;
}
extern "C" {
#[doc = " @brief Returns string for esp_err_t and system error codes"]
#[doc = ""]
#[doc = " This function finds the error code in a pre-generated lookup-table of"]
#[doc = " esp_err_t errors and returns its string representation. If the error code"]
#[doc = " is not found then it is attempted to be found among system errors."]
#[doc = ""]
#[doc = " The function is generated by the Python script"]
#[doc = " tools/gen_esp_err_to_name.py which should be run each time an esp_err_t"]
#[doc = " error is modified, created or removed from the IDF project."]
#[doc = ""]
#[doc = " @param code esp_err_t error code"]
#[doc = " @param[out] buf buffer where the error message should be written"]
#[doc = " @param buflen Size of buffer buf. At most buflen bytes are written into the buf buffer (including the terminating null byte)."]
#[doc = " @return buf containing the string error message"]
pub fn esp_err_to_name_r(
code: esp_err_t,
buf: *mut ::std::os::raw::c_char,
buflen: usize,
) -> *const ::std::os::raw::c_char;
}
extern "C" {
#[doc = " @cond"]
pub fn _esp_error_check_failed(
rc: esp_err_t,
file: *const ::std::os::raw::c_char,
line: ::std::os::raw::c_int,
function: *const ::std::os::raw::c_char,
expression: *const ::std::os::raw::c_char,
);
}
extern "C" {
#[doc = " @cond"]
pub fn _esp_error_check_failed_without_abort(
rc: esp_err_t,
file: *const ::std::os::raw::c_char,
line: ::std::os::raw::c_int,
function: *const ::std::os::raw::c_char,
expression: *const ::std::os::raw::c_char,
);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_timer {
_unused: [u8; 0],
}
#[doc = " @brief Opaque type representing a single esp_timer"]
pub type esp_timer_handle_t = *mut esp_timer;
#[doc = " @brief Timer callback function type"]
#[doc = " @param arg pointer to opaque user-specific data"]
pub type esp_timer_cb_t =
::core::option::Option<unsafe extern "C" fn(arg: *mut ::std::os::raw::c_void)>;
#[doc = "!< Callback is called from timer task"]
pub const esp_timer_dispatch_t_ESP_TIMER_TASK: esp_timer_dispatch_t = 0;
#[doc = " @brief Method for dispatching timer callback"]
pub type esp_timer_dispatch_t = u32;
#[doc = " @brief Timer configuration passed to esp_timer_create"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_timer_create_args_t {
#[doc = "!< Function to call when timer expires"]
pub callback: esp_timer_cb_t,
#[doc = "!< Argument to pass to the callback"]
pub arg: *mut ::std::os::raw::c_void,
#[doc = "!< Call the callback from task or from ISR"]
pub dispatch_method: esp_timer_dispatch_t,
#[doc = "!< Timer name, used in esp_timer_dump function"]
pub name: *const ::std::os::raw::c_char,
}
extern "C" {
#[doc = " @brief Initialize esp_timer library"]
#[doc = ""]
#[doc = " @note This function is called from startup code. Applications do not need"]
#[doc = " to call this function before using other esp_timer APIs."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NO_MEM if allocation has failed"]
#[doc = " - ESP_ERR_INVALID_STATE if already initialized"]
#[doc = " - other errors from interrupt allocator"]
pub fn esp_timer_init() -> esp_err_t;
}
extern "C" {
#[doc = " @brief De-initialize esp_timer library"]
#[doc = ""]
#[doc = " @note Normally this function should not be called from applications"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if not yet initialized"]
pub fn esp_timer_deinit() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Create an esp_timer instance"]
#[doc = ""]
#[doc = " @note When done using the timer, delete it with esp_timer_delete function."]
#[doc = ""]
#[doc = " @param create_args Pointer to a structure with timer creation arguments."]
#[doc = " Not saved by the library, can be allocated on the stack."]
#[doc = " @param[out] out_handle Output, pointer to esp_timer_handle_t variable which"]
#[doc = " will hold the created timer handle."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if some of the create_args are not valid"]
#[doc = " - ESP_ERR_INVALID_STATE if esp_timer library is not initialized yet"]
#[doc = " - ESP_ERR_NO_MEM if memory allocation fails"]
pub fn esp_timer_create(
create_args: *const esp_timer_create_args_t,
out_handle: *mut esp_timer_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start one-shot timer"]
#[doc = ""]
#[doc = " Timer should not be running when this function is called."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @param timeout_us timer timeout, in microseconds relative to the current moment"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the handle is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is already running"]
pub fn esp_timer_start_once(timer: esp_timer_handle_t, timeout_us: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start a periodic timer"]
#[doc = ""]
#[doc = " Timer should not be running when this function is called. This function will"]
#[doc = " start the timer which will trigger every 'period' microseconds."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @param period timer period, in microseconds"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the handle is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is already running"]
pub fn esp_timer_start_periodic(timer: esp_timer_handle_t, period: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Stop the timer"]
#[doc = ""]
#[doc = " This function stops the timer previously started using esp_timer_start_once"]
#[doc = " or esp_timer_start_periodic."]
#[doc = ""]
#[doc = " @param timer timer handle created using esp_timer_create"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is not running"]
pub fn esp_timer_stop(timer: esp_timer_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Delete an esp_timer instance"]
#[doc = ""]
#[doc = " The timer must be stopped before deleting. A one-shot timer which has expired"]
#[doc = " does not need to be stopped."]
#[doc = ""]
#[doc = " @param timer timer handle allocated using esp_timer_create"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if the timer is not running"]
pub fn esp_timer_delete(timer: esp_timer_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get time in microseconds since boot"]
#[doc = " @return number of microseconds since esp_timer_init was called (this normally"]
#[doc = " happens early during application startup)."]
pub fn esp_timer_get_time() -> i64;
}
extern "C" {
#[doc = " @brief Get the timestamp when the next timeout is expected to occur"]
#[doc = " @return Timestamp of the nearest timer event, in microseconds."]
#[doc = " The timebase is the same as for the values returned by esp_timer_get_time."]
pub fn esp_timer_get_next_alarm() -> i64;
}
extern "C" {
#[doc = " @brief Dump the list of timers to a stream"]
#[doc = ""]
#[doc = " If CONFIG_ESP_TIMER_PROFILING option is enabled, this prints the list of all"]
#[doc = " the existing timers. Otherwise, only the list active timers is printed."]
#[doc = ""]
#[doc = " The format is:"]
#[doc = ""]
#[doc = " name period alarm times_armed times_triggered total_callback_run_time"]
#[doc = ""]
#[doc = " where:"]
#[doc = ""]
#[doc = " name \u{2014} timer name (if CONFIG_ESP_TIMER_PROFILING is defined), or timer pointer"]
#[doc = " period \u{2014} period of timer, in microseconds, or 0 for one-shot timer"]
#[doc = " alarm - time of the next alarm, in microseconds since boot, or 0 if the timer"]
#[doc = " is not started"]
#[doc = ""]
#[doc = " The following fields are printed if CONFIG_ESP_TIMER_PROFILING is defined:"]
#[doc = ""]
#[doc = " times_armed \u{2014} number of times the timer was armed via esp_timer_start_X"]
#[doc = " times_triggered - number of times the callback was called"]
#[doc = " total_callback_run_time - total time taken by callback to execute, across all calls"]
#[doc = ""]
#[doc = " @param stream stream (such as stdout) to dump the information to"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NO_MEM if can not allocate temporary buffer for the output"]
pub fn esp_timer_dump(stream: *mut FILE) -> esp_err_t;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct multi_heap_info {
_unused: [u8; 0],
}
#[doc = " @brief Opaque handle to a registered heap"]
pub type multi_heap_handle_t = *mut multi_heap_info;
extern "C" {
#[doc = " @brief malloc() a buffer in a given heap"]
#[doc = ""]
#[doc = " Semantics are the same as standard malloc(), only the returned buffer will be allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param size Size of desired buffer."]
#[doc = ""]
#[doc = " @return Pointer to new memory, or NULL if allocation fails."]
pub fn multi_heap_malloc(heap: multi_heap_handle_t, size: usize)
-> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief free() a buffer in a given heap."]
#[doc = ""]
#[doc = " Semantics are the same as standard free(), only the argument 'p' must be NULL or have been allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
pub fn multi_heap_free(heap: multi_heap_handle_t, p: *mut ::std::os::raw::c_void);
}
extern "C" {
#[doc = " @brief realloc() a buffer in a given heap."]
#[doc = ""]
#[doc = " Semantics are the same as standard realloc(), only the argument 'p' must be NULL or have been allocated in the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
#[doc = " @param size Desired new size for buffer."]
#[doc = ""]
#[doc = " @return New buffer of 'size' containing contents of 'p', or NULL if reallocation failed."]
pub fn multi_heap_realloc(
heap: multi_heap_handle_t,
p: *mut ::std::os::raw::c_void,
size: usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Return the size that a particular pointer was allocated with."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param p Pointer, must have been previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap."]
#[doc = ""]
#[doc = " @return Size of the memory allocated at this block. May be more than the original size argument, due"]
#[doc = " to padding and minimum block sizes."]
pub fn multi_heap_get_allocated_size(
heap: multi_heap_handle_t,
p: *mut ::std::os::raw::c_void,
) -> usize;
}
extern "C" {
#[doc = " @brief Register a new heap for use"]
#[doc = ""]
#[doc = " This function initialises a heap at the specified address, and returns a handle for future heap operations."]
#[doc = ""]
#[doc = " There is no equivalent function for deregistering a heap - if all blocks in the heap are free, you can immediately start using the memory for other purposes."]
#[doc = ""]
#[doc = " @param start Start address of the memory to use for a new heap."]
#[doc = " @param size Size (in bytes) of the new heap."]
#[doc = ""]
#[doc = " @return Handle of a new heap ready for use, or NULL if the heap region was too small to be initialised."]
pub fn multi_heap_register(
start: *mut ::std::os::raw::c_void,
size: usize,
) -> multi_heap_handle_t;
}
extern "C" {
#[doc = " @brief Associate a private lock pointer with a heap"]
#[doc = ""]
#[doc = " The lock argument is supplied to the MULTI_HEAP_LOCK() and MULTI_HEAP_UNLOCK() macros, defined in multi_heap_platform.h."]
#[doc = ""]
#[doc = " The lock in question must be recursive."]
#[doc = ""]
#[doc = " When the heap is first registered, the associated lock is NULL."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param lock Optional pointer to a locking structure to associate with this heap."]
pub fn multi_heap_set_lock(heap: multi_heap_handle_t, lock: *mut ::std::os::raw::c_void);
}
extern "C" {
#[doc = " @brief Dump heap information to stdout"]
#[doc = ""]
#[doc = " For debugging purposes, this function dumps information about every block in the heap to stdout."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
pub fn multi_heap_dump(heap: multi_heap_handle_t);
}
extern "C" {
#[doc = " @brief Check heap integrity"]
#[doc = ""]
#[doc = " Walks the heap and checks all heap data structures are valid. If any errors are detected, an error-specific message"]
#[doc = " can be optionally printed to stderr. Print behaviour can be overriden at compile time by defining"]
#[doc = " MULTI_CHECK_FAIL_PRINTF in multi_heap_platform.h."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param print_errors If true, errors will be printed to stderr."]
#[doc = " @return true if heap is valid, false otherwise."]
pub fn multi_heap_check(heap: multi_heap_handle_t, print_errors: bool) -> bool;
}
extern "C" {
#[doc = " @brief Return free heap size"]
#[doc = ""]
#[doc = " Returns the number of bytes available in the heap."]
#[doc = ""]
#[doc = " Equivalent to the total_free_bytes member returned by multi_heap_get_heap_info()."]
#[doc = ""]
#[doc = " Note that the heap may be fragmented, so the actual maximum size for a single malloc() may be lower. To know this"]
#[doc = " size, see the largest_free_block member returned by multi_heap_get_heap_info()."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @return Number of free bytes."]
pub fn multi_heap_free_size(heap: multi_heap_handle_t) -> usize;
}
extern "C" {
#[doc = " @brief Return the lifetime minimum free heap size"]
#[doc = ""]
#[doc = " Equivalent to the minimum_free_bytes member returned by multi_heap_get_info()."]
#[doc = ""]
#[doc = " Returns the lifetime \"low water mark\" of possible values returned from multi_free_heap_size(), for the specified"]
#[doc = " heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @return Number of free bytes."]
pub fn multi_heap_minimum_free_size(heap: multi_heap_handle_t) -> usize;
}
#[doc = " @brief Structure to access heap metadata via multi_heap_get_info"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct multi_heap_info_t {
#[doc = "< Total free bytes in the heap. Equivalent to multi_free_heap_size()."]
pub total_free_bytes: usize,
#[doc = "< Total bytes allocated to data in the heap."]
pub total_allocated_bytes: usize,
#[doc = "< Size of largest free block in the heap. This is the largest malloc-able size."]
pub largest_free_block: usize,
#[doc = "< Lifetime minimum free heap size. Equivalent to multi_minimum_free_heap_size()."]
pub minimum_free_bytes: usize,
#[doc = "< Number of (variable size) blocks allocated in the heap."]
pub allocated_blocks: usize,
#[doc = "< Number of (variable size) free blocks in the heap."]
pub free_blocks: usize,
#[doc = "< Total number of (variable size) blocks in the heap."]
pub total_blocks: usize,
}
extern "C" {
#[doc = " @brief Return metadata about a given heap"]
#[doc = ""]
#[doc = " Fills a multi_heap_info_t structure with information about the specified heap."]
#[doc = ""]
#[doc = " @param heap Handle to a registered heap."]
#[doc = " @param info Pointer to a structure to fill with heap metadata."]
pub fn multi_heap_get_info(heap: multi_heap_handle_t, info: *mut multi_heap_info_t);
}
extern "C" {
#[doc = " @brief Allocate a chunk of memory which has the given capabilities"]
#[doc = ""]
#[doc = " Equivalent semantics to libc malloc(), for capability-aware memory."]
#[doc = ""]
#[doc = " In IDF, ``malloc(p)`` is equivalent to ``heap_caps_malloc(p, MALLOC_CAP_8BIT)``."]
#[doc = ""]
#[doc = " @param size Size, in bytes, of the amount of memory to allocate"]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory to be returned"]
#[doc = ""]
#[doc = " @return A pointer to the memory allocated on success, NULL on failure"]
pub fn heap_caps_malloc(size: usize, caps: u32) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Free memory previously allocated via heap_caps_malloc() or heap_caps_realloc()."]
#[doc = ""]
#[doc = " Equivalent semantics to libc free(), for capability-aware memory."]
#[doc = ""]
#[doc = " In IDF, ``free(p)`` is equivalent to ``heap_caps_free(p)``."]
#[doc = ""]
#[doc = " @param ptr Pointer to memory previously returned from heap_caps_malloc() or heap_caps_realloc(). Can be NULL."]
pub fn heap_caps_free(ptr: *mut ::std::os::raw::c_void);
}
extern "C" {
#[doc = " @brief Reallocate memory previously allocated via heap_caps_malloc() or heap_caps_realloc()."]
#[doc = ""]
#[doc = " Equivalent semantics to libc realloc(), for capability-aware memory."]
#[doc = ""]
#[doc = " In IDF, ``realloc(p, s)`` is equivalent to ``heap_caps_realloc(p, s, MALLOC_CAP_8BIT)``."]
#[doc = ""]
#[doc = " 'caps' parameter can be different to the capabilities that any original 'ptr' was allocated with. In this way,"]
#[doc = " realloc can be used to \"move\" a buffer if necessary to ensure it meets a new set of capabilities."]
#[doc = ""]
#[doc = " @param ptr Pointer to previously allocated memory, or NULL for a new allocation."]
#[doc = " @param size Size of the new buffer requested, or 0 to free the buffer."]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory desired for the new allocation."]
#[doc = ""]
#[doc = " @return Pointer to a new buffer of size 'size' with capabilities 'caps', or NULL if allocation failed."]
pub fn heap_caps_realloc(
ptr: *mut ::std::os::raw::c_void,
size: usize,
caps: ::std::os::raw::c_int,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Allocate a chunk of memory which has the given capabilities. The initialized value in the memory is set to zero."]
#[doc = ""]
#[doc = " Equivalent semantics to libc calloc(), for capability-aware memory."]
#[doc = ""]
#[doc = " In IDF, ``calloc(p)`` is equivalent to ``heap_caps_calloc(p, MALLOC_CAP_8BIT)``."]
#[doc = ""]
#[doc = " @param n Number of continuing chunks of memory to allocate"]
#[doc = " @param size Size, in bytes, of a chunk of memory to allocate"]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory to be returned"]
#[doc = ""]
#[doc = " @return A pointer to the memory allocated on success, NULL on failure"]
pub fn heap_caps_calloc(n: usize, size: usize, caps: u32) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Get the total free size of all the regions that have the given capabilities"]
#[doc = ""]
#[doc = " This function takes all regions capable of having the given capabilities allocated in them"]
#[doc = " and adds up the free space they have."]
#[doc = ""]
#[doc = " Note that because of heap fragmentation it is probably not possible to allocate a single block of memory"]
#[doc = " of this size. Use heap_caps_get_largest_free_block() for this purpose."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = ""]
#[doc = " @return Amount of free bytes in the regions"]
pub fn heap_caps_get_free_size(caps: u32) -> usize;
}
extern "C" {
#[doc = " @brief Get the total minimum free memory of all regions with the given capabilities"]
#[doc = ""]
#[doc = " This adds all the low water marks of the regions capable of delivering the memory"]
#[doc = " with the given capabilities."]
#[doc = ""]
#[doc = " Note the result may be less than the global all-time minimum available heap of this kind, as \"low water marks\" are"]
#[doc = " tracked per-region. Individual regions' heaps may have reached their \"low water marks\" at different points in time. However"]
#[doc = " this result still gives a \"worst case\" indication for all-time minimum free heap."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = ""]
#[doc = " @return Amount of free bytes in the regions"]
pub fn heap_caps_get_minimum_free_size(caps: u32) -> usize;
}
extern "C" {
#[doc = " @brief Get the largest free block of memory able to be allocated with the given capabilities."]
#[doc = ""]
#[doc = " Returns the largest value of ``s`` for which ``heap_caps_malloc(s, caps)`` will succeed."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = ""]
#[doc = " @return Size of largest free block in bytes."]
pub fn heap_caps_get_largest_free_block(caps: u32) -> usize;
}
extern "C" {
#[doc = " @brief Get heap info for all regions with the given capabilities."]
#[doc = ""]
#[doc = " Calls multi_heap_info() on all heaps which share the given capabilities. The information returned is an aggregate"]
#[doc = " across all matching heaps. The meanings of fields are the same as defined for multi_heap_info_t, except that"]
#[doc = " ``minimum_free_bytes`` has the same caveats described in heap_caps_get_minimum_free_size()."]
#[doc = ""]
#[doc = " @param info Pointer to a structure which will be filled with relevant"]
#[doc = " heap metadata."]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = ""]
pub fn heap_caps_get_info(info: *mut multi_heap_info_t, caps: u32);
}
extern "C" {
#[doc = " @brief Print a summary of all memory with the given capabilities."]
#[doc = ""]
#[doc = " Calls multi_heap_info on all heaps which share the given capabilities, and"]
#[doc = " prints a two-line summary for each, then a total summary."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = ""]
pub fn heap_caps_print_heap_info(caps: u32);
}
extern "C" {
#[doc = " @brief Check integrity of all heap memory in the system."]
#[doc = ""]
#[doc = " Calls multi_heap_check on all heaps. Optionally print errors if heaps are corrupt."]
#[doc = ""]
#[doc = " Calling this function is equivalent to calling heap_caps_check_integrity"]
#[doc = " with the caps argument set to MALLOC_CAP_INVALID."]
#[doc = ""]
#[doc = " @param print_errors Print specific errors if heap corruption is found."]
#[doc = ""]
#[doc = " @return True if all heaps are valid, False if at least one heap is corrupt."]
pub fn heap_caps_check_integrity_all(print_errors: bool) -> bool;
}
extern "C" {
#[doc = " @brief Check integrity of all heaps with the given capabilities."]
#[doc = ""]
#[doc = " Calls multi_heap_check on all heaps which share the given capabilities. Optionally"]
#[doc = " print errors if the heaps are corrupt."]
#[doc = ""]
#[doc = " See also heap_caps_check_integrity_all to check all heap memory"]
#[doc = " in the system and heap_caps_check_integrity_addr to check memory"]
#[doc = " around a single address."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
#[doc = " @param print_errors Print specific errors if heap corruption is found."]
#[doc = ""]
#[doc = " @return True if all heaps are valid, False if at least one heap is corrupt."]
pub fn heap_caps_check_integrity(caps: u32, print_errors: bool) -> bool;
}
extern "C" {
#[doc = " @brief Check integrity of heap memory around a given address."]
#[doc = ""]
#[doc = " This function can be used to check the integrity of a single region of heap memory,"]
#[doc = " which contains the given address."]
#[doc = ""]
#[doc = " This can be useful if debugging heap integrity for corruption at a known address,"]
#[doc = " as it has a lower overhead than checking all heap regions. Note that if the corrupt"]
#[doc = " address moves around between runs (due to timing or other factors) then this approach"]
#[doc = " won't work and you should call heap_caps_check_integrity or"]
#[doc = " heap_caps_check_integrity_all instead."]
#[doc = ""]
#[doc = " @note The entire heap region around the address is checked, not only the adjacent"]
#[doc = " heap blocks."]
#[doc = ""]
#[doc = " @param addr Address in memory. Check for corruption in region containing this address."]
#[doc = " @param print_errors Print specific errors if heap corruption is found."]
#[doc = ""]
#[doc = " @return True if the heap containing the specified address is valid,"]
#[doc = " False if at least one heap is corrupt or the address doesn't belong to a heap region."]
pub fn heap_caps_check_integrity_addr(addr: isize, print_errors: bool) -> bool;
}
extern "C" {
#[doc = " @brief Enable malloc() in external memory and set limit below which"]
#[doc = " malloc() attempts are placed in internal memory."]
#[doc = ""]
#[doc = " When external memory is in use, the allocation strategy is to initially try to"]
#[doc = " satisfy smaller allocation requests with internal memory and larger requests"]
#[doc = " with external memory. This sets the limit between the two, as well as generally"]
#[doc = " enabling allocation in external memory."]
#[doc = ""]
#[doc = " @param limit Limit, in bytes."]
pub fn heap_caps_malloc_extmem_enable(limit: usize);
}
extern "C" {
#[doc = " @brief Allocate a chunk of memory as preference in decreasing order."]
#[doc = ""]
#[doc = " @attention The variable parameters are bitwise OR of MALLOC_CAP_* flags indicating the type of memory."]
#[doc = " This API prefers to allocate memory with the first parameter. If failed, allocate memory with"]
#[doc = " the next parameter. It will try in this order until allocating a chunk of memory successfully"]
#[doc = " or fail to allocate memories with any of the parameters."]
#[doc = ""]
#[doc = " @param size Size, in bytes, of the amount of memory to allocate"]
#[doc = " @param num Number of variable paramters"]
#[doc = ""]
#[doc = " @return A pointer to the memory allocated on success, NULL on failure"]
pub fn heap_caps_malloc_prefer(size: usize, num: usize, ...) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Allocate a chunk of memory as preference in decreasing order."]
#[doc = ""]
#[doc = " @param ptr Pointer to previously allocated memory, or NULL for a new allocation."]
#[doc = " @param size Size of the new buffer requested, or 0 to free the buffer."]
#[doc = " @param num Number of variable paramters"]
#[doc = ""]
#[doc = " @return Pointer to a new buffer of size 'size', or NULL if allocation failed."]
pub fn heap_caps_realloc_prefer(
ptr: *mut ::std::os::raw::c_void,
size: usize,
num: usize,
...
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Allocate a chunk of memory as preference in decreasing order."]
#[doc = ""]
#[doc = " @param n Number of continuing chunks of memory to allocate"]
#[doc = " @param size Size, in bytes, of a chunk of memory to allocate"]
#[doc = " @param num Number of variable paramters"]
#[doc = ""]
#[doc = " @return A pointer to the memory allocated on success, NULL on failure"]
pub fn heap_caps_calloc_prefer(
n: usize,
size: usize,
num: usize,
...
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Dump the full structure of all heaps with matching capabilities."]
#[doc = ""]
#[doc = " Prints a large amount of output to serial (because of locking limitations,"]
#[doc = " the output bypasses stdout/stderr). For each (variable sized) block"]
#[doc = " in each matching heap, the following output is printed on a single line:"]
#[doc = ""]
#[doc = " - Block address (the data buffer returned by malloc is 4 bytes after this"]
#[doc = " if heap debugging is set to Basic, or 8 bytes otherwise)."]
#[doc = " - Data size (the data size may be larger than the size requested by malloc,"]
#[doc = " either due to heap fragmentation or because of heap debugging level)."]
#[doc = " - Address of next block in the heap."]
#[doc = " - If the block is free, the address of the next free block is also printed."]
#[doc = ""]
#[doc = " @param caps Bitwise OR of MALLOC_CAP_* flags indicating the type"]
#[doc = " of memory"]
pub fn heap_caps_dump(caps: u32);
}
extern "C" {
#[doc = " @brief Dump the full structure of all heaps."]
#[doc = ""]
#[doc = " Covers all registered heaps. Prints a large amount of output to serial."]
#[doc = ""]
#[doc = " Output is the same as for heap_caps_dump."]
#[doc = ""]
pub fn heap_caps_dump_all();
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct soc_memory_type_desc_t {
#[doc = "< Name of this memory type"]
pub name: *const ::std::os::raw::c_char,
#[doc = "< Capabilities for this memory type (as a prioritised set)"]
pub caps: [u32; 3usize],
#[doc = "< If true, this is data memory that is is also mapped in IRAM"]
pub aliased_iram: bool,
#[doc = "< If true, memory of this type is used for ROM stack during startup"]
pub startup_stack: bool,
}
extern "C" {
pub static mut soc_memory_types: [soc_memory_type_desc_t; 0usize];
}
extern "C" {
pub static soc_memory_type_count: usize;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct soc_memory_region_t {
#[doc = "< Start address of the region"]
pub start: isize,
#[doc = "< Size of the region in bytes"]
pub size: usize,
#[doc = "< Type of the region (index into soc_memory_types array)"]
pub type_: usize,
#[doc = "< If non-zero, is equivalent address in IRAM"]
pub iram_address: isize,
}
extern "C" {
pub static mut soc_memory_regions: [soc_memory_region_t; 0usize];
}
extern "C" {
pub static soc_memory_region_count: usize;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct soc_reserved_region_t {
pub start: isize,
pub end: isize,
}
extern "C" {
pub fn soc_get_available_memory_regions(regions: *mut soc_memory_region_t) -> usize;
}
extern "C" {
pub fn soc_get_available_memory_region_max_count() -> usize;
}
pub type StackType_t = u8;
pub type BaseType_t = ::std::os::raw::c_int;
pub type UBaseType_t = ::std::os::raw::c_uint;
pub type TickType_t = u32;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct portMUX_TYPE {
pub owner: u32,
pub count: u32,
}
extern "C" {
pub fn vPortAssertIfInISR();
}
extern "C" {
pub fn vPortCPUInitializeMutex(mux: *mut portMUX_TYPE);
}
extern "C" {
pub fn vTaskExitCritical(mux: *mut portMUX_TYPE);
}
extern "C" {
pub fn vTaskEnterCritical(mux: *mut portMUX_TYPE);
}
extern "C" {
pub fn vPortCPUAcquireMutex(mux: *mut portMUX_TYPE);
}
extern "C" {
#[doc = " @brief Acquire a portmux spinlock with a timeout"]
#[doc = ""]
#[doc = " @param mux Pointer to portmux to acquire."]
#[doc = " @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,"]
#[doc = " portMUX_TRY_LOCK to try a single time to acquire the lock."]
#[doc = ""]
#[doc = " @return true if mutex is successfully acquired, false on timeout."]
pub fn vPortCPUAcquireMutexTimeout(
mux: *mut portMUX_TYPE,
timeout_cycles: ::std::os::raw::c_int,
) -> bool;
}
extern "C" {
pub fn vPortCPUReleaseMutex(mux: *mut portMUX_TYPE);
}
extern "C" {
pub fn vPortYield();
}
extern "C" {
pub fn _frxt_setup_switch();
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xMPU_SETTINGS {
pub coproc_area: *mut StackType_t,
}
extern "C" {
pub fn esp_vApplicationIdleHook();
}
extern "C" {
pub fn esp_vApplicationTickHook();
}
extern "C" {
pub fn _xt_coproc_release(coproc_sa_base: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn vApplicationSleep(xExpectedIdleTime: TickType_t);
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_1 {
pub bt_select: u32,
pub out: u32,
pub out_w1ts: u32,
pub out_w1tc: u32,
pub out1: _bindgen_ty_1__bindgen_ty_1,
pub out1_w1ts: _bindgen_ty_1__bindgen_ty_2,
pub out1_w1tc: _bindgen_ty_1__bindgen_ty_3,
pub sdio_select: _bindgen_ty_1__bindgen_ty_4,
pub enable: u32,
pub enable_w1ts: u32,
pub enable_w1tc: u32,
pub enable1: _bindgen_ty_1__bindgen_ty_5,
pub enable1_w1ts: _bindgen_ty_1__bindgen_ty_6,
pub enable1_w1tc: _bindgen_ty_1__bindgen_ty_7,
pub strap: _bindgen_ty_1__bindgen_ty_8,
pub in_: u32,
pub in1: _bindgen_ty_1__bindgen_ty_9,
pub status: u32,
pub status_w1ts: u32,
pub status_w1tc: u32,
pub status1: _bindgen_ty_1__bindgen_ty_10,
pub status1_w1ts: _bindgen_ty_1__bindgen_ty_11,
pub status1_w1tc: _bindgen_ty_1__bindgen_ty_12,
pub reserved_5c: u32,
pub acpu_int: u32,
pub acpu_nmi_int: u32,
pub pcpu_int: u32,
pub pcpu_nmi_int: u32,
pub cpusdio_int: u32,
pub acpu_int1: _bindgen_ty_1__bindgen_ty_13,
pub acpu_nmi_int1: _bindgen_ty_1__bindgen_ty_14,
pub pcpu_int1: _bindgen_ty_1__bindgen_ty_15,
pub pcpu_nmi_int1: _bindgen_ty_1__bindgen_ty_16,
pub cpusdio_int1: _bindgen_ty_1__bindgen_ty_17,
pub pin: [_bindgen_ty_1__bindgen_ty_18; 40usize],
pub cali_conf: _bindgen_ty_1__bindgen_ty_19,
pub cali_data: _bindgen_ty_1__bindgen_ty_20,
pub func_in_sel_cfg: [_bindgen_ty_1__bindgen_ty_21; 256usize],
pub func_out_sel_cfg: [_bindgen_ty_1__bindgen_ty_22; 40usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_1 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_2 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_3 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_4 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(sel: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let sel: u32 = unsafe { ::core::mem::transmute(sel) };
sel as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_5 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_6 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_7 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_8 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_1__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn strapping(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_strapping(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
strapping: u32,
reserved16: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let strapping: u32 = unsafe { ::core::mem::transmute(strapping) };
strapping as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_9 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(data: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_10 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
intr_st: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_11 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
intr_st: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_12 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn intr_st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
intr_st: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr_st: u32 = unsafe { ::core::mem::transmute(intr_st) };
intr_st as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_13 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_14 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_14__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_14__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_14__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_15 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_15__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_15__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_15__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_16 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_16__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_16__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_16__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_17 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_17__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_17__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_17__bindgen_ty_1 {
#[inline]
pub fn intr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_intr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(intr: u32, reserved8: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let intr: u32 = unsafe { ::core::mem::transmute(intr) };
intr as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_18 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_18__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_18__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_1__bindgen_ty_18__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn pad_driver(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_pad_driver(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 4u8, val as u64)
}
}
#[inline]
pub fn int_type(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 3u8) as u32) }
}
#[inline]
pub fn set_int_type(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 3u8, val as u64)
}
}
#[inline]
pub fn wakeup_enable(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_wakeup_enable(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn config(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 2u8) as u32) }
}
#[inline]
pub fn set_config(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 2u8, val as u64)
}
}
#[inline]
pub fn int_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 5u8) as u32) }
}
#[inline]
pub fn set_int_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 5u8, val as u64)
}
}
#[inline]
pub fn reserved18(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 14u8) as u32) }
}
#[inline]
pub fn set_reserved18(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 14u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
pad_driver: u32,
reserved3: u32,
int_type: u32,
wakeup_enable: u32,
config: u32,
int_ena: u32,
reserved18: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let pad_driver: u32 = unsafe { ::core::mem::transmute(pad_driver) };
pad_driver as u64
});
__bindgen_bitfield_unit.set(3usize, 4u8, {
let reserved3: u32 = unsafe { ::core::mem::transmute(reserved3) };
reserved3 as u64
});
__bindgen_bitfield_unit.set(7usize, 3u8, {
let int_type: u32 = unsafe { ::core::mem::transmute(int_type) };
int_type as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let wakeup_enable: u32 = unsafe { ::core::mem::transmute(wakeup_enable) };
wakeup_enable as u64
});
__bindgen_bitfield_unit.set(11usize, 2u8, {
let config: u32 = unsafe { ::core::mem::transmute(config) };
config as u64
});
__bindgen_bitfield_unit.set(13usize, 5u8, {
let int_ena: u32 = unsafe { ::core::mem::transmute(int_ena) };
int_ena as u64
});
__bindgen_bitfield_unit.set(18usize, 14u8, {
let reserved18: u32 = unsafe { ::core::mem::transmute(reserved18) };
reserved18 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_19 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_19__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_19__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_19__bindgen_ty_1 {
#[inline]
pub fn rtc_max(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_rtc_max(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn reserved10(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 21u8) as u32) }
}
#[inline]
pub fn set_reserved10(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 21u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rtc_max: u32,
reserved10: u32,
start: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let rtc_max: u32 = unsafe { ::core::mem::transmute(rtc_max) };
rtc_max as u64
});
__bindgen_bitfield_unit.set(10usize, 21u8, {
let reserved10: u32 = unsafe { ::core::mem::transmute(reserved10) };
reserved10 as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_20 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_20__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_20__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_20__bindgen_ty_1 {
#[inline]
pub fn value_sync2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_value_sync2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 10u8, val as u64)
}
}
#[inline]
pub fn rdy_real(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_rdy_real(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn rdy_sync2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_rdy_sync2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
value_sync2: u32,
reserved20: u32,
rdy_real: u32,
rdy_sync2: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let value_sync2: u32 = unsafe { ::core::mem::transmute(value_sync2) };
value_sync2 as u64
});
__bindgen_bitfield_unit.set(20usize, 10u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let rdy_real: u32 = unsafe { ::core::mem::transmute(rdy_real) };
rdy_real as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let rdy_sync2: u32 = unsafe { ::core::mem::transmute(rdy_sync2) };
rdy_sync2 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_21 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_21__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_21__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_21__bindgen_ty_1 {
#[inline]
pub fn func_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_func_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn sig_in_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_sig_in_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn sig_in_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_sig_in_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
func_sel: u32,
sig_in_inv: u32,
sig_in_sel: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let func_sel: u32 = unsafe { ::core::mem::transmute(func_sel) };
func_sel as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let sig_in_inv: u32 = unsafe { ::core::mem::transmute(sig_in_inv) };
sig_in_inv as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let sig_in_sel: u32 = unsafe { ::core::mem::transmute(sig_in_sel) };
sig_in_sel as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_1__bindgen_ty_22 {
pub __bindgen_anon_1: _bindgen_ty_1__bindgen_ty_22__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_1__bindgen_ty_22__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_1__bindgen_ty_22__bindgen_ty_1 {
#[inline]
pub fn func_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 9u8) as u32) }
}
#[inline]
pub fn set_func_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 9u8, val as u64)
}
}
#[inline]
pub fn inv_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_inv_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn oen_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_oen_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn oen_inv_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_oen_inv_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 20u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 20u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
func_sel: u32,
inv_sel: u32,
oen_sel: u32,
oen_inv_sel: u32,
reserved12: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 9u8, {
let func_sel: u32 = unsafe { ::core::mem::transmute(func_sel) };
func_sel as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let inv_sel: u32 = unsafe { ::core::mem::transmute(inv_sel) };
inv_sel as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let oen_sel: u32 = unsafe { ::core::mem::transmute(oen_sel) };
oen_sel as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let oen_inv_sel: u32 = unsafe { ::core::mem::transmute(oen_inv_sel) };
oen_inv_sel as u64
});
__bindgen_bitfield_unit.set(12usize, 20u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit
}
}
pub type gpio_dev_t = _bindgen_ty_1;
extern "C" {
pub static mut GPIO: gpio_dev_t;
}
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_DISABLE: GPIO_INT_TYPE = 0;
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_POSEDGE: GPIO_INT_TYPE = 1;
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_NEGEDGE: GPIO_INT_TYPE = 2;
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_ANYEDGE: GPIO_INT_TYPE = 3;
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_LOLEVEL: GPIO_INT_TYPE = 4;
pub const GPIO_INT_TYPE_GPIO_PIN_INTR_HILEVEL: GPIO_INT_TYPE = 5;
pub type GPIO_INT_TYPE = u32;
pub type gpio_intr_handler_fn_t = ::core::option::Option<
unsafe extern "C" fn(intr_mask: u32, high: bool, arg: *mut ::std::os::raw::c_void),
>;
extern "C" {
#[doc = " @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet"]
#[doc = " to initialize \"output enables\" and pin configurations for each gpio pin."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_init();
}
extern "C" {
#[doc = " @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0)."]
#[doc = " There is no particular ordering guaranteed; so if the order of writes is significant,"]
#[doc = " calling code should divide a single call into multiple calls."]
#[doc = ""]
#[doc = " @param uint32_t set_mask : the gpios that need high level."]
#[doc = ""]
#[doc = " @param uint32_t clear_mask : the gpios that need low level."]
#[doc = ""]
#[doc = " @param uint32_t enable_mask : the gpios that need be changed."]
#[doc = ""]
#[doc = " @param uint32_t disable_mask : the gpios that need diable output."]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_output_set(set_mask: u32, clear_mask: u32, enable_mask: u32, disable_mask: u32);
}
extern "C" {
#[doc = " @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0)."]
#[doc = " There is no particular ordering guaranteed; so if the order of writes is significant,"]
#[doc = " calling code should divide a single call into multiple calls."]
#[doc = ""]
#[doc = " @param uint32_t set_mask : the gpios that need high level."]
#[doc = ""]
#[doc = " @param uint32_t clear_mask : the gpios that need low level."]
#[doc = ""]
#[doc = " @param uint32_t enable_mask : the gpios that need be changed."]
#[doc = ""]
#[doc = " @param uint32_t disable_mask : the gpios that need diable output."]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_output_set_high(
set_mask: u32,
clear_mask: u32,
enable_mask: u32,
disable_mask: u32,
);
}
extern "C" {
#[doc = " @brief Sample the value of GPIO input pins(0-31) and returns a bitmask."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0."]
pub fn gpio_input_get() -> u32;
}
extern "C" {
#[doc = " @brief Sample the value of GPIO input pins(32-39) and returns a bitmask."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32."]
pub fn gpio_input_get_high() -> u32;
}
extern "C" {
#[doc = " @brief Register an application-specific interrupt handler for GPIO pin interrupts."]
#[doc = " Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler"]
#[doc = ""]
#[doc = " @param void *arg : gpio application-specific interrupt handler argument."]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_intr_handler_register(
fn_: gpio_intr_handler_fn_t,
arg: *mut ::std::os::raw::c_void,
);
}
extern "C" {
#[doc = " @brief Get gpio interrupts which happens but not processed."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0."]
pub fn gpio_intr_pending() -> u32;
}
extern "C" {
#[doc = " @brief Get gpio interrupts which happens but not processed."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32."]
pub fn gpio_intr_pending_high() -> u32;
}
extern "C" {
#[doc = " @brief Ack gpio interrupts to process pending interrupts."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0."]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_intr_ack(ack_mask: u32);
}
extern "C" {
#[doc = " @brief Ack gpio interrupts to process pending interrupts."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32."]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_intr_ack_high(ack_mask: u32);
}
extern "C" {
#[doc = " @brief Set GPIO to wakeup the ESP32."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param uint32_t i: gpio number."]
#[doc = ""]
#[doc = " @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\\GPIO_PIN_INTR_HILEVEL can be used"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pin_wakeup_enable(i: u32, intr_state: GPIO_INT_TYPE);
}
extern "C" {
#[doc = " @brief disable GPIOs to wakeup the ESP32."]
#[doc = " Please do not call this function in SDK."]
#[doc = ""]
#[doc = " @param None"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pin_wakeup_disable();
}
extern "C" {
#[doc = " @brief set gpio input to a signal, one gpio can input to several signals."]
#[doc = ""]
#[doc = " @param uint32_t gpio : gpio number, 0~0x27"]
#[doc = " gpio == 0x30, input 0 to signal"]
#[doc = " gpio == 0x34, ???"]
#[doc = " gpio == 0x38, input 1 to signal"]
#[doc = ""]
#[doc = " @param uint32_t signal_idx : signal index."]
#[doc = ""]
#[doc = " @param bool inv : the signal is inv or not"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_matrix_in(gpio: u32, signal_idx: u32, inv: bool);
}
extern "C" {
#[doc = " @brief set signal output to gpio, one signal can output to several gpios."]
#[doc = ""]
#[doc = " @param uint32_t gpio : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @param uint32_t signal_idx : signal index."]
#[doc = " signal_idx == 0x100, cancel output put to the gpio"]
#[doc = ""]
#[doc = " @param bool out_inv : the signal output is inv or not"]
#[doc = ""]
#[doc = " @param bool oen_inv : the signal output enable is inv or not"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_matrix_out(gpio: u32, signal_idx: u32, out_inv: bool, oen_inv: bool);
}
extern "C" {
#[doc = " @brief Select pad as a gpio function from IOMUX."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_select_gpio(gpio_num: u8);
}
extern "C" {
#[doc = " @brief Set pad driver capability."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @param uint8_t drv : 0-3"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_set_drv(gpio_num: u8, drv: u8);
}
extern "C" {
#[doc = " @brief Pull up the pad from gpio number."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_pullup(gpio_num: u8);
}
extern "C" {
#[doc = " @brief Pull down the pad from gpio number."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_pulldown(gpio_num: u8);
}
extern "C" {
#[doc = " @brief Unhold the pad from gpio number."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_unhold(gpio_num: u8);
}
extern "C" {
#[doc = " @brief Hold the pad from gpio number."]
#[doc = ""]
#[doc = " @param uint32_t gpio_num : gpio number, 0~0x27"]
#[doc = ""]
#[doc = " @return None"]
pub fn gpio_pad_hold(gpio_num: u8);
}
pub type intr_handler_t =
::core::option::Option<unsafe extern "C" fn(arg: *mut ::std::os::raw::c_void)>;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct intr_handle_data_t {
_unused: [u8; 0],
}
pub type intr_handle_t = *mut intr_handle_data_t;
extern "C" {
#[doc = " @brief Mark an interrupt as a shared interrupt"]
#[doc = ""]
#[doc = " This will mark a certain interrupt on the specified CPU as"]
#[doc = " an interrupt that can be used to hook shared interrupt handlers"]
#[doc = " to."]
#[doc = ""]
#[doc = " @param intno The number of the interrupt (0-31)"]
#[doc = " @param cpu CPU on which the interrupt should be marked as shared (0 or 1)"]
#[doc = " @param is_in_iram Shared interrupt is for handlers that reside in IRAM and"]
#[doc = " the int can be left enabled while the flash cache is disabled."]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if cpu or intno is invalid"]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_mark_shared(
intno: ::std::os::raw::c_int,
cpu: ::std::os::raw::c_int,
is_in_iram: bool,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Reserve an interrupt to be used outside of this framework"]
#[doc = ""]
#[doc = " This will mark a certain interrupt on the specified CPU as"]
#[doc = " reserved, not to be allocated for any reason."]
#[doc = ""]
#[doc = " @param intno The number of the interrupt (0-31)"]
#[doc = " @param cpu CPU on which the interrupt should be marked as shared (0 or 1)"]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if cpu or intno is invalid"]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_reserve(intno: ::std::os::raw::c_int, cpu: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Allocate an interrupt with the given parameters."]
#[doc = ""]
#[doc = " This finds an interrupt that matches the restrictions as given in the flags"]
#[doc = " parameter, maps the given interrupt source to it and hooks up the given"]
#[doc = " interrupt handler (with optional argument) as well. If needed, it can return"]
#[doc = " a handle for the interrupt as well."]
#[doc = ""]
#[doc = " The interrupt will always be allocated on the core that runs this function."]
#[doc = ""]
#[doc = " If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or"]
#[doc = " RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned."]
#[doc = ""]
#[doc = " @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux"]
#[doc = " sources, as defined in soc/soc.h, or one of the internal"]
#[doc = " ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header."]
#[doc = " @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the"]
#[doc = " choice of interrupts that this routine can choose from. If this value"]
#[doc = " is 0, it will default to allocating a non-shared interrupt of level"]
#[doc = " 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared"]
#[doc = " interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return"]
#[doc = " from this function with the interrupt disabled."]
#[doc = " @param handler The interrupt handler. Must be NULL when an interrupt of level >3"]
#[doc = " is requested, because these types of interrupts aren't C-callable."]
#[doc = " @param arg Optional argument for passed to the interrupt handler"]
#[doc = " @param ret_handle Pointer to an intr_handle_t to store a handle that can later be"]
#[doc = " used to request details or free the interrupt. Can be NULL if no handle"]
#[doc = " is required."]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid."]
#[doc = " ESP_ERR_NOT_FOUND No free interrupt found with the specified flags"]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_alloc(
source: ::std::os::raw::c_int,
flags: ::std::os::raw::c_int,
handler: intr_handler_t,
arg: *mut ::std::os::raw::c_void,
ret_handle: *mut intr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Allocate an interrupt with the given parameters."]
#[doc = ""]
#[doc = ""]
#[doc = " This essentially does the same as esp_intr_alloc, but allows specifying a register and mask"]
#[doc = " combo. For shared interrupts, the handler is only called if a read from the specified"]
#[doc = " register, ANDed with the mask, returns non-zero. By passing an interrupt status register"]
#[doc = " address and a fitting mask, this can be used to accelerate interrupt handling in the case"]
#[doc = " a shared interrupt is triggered; by checking the interrupt statuses first, the code can"]
#[doc = " decide which ISRs can be skipped"]
#[doc = ""]
#[doc = " @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux"]
#[doc = " sources, as defined in soc/soc.h, or one of the internal"]
#[doc = " ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header."]
#[doc = " @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the"]
#[doc = " choice of interrupts that this routine can choose from. If this value"]
#[doc = " is 0, it will default to allocating a non-shared interrupt of level"]
#[doc = " 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared"]
#[doc = " interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return"]
#[doc = " from this function with the interrupt disabled."]
#[doc = " @param intrstatusreg The address of an interrupt status register"]
#[doc = " @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits"]
#[doc = " that are 1 in the mask set, the ISR will be called. If not, it will be"]
#[doc = " skipped."]
#[doc = " @param handler The interrupt handler. Must be NULL when an interrupt of level >3"]
#[doc = " is requested, because these types of interrupts aren't C-callable."]
#[doc = " @param arg Optional argument for passed to the interrupt handler"]
#[doc = " @param ret_handle Pointer to an intr_handle_t to store a handle that can later be"]
#[doc = " used to request details or free the interrupt. Can be NULL if no handle"]
#[doc = " is required."]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid."]
#[doc = " ESP_ERR_NOT_FOUND No free interrupt found with the specified flags"]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_alloc_intrstatus(
source: ::std::os::raw::c_int,
flags: ::std::os::raw::c_int,
intrstatusreg: u32,
intrstatusmask: u32,
handler: intr_handler_t,
arg: *mut ::std::os::raw::c_void,
ret_handle: *mut intr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable and free an interrupt."]
#[doc = ""]
#[doc = " Use an interrupt handle to disable the interrupt and release the resources associated with it."]
#[doc = " If the current core is not the core that registered this interrupt, this routine will be assigned to"]
#[doc = " the core that allocated this interrupt, blocking and waiting until the resource is successfully released."]
#[doc = ""]
#[doc = " @note"]
#[doc = " When the handler shares its source with other handlers, the interrupt status"]
#[doc = " bits it's responsible for should be managed properly before freeing it. see"]
#[doc = " ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``."]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG the handle is NULL"]
#[doc = " ESP_FAIL failed to release this handle"]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_free(handle: intr_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get CPU number an interrupt is tied to"]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = ""]
#[doc = " @return The core number where the interrupt is allocated"]
pub fn esp_intr_get_cpu(handle: intr_handle_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Get the allocated interrupt for a certain handle"]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = ""]
#[doc = " @return The interrupt number"]
pub fn esp_intr_get_intno(handle: intr_handle_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Disable the interrupt associated with the handle"]
#[doc = ""]
#[doc = " @note"]
#[doc = " 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the"]
#[doc = " CPU the interrupt is allocated on. Other interrupts have no such restriction."]
#[doc = " 2. When several handlers sharing a same interrupt source, interrupt status bits, which are"]
#[doc = " handled in the handler to be disabled, should be masked before the disabling, or handled"]
#[doc = " in other enabled interrupts properly. Miss of interrupt status handling will cause infinite"]
#[doc = " interrupt calls and finally system crash."]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid."]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_disable(handle: intr_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable the interrupt associated with the handle"]
#[doc = ""]
#[doc = " @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the"]
#[doc = " CPU the interrupt is allocated on. Other interrupts have no such restriction."]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid."]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_enable(handle: intr_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set the \"in IRAM\" status of the handler."]
#[doc = ""]
#[doc = " @note Does not work on shared interrupts."]
#[doc = ""]
#[doc = " @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus"]
#[doc = " @param is_in_iram Whether the handler associated with this handle resides in IRAM."]
#[doc = " Handlers residing in IRAM can be called when cache is disabled."]
#[doc = ""]
#[doc = " @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid."]
#[doc = " ESP_OK otherwise"]
pub fn esp_intr_set_in_iram(handle: intr_handle_t, is_in_iram: bool) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable interrupts that aren't specifically marked as running from IRAM"]
pub fn esp_intr_noniram_disable();
}
extern "C" {
#[doc = " @brief Re-enable interrupts disabled by esp_intr_noniram_disable"]
pub fn esp_intr_noniram_enable();
}
extern "C" {
pub static mut GPIO_PIN_MUX_REG: [u32; 40usize];
}
#[doc = "< GPIO0, input and output"]
pub const gpio_num_t_GPIO_NUM_0: gpio_num_t = 0;
#[doc = "< GPIO1, input and output"]
pub const gpio_num_t_GPIO_NUM_1: gpio_num_t = 1;
#[doc = "< GPIO2, input and output"]
#[doc = "@note There are more enumerations like that"]
#[doc = "up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31."]
#[doc = "They are not shown here to reduce redundant information."]
#[doc = "@note GPIO34..39 are input mode only."]
pub const gpio_num_t_GPIO_NUM_2: gpio_num_t = 2;
#[doc = "< GPIO3, input and output"]
pub const gpio_num_t_GPIO_NUM_3: gpio_num_t = 3;
#[doc = "< GPIO4, input and output"]
pub const gpio_num_t_GPIO_NUM_4: gpio_num_t = 4;
#[doc = "< GPIO5, input and output"]
pub const gpio_num_t_GPIO_NUM_5: gpio_num_t = 5;
#[doc = "< GPIO6, input and output"]
pub const gpio_num_t_GPIO_NUM_6: gpio_num_t = 6;
#[doc = "< GPIO7, input and output"]
pub const gpio_num_t_GPIO_NUM_7: gpio_num_t = 7;
#[doc = "< GPIO8, input and output"]
pub const gpio_num_t_GPIO_NUM_8: gpio_num_t = 8;
#[doc = "< GPIO9, input and output"]
pub const gpio_num_t_GPIO_NUM_9: gpio_num_t = 9;
#[doc = "< GPIO10, input and output"]
pub const gpio_num_t_GPIO_NUM_10: gpio_num_t = 10;
#[doc = "< GPIO11, input and output"]
pub const gpio_num_t_GPIO_NUM_11: gpio_num_t = 11;
#[doc = "< GPIO12, input and output"]
pub const gpio_num_t_GPIO_NUM_12: gpio_num_t = 12;
#[doc = "< GPIO13, input and output"]
pub const gpio_num_t_GPIO_NUM_13: gpio_num_t = 13;
#[doc = "< GPIO14, input and output"]
pub const gpio_num_t_GPIO_NUM_14: gpio_num_t = 14;
#[doc = "< GPIO15, input and output"]
pub const gpio_num_t_GPIO_NUM_15: gpio_num_t = 15;
#[doc = "< GPIO16, input and output"]
pub const gpio_num_t_GPIO_NUM_16: gpio_num_t = 16;
#[doc = "< GPIO17, input and output"]
pub const gpio_num_t_GPIO_NUM_17: gpio_num_t = 17;
#[doc = "< GPIO18, input and output"]
pub const gpio_num_t_GPIO_NUM_18: gpio_num_t = 18;
#[doc = "< GPIO19, input and output"]
pub const gpio_num_t_GPIO_NUM_19: gpio_num_t = 19;
#[doc = "< GPIO21, input and output"]
pub const gpio_num_t_GPIO_NUM_21: gpio_num_t = 21;
#[doc = "< GPIO22, input and output"]
pub const gpio_num_t_GPIO_NUM_22: gpio_num_t = 22;
#[doc = "< GPIO23, input and output"]
pub const gpio_num_t_GPIO_NUM_23: gpio_num_t = 23;
#[doc = "< GPIO25, input and output"]
pub const gpio_num_t_GPIO_NUM_25: gpio_num_t = 25;
#[doc = "< GPIO26, input and output"]
pub const gpio_num_t_GPIO_NUM_26: gpio_num_t = 26;
#[doc = "< GPIO27, input and output"]
pub const gpio_num_t_GPIO_NUM_27: gpio_num_t = 27;
#[doc = "< GPIO32, input and output"]
pub const gpio_num_t_GPIO_NUM_32: gpio_num_t = 32;
#[doc = "< GPIO33, input and output"]
pub const gpio_num_t_GPIO_NUM_33: gpio_num_t = 33;
#[doc = "< GPIO34, input mode only"]
pub const gpio_num_t_GPIO_NUM_34: gpio_num_t = 34;
#[doc = "< GPIO35, input mode only"]
pub const gpio_num_t_GPIO_NUM_35: gpio_num_t = 35;
#[doc = "< GPIO36, input mode only"]
pub const gpio_num_t_GPIO_NUM_36: gpio_num_t = 36;
#[doc = "< GPIO37, input mode only"]
pub const gpio_num_t_GPIO_NUM_37: gpio_num_t = 37;
#[doc = "< GPIO38, input mode only"]
pub const gpio_num_t_GPIO_NUM_38: gpio_num_t = 38;
#[doc = "< GPIO39, input mode only"]
pub const gpio_num_t_GPIO_NUM_39: gpio_num_t = 39;
pub const gpio_num_t_GPIO_NUM_MAX: gpio_num_t = 40;
pub type gpio_num_t = u32;
#[doc = "< Disable GPIO interrupt"]
pub const gpio_int_type_t_GPIO_INTR_DISABLE: gpio_int_type_t = 0;
#[doc = "< GPIO interrupt type : rising edge"]
pub const gpio_int_type_t_GPIO_INTR_POSEDGE: gpio_int_type_t = 1;
#[doc = "< GPIO interrupt type : falling edge"]
pub const gpio_int_type_t_GPIO_INTR_NEGEDGE: gpio_int_type_t = 2;
#[doc = "< GPIO interrupt type : both rising and falling edge"]
pub const gpio_int_type_t_GPIO_INTR_ANYEDGE: gpio_int_type_t = 3;
#[doc = "< GPIO interrupt type : input low level trigger"]
pub const gpio_int_type_t_GPIO_INTR_LOW_LEVEL: gpio_int_type_t = 4;
#[doc = "< GPIO interrupt type : input high level trigger"]
pub const gpio_int_type_t_GPIO_INTR_HIGH_LEVEL: gpio_int_type_t = 5;
pub const gpio_int_type_t_GPIO_INTR_MAX: gpio_int_type_t = 6;
pub type gpio_int_type_t = u32;
#[doc = "< GPIO mode : disable input and output"]
pub const gpio_mode_t_GPIO_MODE_DISABLE: gpio_mode_t = 0;
#[doc = "< GPIO mode : input only"]
pub const gpio_mode_t_GPIO_MODE_INPUT: gpio_mode_t = 1;
#[doc = "< GPIO mode : output only mode"]
pub const gpio_mode_t_GPIO_MODE_OUTPUT: gpio_mode_t = 2;
#[doc = "< GPIO mode : output only with open-drain mode"]
pub const gpio_mode_t_GPIO_MODE_OUTPUT_OD: gpio_mode_t = 6;
#[doc = "< GPIO mode : output and input with open-drain mode"]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT_OD: gpio_mode_t = 7;
#[doc = "< GPIO mode : output and input mode"]
pub const gpio_mode_t_GPIO_MODE_INPUT_OUTPUT: gpio_mode_t = 3;
pub type gpio_mode_t = u32;
#[doc = "< Disable GPIO pull-up resistor"]
pub const gpio_pullup_t_GPIO_PULLUP_DISABLE: gpio_pullup_t = 0;
#[doc = "< Enable GPIO pull-up resistor"]
pub const gpio_pullup_t_GPIO_PULLUP_ENABLE: gpio_pullup_t = 1;
pub type gpio_pullup_t = u32;
#[doc = "< Disable GPIO pull-down resistor"]
pub const gpio_pulldown_t_GPIO_PULLDOWN_DISABLE: gpio_pulldown_t = 0;
#[doc = "< Enable GPIO pull-down resistor"]
pub const gpio_pulldown_t_GPIO_PULLDOWN_ENABLE: gpio_pulldown_t = 1;
pub type gpio_pulldown_t = u32;
#[doc = " @brief Configuration parameters of GPIO pad for gpio_config function"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct gpio_config_t {
#[doc = "< GPIO pin: set with bit mask, each bit maps to a GPIO"]
pub pin_bit_mask: u64,
#[doc = "< GPIO mode: set input/output mode"]
pub mode: gpio_mode_t,
#[doc = "< GPIO pull-up"]
pub pull_up_en: gpio_pullup_t,
#[doc = "< GPIO pull-down"]
pub pull_down_en: gpio_pulldown_t,
#[doc = "< GPIO interrupt type"]
pub intr_type: gpio_int_type_t,
}
#[doc = "< Pad pull up"]
pub const gpio_pull_mode_t_GPIO_PULLUP_ONLY: gpio_pull_mode_t = 0;
#[doc = "< Pad pull down"]
pub const gpio_pull_mode_t_GPIO_PULLDOWN_ONLY: gpio_pull_mode_t = 1;
#[doc = "< Pad pull up + pull down"]
pub const gpio_pull_mode_t_GPIO_PULLUP_PULLDOWN: gpio_pull_mode_t = 2;
#[doc = "< Pad floating"]
pub const gpio_pull_mode_t_GPIO_FLOATING: gpio_pull_mode_t = 3;
pub type gpio_pull_mode_t = u32;
#[doc = "< Pad drive capability: weak"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_0: gpio_drive_cap_t = 0;
#[doc = "< Pad drive capability: stronger"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_1: gpio_drive_cap_t = 1;
#[doc = "< Pad drive capability: default value"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_2: gpio_drive_cap_t = 2;
#[doc = "< Pad drive capability: default value"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_DEFAULT: gpio_drive_cap_t = 2;
#[doc = "< Pad drive capability: strongest"]
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_3: gpio_drive_cap_t = 3;
pub const gpio_drive_cap_t_GPIO_DRIVE_CAP_MAX: gpio_drive_cap_t = 4;
pub type gpio_drive_cap_t = u32;
pub type gpio_isr_t =
::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>;
pub type gpio_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief GPIO common configuration"]
#[doc = ""]
#[doc = " Configure GPIO's Mode,pull-up,PullDown,IntrType"]
#[doc = ""]
#[doc = " @param pGPIOConfig Pointer to GPIO configure struct"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = ""]
pub fn gpio_config(pGPIOConfig: *const gpio_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Reset an gpio to default state (select gpio function, enable pullup and disable input and output)."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number."]
#[doc = ""]
#[doc = " @note This function also configures the IOMUX for this pin to the GPIO"]
#[doc = " function, and disconnects any other peripheral output configured via GPIO"]
#[doc = " Matrix."]
#[doc = ""]
#[doc = " @return Always return ESP_OK."]
pub fn gpio_reset_pin(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief GPIO set interrupt trigger type"]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = " @param intr_type Interrupt type, select from gpio_int_type_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = ""]
pub fn gpio_set_intr_type(gpio_num: gpio_num_t, intr_type: gpio_int_type_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable GPIO module interrupt signal"]
#[doc = ""]
#[doc = " @note Please do not use the interrupt of GPIO36 and GPIO39 when using ADC."]
#[doc = " Please refer to the comments of `adc1_get_raw`."]
#[doc = " Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to enable an interrupt on e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = ""]
pub fn gpio_intr_enable(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable GPIO module interrupt signal"]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = ""]
pub fn gpio_intr_disable(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief GPIO set output level"]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = " @param level Output level. 0: low ; 1: high"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO number error"]
#[doc = ""]
pub fn gpio_set_level(gpio_num: gpio_num_t, level: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief GPIO get input level"]
#[doc = ""]
#[doc = " @warning If the pad is not configured for input (or input and output) the returned value is always 0."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - 0 the GPIO input level is 0"]
#[doc = " - 1 the GPIO input level is 1"]
#[doc = ""]
pub fn gpio_get_level(gpio_num: gpio_num_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief\t GPIO set direction"]
#[doc = ""]
#[doc = " Configure GPIO direction,such as output_only,input_only,output_and_input"]
#[doc = ""]
#[doc = " @param gpio_num Configure GPIO pins number, it should be GPIO number. If you want to set direction of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = " @param mode GPIO direction"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO error"]
#[doc = ""]
pub fn gpio_set_direction(gpio_num: gpio_num_t, mode: gpio_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure GPIO pull-up/pull-down resistors"]
#[doc = ""]
#[doc = " Only pins that support both input & output have integrated pull-up and pull-down resistors. Input-only GPIOs 34-39 do not."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);"]
#[doc = " @param pull GPIO pull up/down mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG : Parameter error"]
#[doc = ""]
pub fn gpio_set_pull_mode(gpio_num: gpio_num_t, pull: gpio_pull_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable GPIO wake-up function."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number."]
#[doc = ""]
#[doc = " @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_wakeup_enable(gpio_num: gpio_num_t, intr_type: gpio_int_type_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable GPIO wake-up function."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_wakeup_disable(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register GPIO interrupt handler, the handler is an ISR."]
#[doc = " The handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " This ISR function is called whenever any GPIO interrupt occurs. See"]
#[doc = " the alternative gpio_install_isr_service() and"]
#[doc = " gpio_isr_handler_add() API in order to have the driver support"]
#[doc = " per-GPIO ISRs."]
#[doc = ""]
#[doc = " @param fn Interrupt handler function."]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @param arg Parameter for handler function"]
#[doc = " @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will be returned here."]
#[doc = ""]
#[doc = " \\verbatim embed:rst:leading-asterisk"]
#[doc = " To disable or remove the ISR, pass the returned handle to the :doc:`interrupt allocation functions </api-reference/system/intr_alloc>`."]
#[doc = " \\endverbatim"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success ;"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO error"]
#[doc = " - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags"]
pub fn gpio_isr_register(
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut gpio_isr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable pull-up on GPIO."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_pullup_en(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable pull-up on GPIO."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_pullup_dis(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable pull-down on GPIO."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_pulldown_en(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable pull-down on GPIO."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_pulldown_dis(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Install the driver's GPIO ISR handler service, which allows per-pin GPIO interrupt handlers."]
#[doc = ""]
#[doc = " This function is incompatible with gpio_isr_register() - if that function is used, a single global ISR is registered for all GPIO interrupts. If this function is used, the ISR service provides a global GPIO ISR and individual pin handlers are registered via the gpio_isr_handler_add() function."]
#[doc = ""]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_NO_MEM No memory to install this service"]
#[doc = " - ESP_ERR_INVALID_STATE ISR service already installed."]
#[doc = " - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO error"]
pub fn gpio_install_isr_service(intr_alloc_flags: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Uninstall the driver's GPIO ISR service, freeing related resources."]
pub fn gpio_uninstall_isr_service();
}
extern "C" {
#[doc = " @brief Add ISR handler for the corresponding GPIO pin."]
#[doc = ""]
#[doc = " Call this function after using gpio_install_isr_service() to"]
#[doc = " install the driver's GPIO ISR handler service."]
#[doc = ""]
#[doc = " The pin ISR handlers no longer need to be declared with IRAM_ATTR,"]
#[doc = " unless you pass the ESP_INTR_FLAG_IRAM flag when allocating the"]
#[doc = " ISR in gpio_install_isr_service()."]
#[doc = ""]
#[doc = " This ISR handler will be called from an ISR. So there is a stack"]
#[doc = " size limit (configurable as \"ISR stack size\" in menuconfig). This"]
#[doc = " limit is smaller compared to a global GPIO interrupt handler due"]
#[doc = " to the additional level of indirection."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = " @param isr_handler ISR handler function for the corresponding GPIO number."]
#[doc = " @param args parameter for ISR handler."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized."]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_isr_handler_add(
gpio_num: gpio_num_t,
isr_handler: gpio_isr_t,
args: *mut ::std::os::raw::c_void,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Remove ISR handler for the corresponding GPIO pin."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized."]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_isr_handler_remove(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set GPIO pad drive capability"]
#[doc = ""]
#[doc = " @param gpio_num GPIO number, only support output GPIOs"]
#[doc = " @param strength Drive capability of the pad"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_set_drive_capability(gpio_num: gpio_num_t, strength: gpio_drive_cap_t)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Get GPIO pad drive capability"]
#[doc = ""]
#[doc = " @param gpio_num GPIO number, only support output GPIOs"]
#[doc = " @param strength Pointer to accept drive capability of the pad"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn gpio_get_drive_capability(
gpio_num: gpio_num_t,
strength: *mut gpio_drive_cap_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable gpio pad hold function."]
#[doc = ""]
#[doc = " The gpio pad hold function works in both input and output modes, but must be output-capable gpios."]
#[doc = " If pad hold enabled:"]
#[doc = " in output mode: the output level of the pad will be force locked and can not be changed."]
#[doc = " in input mode: the input value read will not change, regardless the changes of input signal."]
#[doc = ""]
#[doc = " The state of digital gpio cannot be held during Deep-sleep, and it will resume the hold function"]
#[doc = " when the chip wakes up from Deep-sleep. If the digital gpio also needs to be held during Deep-sleep,"]
#[doc = " `gpio_deep_sleep_hold_en` should also be called."]
#[doc = ""]
#[doc = " Power down or call gpio_hold_dis will disable this function."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number, only support output-capable GPIOs"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED Not support pad hold function"]
pub fn gpio_hold_en(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable gpio pad hold function."]
#[doc = ""]
#[doc = " When the chip is woken up from Deep-sleep, the gpio will be set to the default mode, so, the gpio will output"]
#[doc = " the default level if this function is called. If you dont't want the level changes, the gpio should be configured to"]
#[doc = " a known state before this function is called."]
#[doc = " e.g."]
#[doc = " If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called,"]
#[doc = " gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior,"]
#[doc = " you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number, only support output-capable GPIOs"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED Not support pad hold function"]
pub fn gpio_hold_dis(gpio_num: gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable all digital gpio pad hold function during Deep-sleep."]
#[doc = ""]
#[doc = " When the chip is in Deep-sleep mode, all digital gpio will hold the state before sleep, and when the chip is woken up,"]
#[doc = " the status of digital gpio will not be held. Note that the pad hold feature only works when the chip is in Deep-sleep mode,"]
#[doc = " when not in sleep mode, the digital gpio state can be changed even you have called this function."]
#[doc = ""]
#[doc = " Power down or call gpio_hold_dis will disable this function, otherwise, the digital gpio hold feature works as long as the chip enter Deep-sleep."]
pub fn gpio_deep_sleep_hold_en();
}
extern "C" {
#[doc = " @brief Disable all digital gpio pad hold function during Deep-sleep."]
#[doc = ""]
pub fn gpio_deep_sleep_hold_dis();
}
extern "C" {
#[doc = " @brief Set pad input to a peripheral signal through the IOMUX."]
#[doc = " @param gpio_num GPIO number of the pad."]
#[doc = " @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``."]
pub fn gpio_iomux_in(gpio_num: u32, signal_idx: u32);
}
extern "C" {
#[doc = " @brief Set peripheral output to an GPIO pad through the IOMUX."]
#[doc = " @param gpio_num gpio_num GPIO number of the pad."]
#[doc = " @param func The function number of the peripheral pin to output pin."]
#[doc = " One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``."]
#[doc = " @param oen_inv True if the output enable needs to be inversed, otherwise False."]
pub fn gpio_iomux_out(gpio_num: u8, func: ::std::os::raw::c_int, oen_inv: bool);
}
pub type xt_handler =
::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>;
pub type xt_exc_handler = ::core::option::Option<unsafe extern "C" fn(arg1: *mut XtExcFrame)>;
extern "C" {
pub fn xt_set_exception_handler(n: ::std::os::raw::c_int, f: xt_exc_handler) -> xt_exc_handler;
}
extern "C" {
pub fn xt_set_interrupt_handler(
n: ::std::os::raw::c_int,
f: xt_handler,
arg: *mut ::std::os::raw::c_void,
) -> xt_handler;
}
extern "C" {
pub fn xt_ints_on(mask: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xt_ints_off(mask: ::std::os::raw::c_uint);
}
extern "C" {
pub fn xt_get_interrupt_handler_arg(n: ::std::os::raw::c_int) -> *mut ::std::os::raw::c_void;
}
#[doc = "< Touch pad channel 0 is GPIO4"]
pub const touch_pad_t_TOUCH_PAD_NUM0: touch_pad_t = 0;
#[doc = "< Touch pad channel 1 is GPIO0"]
pub const touch_pad_t_TOUCH_PAD_NUM1: touch_pad_t = 1;
#[doc = "< Touch pad channel 2 is GPIO2"]
pub const touch_pad_t_TOUCH_PAD_NUM2: touch_pad_t = 2;
#[doc = "< Touch pad channel 3 is GPIO15"]
pub const touch_pad_t_TOUCH_PAD_NUM3: touch_pad_t = 3;
#[doc = "< Touch pad channel 4 is GPIO13"]
pub const touch_pad_t_TOUCH_PAD_NUM4: touch_pad_t = 4;
#[doc = "< Touch pad channel 5 is GPIO12"]
pub const touch_pad_t_TOUCH_PAD_NUM5: touch_pad_t = 5;
#[doc = "< Touch pad channel 6 is GPIO14"]
pub const touch_pad_t_TOUCH_PAD_NUM6: touch_pad_t = 6;
#[doc = "< Touch pad channel 7 is GPIO27"]
pub const touch_pad_t_TOUCH_PAD_NUM7: touch_pad_t = 7;
#[doc = "< Touch pad channel 8 is GPIO33"]
pub const touch_pad_t_TOUCH_PAD_NUM8: touch_pad_t = 8;
#[doc = "< Touch pad channel 9 is GPIO32"]
pub const touch_pad_t_TOUCH_PAD_NUM9: touch_pad_t = 9;
pub const touch_pad_t_TOUCH_PAD_MAX: touch_pad_t = 10;
pub type touch_pad_t = u32;
#[doc = "<Touch sensor high reference voltage, no change"]
pub const touch_high_volt_t_TOUCH_HVOLT_KEEP: touch_high_volt_t = -1;
#[doc = "<Touch sensor high reference voltage, 2.4V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V4: touch_high_volt_t = 0;
#[doc = "<Touch sensor high reference voltage, 2.5V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V5: touch_high_volt_t = 1;
#[doc = "<Touch sensor high reference voltage, 2.6V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V6: touch_high_volt_t = 2;
#[doc = "<Touch sensor high reference voltage, 2.7V"]
pub const touch_high_volt_t_TOUCH_HVOLT_2V7: touch_high_volt_t = 3;
pub const touch_high_volt_t_TOUCH_HVOLT_MAX: touch_high_volt_t = 4;
pub type touch_high_volt_t = i32;
#[doc = "<Touch sensor low reference voltage, no change"]
pub const touch_low_volt_t_TOUCH_LVOLT_KEEP: touch_low_volt_t = -1;
#[doc = "<Touch sensor low reference voltage, 0.5V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V5: touch_low_volt_t = 0;
#[doc = "<Touch sensor low reference voltage, 0.6V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V6: touch_low_volt_t = 1;
#[doc = "<Touch sensor low reference voltage, 0.7V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V7: touch_low_volt_t = 2;
#[doc = "<Touch sensor low reference voltage, 0.8V"]
pub const touch_low_volt_t_TOUCH_LVOLT_0V8: touch_low_volt_t = 3;
pub const touch_low_volt_t_TOUCH_LVOLT_MAX: touch_low_volt_t = 4;
pub type touch_low_volt_t = i32;
#[doc = "<Touch sensor high reference voltage attenuation, no change"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_KEEP: touch_volt_atten_t = -1;
#[doc = "<Touch sensor high reference voltage attenuation, 1.5V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_1V5: touch_volt_atten_t = 0;
#[doc = "<Touch sensor high reference voltage attenuation, 1.0V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_1V: touch_volt_atten_t = 1;
#[doc = "<Touch sensor high reference voltage attenuation, 0.5V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_0V5: touch_volt_atten_t = 2;
#[doc = "<Touch sensor high reference voltage attenuation, 0V attenuation"]
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_0V: touch_volt_atten_t = 3;
pub const touch_volt_atten_t_TOUCH_HVOLT_ATTEN_MAX: touch_volt_atten_t = 4;
pub type touch_volt_atten_t = i32;
#[doc = "<Touch sensor charge / discharge speed, always zero"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_0: touch_cnt_slope_t = 0;
#[doc = "<Touch sensor charge / discharge speed, slowest"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_1: touch_cnt_slope_t = 1;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_2: touch_cnt_slope_t = 2;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_3: touch_cnt_slope_t = 3;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_4: touch_cnt_slope_t = 4;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_5: touch_cnt_slope_t = 5;
#[doc = "<Touch sensor charge / discharge speed"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_6: touch_cnt_slope_t = 6;
#[doc = "<Touch sensor charge / discharge speed, fast"]
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_7: touch_cnt_slope_t = 7;
pub const touch_cnt_slope_t_TOUCH_PAD_SLOPE_MAX: touch_cnt_slope_t = 8;
pub type touch_cnt_slope_t = u32;
#[doc = "<Touch interrupt will happen if counter value is less than threshold."]
pub const touch_trigger_mode_t_TOUCH_TRIGGER_BELOW: touch_trigger_mode_t = 0;
#[doc = "<Touch interrupt will happen if counter value is larger than threshold."]
pub const touch_trigger_mode_t_TOUCH_TRIGGER_ABOVE: touch_trigger_mode_t = 1;
pub const touch_trigger_mode_t_TOUCH_TRIGGER_MAX: touch_trigger_mode_t = 2;
pub type touch_trigger_mode_t = u32;
#[doc = "< wakeup interrupt is generated if both SET1 and SET2 are \"touched\""]
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_BOTH: touch_trigger_src_t = 0;
#[doc = "< wakeup interrupt is generated if SET1 is \"touched\""]
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_SET1: touch_trigger_src_t = 1;
pub const touch_trigger_src_t_TOUCH_TRIGGER_SOURCE_MAX: touch_trigger_src_t = 2;
pub type touch_trigger_src_t = u32;
#[doc = "<Initial level of charging voltage, low level"]
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_LOW: touch_tie_opt_t = 0;
#[doc = "<Initial level of charging voltage, high level"]
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_HIGH: touch_tie_opt_t = 1;
pub const touch_tie_opt_t_TOUCH_PAD_TIE_OPT_MAX: touch_tie_opt_t = 2;
pub type touch_tie_opt_t = u32;
#[doc = "<To start touch FSM by timer"]
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_TIMER: touch_fsm_mode_t = 0;
#[doc = "<To start touch FSM by software trigger"]
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_SW: touch_fsm_mode_t = 1;
pub const touch_fsm_mode_t_TOUCH_FSM_MODE_MAX: touch_fsm_mode_t = 2;
pub type touch_fsm_mode_t = u32;
pub type touch_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief Initialize touch module."]
#[doc = " @note The default FSM mode is 'TOUCH_FSM_MODE_SW'. If you want to use interrupt trigger mode,"]
#[doc = " then set it using function 'touch_pad_set_fsm_mode' to 'TOUCH_FSM_MODE_TIMER' after calling 'touch_pad_init'."]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Touch pad init error"]
pub fn touch_pad_init() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Un-install touch pad driver."]
#[doc = " @note After this function is called, other touch functions are prohibited from being called."]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Touch pad driver not initialized"]
pub fn touch_pad_deinit() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure touch pad interrupt threshold."]
#[doc = ""]
#[doc = " @note If FSM mode is set to TOUCH_FSM_MODE_TIMER, this function will be blocked for one measurement cycle and wait for data to be valid."]
#[doc = ""]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param threshold interrupt threshold,"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument wrong"]
#[doc = " - ESP_FAIL if touch pad not initialized"]
pub fn touch_pad_config(touch_num: touch_pad_t, threshold: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get touch sensor counter value."]
#[doc = " Each touch sensor has a counter to count the number of charge/discharge cycles."]
#[doc = " When the pad is not 'touched', we can get a number of the counter."]
#[doc = " When the pad is 'touched', the value in counter will get smaller because of the larger equivalent capacitance."]
#[doc = ""]
#[doc = " @note This API requests hardware measurement once. If IIR filter mode is enabled,"]
#[doc = " please use 'touch_pad_read_raw_data' interface instead."]
#[doc = ""]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param touch_value pointer to accept touch sensor value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Touch pad parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of \"touch_value\" is 0."]
#[doc = " - ESP_FAIL Touch pad not initialized"]
pub fn touch_pad_read(touch_num: touch_pad_t, touch_value: *mut u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get filtered touch sensor counter value by IIR filter."]
#[doc = ""]
#[doc = " @note touch_pad_filter_start has to be called before calling touch_pad_read_filtered."]
#[doc = " This function can be called from ISR"]
#[doc = ""]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param touch_value pointer to accept touch sensor value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Touch pad parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of \"touch_value\" is 0."]
#[doc = " - ESP_FAIL Touch pad not initialized"]
pub fn touch_pad_read_filtered(touch_num: touch_pad_t, touch_value: *mut u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get raw data (touch sensor counter value) from IIR filter process."]
#[doc = " Need not request hardware measurements."]
#[doc = ""]
#[doc = " @note touch_pad_filter_start has to be called before calling touch_pad_read_raw_data."]
#[doc = " This function can be called from ISR"]
#[doc = ""]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param touch_value pointer to accept touch sensor value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Touch pad parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of \"touch_value\" is 0."]
#[doc = " - ESP_FAIL Touch pad not initialized"]
pub fn touch_pad_read_raw_data(touch_num: touch_pad_t, touch_value: *mut u16) -> esp_err_t;
}
#[doc = " @brief Callback function that is called after each IIR filter calculation."]
#[doc = " @note This callback is called in timer task in each filtering cycle."]
#[doc = " @note This callback should not be blocked."]
#[doc = " @param raw_value The latest raw data(touch sensor counter value) that"]
#[doc = " points to all channels(raw_value[0..TOUCH_PAD_MAX-1])."]
#[doc = " @param filtered_value The latest IIR filtered data(calculated from raw data) that"]
#[doc = " points to all channels(filtered_value[0..TOUCH_PAD_MAX-1])."]
#[doc = ""]
pub type filter_cb_t =
::core::option::Option<unsafe extern "C" fn(raw_value: *mut u16, filtered_value: *mut u16)>;
extern "C" {
#[doc = " @brief Register the callback function that is called after each IIR filter calculation."]
#[doc = " @note The 'read_cb' callback is called in timer task in each filtering cycle."]
#[doc = " @param read_cb Pointer to filtered callback function."]
#[doc = " If the argument passed in is NULL, the callback will stop."]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG set error"]
pub fn touch_pad_set_filter_read_cb(read_cb: filter_cb_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register touch-pad ISR,"]
#[doc = " @note Deprecated function, users should replace this with touch_pad_isr_register,"]
#[doc = " because RTC modules share a same interrupt index."]
#[doc = " @param fn Pointer to ISR handler"]
#[doc = " @param arg Parameter for ISR"]
#[doc = " @param unused Reserved, not used"]
#[doc = " @param handle_unused Reserved, not used"]
#[doc = " @return"]
#[doc = " - ESP_OK Success ;"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO error"]
#[doc = " - ESP_ERR_NO_MEM No memory"]
pub fn touch_pad_isr_handler_register(
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
unused: ::std::os::raw::c_int,
handle_unused: *mut intr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register touch-pad ISR."]
#[doc = " The handler will be attached to the same CPU core that this function is running on."]
#[doc = " @param fn Pointer to ISR handler"]
#[doc = " @param arg Parameter for ISR"]
#[doc = " @return"]
#[doc = " - ESP_OK Success ;"]
#[doc = " - ESP_ERR_INVALID_ARG GPIO error"]
#[doc = " - ESP_ERR_NO_MEM No memory"]
pub fn touch_pad_isr_register(
fn_: intr_handler_t,
arg: *mut ::std::os::raw::c_void,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Deregister the handler previously registered using touch_pad_isr_handler_register"]
#[doc = " @param fn handler function to call (as passed to touch_pad_isr_handler_register)"]
#[doc = " @param arg argument of the handler (as passed to touch_pad_isr_handler_register)"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if a handler matching both fn and"]
#[doc = " arg isn't registered"]
pub fn touch_pad_isr_deregister(
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor measurement and sleep time"]
#[doc = " @param sleep_cycle The touch sensor will sleep after each measurement."]
#[doc = " sleep_cycle decide the interval between each measurement."]
#[doc = " t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency)."]
#[doc = " The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function."]
#[doc = " @param meas_cycle The duration of the touch sensor measurement."]
#[doc = " t_meas = meas_cycle / 8M, the maximum measure time is 0xffff / 8M = 8.19 ms"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_set_meas_time(sleep_cycle: u16, meas_cycle: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor measurement and sleep time"]
#[doc = " @param sleep_cycle Pointer to accept sleep cycle number"]
#[doc = " @param meas_cycle Pointer to accept measurement cycle count."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_meas_time(sleep_cycle: *mut u16, meas_cycle: *mut u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor reference voltage, if the voltage gap between high and low reference voltage get less,"]
#[doc = " the charging and discharging time would be faster, accordingly, the counter value would be larger."]
#[doc = " In the case of detecting very slight change of capacitance, we can narrow down the gap so as to increase"]
#[doc = " the sensitivity. On the other hand, narrow voltage gap would also introduce more noise, but we can use a"]
#[doc = " software filter to pre-process the counter value."]
#[doc = " @param refh the value of DREFH"]
#[doc = " @param refl the value of DREFL"]
#[doc = " @param atten the attenuation on DREFH"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_voltage(
refh: touch_high_volt_t,
refl: touch_low_volt_t,
atten: touch_volt_atten_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor reference voltage,"]
#[doc = " @param refh pointer to accept DREFH value"]
#[doc = " @param refl pointer to accept DREFL value"]
#[doc = " @param atten pointer to accept the attenuation on DREFH"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_voltage(
refh: *mut touch_high_volt_t,
refl: *mut touch_low_volt_t,
atten: *mut touch_volt_atten_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor charge/discharge speed for each pad."]
#[doc = " If the slope is 0, the counter would always be zero."]
#[doc = " If the slope is 1, the charging and discharging would be slow, accordingly, the counter value would be small."]
#[doc = " If the slope is set 7, which is the maximum value, the charging and discharging would be fast, accordingly, the"]
#[doc = " counter value would be larger."]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param slope touch pad charge/discharge speed"]
#[doc = " @param opt the initial voltage"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_cnt_mode(
touch_num: touch_pad_t,
slope: touch_cnt_slope_t,
opt: touch_tie_opt_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor charge/discharge speed for each pad"]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param slope pointer to accept touch pad charge/discharge slope"]
#[doc = " @param opt pointer to accept the initial voltage"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_get_cnt_mode(
touch_num: touch_pad_t,
slope: *mut touch_cnt_slope_t,
opt: *mut touch_tie_opt_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize touch pad GPIO"]
#[doc = " @param touch_num touch pad index"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_io_init(touch_num: touch_pad_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor FSM mode, the test action can be triggered by the timer,"]
#[doc = " as well as by the software."]
#[doc = " @param mode FSM mode"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_fsm_mode(mode: touch_fsm_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor FSM mode"]
#[doc = " @param mode pointer to accept FSM mode"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_fsm_mode(mode: *mut touch_fsm_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Trigger a touch sensor measurement, only support in SW mode of FSM"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_sw_start() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor interrupt threshold"]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param threshold threshold of touchpad count, refer to touch_pad_set_trigger_mode to see how to set trigger mode."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_thresh(touch_num: touch_pad_t, threshold: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor interrupt threshold"]
#[doc = " @param touch_num touch pad index"]
#[doc = " @param threshold pointer to accept threshold"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_get_thresh(touch_num: touch_pad_t, threshold: *mut u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor interrupt trigger mode."]
#[doc = " Interrupt can be triggered either when counter result is less than"]
#[doc = " threshold or when counter result is more than threshold."]
#[doc = " @param mode touch sensor interrupt trigger mode"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_trigger_mode(mode: touch_trigger_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor interrupt trigger mode"]
#[doc = " @param mode pointer to accept touch sensor interrupt trigger mode"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_trigger_mode(mode: *mut touch_trigger_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor interrupt trigger source. There are two sets of touch signals."]
#[doc = " Set1 and set2 can be mapped to several touch signals. Either set will be triggered"]
#[doc = " if at least one of its touch signal is 'touched'. The interrupt can be configured to be generated"]
#[doc = " if set1 is triggered, or only if both sets are triggered."]
#[doc = " @param src touch sensor interrupt trigger source"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_trigger_source(src: touch_trigger_src_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor interrupt trigger source"]
#[doc = " @param src pointer to accept touch sensor interrupt trigger source"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_trigger_source(src: *mut touch_trigger_src_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set touch sensor group mask."]
#[doc = " Touch pad module has two sets of signals, 'Touched' signal is triggered only if"]
#[doc = " at least one of touch pad in this group is \"touched\"."]
#[doc = " This function will set the register bits according to the given bitmask."]
#[doc = " @param set1_mask bitmask of touch sensor signal group1, it's a 10-bit value"]
#[doc = " @param set2_mask bitmask of touch sensor signal group2, it's a 10-bit value"]
#[doc = " @param en_mask bitmask of touch sensor work enable, it's a 10-bit value"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_set_group_mask(set1_mask: u16, set2_mask: u16, en_mask: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get touch sensor group mask."]
#[doc = " @param set1_mask pointer to accept bitmask of touch sensor signal group1, it's a 10-bit value"]
#[doc = " @param set2_mask pointer to accept bitmask of touch sensor signal group2, it's a 10-bit value"]
#[doc = " @param en_mask pointer to accept bitmask of touch sensor work enable, it's a 10-bit value"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_get_group_mask(
set1_mask: *mut u16,
set2_mask: *mut u16,
en_mask: *mut u16,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Clear touch sensor group mask."]
#[doc = " Touch pad module has two sets of signals, Interrupt is triggered only if"]
#[doc = " at least one of touch pad in this group is \"touched\"."]
#[doc = " This function will clear the register bits according to the given bitmask."]
#[doc = " @param set1_mask bitmask touch sensor signal group1, it's a 10-bit value"]
#[doc = " @param set2_mask bitmask touch sensor signal group2, it's a 10-bit value"]
#[doc = " @param en_mask bitmask of touch sensor work enable, it's a 10-bit value"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if argument is wrong"]
pub fn touch_pad_clear_group_mask(set1_mask: u16, set2_mask: u16, en_mask: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief To clear the touch status register, usually use this function in touch ISR to clear status."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_clear_status() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the touch sensor status, usually used in ISR to decide which pads are 'touched'."]
#[doc = " @return"]
#[doc = " - touch status"]
pub fn touch_pad_get_status() -> u32;
}
extern "C" {
#[doc = " @brief To enable touch pad interrupt"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_intr_enable() -> esp_err_t;
}
extern "C" {
#[doc = " @brief To disable touch pad interrupt"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
pub fn touch_pad_intr_disable() -> esp_err_t;
}
extern "C" {
#[doc = " @brief set touch pad filter calibration period, in ms."]
#[doc = " Need to call touch_pad_filter_start before all touch filter APIs"]
#[doc = " @param new_period_ms filter period, in ms"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE driver state error"]
#[doc = " - ESP_ERR_INVALID_ARG parameter error"]
pub fn touch_pad_set_filter_period(new_period_ms: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get touch pad filter calibration period, in ms"]
#[doc = " Need to call touch_pad_filter_start before all touch filter APIs"]
#[doc = " @param p_period_ms pointer to accept period"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE driver state error"]
#[doc = " - ESP_ERR_INVALID_ARG parameter error"]
pub fn touch_pad_get_filter_period(p_period_ms: *mut u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief start touch pad filter function"]
#[doc = " This API will start a filter to process the noise in order to prevent false triggering"]
#[doc = " when detecting slight change of capacitance."]
#[doc = " Need to call touch_pad_filter_start before all touch filter APIs"]
#[doc = ""]
#[doc = " @note This filter uses FreeRTOS timer, which is dispatched from a task with"]
#[doc = " priority 1 by default on CPU 0. So if some application task with higher priority"]
#[doc = " takes a lot of CPU0 time, then the quality of data obtained from this filter will be affected."]
#[doc = " You can adjust FreeRTOS timer task priority in menuconfig."]
#[doc = " @param filter_period_ms filter calibration period, in ms"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG parameter error"]
#[doc = " - ESP_ERR_NO_MEM No memory for driver"]
#[doc = " - ESP_ERR_INVALID_STATE driver state error"]
pub fn touch_pad_filter_start(filter_period_ms: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief stop touch pad filter function"]
#[doc = " Need to call touch_pad_filter_start before all touch filter APIs"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE driver state error"]
pub fn touch_pad_filter_stop() -> esp_err_t;
}
extern "C" {
#[doc = " @brief delete touch pad filter driver and release the memory"]
#[doc = " Need to call touch_pad_filter_start before all touch filter APIs"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE driver state error"]
pub fn touch_pad_filter_delete() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the touch pad which caused wakeup from sleep"]
#[doc = " @param pad_num pointer to touch pad which caused wakeup"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL get status err"]
pub fn touch_pad_get_wakeup_status(pad_num: *mut touch_pad_t) -> esp_err_t;
}
#[doc = "!< Wake the chip when all selected GPIOs go low"]
pub const esp_sleep_ext1_wakeup_mode_t_ESP_EXT1_WAKEUP_ALL_LOW: esp_sleep_ext1_wakeup_mode_t = 0;
#[doc = "!< Wake the chip when any of the selected GPIOs go high"]
pub const esp_sleep_ext1_wakeup_mode_t_ESP_EXT1_WAKEUP_ANY_HIGH: esp_sleep_ext1_wakeup_mode_t = 1;
#[doc = " @brief Logic function used for EXT1 wakeup mode."]
pub type esp_sleep_ext1_wakeup_mode_t = u32;
#[doc = "!< RTC IO, sensors and ULP co-processor"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_PERIPH: esp_sleep_pd_domain_t = 0;
#[doc = "!< RTC slow memory"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_SLOW_MEM: esp_sleep_pd_domain_t = 1;
#[doc = "!< RTC fast memory"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_RTC_FAST_MEM: esp_sleep_pd_domain_t = 2;
#[doc = "!< XTAL oscillator"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_XTAL: esp_sleep_pd_domain_t = 3;
#[doc = "!< Number of domains"]
pub const esp_sleep_pd_domain_t_ESP_PD_DOMAIN_MAX: esp_sleep_pd_domain_t = 4;
#[doc = " @brief Power domains which can be powered down in sleep mode"]
pub type esp_sleep_pd_domain_t = u32;
#[doc = "!< Power down the power domain in sleep mode"]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_OFF: esp_sleep_pd_option_t = 0;
#[doc = "!< Keep power domain enabled during sleep mode"]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_ON: esp_sleep_pd_option_t = 1;
#[doc = "!< Keep power domain enabled in sleep mode, if it is needed by one of the wakeup options. Otherwise power it down."]
pub const esp_sleep_pd_option_t_ESP_PD_OPTION_AUTO: esp_sleep_pd_option_t = 2;
#[doc = " @brief Power down options"]
pub type esp_sleep_pd_option_t = u32;
#[doc = "!< In case of deep sleep, reset was not caused by exit from deep sleep"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_UNDEFINED: esp_sleep_source_t = 0;
#[doc = "!< Not a wakeup cause, used to disable all wakeup sources with esp_sleep_disable_wakeup_source"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_ALL: esp_sleep_source_t = 1;
#[doc = "!< Wakeup caused by external signal using RTC_IO"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_EXT0: esp_sleep_source_t = 2;
#[doc = "!< Wakeup caused by external signal using RTC_CNTL"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_EXT1: esp_sleep_source_t = 3;
#[doc = "!< Wakeup caused by timer"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_TIMER: esp_sleep_source_t = 4;
#[doc = "!< Wakeup caused by touchpad"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_TOUCHPAD: esp_sleep_source_t = 5;
#[doc = "!< Wakeup caused by ULP program"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_ULP: esp_sleep_source_t = 6;
#[doc = "!< Wakeup caused by GPIO (light sleep only)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_GPIO: esp_sleep_source_t = 7;
#[doc = "!< Wakeup caused by UART (light sleep only)"]
pub const esp_sleep_source_t_ESP_SLEEP_WAKEUP_UART: esp_sleep_source_t = 8;
#[doc = " @brief Sleep wakeup cause"]
pub type esp_sleep_source_t = u32;
pub use self::esp_sleep_source_t as esp_sleep_wakeup_cause_t;
extern "C" {
#[doc = " @brief Disable wakeup source"]
#[doc = ""]
#[doc = " This function is used to deactivate wake up trigger for source"]
#[doc = " defined as parameter of the function."]
#[doc = ""]
#[doc = " @note This function does not modify wake up configuration in RTC."]
#[doc = " It will be performed in esp_sleep_start function."]
#[doc = ""]
#[doc = " See docs/sleep-modes.rst for details."]
#[doc = ""]
#[doc = " @param source - number of source to disable of type esp_sleep_source_t"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if trigger was not active"]
pub fn esp_sleep_disable_wakeup_source(source: esp_sleep_source_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by ULP coprocessor"]
#[doc = " @note In revisions 0 and 1 of the ESP32, ULP wakeup source"]
#[doc = " can not be used when RTC_PERIPH power domain is forced"]
#[doc = " to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup"]
#[doc = " source is used."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled."]
#[doc = " - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict"]
pub fn esp_sleep_enable_ulp_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by timer"]
#[doc = " @param time_in_us time before wakeup, in microseconds"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if value is out of range (TBD)"]
pub fn esp_sleep_enable_timer_wakeup(time_in_us: u64) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup by touch sensor"]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, touch wakeup source"]
#[doc = " can not be used when RTC_PERIPH power domain is forced"]
#[doc = " to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup"]
#[doc = " source is used."]
#[doc = ""]
#[doc = " @note The FSM mode of the touch button should be configured"]
#[doc = " as the timer trigger mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled."]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_touchpad_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the touch pad which caused wakeup"]
#[doc = ""]
#[doc = " If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;"]
#[doc = ""]
#[doc = " @return touch pad which caused wakeup"]
pub fn esp_sleep_get_touchpad_wakeup_status() -> touch_pad_t;
}
extern "C" {
#[doc = " @brief Enable wakeup using a pin"]
#[doc = ""]
#[doc = " This function uses external wakeup feature of RTC_IO peripheral."]
#[doc = " It will work only if RTC peripherals are kept on during sleep."]
#[doc = ""]
#[doc = " This feature can monitor any pin which is an RTC IO. Once the pin transitions"]
#[doc = " into the state given by level argument, the chip will be woken up."]
#[doc = ""]
#[doc = " @note This function does not modify pin configuration. The pin is"]
#[doc = " configured in esp_sleep_start, immediately before entering sleep mode."]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, ext0 wakeup source"]
#[doc = " can not be used together with touch or ULP wakeup sources."]
#[doc = ""]
#[doc = " @param gpio_num GPIO number used as wakeup source. Only GPIOs which are have RTC"]
#[doc = " functionality can be used: 0,2,4,12-15,25-27,32-39."]
#[doc = " @param level input level which will trigger wakeup (0=low, 1=high)"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,"]
#[doc = " or the mode is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_ext0_wakeup(
gpio_num: gpio_num_t,
level: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup using multiple pins"]
#[doc = ""]
#[doc = " This function uses external wakeup feature of RTC controller."]
#[doc = " It will work even if RTC peripherals are shut down during sleep."]
#[doc = ""]
#[doc = " This feature can monitor any number of pins which are in RTC IOs."]
#[doc = " Once any of the selected pins goes into the state given by mode argument,"]
#[doc = " the chip will be woken up."]
#[doc = ""]
#[doc = " @note This function does not modify pin configuration. The pins are"]
#[doc = " configured in esp_sleep_start, immediately before"]
#[doc = " entering sleep mode."]
#[doc = ""]
#[doc = " @note internal pullups and pulldowns don't work when RTC peripherals are"]
#[doc = " shut down. In this case, external resistors need to be added."]
#[doc = " Alternatively, RTC peripherals (and pullups/pulldowns) may be"]
#[doc = " kept enabled using esp_sleep_pd_config function."]
#[doc = ""]
#[doc = " @param mask bit mask of GPIO numbers which will cause wakeup. Only GPIOs"]
#[doc = " which are have RTC functionality can be used in this bit map:"]
#[doc = " 0,2,4,12-15,25-27,32-39."]
#[doc = " @param mode select logic function used to determine wakeup condition:"]
#[doc = " - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low"]
#[doc = " - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,"]
#[doc = " or mode is invalid"]
pub fn esp_sleep_enable_ext1_wakeup(mask: u64, mode: esp_sleep_ext1_wakeup_mode_t)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup from light sleep using GPIOs"]
#[doc = ""]
#[doc = " Each GPIO supports wakeup function, which can be triggered on either low level"]
#[doc = " or high level. Unlike EXT0 and EXT1 wakeup sources, this method can be used"]
#[doc = " both for all IOs: RTC IOs and digital IOs. It can only be used to wakeup from"]
#[doc = " light sleep though."]
#[doc = ""]
#[doc = " To enable wakeup, first call gpio_wakeup_enable, specifying gpio number and"]
#[doc = " wakeup level, for each GPIO which is used for wakeup."]
#[doc = " Then call this function to enable wakeup feature."]
#[doc = ""]
#[doc = " @note In revisions 0 and 1 of the ESP32, GPIO wakeup source"]
#[doc = " can not be used together with touch or ULP wakeup sources."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_STATE if wakeup triggers conflict"]
pub fn esp_sleep_enable_gpio_wakeup() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable wakeup from light sleep using UART"]
#[doc = ""]
#[doc = " Use uart_set_wakeup_threshold function to configure UART wakeup threshold."]
#[doc = ""]
#[doc = " Wakeup from light sleep takes some time, so not every character sent"]
#[doc = " to the UART can be received by the application."]
#[doc = ""]
#[doc = " @note ESP32 does not support wakeup from UART2."]
#[doc = ""]
#[doc = " @param uart_num UART port to wake up from"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if wakeup from given UART is not supported"]
pub fn esp_sleep_enable_uart_wakeup(uart_num: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the bit mask of GPIOs which caused wakeup (ext1)"]
#[doc = ""]
#[doc = " If wakeup was caused by another source, this function will return 0."]
#[doc = ""]
#[doc = " @return bit mask, if GPIOn caused wakeup, BIT(n) will be set"]
pub fn esp_sleep_get_ext1_wakeup_status() -> u64;
}
extern "C" {
#[doc = " @brief Set power down mode for an RTC power domain in sleep mode"]
#[doc = ""]
#[doc = " If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO."]
#[doc = ""]
#[doc = " @param domain power domain to configure"]
#[doc = " @param option power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO)"]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if either of the arguments is out of range"]
pub fn esp_sleep_pd_config(
domain: esp_sleep_pd_domain_t,
option: esp_sleep_pd_option_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enter deep sleep with the configured wakeup options"]
#[doc = ""]
#[doc = " This function does not return."]
pub fn esp_deep_sleep_start();
}
extern "C" {
#[doc = " @brief Enter light sleep with the configured wakeup options"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK on success (returned after wakeup)"]
#[doc = " - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped"]
pub fn esp_light_sleep_start() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enter deep-sleep mode"]
#[doc = ""]
#[doc = " The device will automatically wake up after the deep-sleep time"]
#[doc = " Upon waking up, the device calls deep sleep wake stub, and then proceeds"]
#[doc = " to load application."]
#[doc = ""]
#[doc = " Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup"]
#[doc = " followed by a call to esp_deep_sleep_start."]
#[doc = ""]
#[doc = " esp_deep_sleep does not shut down WiFi, BT, and higher level protocol"]
#[doc = " connections gracefully."]
#[doc = " Make sure relevant WiFi and BT stack functions are called to close any"]
#[doc = " connections and deinitialize the peripherals. These include:"]
#[doc = " - esp_bluedroid_disable"]
#[doc = " - esp_bt_controller_disable"]
#[doc = " - esp_wifi_stop"]
#[doc = ""]
#[doc = " This function does not return."]
#[doc = ""]
#[doc = " @param time_in_us deep-sleep time, unit: microsecond"]
pub fn esp_deep_sleep(time_in_us: u64);
}
extern "C" {
#[doc = " @brief Enter deep-sleep mode"]
#[doc = ""]
#[doc = " Function has been renamed to esp_deep_sleep."]
#[doc = " This name is deprecated and will be removed in a future version."]
#[doc = ""]
#[doc = " @param time_in_us deep-sleep time, unit: microsecond"]
pub fn system_deep_sleep(time_in_us: u64);
}
extern "C" {
#[doc = " @brief Get the wakeup source which caused wakeup from sleep"]
#[doc = ""]
#[doc = " @return cause of wake up from last sleep (deep sleep or light sleep)"]
pub fn esp_sleep_get_wakeup_cause() -> esp_sleep_wakeup_cause_t;
}
extern "C" {
#[doc = " @brief Default stub to run on wake from deep sleep."]
#[doc = ""]
#[doc = " Allows for executing code immediately on wake from sleep, before"]
#[doc = " the software bootloader or ESP-IDF app has started up."]
#[doc = ""]
#[doc = " This function is weak-linked, so you can implement your own version"]
#[doc = " to run code immediately when the chip wakes from"]
#[doc = " sleep."]
#[doc = ""]
#[doc = " See docs/deep-sleep-stub.rst for details."]
pub fn esp_wake_deep_sleep();
}
#[doc = " @brief Function type for stub to run on wake from sleep."]
#[doc = ""]
pub type esp_deep_sleep_wake_stub_fn_t = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
#[doc = " @brief Install a new stub at runtime to run on wake from deep sleep"]
#[doc = ""]
#[doc = " If implementing esp_wake_deep_sleep() then it is not necessary to"]
#[doc = " call this function."]
#[doc = ""]
#[doc = " However, it is possible to call this function to substitute a"]
#[doc = " different deep sleep stub. Any function used as a deep sleep stub"]
#[doc = " must be marked RTC_IRAM_ATTR, and must obey the same rules given"]
#[doc = " for esp_wake_deep_sleep()."]
pub fn esp_set_deep_sleep_wake_stub(new_stub: esp_deep_sleep_wake_stub_fn_t);
}
extern "C" {
#[doc = " @brief Get current wake from deep sleep stub"]
#[doc = " @return Return current wake from deep sleep stub, or NULL if"]
#[doc = " no stub is installed."]
pub fn esp_get_deep_sleep_wake_stub() -> esp_deep_sleep_wake_stub_fn_t;
}
extern "C" {
#[doc = " @brief The default esp-idf-provided esp_wake_deep_sleep() stub."]
#[doc = ""]
#[doc = " See docs/deep-sleep-stub.rst for details."]
pub fn esp_default_wake_deep_sleep();
}
extern "C" {
#[doc = " @brief Disable logging from the ROM code after deep sleep."]
#[doc = ""]
#[doc = " Using LSB of RTC_STORE4."]
pub fn esp_deep_sleep_disable_rom_logging();
}
pub const esp_mac_type_t_ESP_MAC_WIFI_STA: esp_mac_type_t = 0;
pub const esp_mac_type_t_ESP_MAC_WIFI_SOFTAP: esp_mac_type_t = 1;
pub const esp_mac_type_t_ESP_MAC_BT: esp_mac_type_t = 2;
pub const esp_mac_type_t_ESP_MAC_ETH: esp_mac_type_t = 3;
pub type esp_mac_type_t = u32;
#[doc = "!< Reset reason can not be determined"]
pub const esp_reset_reason_t_ESP_RST_UNKNOWN: esp_reset_reason_t = 0;
#[doc = "!< Reset due to power-on event"]
pub const esp_reset_reason_t_ESP_RST_POWERON: esp_reset_reason_t = 1;
#[doc = "!< Reset by external pin (not applicable for ESP32)"]
pub const esp_reset_reason_t_ESP_RST_EXT: esp_reset_reason_t = 2;
#[doc = "!< Software reset via esp_restart"]
pub const esp_reset_reason_t_ESP_RST_SW: esp_reset_reason_t = 3;
#[doc = "!< Software reset due to exception/panic"]
pub const esp_reset_reason_t_ESP_RST_PANIC: esp_reset_reason_t = 4;
#[doc = "!< Reset (software or hardware) due to interrupt watchdog"]
pub const esp_reset_reason_t_ESP_RST_INT_WDT: esp_reset_reason_t = 5;
#[doc = "!< Reset due to task watchdog"]
pub const esp_reset_reason_t_ESP_RST_TASK_WDT: esp_reset_reason_t = 6;
#[doc = "!< Reset due to other watchdogs"]
pub const esp_reset_reason_t_ESP_RST_WDT: esp_reset_reason_t = 7;
#[doc = "!< Reset after exiting deep sleep mode"]
pub const esp_reset_reason_t_ESP_RST_DEEPSLEEP: esp_reset_reason_t = 8;
#[doc = "!< Brownout reset (software or hardware)"]
pub const esp_reset_reason_t_ESP_RST_BROWNOUT: esp_reset_reason_t = 9;
#[doc = "!< Reset over SDIO"]
pub const esp_reset_reason_t_ESP_RST_SDIO: esp_reset_reason_t = 10;
#[doc = " @brief Reset reasons"]
pub type esp_reset_reason_t = u32;
extern "C" {
#[doc = " @cond */"]
#[doc = " @attention Applications don't need to call this function anymore. It does nothing and will"]
#[doc = " be removed in future version."]
pub fn system_init();
}
extern "C" {
#[doc = " @brief Reset to default settings."]
#[doc = ""]
#[doc = " Function has been deprecated, please use esp_wifi_restore instead."]
#[doc = " This name will be removed in a future release."]
pub fn system_restore();
}
#[doc = " Shutdown handler type"]
pub type shutdown_handler_t = ::core::option::Option<unsafe extern "C" fn()>;
extern "C" {
#[doc = " @brief Register shutdown handler"]
#[doc = ""]
#[doc = " This function allows you to register a handler that gets invoked before"]
#[doc = " the application is restarted using esp_restart function."]
pub fn esp_register_shutdown_handler(handle: shutdown_handler_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Restart PRO and APP CPUs."]
#[doc = ""]
#[doc = " This function can be called both from PRO and APP CPUs."]
#[doc = " After successful restart, CPU reset reason will be SW_CPU_RESET."]
#[doc = " Peripherals (except for WiFi, BT, UART0, SPI1, and legacy timers) are not reset."]
#[doc = " This function does not return."]
pub fn esp_restart();
}
extern "C" {
#[doc = " @cond */"]
#[doc = " @brief Restart system."]
#[doc = ""]
#[doc = " Function has been renamed to esp_restart."]
#[doc = " This name will be removed in a future release."]
pub fn system_restart();
}
extern "C" {
#[doc = " @brief Get reason of last reset"]
#[doc = " @return See description of esp_reset_reason_t for explanation of each value."]
pub fn esp_reset_reason() -> esp_reset_reason_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " @brief Get system time, unit: microsecond."]
#[doc = ""]
#[doc = " This function is deprecated. Use 'gettimeofday' function for 64-bit precision."]
#[doc = " This definition will be removed in a future release."]
pub fn system_get_time() -> u32;
}
extern "C" {
#[doc = " @brief Get the size of available heap."]
#[doc = ""]
#[doc = " Note that the returned value may be larger than the maximum contiguous block"]
#[doc = " which can be allocated."]
#[doc = ""]
#[doc = " @return Available heap size, in bytes."]
pub fn esp_get_free_heap_size() -> u32;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " @brief Get the size of available heap."]
#[doc = ""]
#[doc = " Function has been renamed to esp_get_free_heap_size."]
#[doc = " This name will be removed in a future release."]
#[doc = ""]
#[doc = " @return Available heap size, in bytes."]
pub fn system_get_free_heap_size() -> u32;
}
extern "C" {
#[doc = " @brief Get the minimum heap that has ever been available"]
#[doc = ""]
#[doc = " @return Minimum free heap ever available"]
pub fn esp_get_minimum_free_heap_size() -> u32;
}
extern "C" {
#[doc = " @brief Get one random 32-bit word from hardware RNG"]
#[doc = ""]
#[doc = " The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For"]
#[doc = " random values, call this function after WiFi or Bluetooth are started."]
#[doc = ""]
#[doc = " If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an"]
#[doc = " entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'"]
#[doc = " documentation for more details."]
#[doc = ""]
#[doc = " Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be"]
#[doc = " considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF"]
#[doc = " bootloader is running, but this should not be relied upon for any use."]
#[doc = ""]
#[doc = " @return Random value between 0 and UINT32_MAX"]
pub fn esp_random() -> u32;
}
extern "C" {
#[doc = " @brief Fill a buffer with random bytes from hardware RNG"]
#[doc = ""]
#[doc = " @note This function has the same restrictions regarding available entropy as esp_random()"]
#[doc = ""]
#[doc = " @param buf Pointer to buffer to fill with random numbers."]
#[doc = " @param len Length of buffer in bytes"]
pub fn esp_fill_random(buf: *mut ::std::os::raw::c_void, len: usize);
}
extern "C" {
#[doc = " @brief Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or"]
#[doc = " external storage e.g. flash and EEPROM."]
#[doc = ""]
#[doc = " Base MAC address is used to generate the MAC addresses used by the networking interfaces."]
#[doc = " If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC"]
#[doc = " address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing"]
#[doc = " WiFi/BT/Ethernet."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_base_mac_addr_set(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which is set using esp_base_mac_addr_set."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_MAC base MAC address has not been set"]
pub fn esp_base_mac_addr_get(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which was previously written to BLK3 of EFUSE."]
#[doc = ""]
#[doc = " Base MAC address is used to generate the MAC addresses used by the networking interfaces."]
#[doc = " This API returns the custom base MAC address which was previously written to BLK3 of EFUSE."]
#[doc = " Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also"]
#[doc = " possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
#[doc = " ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE"]
#[doc = " ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE"]
pub fn esp_efuse_mac_get_custom(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE."]
#[doc = ""]
#[doc = " @param mac base MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_efuse_mac_get_default(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " @brief Read hardware MAC address from efuse."]
#[doc = ""]
#[doc = " Function has been renamed to esp_efuse_mac_get_default."]
#[doc = " This name will be removed in a future release."]
#[doc = ""]
#[doc = " @param mac hardware MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_efuse_read_mac(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read hardware MAC address."]
#[doc = ""]
#[doc = " Function has been renamed to esp_efuse_mac_get_default."]
#[doc = " This name will be removed in a future release."]
#[doc = ""]
#[doc = " @param mac hardware MAC address, length: 6 bytes."]
#[doc = " @return ESP_OK on success"]
pub fn system_efuse_read_mac(mac: *mut u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read base MAC address and set MAC address of the interface."]
#[doc = ""]
#[doc = " This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address"]
#[doc = " from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,"]
#[doc = " bluetooth and ethernet."]
#[doc = ""]
#[doc = " @param mac MAC address of the interface, length: 6 bytes."]
#[doc = " @param type type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_read_mac(mac: *mut u8, type_: esp_mac_type_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Derive local MAC address from universal MAC address."]
#[doc = ""]
#[doc = " This function derives a local MAC address from an universal MAC address."]
#[doc = " A `definition of local vs universal MAC address can be found on Wikipedia"]
#[doc = " <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`."]
#[doc = " In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage."]
#[doc = " Local MAC address is derived from the universal MAC address."]
#[doc = ""]
#[doc = " @param local_mac Derived local MAC address, length: 6 bytes."]
#[doc = " @param universal_mac Source universal MAC address, length: 6 bytes."]
#[doc = ""]
#[doc = " @return ESP_OK on success"]
pub fn esp_derive_local_mac(local_mac: *mut u8, universal_mac: *const u8) -> esp_err_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " Get SDK version"]
#[doc = ""]
#[doc = " This function is deprecated and will be removed in a future release."]
#[doc = ""]
#[doc = " @return constant string \"master\""]
pub fn system_get_sdk_version() -> *const ::std::os::raw::c_char;
}
extern "C" {
#[doc = " Get IDF version"]
#[doc = ""]
#[doc = " @return constant string from IDF_VER"]
pub fn esp_get_idf_version() -> *const ::std::os::raw::c_char;
}
#[doc = "!< ESP32"]
pub const esp_chip_model_t_CHIP_ESP32: esp_chip_model_t = 1;
#[doc = " @brief Chip models"]
pub type esp_chip_model_t = u32;
#[doc = " @brief The structure represents information about the chip"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct esp_chip_info_t {
#[doc = "!< chip model, one of esp_chip_model_t"]
pub model: esp_chip_model_t,
#[doc = "!< bit mask of CHIP_FEATURE_x feature flags"]
pub features: u32,
#[doc = "!< number of CPU cores"]
pub cores: u8,
#[doc = "!< chip revision number"]
pub revision: u8,
}
extern "C" {
#[doc = " @brief Fill an esp_chip_info_t structure with information about the chip"]
#[doc = " @param[out] out_info structure to be filled"]
pub fn esp_chip_info(out_info: *mut esp_chip_info_t);
}
extern "C" {
pub fn pxPortInitialiseStack(
pxTopOfStack: *mut StackType_t,
pxCode: TaskFunction_t,
pvParameters: *mut ::std::os::raw::c_void,
xRunPrivileged: BaseType_t,
) -> *mut StackType_t;
}
extern "C" {
pub fn xPortStartScheduler() -> BaseType_t;
}
extern "C" {
pub fn vPortEndScheduler();
}
extern "C" {
pub fn vPortYieldOtherCore(coreid: BaseType_t);
}
extern "C" {
pub fn vPortSetStackWatchpoint(pxStackStart: *mut ::std::os::raw::c_void);
}
extern "C" {
pub fn xPortInIsrContext() -> BaseType_t;
}
extern "C" {
pub fn xPortInterruptedFromISRContext() -> BaseType_t;
}
extern "C" {
pub fn vPortStoreTaskMPUSettings(
xMPUSettings: *mut xMPU_SETTINGS,
xRegions: *const xMEMORY_REGION,
pxBottomOfStack: *mut StackType_t,
usStackDepth: u32,
);
}
extern "C" {
pub fn vPortReleaseTaskMPUSettings(xMPUSettings: *mut xMPU_SETTINGS);
}
extern "C" {
pub fn xPortGetTickRateHz() -> u32;
}
extern "C" {
pub fn uxPortCompareSetExtram(addr: *mut u32, compare: u32, set: *mut u32);
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_LIST_ITEM {
pub xDummy1: TickType_t,
pub pvDummy2: [*mut ::std::os::raw::c_void; 4usize],
}
pub type StaticListItem_t = xSTATIC_LIST_ITEM;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_MINI_LIST_ITEM {
pub xDummy1: TickType_t,
pub pvDummy2: [*mut ::std::os::raw::c_void; 2usize],
}
pub type StaticMiniListItem_t = xSTATIC_MINI_LIST_ITEM;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_LIST {
pub uxDummy1: UBaseType_t,
pub pvDummy2: *mut ::std::os::raw::c_void,
pub xDummy3: StaticMiniListItem_t,
}
pub type StaticList_t = xSTATIC_LIST;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_TCB {
pub pxDummy1: *mut ::std::os::raw::c_void,
pub xDummy2: xMPU_SETTINGS,
pub xDummy3: [StaticListItem_t; 2usize],
pub uxDummy5: UBaseType_t,
pub pxDummy6: *mut ::std::os::raw::c_void,
pub ucDummy7: [u8; 16usize],
pub uxDummyCoreId: UBaseType_t,
pub pxDummy8: *mut ::std::os::raw::c_void,
pub uxDummy9: UBaseType_t,
pub OldInterruptState: u32,
pub uxDummy12: [UBaseType_t; 2usize],
pub pvDummy15: [*mut ::std::os::raw::c_void; 1usize],
pub pvDummyLocalStorageCallBack: [*mut ::std::os::raw::c_void; 1usize],
pub xDummy17: _reent,
pub ulDummy18: u32,
pub ucDummy19: u32,
pub uxDummy20: u8,
}
pub type StaticTask_t = xSTATIC_TCB;
#[repr(C)]
#[derive(Copy, Clone)]
pub struct xSTATIC_QUEUE {
pub pvDummy1: [*mut ::std::os::raw::c_void; 3usize],
pub u: xSTATIC_QUEUE__bindgen_ty_1,
pub xDummy3: [StaticList_t; 2usize],
pub uxDummy4: [UBaseType_t; 3usize],
pub pvDummy7: *mut ::std::os::raw::c_void,
pub muxDummy: portMUX_TYPE,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union xSTATIC_QUEUE__bindgen_ty_1 {
pub pvDummy2: *mut ::std::os::raw::c_void,
pub uxDummy2: UBaseType_t,
_bindgen_union_align: u32,
}
pub type StaticQueue_t = xSTATIC_QUEUE;
pub type StaticSemaphore_t = StaticQueue_t;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_EVENT_GROUP {
pub xDummy1: TickType_t,
pub xDummy2: StaticList_t,
pub muxDummy: portMUX_TYPE,
}
pub type StaticEventGroup_t = xSTATIC_EVENT_GROUP;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xSTATIC_TIMER {
pub pvDummy1: *mut ::std::os::raw::c_void,
pub xDummy2: StaticListItem_t,
pub xDummy3: TickType_t,
pub uxDummy4: UBaseType_t,
pub pvDummy5: [*mut ::std::os::raw::c_void; 2usize],
}
pub type StaticTimer_t = xSTATIC_TIMER;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xLIST_ITEM {
pub xItemValue: TickType_t,
pub pxNext: *mut xLIST_ITEM,
pub pxPrevious: *mut xLIST_ITEM,
pub pvOwner: *mut ::std::os::raw::c_void,
pub pvContainer: *mut ::std::os::raw::c_void,
}
pub type ListItem_t = xLIST_ITEM;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xMINI_LIST_ITEM {
pub xItemValue: TickType_t,
pub pxNext: *mut xLIST_ITEM,
pub pxPrevious: *mut xLIST_ITEM,
}
pub type MiniListItem_t = xMINI_LIST_ITEM;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xLIST {
pub uxNumberOfItems: UBaseType_t,
pub pxIndex: *mut ListItem_t,
pub xListEnd: MiniListItem_t,
}
pub type List_t = xLIST;
extern "C" {
pub fn vListInitialise(pxList: *mut List_t);
}
extern "C" {
pub fn vListInitialiseItem(pxItem: *mut ListItem_t);
}
extern "C" {
pub fn vListInsert(pxList: *mut List_t, pxNewListItem: *mut ListItem_t);
}
extern "C" {
pub fn vListInsertEnd(pxList: *mut List_t, pxNewListItem: *mut ListItem_t);
}
extern "C" {
pub fn uxListRemove(pxItemToRemove: *mut ListItem_t) -> UBaseType_t;
}
#[doc = " task. h"]
#[doc = ""]
#[doc = " Type by which tasks are referenced. For example, a call to xTaskCreate"]
#[doc = " returns (via a pointer parameter) an TaskHandle_t variable that can then"]
#[doc = " be used as a parameter to vTaskDelete to delete the task."]
#[doc = ""]
#[doc = " \\ingroup Tasks"]
pub type TaskHandle_t = *mut ::std::os::raw::c_void;
#[doc = " Defines the prototype to which the application task hook function must"]
#[doc = " conform."]
pub type TaskHookFunction_t =
::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void) -> BaseType_t>;
#[doc = "< A task is querying the state of itself, so must be running."]
pub const eTaskState_eRunning: eTaskState = 0;
#[doc = "< The task being queried is in a read or pending ready list."]
pub const eTaskState_eReady: eTaskState = 1;
#[doc = "< The task being queried is in the Blocked state."]
pub const eTaskState_eBlocked: eTaskState = 2;
#[doc = "< The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out."]
pub const eTaskState_eSuspended: eTaskState = 3;
#[doc = "< The task being queried has been deleted, but its TCB has not yet been freed."]
pub const eTaskState_eDeleted: eTaskState = 4;
#[doc = " Task states returned by eTaskGetState."]
pub type eTaskState = u32;
#[doc = "< Notify the task without updating its notify value."]
pub const eNotifyAction_eNoAction: eNotifyAction = 0;
#[doc = "< Set bits in the task's notification value."]
pub const eNotifyAction_eSetBits: eNotifyAction = 1;
#[doc = "< Increment the task's notification value."]
pub const eNotifyAction_eIncrement: eNotifyAction = 2;
#[doc = "< Set the task's notification value to a specific value even if the previous value has not yet been read by the task."]
pub const eNotifyAction_eSetValueWithOverwrite: eNotifyAction = 3;
#[doc = "< Set the task's notification value if the previous value has been read by the task."]
pub const eNotifyAction_eSetValueWithoutOverwrite: eNotifyAction = 4;
#[doc = " Actions that can be performed when vTaskNotify() is called."]
pub type eNotifyAction = u32;
#[doc = " @cond */"]
#[doc = " Used internally only."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xTIME_OUT {
pub xOverflowCount: BaseType_t,
pub xTimeOnEntering: TickType_t,
}
pub type TimeOut_t = xTIME_OUT;
#[doc = " Defines the memory ranges allocated to the task when an MPU is used."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xMEMORY_REGION {
pub pvBaseAddress: *mut ::std::os::raw::c_void,
pub ulLengthInBytes: u32,
pub ulParameters: u32,
}
pub type MemoryRegion_t = xMEMORY_REGION;
#[doc = " Parameters required to create an MPU protected task."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xTASK_PARAMETERS {
pub pvTaskCode: TaskFunction_t,
pub pcName: *const ::std::os::raw::c_char,
pub usStackDepth: u32,
pub pvParameters: *mut ::std::os::raw::c_void,
pub uxPriority: UBaseType_t,
pub puxStackBuffer: *mut StackType_t,
pub xRegions: [MemoryRegion_t; 1usize],
}
pub type TaskParameters_t = xTASK_PARAMETERS;
#[doc = " Used with the uxTaskGetSystemState() function to return the state of each task in the system."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xTASK_STATUS {
#[doc = "< The handle of the task to which the rest of the information in the structure relates."]
pub xHandle: TaskHandle_t,
#[doc = "< A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated!"]
pub pcTaskName: *const ::std::os::raw::c_char,
#[doc = "< A number unique to the task."]
pub xTaskNumber: UBaseType_t,
#[doc = "< The state in which the task existed when the structure was populated."]
pub eCurrentState: eTaskState,
#[doc = "< The priority at which the task was running (may be inherited) when the structure was populated."]
pub uxCurrentPriority: UBaseType_t,
#[doc = "< The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h."]
pub uxBasePriority: UBaseType_t,
#[doc = "< The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h."]
pub ulRunTimeCounter: u32,
#[doc = "< Points to the lowest address of the task's stack area."]
pub pxStackBase: *mut StackType_t,
#[doc = "< The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack."]
pub usStackHighWaterMark: u32,
}
pub type TaskStatus_t = xTASK_STATUS;
#[doc = " Used with the uxTaskGetSnapshotAll() function to save memory snapshot of each task in the system."]
#[doc = " We need this struct because TCB_t is defined (hidden) in tasks.c."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct xTASK_SNAPSHOT {
#[doc = "< Address of task control block."]
pub pxTCB: *mut ::std::os::raw::c_void,
#[doc = "< Points to the location of the last item placed on the tasks stack."]
pub pxTopOfStack: *mut StackType_t,
#[doc = "< Points to the end of the stack. pxTopOfStack < pxEndOfStack, stack grows hi2lo"]
#[doc = "pxTopOfStack > pxEndOfStack, stack grows lo2hi"]
pub pxEndOfStack: *mut StackType_t,
}
pub type TaskSnapshot_t = xTASK_SNAPSHOT;
#[doc = "< A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode."]
pub const eSleepModeStatus_eAbortSleep: eSleepModeStatus = 0;
#[doc = "< Enter a sleep mode that will not last any longer than the expected idle time."]
pub const eSleepModeStatus_eStandardSleep: eSleepModeStatus = 1;
#[doc = "< No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt."]
pub const eSleepModeStatus_eNoTasksWaitingTimeout: eSleepModeStatus = 2;
#[doc = " Possible return values for eTaskConfirmSleepModeStatus()."]
pub type eSleepModeStatus = u32;
extern "C" {
pub fn xTaskCreatePinnedToCore(
pvTaskCode: TaskFunction_t,
pcName: *const ::std::os::raw::c_char,
usStackDepth: u32,
pvParameters: *mut ::std::os::raw::c_void,
uxPriority: UBaseType_t,
pvCreatedTask: *mut TaskHandle_t,
xCoreID: BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xTaskCreateRestricted(
pxTaskDefinition: *const TaskParameters_t,
pxCreatedTask: *mut TaskHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Memory regions are assigned to a restricted task when the task is created by"]
#[doc = " a call to xTaskCreateRestricted(). These regions can be redefined using"]
#[doc = " vTaskAllocateMPURegions()."]
#[doc = ""]
#[doc = " @param xTask The handle of the task being updated."]
#[doc = ""]
#[doc = " @param xRegions A pointer to an MemoryRegion_t structure that contains the"]
#[doc = " new memory region definitions."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = ""]
#[doc = " @code{c}"]
#[doc = " // Define an array of MemoryRegion_t structures that configures an MPU region"]
#[doc = " // allowing read/write access for 1024 bytes starting at the beginning of the"]
#[doc = " // ucOneKByte array. The other two of the maximum 3 definable regions are"]
#[doc = " // unused so set to zero."]
#[doc = " static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] ="]
#[doc = " {"]
#[doc = " \t// Base address\t\tLength\t\tParameters"]
#[doc = " \t{ ucOneKByte,\t\t1024,\t\tportMPU_REGION_READ_WRITE },"]
#[doc = " \t{ 0,\t\t\t\t0,\t\t\t0 },"]
#[doc = " \t{ 0,\t\t\t\t0,\t\t\t0 }"]
#[doc = " };"]
#[doc = ""]
#[doc = " void vATask( void *pvParameters )"]
#[doc = " {"]
#[doc = " \t// This task was created such that it has access to certain regions of"]
#[doc = " \t// memory as defined by the MPU configuration. At some point it is"]
#[doc = " \t// desired that these MPU regions are replaced with that defined in the"]
#[doc = " \t// xAltRegions const struct above. Use a call to vTaskAllocateMPURegions()"]
#[doc = " \t// for this purpose. NULL is used as the task handle to indicate that this"]
#[doc = " \t// function should modify the MPU regions of the calling task."]
#[doc = " \tvTaskAllocateMPURegions( NULL, xAltRegions );"]
#[doc = ""]
#[doc = " \t// Now the task can continue its function, but from this point on can only"]
#[doc = " \t// access its stack and the ucOneKByte array (unless any other statically"]
#[doc = " \t// defined or shared regions have been declared elsewhere)."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup Tasks"]
pub fn vTaskAllocateMPURegions(xTask: TaskHandle_t, pxRegions: *const MemoryRegion_t);
}
extern "C" {
#[doc = " Remove a task from the RTOS real time kernel's management."]
#[doc = ""]
#[doc = " The task being deleted will be removed from all ready, blocked, suspended"]
#[doc = " and event lists."]
#[doc = ""]
#[doc = " INCLUDE_vTaskDelete must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " @note The idle task is responsible for freeing the kernel allocated"]
#[doc = " memory from tasks that have been deleted. It is therefore important that"]
#[doc = " the idle task is not starved of microcontroller processing time if your"]
#[doc = " application makes any calls to vTaskDelete (). Memory allocated by the"]
#[doc = " task code is not automatically freed, and should be freed before the task"]
#[doc = " is deleted."]
#[doc = ""]
#[doc = " See the demo application file death.c for sample code that utilises"]
#[doc = " vTaskDelete ()."]
#[doc = ""]
#[doc = " @param xTaskToDelete The handle of the task to be deleted. Passing NULL will"]
#[doc = " cause the calling task to be deleted."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vOtherFunction( void )"]
#[doc = " {"]
#[doc = " TaskHandle_t xHandle;"]
#[doc = ""]
#[doc = " \t // Create the task, storing the handle."]
#[doc = " \t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );"]
#[doc = ""]
#[doc = " \t // Use the handle to delete the task."]
#[doc = " \t vTaskDelete( xHandle );"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup Tasks"]
pub fn vTaskDelete(xTaskToDelete: TaskHandle_t);
}
extern "C" {
#[doc = " Delay a task for a given number of ticks."]
#[doc = ""]
#[doc = " The actual time that the task remains blocked depends on the tick rate."]
#[doc = " The constant portTICK_PERIOD_MS can be used to calculate real time from"]
#[doc = " the tick rate - with the resolution of one tick period."]
#[doc = ""]
#[doc = " INCLUDE_vTaskDelay must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " vTaskDelay() specifies a time at which the task wishes to unblock relative to"]
#[doc = " the time at which vTaskDelay() is called. For example, specifying a block"]
#[doc = " period of 100 ticks will cause the task to unblock 100 ticks after"]
#[doc = " vTaskDelay() is called. vTaskDelay() does not therefore provide a good method"]
#[doc = " of controlling the frequency of a periodic task as the path taken through the"]
#[doc = " code, as well as other task and interrupt activity, will effect the frequency"]
#[doc = " at which vTaskDelay() gets called and therefore the time at which the task"]
#[doc = " next executes. See vTaskDelayUntil() for an alternative API function designed"]
#[doc = " to facilitate fixed frequency execution. It does this by specifying an"]
#[doc = " absolute time (rather than a relative time) at which the calling task should"]
#[doc = " unblock."]
#[doc = ""]
#[doc = " @param xTicksToDelay The amount of time, in tick periods, that"]
#[doc = " the calling task should block."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vTaskFunction( void * pvParameters )"]
#[doc = " {"]
#[doc = " // Block for 500ms."]
#[doc = " const TickType_t xDelay = 500 / portTICK_PERIOD_MS;"]
#[doc = ""]
#[doc = " \t for( ;; )"]
#[doc = " \t {"]
#[doc = " \t\t // Simply toggle the LED every 500ms, blocking between each toggle."]
#[doc = " \t\t vToggleLED();"]
#[doc = " \t\t vTaskDelay( xDelay );"]
#[doc = " \t }"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn vTaskDelay(xTicksToDelay: TickType_t);
}
extern "C" {
#[doc = " Delay a task until a specified time."]
#[doc = ""]
#[doc = " INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " This function can be used by periodic tasks to ensure a constant execution frequency."]
#[doc = ""]
#[doc = " This function differs from vTaskDelay () in one important aspect: vTaskDelay () will"]
#[doc = " cause a task to block for the specified number of ticks from the time vTaskDelay () is"]
#[doc = " called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed"]
#[doc = " execution frequency as the time between a task starting to execute and that task"]
#[doc = " calling vTaskDelay () may not be fixed [the task may take a different path though the"]
#[doc = " code between calls, or may get interrupted or preempted a different number of times"]
#[doc = " each time it executes]."]
#[doc = ""]
#[doc = " Whereas vTaskDelay () specifies a wake time relative to the time at which the function"]
#[doc = " is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to"]
#[doc = " unblock."]
#[doc = ""]
#[doc = " The constant portTICK_PERIOD_MS can be used to calculate real time from the tick"]
#[doc = " rate - with the resolution of one tick period."]
#[doc = ""]
#[doc = " @param pxPreviousWakeTime Pointer to a variable that holds the time at which the"]
#[doc = " task was last unblocked. The variable must be initialised with the current time"]
#[doc = " prior to its first use (see the example below). Following this the variable is"]
#[doc = " automatically updated within vTaskDelayUntil ()."]
#[doc = ""]
#[doc = " @param xTimeIncrement The cycle time period. The task will be unblocked at"]
#[doc = " time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the"]
#[doc = " same xTimeIncrement parameter value will cause the task to execute with"]
#[doc = " a fixed interface period."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " // Perform an action every 10 ticks."]
#[doc = " void vTaskFunction( void * pvParameters )"]
#[doc = " {"]
#[doc = " TickType_t xLastWakeTime;"]
#[doc = " const TickType_t xFrequency = 10;"]
#[doc = ""]
#[doc = " \t // Initialise the xLastWakeTime variable with the current time."]
#[doc = " \t xLastWakeTime = xTaskGetTickCount ();"]
#[doc = " \t for( ;; )"]
#[doc = " \t {"]
#[doc = " \t\t // Wait for the next cycle."]
#[doc = " \t\t vTaskDelayUntil( &xLastWakeTime, xFrequency );"]
#[doc = ""]
#[doc = " \t\t // Perform action here."]
#[doc = " \t }"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn vTaskDelayUntil(pxPreviousWakeTime: *mut TickType_t, xTimeIncrement: TickType_t);
}
extern "C" {
#[doc = " Obtain the priority of any task."]
#[doc = ""]
#[doc = " INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " @param xTask Handle of the task to be queried. Passing a NULL"]
#[doc = " handle results in the priority of the calling task being returned."]
#[doc = ""]
#[doc = " @return The priority of xTask."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " TaskHandle_t xHandle;"]
#[doc = ""]
#[doc = " // Create a task, storing the handle."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Use the handle to obtain the priority of the created task."]
#[doc = " // It was created with tskIDLE_PRIORITY, but may have changed"]
#[doc = " // it itself."]
#[doc = " if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )"]
#[doc = " {"]
#[doc = " // The task has changed it's priority."]
#[doc = " }"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Is our priority higher than the created task?"]
#[doc = " if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )"]
#[doc = " {"]
#[doc = " // Our priority (obtained using NULL handle) is higher."]
#[doc = " }"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn uxTaskPriorityGet(xTask: TaskHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " A version of uxTaskPriorityGet() that can be used from an ISR."]
#[doc = ""]
#[doc = " @param xTask Handle of the task to be queried. Passing a NULL"]
#[doc = " handle results in the priority of the calling task being returned."]
#[doc = ""]
#[doc = " @return The priority of xTask."]
#[doc = ""]
pub fn uxTaskPriorityGetFromISR(xTask: TaskHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " Obtain the state of any task."]
#[doc = ""]
#[doc = " States are encoded by the eTaskState enumerated type."]
#[doc = ""]
#[doc = " INCLUDE_eTaskGetState must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " @param xTask Handle of the task to be queried."]
#[doc = ""]
#[doc = " @return The state of xTask at the time the function was called. Note the"]
#[doc = " state of the task might change between the function being called, and the"]
#[doc = " functions return value being tested by the calling task."]
pub fn eTaskGetState(xTask: TaskHandle_t) -> eTaskState;
}
extern "C" {
#[doc = " Set the priority of any task."]
#[doc = ""]
#[doc = " INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " A context switch will occur before the function returns if the priority"]
#[doc = " being set is higher than the currently executing task."]
#[doc = ""]
#[doc = " @param xTask Handle to the task for which the priority is being set."]
#[doc = " Passing a NULL handle results in the priority of the calling task being set."]
#[doc = ""]
#[doc = " @param uxNewPriority The priority to which the task will be set."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " TaskHandle_t xHandle;"]
#[doc = ""]
#[doc = " // Create a task, storing the handle."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Use the handle to raise the priority of the created task."]
#[doc = " vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Use a NULL handle to raise our priority to the same value."]
#[doc = " vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn vTaskPrioritySet(xTask: TaskHandle_t, uxNewPriority: UBaseType_t);
}
extern "C" {
#[doc = " Suspend a task."]
#[doc = ""]
#[doc = " INCLUDE_vTaskSuspend must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " When suspended, a task will never get any microcontroller processing time,"]
#[doc = " no matter what its priority."]
#[doc = ""]
#[doc = " Calls to vTaskSuspend are not accumulative -"]
#[doc = " i.e. calling vTaskSuspend () twice on the same task still only requires one"]
#[doc = " call to vTaskResume () to ready the suspended task."]
#[doc = ""]
#[doc = " @param xTaskToSuspend Handle to the task being suspended. Passing a NULL"]
#[doc = " handle will cause the calling task to be suspended."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " TaskHandle_t xHandle;"]
#[doc = ""]
#[doc = " // Create a task, storing the handle."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Use the handle to suspend the created task."]
#[doc = " vTaskSuspend( xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // The created task will not run during this period, unless"]
#[doc = " // another task calls vTaskResume( xHandle )."]
#[doc = ""]
#[doc = " //..."]
#[doc = ""]
#[doc = ""]
#[doc = " // Suspend ourselves."]
#[doc = " vTaskSuspend( NULL );"]
#[doc = ""]
#[doc = " // We cannot get here unless another task calls vTaskResume"]
#[doc = " // with our handle as the parameter."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn vTaskSuspend(xTaskToSuspend: TaskHandle_t);
}
extern "C" {
#[doc = " Resumes a suspended task."]
#[doc = ""]
#[doc = " INCLUDE_vTaskSuspend must be defined as 1 for this function to be available."]
#[doc = " See the configuration section for more information."]
#[doc = ""]
#[doc = " A task that has been suspended by one or more calls to vTaskSuspend ()"]
#[doc = " will be made available for running again by a single call to"]
#[doc = " vTaskResume ()."]
#[doc = ""]
#[doc = " @param xTaskToResume Handle to the task being readied."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " TaskHandle_t xHandle;"]
#[doc = ""]
#[doc = " // Create a task, storing the handle."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // Use the handle to suspend the created task."]
#[doc = " vTaskSuspend( xHandle );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // The created task will not run during this period, unless"]
#[doc = " // another task calls vTaskResume( xHandle )."]
#[doc = ""]
#[doc = " //..."]
#[doc = ""]
#[doc = ""]
#[doc = " // Resume the suspended task ourselves."]
#[doc = " vTaskResume( xHandle );"]
#[doc = ""]
#[doc = " // The created task will once again get microcontroller processing"]
#[doc = " // time in accordance with its priority within the system."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup TaskCtrl"]
pub fn vTaskResume(xTaskToResume: TaskHandle_t);
}
extern "C" {
#[doc = " An implementation of vTaskResume() that can be called from within an ISR."]
#[doc = ""]
#[doc = " INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be"]
#[doc = " available. See the configuration section for more information."]
#[doc = ""]
#[doc = " A task that has been suspended by one or more calls to vTaskSuspend ()"]
#[doc = " will be made available for running again by a single call to"]
#[doc = " xTaskResumeFromISR ()."]
#[doc = ""]
#[doc = " xTaskResumeFromISR() should not be used to synchronise a task with an"]
#[doc = " interrupt if there is a chance that the interrupt could arrive prior to the"]
#[doc = " task being suspended - as this can lead to interrupts being missed. Use of a"]
#[doc = " semaphore as a synchronisation mechanism would avoid this eventuality."]
#[doc = ""]
#[doc = " @param xTaskToResume Handle to the task being readied."]
#[doc = ""]
#[doc = " @return pdTRUE if resuming the task should result in a context switch,"]
#[doc = " otherwise pdFALSE. This is used by the ISR to determine if a context switch"]
#[doc = " may be required following the ISR."]
#[doc = ""]
#[doc = " \\ingroup TaskCtrl"]
pub fn xTaskResumeFromISR(xTaskToResume: TaskHandle_t) -> BaseType_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " Starts the real time kernel tick processing."]
#[doc = ""]
#[doc = " After calling the kernel has control over which tasks are executed and when."]
#[doc = ""]
#[doc = " See the demo application file main.c for an example of creating"]
#[doc = " tasks and starting the kernel."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " // Create at least one task before starting the kernel."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );"]
#[doc = ""]
#[doc = " // Start the real time kernel with preemption."]
#[doc = " vTaskStartScheduler ();"]
#[doc = ""]
#[doc = " // Will not get here unless a task calls vTaskEndScheduler ()"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = ""]
#[doc = " \\ingroup SchedulerControl"]
pub fn vTaskStartScheduler();
}
extern "C" {
#[doc = " Stops the real time kernel tick."]
#[doc = ""]
#[doc = " @note At the time of writing only the x86 real mode port, which runs on a PC"]
#[doc = " in place of DOS, implements this function."]
#[doc = ""]
#[doc = " All created tasks will be automatically deleted and multitasking"]
#[doc = " (either preemptive or cooperative) will stop."]
#[doc = " Execution then resumes from the point where vTaskStartScheduler ()"]
#[doc = " was called, as if vTaskStartScheduler () had just returned."]
#[doc = ""]
#[doc = " See the demo application file main. c in the demo/PC directory for an"]
#[doc = " example that uses vTaskEndScheduler ()."]
#[doc = ""]
#[doc = " vTaskEndScheduler () requires an exit function to be defined within the"]
#[doc = " portable layer (see vPortEndScheduler () in port. c for the PC port). This"]
#[doc = " performs hardware specific operations such as stopping the kernel tick."]
#[doc = ""]
#[doc = " vTaskEndScheduler () will cause all of the resources allocated by the"]
#[doc = " kernel to be freed - but will not free resources allocated by application"]
#[doc = " tasks."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vTaskCode( void * pvParameters )"]
#[doc = " {"]
#[doc = " for( ;; )"]
#[doc = " {"]
#[doc = " // Task code goes here."]
#[doc = ""]
#[doc = " // At some point we want to end the real time kernel processing"]
#[doc = " // so call ..."]
#[doc = " vTaskEndScheduler ();"]
#[doc = " }"]
#[doc = " }"]
#[doc = ""]
#[doc = " void vAFunction( void )"]
#[doc = " {"]
#[doc = " // Create at least one task before starting the kernel."]
#[doc = " xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );"]
#[doc = ""]
#[doc = " // Start the real time kernel with preemption."]
#[doc = " vTaskStartScheduler ();"]
#[doc = ""]
#[doc = " // Will only get here when the vTaskCode () task has called"]
#[doc = " // vTaskEndScheduler (). When we get here we are back to single task"]
#[doc = " // execution."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup SchedulerControl"]
pub fn vTaskEndScheduler();
}
extern "C" {
#[doc = " Suspends the scheduler without disabling interrupts."]
#[doc = ""]
#[doc = " Context switches will not occur while the scheduler is suspended."]
#[doc = ""]
#[doc = " After calling vTaskSuspendAll () the calling task will continue to execute"]
#[doc = " without risk of being swapped out until a call to xTaskResumeAll () has been"]
#[doc = " made."]
#[doc = ""]
#[doc = " API functions that have the potential to cause a context switch (for example,"]
#[doc = " vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler"]
#[doc = " is suspended."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vTask1( void * pvParameters )"]
#[doc = " {"]
#[doc = " for( ;; )"]
#[doc = " {"]
#[doc = " // Task code goes here."]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // At some point the task wants to perform a long operation during"]
#[doc = " // which it does not want to get swapped out. It cannot use"]
#[doc = " // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the"]
#[doc = " // operation may cause interrupts to be missed - including the"]
#[doc = " // ticks."]
#[doc = ""]
#[doc = " // Prevent the real time kernel swapping out the task."]
#[doc = " vTaskSuspendAll ();"]
#[doc = ""]
#[doc = " // Perform the operation here. There is no need to use critical"]
#[doc = " // sections as we have all the microcontroller processing time."]
#[doc = " // During this time interrupts will still operate and the kernel"]
#[doc = " // tick count will be maintained."]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // The operation is complete. Restart the kernel."]
#[doc = " xTaskResumeAll ();"]
#[doc = " }"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup SchedulerControl"]
pub fn vTaskSuspendAll();
}
extern "C" {
#[doc = " Resumes scheduler activity after it was suspended by a call to"]
#[doc = " vTaskSuspendAll()."]
#[doc = ""]
#[doc = " xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks"]
#[doc = " that were previously suspended by a call to vTaskSuspend()."]
#[doc = ""]
#[doc = " @return If resuming the scheduler caused a context switch then pdTRUE is"]
#[doc = "\t\t returned, otherwise pdFALSE is returned."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " void vTask1( void * pvParameters )"]
#[doc = " {"]
#[doc = " for( ;; )"]
#[doc = " {"]
#[doc = " // Task code goes here."]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // At some point the task wants to perform a long operation during"]
#[doc = " // which it does not want to get swapped out. It cannot use"]
#[doc = " // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the"]
#[doc = " // operation may cause interrupts to be missed - including the"]
#[doc = " // ticks."]
#[doc = ""]
#[doc = " // Prevent the real time kernel swapping out the task."]
#[doc = " vTaskSuspendAll ();"]
#[doc = ""]
#[doc = " // Perform the operation here. There is no need to use critical"]
#[doc = " // sections as we have all the microcontroller processing time."]
#[doc = " // During this time interrupts will still operate and the real"]
#[doc = " // time kernel tick count will be maintained."]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " // The operation is complete. Restart the kernel. We want to force"]
#[doc = " // a context switch - but there is no point if resuming the scheduler"]
#[doc = " // caused a context switch already."]
#[doc = " if( !xTaskResumeAll () )"]
#[doc = " {"]
#[doc = " taskYIELD ();"]
#[doc = " }"]
#[doc = " }"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup SchedulerControl"]
pub fn xTaskResumeAll() -> BaseType_t;
}
extern "C" {
#[doc = " Get tick count"]
#[doc = ""]
#[doc = " @return The count of ticks since vTaskStartScheduler was called."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn xTaskGetTickCount() -> TickType_t;
}
extern "C" {
#[doc = " Get tick count from ISR"]
#[doc = ""]
#[doc = " @return The count of ticks since vTaskStartScheduler was called."]
#[doc = ""]
#[doc = " This is a version of xTaskGetTickCount() that is safe to be called from an"]
#[doc = " ISR - provided that TickType_t is the natural word size of the"]
#[doc = " microcontroller being used or interrupt nesting is either not supported or"]
#[doc = " not being used."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn xTaskGetTickCountFromISR() -> TickType_t;
}
extern "C" {
#[doc = " Get current number of tasks"]
#[doc = ""]
#[doc = " @return The number of tasks that the real time kernel is currently managing."]
#[doc = " This includes all ready, blocked and suspended tasks. A task that"]
#[doc = " has been deleted but not yet freed by the idle task will also be"]
#[doc = " included in the count."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn uxTaskGetNumberOfTasks() -> UBaseType_t;
}
extern "C" {
#[doc = " Get task name"]
#[doc = ""]
#[doc = " @return The text (human readable) name of the task referenced by the handle"]
#[doc = " xTaskToQuery. A task can query its own name by either passing in its own"]
#[doc = " handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be"]
#[doc = " set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn pcTaskGetTaskName(xTaskToQuery: TaskHandle_t) -> *mut ::std::os::raw::c_char;
}
extern "C" {
#[doc = " Returns the high water mark of the stack associated with xTask."]
#[doc = ""]
#[doc = " INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for"]
#[doc = " this function to be available."]
#[doc = ""]
#[doc = " High water mark is the minimum free stack space there has been (in bytes"]
#[doc = " rather than words as found in vanilla FreeRTOS) since the task started."]
#[doc = " The smaller the returned number the closer the task has come to overflowing its stack."]
#[doc = ""]
#[doc = " @param xTask Handle of the task associated with the stack to be checked."]
#[doc = " Set xTask to NULL to check the stack of the calling task."]
#[doc = ""]
#[doc = " @return The smallest amount of free stack space there has been (in bytes"]
#[doc = " rather than words as found in vanilla FreeRTOS) since the task referenced by"]
#[doc = " xTask was created."]
pub fn uxTaskGetStackHighWaterMark(xTask: TaskHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " Returns the start of the stack associated with xTask."]
#[doc = ""]
#[doc = " INCLUDE_pxTaskGetStackStart must be set to 1 in FreeRTOSConfig.h for"]
#[doc = " this function to be available."]
#[doc = ""]
#[doc = " Returns the highest stack memory address on architectures where the stack grows down"]
#[doc = " from high memory, and the lowest memory address on architectures where the"]
#[doc = " stack grows up from low memory."]
#[doc = ""]
#[doc = " @param xTask Handle of the task associated with the stack returned."]
#[doc = " Set xTask to NULL to return the stack of the calling task."]
#[doc = ""]
#[doc = " @return A pointer to the start of the stack."]
pub fn pxTaskGetStackStart(xTask: TaskHandle_t) -> *mut u8;
}
extern "C" {
#[doc = " Set local storage pointer specific to the given task."]
#[doc = ""]
#[doc = " Each task contains an array of pointers that is dimensioned by the"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h."]
#[doc = " The kernel does not use the pointers itself, so the application writer"]
#[doc = " can use the pointers for any purpose they wish."]
#[doc = ""]
#[doc = " @param xTaskToSet Task to set thread local storage pointer for"]
#[doc = " @param xIndex The index of the pointer to set, from 0 to"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1."]
#[doc = " @param pvValue Pointer value to set."]
pub fn vTaskSetThreadLocalStoragePointer(
xTaskToSet: TaskHandle_t,
xIndex: BaseType_t,
pvValue: *mut ::std::os::raw::c_void,
);
}
extern "C" {
#[doc = " Get local storage pointer specific to the given task."]
#[doc = ""]
#[doc = " Each task contains an array of pointers that is dimensioned by the"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h."]
#[doc = " The kernel does not use the pointers itself, so the application writer"]
#[doc = " can use the pointers for any purpose they wish."]
#[doc = ""]
#[doc = " @param xTaskToQuery Task to get thread local storage pointer for"]
#[doc = " @param xIndex The index of the pointer to get, from 0 to"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1."]
#[doc = " @return Pointer value"]
pub fn pvTaskGetThreadLocalStoragePointer(
xTaskToQuery: TaskHandle_t,
xIndex: BaseType_t,
) -> *mut ::std::os::raw::c_void;
}
#[doc = " Prototype of local storage pointer deletion callback."]
pub type TlsDeleteCallbackFunction_t = ::core::option::Option<
unsafe extern "C" fn(arg1: ::std::os::raw::c_int, arg2: *mut ::std::os::raw::c_void),
>;
extern "C" {
#[doc = " Set local storage pointer and deletion callback."]
#[doc = ""]
#[doc = " Each task contains an array of pointers that is dimensioned by the"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h."]
#[doc = " The kernel does not use the pointers itself, so the application writer"]
#[doc = " can use the pointers for any purpose they wish."]
#[doc = ""]
#[doc = " Local storage pointers set for a task can reference dynamically"]
#[doc = " allocated resources. This function is similar to"]
#[doc = " vTaskSetThreadLocalStoragePointer, but provides a way to release"]
#[doc = " these resources when the task gets deleted. For each pointer,"]
#[doc = " a callback function can be set. This function will be called"]
#[doc = " when task is deleted, with the local storage pointer index"]
#[doc = " and value as arguments."]
#[doc = ""]
#[doc = " @param xTaskToSet Task to set thread local storage pointer for"]
#[doc = " @param xIndex The index of the pointer to set, from 0 to"]
#[doc = " configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1."]
#[doc = " @param pvValue Pointer value to set."]
#[doc = " @param pvDelCallback Function to call to dispose of the local"]
#[doc = " storage pointer when the task is deleted."]
pub fn vTaskSetThreadLocalStoragePointerAndDelCallback(
xTaskToSet: TaskHandle_t,
xIndex: BaseType_t,
pvValue: *mut ::std::os::raw::c_void,
pvDelCallback: TlsDeleteCallbackFunction_t,
);
}
extern "C" {
#[doc = " Calls the hook function associated with xTask. Passing xTask as NULL has"]
#[doc = " the effect of calling the Running tasks (the calling task) hook function."]
#[doc = ""]
#[doc = " @param xTask Handle of the task to call the hook for."]
#[doc = " @param pvParameter Parameter passed to the hook function for the task to interpret as it"]
#[doc = " wants. The return value is the value returned by the task hook function"]
#[doc = " registered by the user."]
pub fn xTaskCallApplicationTaskHook(
xTask: TaskHandle_t,
pvParameter: *mut ::std::os::raw::c_void,
) -> BaseType_t;
}
extern "C" {
#[doc = " Get the handle of idle task for the current CPU."]
#[doc = ""]
#[doc = " xTaskGetIdleTaskHandle() is only available if"]
#[doc = " INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h."]
#[doc = ""]
#[doc = " @return The handle of the idle task. It is not valid to call"]
#[doc = " xTaskGetIdleTaskHandle() before the scheduler has been started."]
pub fn xTaskGetIdleTaskHandle() -> TaskHandle_t;
}
extern "C" {
#[doc = " Get the handle of idle task for the given CPU."]
#[doc = ""]
#[doc = " xTaskGetIdleTaskHandleForCPU() is only available if"]
#[doc = " INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h."]
#[doc = ""]
#[doc = " @param cpuid The CPU to get the handle for"]
#[doc = ""]
#[doc = " @return Idle task handle of a given cpu. It is not valid to call"]
#[doc = " xTaskGetIdleTaskHandleForCPU() before the scheduler has been started."]
pub fn xTaskGetIdleTaskHandleForCPU(cpuid: UBaseType_t) -> TaskHandle_t;
}
extern "C" {
#[doc = " Get the state of tasks in the system."]
#[doc = ""]
#[doc = " configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for"]
#[doc = " uxTaskGetSystemState() to be available."]
#[doc = ""]
#[doc = " uxTaskGetSystemState() populates an TaskStatus_t structure for each task in"]
#[doc = " the system. TaskStatus_t structures contain, among other things, members"]
#[doc = " for the task handle, task name, task priority, task state, and total amount"]
#[doc = " of run time consumed by the task. See the TaskStatus_t structure"]
#[doc = " definition in this file for the full member list."]
#[doc = ""]
#[doc = " @note This function is intended for debugging use only as its use results in"]
#[doc = " the scheduler remaining suspended for an extended period."]
#[doc = ""]
#[doc = " @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures."]
#[doc = " The array must contain at least one TaskStatus_t structure for each task"]
#[doc = " that is under the control of the RTOS. The number of tasks under the control"]
#[doc = " of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function."]
#[doc = ""]
#[doc = " @param uxArraySize The size of the array pointed to by the pxTaskStatusArray"]
#[doc = " parameter. The size is specified as the number of indexes in the array, or"]
#[doc = " the number of TaskStatus_t structures contained in the array, not by the"]
#[doc = " number of bytes in the array."]
#[doc = ""]
#[doc = " @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in"]
#[doc = " FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the"]
#[doc = " total run time (as defined by the run time stats clock, see"]
#[doc = " http://www.freertos.org/rtos-run-time-stats.html) since the target booted."]
#[doc = " pulTotalRunTime can be set to NULL to omit the total run time information."]
#[doc = ""]
#[doc = " @return The number of TaskStatus_t structures that were populated by"]
#[doc = " uxTaskGetSystemState(). This should equal the number returned by the"]
#[doc = " uxTaskGetNumberOfTasks() API function, but will be zero if the value passed"]
#[doc = " in the uxArraySize parameter was too small."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " // This example demonstrates how a human readable table of run time stats"]
#[doc = " // information is generated from raw data provided by uxTaskGetSystemState()."]
#[doc = " // The human readable table is written to pcWriteBuffer"]
#[doc = " void vTaskGetRunTimeStats( char *pcWriteBuffer )"]
#[doc = " {"]
#[doc = " TaskStatus_t *pxTaskStatusArray;"]
#[doc = " volatile UBaseType_t uxArraySize, x;"]
#[doc = " uint32_t ulTotalRunTime, ulStatsAsPercentage;"]
#[doc = ""]
#[doc = " // Make sure the write buffer does not contain a string."]
#[doc = " *pcWriteBuffer = 0x00;"]
#[doc = ""]
#[doc = " // Take a snapshot of the number of tasks in case it changes while this"]
#[doc = " // function is executing."]
#[doc = " uxArraySize = uxTaskGetNumberOfTasks();"]
#[doc = ""]
#[doc = " // Allocate a TaskStatus_t structure for each task. An array could be"]
#[doc = " // allocated statically at compile time."]
#[doc = " pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );"]
#[doc = ""]
#[doc = " if( pxTaskStatusArray != NULL )"]
#[doc = " {"]
#[doc = " // Generate raw status information about each task."]
#[doc = " uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );"]
#[doc = ""]
#[doc = " // For percentage calculations."]
#[doc = " ulTotalRunTime /= 100UL;"]
#[doc = ""]
#[doc = " // Avoid divide by zero errors."]
#[doc = " if( ulTotalRunTime > 0 )"]
#[doc = " {"]
#[doc = " // For each populated position in the pxTaskStatusArray array,"]
#[doc = " // format the raw data as human readable ASCII data"]
#[doc = " for( x = 0; x < uxArraySize; x++ )"]
#[doc = " {"]
#[doc = " // What percentage of the total run time has the task used?"]
#[doc = " // This will always be rounded down to the nearest integer."]
#[doc = " // ulTotalRunTimeDiv100 has already been divided by 100."]
#[doc = " ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;"]
#[doc = ""]
#[doc = " if( ulStatsAsPercentage > 0UL )"]
#[doc = " {"]
#[doc = " sprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );"]
#[doc = " }"]
#[doc = " else"]
#[doc = " {"]
#[doc = " // If the percentage is zero here then the task has"]
#[doc = " // consumed less than 1% of the total run time."]
#[doc = " sprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );"]
#[doc = " }"]
#[doc = ""]
#[doc = " pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );"]
#[doc = " }"]
#[doc = " }"]
#[doc = ""]
#[doc = " // The array is no longer needed, free the memory it consumes."]
#[doc = " vPortFree( pxTaskStatusArray );"]
#[doc = " }"]
#[doc = " }"]
#[doc = " @endcode"]
pub fn uxTaskGetSystemState(
pxTaskStatusArray: *mut TaskStatus_t,
uxArraySize: UBaseType_t,
pulTotalRunTime: *mut u32,
) -> UBaseType_t;
}
extern "C" {
#[doc = " List all the current tasks."]
#[doc = ""]
#[doc = " configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must"]
#[doc = " both be defined as 1 for this function to be available. See the"]
#[doc = " configuration section of the FreeRTOS.org website for more information."]
#[doc = ""]
#[doc = " @note This function will disable interrupts for its duration. It is"]
#[doc = " not intended for normal application runtime use but as a debug aid."]
#[doc = ""]
#[doc = " Lists all the current tasks, along with their current state and stack"]
#[doc = " usage high water mark."]
#[doc = ""]
#[doc = " Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or"]
#[doc = " suspended ('S')."]
#[doc = ""]
#[doc = " @note This function is provided for convenience only, and is used by many of the"]
#[doc = " demo applications. Do not consider it to be part of the scheduler."]
#[doc = ""]
#[doc = " vTaskList() calls uxTaskGetSystemState(), then formats part of the"]
#[doc = " uxTaskGetSystemState() output into a human readable table that displays task"]
#[doc = " names, states and stack usage."]
#[doc = ""]
#[doc = " vTaskList() has a dependency on the sprintf() C library function that might"]
#[doc = " bloat the code size, use a lot of stack, and provide different results on"]
#[doc = " different platforms. An alternative, tiny, third party, and limited"]
#[doc = " functionality implementation of sprintf() is provided in many of the"]
#[doc = " FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note"]
#[doc = " printf-stdarg.c does not provide a full snprintf() implementation!)."]
#[doc = ""]
#[doc = " It is recommended that production systems call uxTaskGetSystemState()"]
#[doc = " directly to get access to raw stats data, rather than indirectly through a"]
#[doc = " call to vTaskList()."]
#[doc = ""]
#[doc = " @param pcWriteBuffer A buffer into which the above mentioned details"]
#[doc = " will be written, in ASCII form. This buffer is assumed to be large"]
#[doc = " enough to contain the generated report. Approximately 40 bytes per"]
#[doc = " task should be sufficient."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn vTaskList(pcWriteBuffer: *mut ::std::os::raw::c_char);
}
extern "C" {
#[doc = " Get the state of running tasks as a string"]
#[doc = ""]
#[doc = " configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS"]
#[doc = " must both be defined as 1 for this function to be available. The application"]
#[doc = " must also then provide definitions for"]
#[doc = " portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()"]
#[doc = " to configure a peripheral timer/counter and return the timers current count"]
#[doc = " value respectively. The counter should be at least 10 times the frequency of"]
#[doc = " the tick count."]
#[doc = ""]
#[doc = " @note This function will disable interrupts for its duration. It is"]
#[doc = " not intended for normal application runtime use but as a debug aid."]
#[doc = ""]
#[doc = " Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total"]
#[doc = " accumulated execution time being stored for each task. The resolution"]
#[doc = " of the accumulated time value depends on the frequency of the timer"]
#[doc = " configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro."]
#[doc = " Calling vTaskGetRunTimeStats() writes the total execution time of each"]
#[doc = " task into a buffer, both as an absolute count value and as a percentage"]
#[doc = " of the total system execution time."]
#[doc = ""]
#[doc = " @note This function is provided for convenience only, and is used by many of the"]
#[doc = " demo applications. Do not consider it to be part of the scheduler."]
#[doc = ""]
#[doc = " vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the"]
#[doc = " uxTaskGetSystemState() output into a human readable table that displays the"]
#[doc = " amount of time each task has spent in the Running state in both absolute and"]
#[doc = " percentage terms."]
#[doc = ""]
#[doc = " vTaskGetRunTimeStats() has a dependency on the sprintf() C library function"]
#[doc = " that might bloat the code size, use a lot of stack, and provide different"]
#[doc = " results on different platforms. An alternative, tiny, third party, and"]
#[doc = " limited functionality implementation of sprintf() is provided in many of the"]
#[doc = " FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note"]
#[doc = " printf-stdarg.c does not provide a full snprintf() implementation!)."]
#[doc = ""]
#[doc = " It is recommended that production systems call uxTaskGetSystemState() directly"]
#[doc = " to get access to raw stats data, rather than indirectly through a call to"]
#[doc = " vTaskGetRunTimeStats()."]
#[doc = ""]
#[doc = " @param pcWriteBuffer A buffer into which the execution times will be"]
#[doc = " written, in ASCII form. This buffer is assumed to be large enough to"]
#[doc = " contain the generated report. Approximately 40 bytes per task should"]
#[doc = " be sufficient."]
#[doc = ""]
#[doc = " \\ingroup TaskUtils"]
pub fn vTaskGetRunTimeStats(pcWriteBuffer: *mut ::std::os::raw::c_char);
}
extern "C" {
#[doc = " Send task notification."]
#[doc = ""]
#[doc = " configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this"]
#[doc = " function to be available."]
#[doc = ""]
#[doc = " When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private"]
#[doc = " \"notification value\", which is a 32-bit unsigned integer (uint32_t)."]
#[doc = ""]
#[doc = " Events can be sent to a task using an intermediary object. Examples of such"]
#[doc = " objects are queues, semaphores, mutexes and event groups. Task notifications"]
#[doc = " are a method of sending an event directly to a task without the need for such"]
#[doc = " an intermediary object."]
#[doc = ""]
#[doc = " A notification sent to a task can optionally perform an action, such as"]
#[doc = " update, overwrite or increment the task's notification value. In that way"]
#[doc = " task notifications can be used to send data to a task, or be used as light"]
#[doc = " weight and fast binary or counting semaphores."]
#[doc = ""]
#[doc = " A notification sent to a task will remain pending until it is cleared by the"]
#[doc = " task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was"]
#[doc = " already in the Blocked state to wait for a notification when the notification"]
#[doc = " arrives then the task will automatically be removed from the Blocked state"]
#[doc = " (unblocked) and the notification cleared."]
#[doc = ""]
#[doc = " A task can use xTaskNotifyWait() to [optionally] block to wait for a"]
#[doc = " notification to be pending, or ulTaskNotifyTake() to [optionally] block"]
#[doc = " to wait for its notification value to have a non-zero value. The task does"]
#[doc = " not consume any CPU time while it is in the Blocked state."]
#[doc = ""]
#[doc = " See http://www.FreeRTOS.org/RTOS-task-notifications.html for details."]
#[doc = ""]
#[doc = " @param xTaskToNotify The handle of the task being notified. The handle to a"]
#[doc = " task can be returned from the xTaskCreate() API function used to create the"]
#[doc = " task, and the handle of the currently running task can be obtained by calling"]
#[doc = " xTaskGetCurrentTaskHandle()."]
#[doc = ""]
#[doc = " @param ulValue Data that can be sent with the notification. How the data is"]
#[doc = " used depends on the value of the eAction parameter."]
#[doc = ""]
#[doc = " @param eAction Specifies how the notification updates the task's notification"]
#[doc = " value, if at all. Valid values for eAction are as follows:"]
#[doc = "\t- eSetBits:"]
#[doc = "\t The task's notification value is bitwise ORed with ulValue. xTaskNofify()"]
#[doc = " \t always returns pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eIncrement:"]
#[doc = "\t The task's notification value is incremented. ulValue is not used and"]
#[doc = "\t xTaskNotify() always returns pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eSetValueWithOverwrite:"]
#[doc = "\t The task's notification value is set to the value of ulValue, even if the"]
#[doc = "\t task being notified had not yet processed the previous notification (the"]
#[doc = "\t task already had a notification pending). xTaskNotify() always returns"]
#[doc = "\t pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eSetValueWithoutOverwrite:"]
#[doc = "\t If the task being notified did not already have a notification pending then"]
#[doc = "\t the task's notification value is set to ulValue and xTaskNotify() will"]
#[doc = "\t return pdPASS. If the task being notified already had a notification"]
#[doc = "\t pending then no action is performed and pdFAIL is returned."]
#[doc = ""]
#[doc = "\t- eNoAction:"]
#[doc = "\t The task receives a notification without its notification value being"]
#[doc = "\t\u{a0}\u{a0}updated. ulValue is not used and xTaskNotify() always returns pdPASS in"]
#[doc = "\t this case."]
#[doc = ""]
#[doc = " @return Dependent on the value of eAction. See the description of the"]
#[doc = " eAction parameter."]
#[doc = ""]
#[doc = " \\ingroup TaskNotifications"]
pub fn xTaskNotify(
xTaskToNotify: TaskHandle_t,
ulValue: u32,
eAction: eNotifyAction,
) -> BaseType_t;
}
extern "C" {
#[doc = " Send task notification from an ISR."]
#[doc = ""]
#[doc = " configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this"]
#[doc = " function to be available."]
#[doc = ""]
#[doc = " When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private"]
#[doc = " \"notification value\", which is a 32-bit unsigned integer (uint32_t)."]
#[doc = ""]
#[doc = " A version of xTaskNotify() that can be used from an interrupt service routine"]
#[doc = " (ISR)."]
#[doc = ""]
#[doc = " Events can be sent to a task using an intermediary object. Examples of such"]
#[doc = " objects are queues, semaphores, mutexes and event groups. Task notifications"]
#[doc = " are a method of sending an event directly to a task without the need for such"]
#[doc = " an intermediary object."]
#[doc = ""]
#[doc = " A notification sent to a task can optionally perform an action, such as"]
#[doc = " update, overwrite or increment the task's notification value. In that way"]
#[doc = " task notifications can be used to send data to a task, or be used as light"]
#[doc = " weight and fast binary or counting semaphores."]
#[doc = ""]
#[doc = " A notification sent to a task will remain pending until it is cleared by the"]
#[doc = " task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was"]
#[doc = " already in the Blocked state to wait for a notification when the notification"]
#[doc = " arrives then the task will automatically be removed from the Blocked state"]
#[doc = " (unblocked) and the notification cleared."]
#[doc = ""]
#[doc = " A task can use xTaskNotifyWait() to [optionally] block to wait for a"]
#[doc = " notification to be pending, or ulTaskNotifyTake() to [optionally] block"]
#[doc = " to wait for its notification value to have a non-zero value. The task does"]
#[doc = " not consume any CPU time while it is in the Blocked state."]
#[doc = ""]
#[doc = " See http://www.FreeRTOS.org/RTOS-task-notifications.html for details."]
#[doc = ""]
#[doc = " @param xTaskToNotify The handle of the task being notified. The handle to a"]
#[doc = " task can be returned from the xTaskCreate() API function used to create the"]
#[doc = " task, and the handle of the currently running task can be obtained by calling"]
#[doc = " xTaskGetCurrentTaskHandle()."]
#[doc = ""]
#[doc = " @param ulValue Data that can be sent with the notification. How the data is"]
#[doc = " used depends on the value of the eAction parameter."]
#[doc = ""]
#[doc = " @param eAction Specifies how the notification updates the task's notification"]
#[doc = " value, if at all. Valid values for eAction are as follows:"]
#[doc = "\t- eSetBits:"]
#[doc = "\t The task's notification value is bitwise ORed with ulValue. xTaskNofify()"]
#[doc = " \t always returns pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eIncrement:"]
#[doc = "\t The task's notification value is incremented. ulValue is not used and"]
#[doc = "\t xTaskNotify() always returns pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eSetValueWithOverwrite:"]
#[doc = "\t The task's notification value is set to the value of ulValue, even if the"]
#[doc = "\t task being notified had not yet processed the previous notification (the"]
#[doc = "\t task already had a notification pending). xTaskNotify() always returns"]
#[doc = "\t pdPASS in this case."]
#[doc = ""]
#[doc = "\t- eSetValueWithoutOverwrite:"]
#[doc = "\t If the task being notified did not already have a notification pending then"]
#[doc = "\t the task's notification value is set to ulValue and xTaskNotify() will"]
#[doc = "\t return pdPASS. If the task being notified already had a notification"]
#[doc = "\t pending then no action is performed and pdFAIL is returned."]
#[doc = ""]
#[doc = "\t- eNoAction:"]
#[doc = "\t The task receives a notification without its notification value being"]
#[doc = "\t updated. ulValue is not used and xTaskNotify() always returns pdPASS in"]
#[doc = "\t this case."]
#[doc = ""]
#[doc = " @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set"]
#[doc = " *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the"]
#[doc = " task to which the notification was sent to leave the Blocked state, and the"]
#[doc = " unblocked task has a priority higher than the currently running task. If"]
#[doc = " xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should"]
#[doc = " be requested before the interrupt is exited. How a context switch is"]
#[doc = " requested from an ISR is dependent on the port - see the documentation page"]
#[doc = " for the port in use."]
#[doc = ""]
#[doc = " @return Dependent on the value of eAction. See the description of the"]
#[doc = " eAction parameter."]
#[doc = ""]
#[doc = " \\ingroup TaskNotifications"]
pub fn xTaskNotifyFromISR(
xTaskToNotify: TaskHandle_t,
ulValue: u32,
eAction: eNotifyAction,
pxHigherPriorityTaskWoken: *mut BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Wait for task notification"]
#[doc = ""]
#[doc = " configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this"]
#[doc = " function to be available."]
#[doc = ""]
#[doc = " When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private"]
#[doc = " \"notification value\", which is a 32-bit unsigned integer (uint32_t)."]
#[doc = ""]
#[doc = " Events can be sent to a task using an intermediary object. Examples of such"]
#[doc = " objects are queues, semaphores, mutexes and event groups. Task notifications"]
#[doc = " are a method of sending an event directly to a task without the need for such"]
#[doc = " an intermediary object."]
#[doc = ""]
#[doc = " A notification sent to a task can optionally perform an action, such as"]
#[doc = " update, overwrite or increment the task's notification value. In that way"]
#[doc = " task notifications can be used to send data to a task, or be used as light"]
#[doc = " weight and fast binary or counting semaphores."]
#[doc = ""]
#[doc = " A notification sent to a task will remain pending until it is cleared by the"]
#[doc = " task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was"]
#[doc = " already in the Blocked state to wait for a notification when the notification"]
#[doc = " arrives then the task will automatically be removed from the Blocked state"]
#[doc = " (unblocked) and the notification cleared."]
#[doc = ""]
#[doc = " A task can use xTaskNotifyWait() to [optionally] block to wait for a"]
#[doc = " notification to be pending, or ulTaskNotifyTake() to [optionally] block"]
#[doc = " to wait for its notification value to have a non-zero value. The task does"]
#[doc = " not consume any CPU time while it is in the Blocked state."]
#[doc = ""]
#[doc = " See http://www.FreeRTOS.org/RTOS-task-notifications.html for details."]
#[doc = ""]
#[doc = " @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value"]
#[doc = " will be cleared in the calling task's notification value before the task"]
#[doc = " checks to see if any notifications are pending, and optionally blocks if no"]
#[doc = " notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if"]
#[doc = " limits.h is included) or 0xffffffffUL (if limits.h is not included) will have"]
#[doc = " the effect of resetting the task's notification value to 0. Setting"]
#[doc = " ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged."]
#[doc = ""]
#[doc = " @param ulBitsToClearOnExit If a notification is pending or received before"]
#[doc = " the calling task exits the xTaskNotifyWait() function then the task's"]
#[doc = " notification value (see the xTaskNotify() API function) is passed out using"]
#[doc = " the pulNotificationValue parameter. Then any bits that are set in"]
#[doc = " ulBitsToClearOnExit will be cleared in the task's notification value (note"]
#[doc = " *pulNotificationValue is set before any bits are cleared). Setting"]
#[doc = " ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL"]
#[doc = " (if limits.h is not included) will have the effect of resetting the task's"]
#[doc = " notification value to 0 before the function exits. Setting"]
#[doc = " ulBitsToClearOnExit to 0 will leave the task's notification value unchanged"]
#[doc = " when the function exits (in which case the value passed out in"]
#[doc = " pulNotificationValue will match the task's notification value)."]
#[doc = ""]
#[doc = " @param pulNotificationValue Used to pass the task's notification value out"]
#[doc = " of the function. Note the value passed out will not be effected by the"]
#[doc = " clearing of any bits caused by ulBitsToClearOnExit being non-zero."]
#[doc = ""]
#[doc = " @param xTicksToWait The maximum amount of time that the task should wait in"]
#[doc = " the Blocked state for a notification to be received, should a notification"]
#[doc = " not already be pending when xTaskNotifyWait() was called. The task"]
#[doc = " will not consume any processing time while it is in the Blocked state. This"]
#[doc = " is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be"]
#[doc = " used to convert a time specified in milliseconds to a time specified in"]
#[doc = " ticks."]
#[doc = ""]
#[doc = " @return If a notification was received (including notifications that were"]
#[doc = " already pending when xTaskNotifyWait was called) then pdPASS is"]
#[doc = " returned. Otherwise pdFAIL is returned."]
#[doc = ""]
#[doc = " \\ingroup TaskNotifications"]
pub fn xTaskNotifyWait(
ulBitsToClearOnEntry: u32,
ulBitsToClearOnExit: u32,
pulNotificationValue: *mut u32,
xTicksToWait: TickType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Simplified macro for sending task notification from ISR."]
#[doc = ""]
#[doc = " configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro"]
#[doc = " to be available."]
#[doc = ""]
#[doc = " When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private"]
#[doc = " \"notification value\", which is a 32-bit unsigned integer (uint32_t)."]
#[doc = ""]
#[doc = " A version of xTaskNotifyGive() that can be called from an interrupt service"]
#[doc = " routine (ISR)."]
#[doc = ""]
#[doc = " Events can be sent to a task using an intermediary object. Examples of such"]
#[doc = " objects are queues, semaphores, mutexes and event groups. Task notifications"]
#[doc = " are a method of sending an event directly to a task without the need for such"]
#[doc = " an intermediary object."]
#[doc = ""]
#[doc = " A notification sent to a task can optionally perform an action, such as"]
#[doc = " update, overwrite or increment the task's notification value. In that way"]
#[doc = " task notifications can be used to send data to a task, or be used as light"]
#[doc = " weight and fast binary or counting semaphores."]
#[doc = ""]
#[doc = " vTaskNotifyGiveFromISR() is intended for use when task notifications are"]
#[doc = " used as light weight and faster binary or counting semaphore equivalents."]
#[doc = " Actual FreeRTOS semaphores are given from an ISR using the"]
#[doc = " xSemaphoreGiveFromISR() API function, the equivalent action that instead uses"]
#[doc = " a task notification is vTaskNotifyGiveFromISR()."]
#[doc = ""]
#[doc = " When task notifications are being used as a binary or counting semaphore"]
#[doc = " equivalent then the task being notified should wait for the notification"]
#[doc = " using the ulTaskNotificationTake() API function rather than the"]
#[doc = " xTaskNotifyWait() API function."]
#[doc = ""]
#[doc = " See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details."]
#[doc = ""]
#[doc = " @param xTaskToNotify The handle of the task being notified. The handle to a"]
#[doc = " task can be returned from the xTaskCreate() API function used to create the"]
#[doc = " task, and the handle of the currently running task can be obtained by calling"]
#[doc = " xTaskGetCurrentTaskHandle()."]
#[doc = ""]
#[doc = " @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set"]
#[doc = " *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the"]
#[doc = " task to which the notification was sent to leave the Blocked state, and the"]
#[doc = " unblocked task has a priority higher than the currently running task. If"]
#[doc = " vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch"]
#[doc = " should be requested before the interrupt is exited. How a context switch is"]
#[doc = " requested from an ISR is dependent on the port - see the documentation page"]
#[doc = " for the port in use."]
#[doc = ""]
#[doc = " \\ingroup TaskNotifications"]
pub fn vTaskNotifyGiveFromISR(
xTaskToNotify: TaskHandle_t,
pxHigherPriorityTaskWoken: *mut BaseType_t,
);
}
extern "C" {
#[doc = " Simplified macro for receiving task notification."]
#[doc = ""]
#[doc = " configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this"]
#[doc = " function to be available."]
#[doc = ""]
#[doc = " When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private"]
#[doc = " \"notification value\", which is a 32-bit unsigned integer (uint32_t)."]
#[doc = ""]
#[doc = " Events can be sent to a task using an intermediary object. Examples of such"]
#[doc = " objects are queues, semaphores, mutexes and event groups. Task notifications"]
#[doc = " are a method of sending an event directly to a task without the need for such"]
#[doc = " an intermediary object."]
#[doc = ""]
#[doc = " A notification sent to a task can optionally perform an action, such as"]
#[doc = " update, overwrite or increment the task's notification value. In that way"]
#[doc = " task notifications can be used to send data to a task, or be used as light"]
#[doc = " weight and fast binary or counting semaphores."]
#[doc = ""]
#[doc = " ulTaskNotifyTake() is intended for use when a task notification is used as a"]
#[doc = " faster and lighter weight binary or counting semaphore alternative. Actual"]
#[doc = " FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the"]
#[doc = " equivalent action that instead uses a task notification is"]
#[doc = " ulTaskNotifyTake()."]
#[doc = ""]
#[doc = " When a task is using its notification value as a binary or counting semaphore"]
#[doc = " other tasks should send notifications to it using the xTaskNotifyGive()"]
#[doc = " macro, or xTaskNotify() function with the eAction parameter set to"]
#[doc = " eIncrement."]
#[doc = ""]
#[doc = " ulTaskNotifyTake() can either clear the task's notification value to"]
#[doc = " zero on exit, in which case the notification value acts like a binary"]
#[doc = " semaphore, or decrement the task's notification value on exit, in which case"]
#[doc = " the notification value acts like a counting semaphore."]
#[doc = ""]
#[doc = " A task can use ulTaskNotifyTake() to [optionally] block to wait for a"]
#[doc = " the task's notification value to be non-zero. The task does not consume any"]
#[doc = " CPU time while it is in the Blocked state."]
#[doc = ""]
#[doc = " Where as xTaskNotifyWait() will return when a notification is pending,"]
#[doc = " ulTaskNotifyTake() will return when the task's notification value is"]
#[doc = " not zero."]
#[doc = ""]
#[doc = " See http://www.FreeRTOS.org/RTOS-task-notifications.html for details."]
#[doc = ""]
#[doc = " @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's"]
#[doc = " notification value is decremented when the function exits. In this way the"]
#[doc = " notification value acts like a counting semaphore. If xClearCountOnExit is"]
#[doc = " not pdFALSE then the task's notification value is cleared to zero when the"]
#[doc = " function exits. In this way the notification value acts like a binary"]
#[doc = " semaphore."]
#[doc = ""]
#[doc = " @param xTicksToWait The maximum amount of time that the task should wait in"]
#[doc = " the Blocked state for the task's notification value to be greater than zero,"]
#[doc = " should the count not already be greater than zero when"]
#[doc = " ulTaskNotifyTake() was called. The task will not consume any processing"]
#[doc = " time while it is in the Blocked state. This is specified in kernel ticks,"]
#[doc = " the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time"]
#[doc = " specified in milliseconds to a time specified in ticks."]
#[doc = ""]
#[doc = " @return The task's notification count before it is either cleared to zero or"]
#[doc = " decremented (see the xClearCountOnExit parameter)."]
#[doc = ""]
#[doc = " \\ingroup TaskNotifications"]
pub fn ulTaskNotifyTake(xClearCountOnExit: BaseType_t, xTicksToWait: TickType_t) -> u32;
}
extern "C" {
#[doc = " @cond"]
pub fn xTaskIncrementTick() -> BaseType_t;
}
extern "C" {
pub fn vTaskPlaceOnEventList(pxEventList: *mut List_t, xTicksToWait: TickType_t);
}
extern "C" {
pub fn vTaskPlaceOnUnorderedEventList(
pxEventList: *mut List_t,
xItemValue: TickType_t,
xTicksToWait: TickType_t,
);
}
extern "C" {
pub fn vTaskPlaceOnEventListRestricted(pxEventList: *mut List_t, xTicksToWait: TickType_t);
}
extern "C" {
pub fn xTaskRemoveFromEventList(pxEventList: *const List_t) -> BaseType_t;
}
extern "C" {
pub fn xTaskRemoveFromUnorderedEventList(
pxEventListItem: *mut ListItem_t,
xItemValue: TickType_t,
) -> BaseType_t;
}
extern "C" {
pub fn vTaskSwitchContext();
}
extern "C" {
pub fn uxTaskResetEventItemValue() -> TickType_t;
}
extern "C" {
pub fn xTaskGetCurrentTaskHandle() -> TaskHandle_t;
}
extern "C" {
pub fn xTaskGetCurrentTaskHandleForCPU(cpuid: BaseType_t) -> TaskHandle_t;
}
extern "C" {
pub fn vTaskSetTimeOutState(pxTimeOut: *mut TimeOut_t);
}
extern "C" {
pub fn xTaskCheckForTimeOut(
pxTimeOut: *mut TimeOut_t,
pxTicksToWait: *mut TickType_t,
) -> BaseType_t;
}
extern "C" {
pub fn vTaskMissedYield();
}
extern "C" {
pub fn xTaskGetSchedulerState() -> BaseType_t;
}
extern "C" {
pub fn vTaskPriorityInherit(pxMutexHolder: TaskHandle_t);
}
extern "C" {
pub fn xTaskPriorityDisinherit(pxMutexHolder: TaskHandle_t) -> BaseType_t;
}
extern "C" {
pub fn uxTaskGetTaskNumber(xTask: TaskHandle_t) -> UBaseType_t;
}
extern "C" {
pub fn xTaskGetAffinity(xTask: TaskHandle_t) -> BaseType_t;
}
extern "C" {
pub fn vTaskSetTaskNumber(xTask: TaskHandle_t, uxHandle: UBaseType_t);
}
extern "C" {
pub fn vTaskStepTick(xTicksToJump: TickType_t);
}
extern "C" {
pub fn eTaskConfirmSleepModeStatus() -> eSleepModeStatus;
}
extern "C" {
pub fn pvTaskIncrementMutexHeldCount() -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn uxTaskGetSnapshotAll(
pxTaskSnapshotArray: *mut TaskSnapshot_t,
uxArraySize: UBaseType_t,
pxTcbSz: *mut UBaseType_t,
) -> UBaseType_t;
}
#[doc = "<The input voltage of ADC will be reduced to about 1/1"]
pub const adc_atten_t_ADC_ATTEN_DB_0: adc_atten_t = 0;
#[doc = "<The input voltage of ADC will be reduced to about 1/1.34"]
pub const adc_atten_t_ADC_ATTEN_DB_2_5: adc_atten_t = 1;
#[doc = "<The input voltage of ADC will be reduced to about 1/2"]
pub const adc_atten_t_ADC_ATTEN_DB_6: adc_atten_t = 2;
#[doc = "<The input voltage of ADC will be reduced to about 1/3.6"]
pub const adc_atten_t_ADC_ATTEN_DB_11: adc_atten_t = 3;
pub const adc_atten_t_ADC_ATTEN_MAX: adc_atten_t = 4;
pub type adc_atten_t = u32;
#[doc = "< ADC capture width is 9Bit"]
pub const adc_bits_width_t_ADC_WIDTH_BIT_9: adc_bits_width_t = 0;
#[doc = "< ADC capture width is 10Bit"]
pub const adc_bits_width_t_ADC_WIDTH_BIT_10: adc_bits_width_t = 1;
#[doc = "< ADC capture width is 11Bit"]
pub const adc_bits_width_t_ADC_WIDTH_BIT_11: adc_bits_width_t = 2;
#[doc = "< ADC capture width is 12Bit"]
pub const adc_bits_width_t_ADC_WIDTH_BIT_12: adc_bits_width_t = 3;
pub const adc_bits_width_t_ADC_WIDTH_MAX: adc_bits_width_t = 4;
pub type adc_bits_width_t = u32;
#[doc = "< ADC1 channel 0 is GPIO36"]
pub const adc1_channel_t_ADC1_CHANNEL_0: adc1_channel_t = 0;
#[doc = "< ADC1 channel 1 is GPIO37"]
pub const adc1_channel_t_ADC1_CHANNEL_1: adc1_channel_t = 1;
#[doc = "< ADC1 channel 2 is GPIO38"]
pub const adc1_channel_t_ADC1_CHANNEL_2: adc1_channel_t = 2;
#[doc = "< ADC1 channel 3 is GPIO39"]
pub const adc1_channel_t_ADC1_CHANNEL_3: adc1_channel_t = 3;
#[doc = "< ADC1 channel 4 is GPIO32"]
pub const adc1_channel_t_ADC1_CHANNEL_4: adc1_channel_t = 4;
#[doc = "< ADC1 channel 5 is GPIO33"]
pub const adc1_channel_t_ADC1_CHANNEL_5: adc1_channel_t = 5;
#[doc = "< ADC1 channel 6 is GPIO34"]
pub const adc1_channel_t_ADC1_CHANNEL_6: adc1_channel_t = 6;
#[doc = "< ADC1 channel 7 is GPIO35"]
pub const adc1_channel_t_ADC1_CHANNEL_7: adc1_channel_t = 7;
pub const adc1_channel_t_ADC1_CHANNEL_MAX: adc1_channel_t = 8;
pub type adc1_channel_t = u32;
#[doc = "< ADC2 channel 0 is GPIO4"]
pub const adc2_channel_t_ADC2_CHANNEL_0: adc2_channel_t = 0;
#[doc = "< ADC2 channel 1 is GPIO0"]
pub const adc2_channel_t_ADC2_CHANNEL_1: adc2_channel_t = 1;
#[doc = "< ADC2 channel 2 is GPIO2"]
pub const adc2_channel_t_ADC2_CHANNEL_2: adc2_channel_t = 2;
#[doc = "< ADC2 channel 3 is GPIO15"]
pub const adc2_channel_t_ADC2_CHANNEL_3: adc2_channel_t = 3;
#[doc = "< ADC2 channel 4 is GPIO13"]
pub const adc2_channel_t_ADC2_CHANNEL_4: adc2_channel_t = 4;
#[doc = "< ADC2 channel 5 is GPIO12"]
pub const adc2_channel_t_ADC2_CHANNEL_5: adc2_channel_t = 5;
#[doc = "< ADC2 channel 6 is GPIO14"]
pub const adc2_channel_t_ADC2_CHANNEL_6: adc2_channel_t = 6;
#[doc = "< ADC2 channel 7 is GPIO27"]
pub const adc2_channel_t_ADC2_CHANNEL_7: adc2_channel_t = 7;
#[doc = "< ADC2 channel 8 is GPIO25"]
pub const adc2_channel_t_ADC2_CHANNEL_8: adc2_channel_t = 8;
#[doc = "< ADC2 channel 9 is GPIO26"]
pub const adc2_channel_t_ADC2_CHANNEL_9: adc2_channel_t = 9;
pub const adc2_channel_t_ADC2_CHANNEL_MAX: adc2_channel_t = 10;
pub type adc2_channel_t = u32;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_0: adc_channel_t = 0;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_1: adc_channel_t = 1;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_2: adc_channel_t = 2;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_3: adc_channel_t = 3;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_4: adc_channel_t = 4;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_5: adc_channel_t = 5;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_6: adc_channel_t = 6;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_7: adc_channel_t = 7;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_8: adc_channel_t = 8;
#[doc = "< ADC channel"]
pub const adc_channel_t_ADC_CHANNEL_9: adc_channel_t = 9;
pub const adc_channel_t_ADC_CHANNEL_MAX: adc_channel_t = 10;
pub type adc_channel_t = u32;
#[doc = "< SAR ADC 1"]
pub const adc_unit_t_ADC_UNIT_1: adc_unit_t = 1;
#[doc = "< SAR ADC 2, not supported yet"]
pub const adc_unit_t_ADC_UNIT_2: adc_unit_t = 2;
#[doc = "< SAR ADC 1 and 2, not supported yet"]
pub const adc_unit_t_ADC_UNIT_BOTH: adc_unit_t = 3;
#[doc = "< SAR ADC 1 and 2 alternative mode, not supported yet"]
pub const adc_unit_t_ADC_UNIT_ALTER: adc_unit_t = 7;
pub const adc_unit_t_ADC_UNIT_MAX: adc_unit_t = 8;
pub type adc_unit_t = u32;
#[doc = "< ADC to I2S data format, [15:12]-channel [11:0]-12 bits ADC data"]
pub const adc_i2s_encode_t_ADC_ENCODE_12BIT: adc_i2s_encode_t = 0;
#[doc = "< ADC to I2S data format, [15]-1 [14:11]-channel [10:0]-11 bits ADC data"]
pub const adc_i2s_encode_t_ADC_ENCODE_11BIT: adc_i2s_encode_t = 1;
pub const adc_i2s_encode_t_ADC_ENCODE_MAX: adc_i2s_encode_t = 2;
pub type adc_i2s_encode_t = u32;
#[doc = "< I2S data from GPIO matrix signal"]
pub const adc_i2s_source_t_ADC_I2S_DATA_SRC_IO_SIG: adc_i2s_source_t = 0;
#[doc = "< I2S data from ADC"]
pub const adc_i2s_source_t_ADC_I2S_DATA_SRC_ADC: adc_i2s_source_t = 1;
pub const adc_i2s_source_t_ADC_I2S_DATA_SRC_MAX: adc_i2s_source_t = 2;
pub type adc_i2s_source_t = u32;
extern "C" {
#[doc = " @brief Get the gpio number of a specific ADC1 channel."]
#[doc = ""]
#[doc = " @param channel Channel to get the gpio number"]
#[doc = ""]
#[doc = " @param gpio_num output buffer to hold the gpio number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK if success"]
#[doc = " - ESP_ERR_INVALID_ARG if channal not valid"]
pub fn adc1_pad_get_io_num(channel: adc1_channel_t, gpio_num: *mut gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure ADC1 capture width, meanwhile enable output invert for ADC1."]
#[doc = " The configuration is for all channels of ADC1"]
#[doc = " @param width_bit Bit capture width for ADC1"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc1_config_width(width_bit: adc_bits_width_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure ADC capture width."]
#[doc = " @param adc_unit ADC unit index"]
#[doc = " @param width_bit Bit capture width for ADC unit."]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc_set_data_width(adc_unit: adc_unit_t, width_bit: adc_bits_width_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set the attenuation of a particular channel on ADC1, and configure its"]
#[doc = " associated GPIO pin mux."]
#[doc = ""]
#[doc = " @note For any given channel, this function must be called before the first time"]
#[doc = " adc1_get_raw() is called for that channel."]
#[doc = ""]
#[doc = " @note This function can be called multiple times to configure multiple"]
#[doc = " ADC channels simultaneously. adc1_get_raw() can then be called for any configured"]
#[doc = " channel."]
#[doc = ""]
#[doc = " The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,"]
#[doc = " usually 3.3V) requires setting >0dB signal attenuation for that ADC channel."]
#[doc = ""]
#[doc = " When VDD_A is 3.3V:"]
#[doc = ""]
#[doc = " - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V"]
#[doc = " - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V"]
#[doc = " - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V"]
#[doc = " - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)"]
#[doc = ""]
#[doc = " @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured"]
#[doc = " bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)"]
#[doc = ""]
#[doc = " @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage."]
#[doc = ""]
#[doc = " Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:"]
#[doc = ""]
#[doc = " - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV"]
#[doc = " - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV"]
#[doc = " - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV"]
#[doc = " - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV"]
#[doc = ""]
#[doc = " For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges."]
#[doc = ""]
#[doc = " @param channel ADC1 channel to configure"]
#[doc = " @param atten Attenuation level"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc1_config_channel_atten(channel: adc1_channel_t, atten: adc_atten_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Take an ADC1 reading from a single channel."]
#[doc = " @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,"]
#[doc = " the input of GPIO36 and GPIO39 will be pulled down for about 80ns."]
#[doc = " When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39."]
#[doc = " Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue."]
#[doc = ""]
#[doc = " @note Call adc1_config_width() before the first time this"]
#[doc = " function is called."]
#[doc = ""]
#[doc = " @note For any given channel, adc1_config_channel_atten(channel)"]
#[doc = " must be called before the first time this function is called. Configuring"]
#[doc = " a new channel does not prevent a previously configured channel from being read."]
#[doc = ""]
#[doc = " @param channel ADC1 channel to read"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - -1: Parameter error"]
#[doc = " - Other: ADC1 channel reading."]
pub fn adc1_get_raw(channel: adc1_channel_t) -> ::std::os::raw::c_int;
}
extern "C" {
pub fn adc1_get_voltage(channel: adc1_channel_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Enable ADC power"]
pub fn adc_power_on();
}
extern "C" {
#[doc = " @brief Power off SAR ADC"]
#[doc = " This function will force power down for ADC"]
pub fn adc_power_off();
}
extern "C" {
#[doc = " @brief Initialize ADC pad"]
#[doc = " @param adc_unit ADC unit index"]
#[doc = " @param channel ADC channel index"]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc_gpio_init(adc_unit: adc_unit_t, channel: adc_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set ADC data invert"]
#[doc = " @param adc_unit ADC unit index"]
#[doc = " @param inv_en whether enable data invert"]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc_set_data_inv(adc_unit: adc_unit_t, inv_en: bool) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set ADC source clock"]
#[doc = " @param clk_div ADC clock divider, ADC clock is divided from APB clock"]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
pub fn adc_set_clk_div(clk_div: u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set I2S data source"]
#[doc = " @param src I2S DMA data source, I2S DMA can get data from digital signals or from ADC."]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
pub fn adc_set_i2s_data_source(src: adc_i2s_source_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize I2S ADC mode"]
#[doc = " @param adc_unit ADC unit index"]
#[doc = " @param channel ADC channel index"]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc_i2s_mode_init(adc_unit: adc_unit_t, channel: adc_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure ADC1 to be usable by the ULP"]
#[doc = ""]
#[doc = " This function reconfigures ADC1 to be controlled by the ULP."]
#[doc = " Effect of this function can be reverted using adc1_get_raw function."]
#[doc = ""]
#[doc = " Note that adc1_config_channel_atten, adc1_config_width functions need"]
#[doc = " to be called to configure ADC1 channels, before ADC1 is used by the ULP."]
pub fn adc1_ulp_enable();
}
extern "C" {
#[doc = " @brief Read Hall Sensor"]
#[doc = ""]
#[doc = " @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,"]
#[doc = " the input of GPIO36 and GPIO39 will be pulled down for about 80ns."]
#[doc = " When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39."]
#[doc = " Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue."]
#[doc = ""]
#[doc = " @note The Hall Sensor uses channels 0 and 3 of ADC1. Do not configure"]
#[doc = " these channels for use as ADC channels."]
#[doc = ""]
#[doc = " @note The ADC1 module must be enabled by calling"]
#[doc = " adc1_config_width() before calling hall_sensor_read(). ADC1"]
#[doc = " should be configured for 12 bit readings, as the hall sensor"]
#[doc = " readings are low values and do not cover the full range of the"]
#[doc = " ADC."]
#[doc = ""]
#[doc = " @return The hall sensor reading."]
pub fn hall_sensor_read() -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Get the gpio number of a specific ADC2 channel."]
#[doc = ""]
#[doc = " @param channel Channel to get the gpio number"]
#[doc = ""]
#[doc = " @param gpio_num output buffer to hold the gpio number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK if success"]
#[doc = " - ESP_ERR_INVALID_ARG if channal not valid"]
pub fn adc2_pad_get_io_num(channel: adc2_channel_t, gpio_num: *mut gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure the ADC2 channel, including setting attenuation."]
#[doc = ""]
#[doc = " @note This function also configures the input GPIO pin mux to"]
#[doc = " connect it to the ADC2 channel. It must be called before calling"]
#[doc = " ``adc2_get_raw()`` for this channel."]
#[doc = ""]
#[doc = " The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,"]
#[doc = " usually 3.3V) requires setting >0dB signal attenuation for that ADC channel."]
#[doc = ""]
#[doc = " When VDD_A is 3.3V:"]
#[doc = ""]
#[doc = " - 0dB attenuaton (ADC_ATTEN_0db) gives full-scale voltage 1.1V"]
#[doc = " - 2.5dB attenuation (ADC_ATTEN_2_5db) gives full-scale voltage 1.5V"]
#[doc = " - 6dB attenuation (ADC_ATTEN_6db) gives full-scale voltage 2.2V"]
#[doc = " - 11dB attenuation (ADC_ATTEN_11db) gives full-scale voltage 3.9V (see note below)"]
#[doc = ""]
#[doc = " @note The full-scale voltage is the voltage corresponding to a maximum reading"]
#[doc = " (depending on ADC2 configured bit width, this value is: 4095 for 12-bits, 2047"]
#[doc = " for 11-bits, 1023 for 10-bits, 511 for 9 bits.)"]
#[doc = ""]
#[doc = " @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage."]
#[doc = ""]
#[doc = " @param channel ADC2 channel to configure"]
#[doc = " @param atten Attenuation level"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn adc2_config_channel_atten(channel: adc2_channel_t, atten: adc_atten_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Take an ADC2 reading on a single channel"]
#[doc = ""]
#[doc = " @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,"]
#[doc = " the input of GPIO36 and GPIO39 will be pulled down for about 80ns."]
#[doc = " When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39."]
#[doc = " Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue."]
#[doc = ""]
#[doc = " @note For a given channel, ``adc2_config_channel_atten()``"]
#[doc = " must be called before the first time this function is called. If Wi-Fi is started via ``esp_wifi_start()``, this"]
#[doc = " function will always fail with ``ESP_ERR_TIMEOUT``."]
#[doc = ""]
#[doc = " @param channel ADC2 channel to read"]
#[doc = ""]
#[doc = " @param width_bit Bit capture width for ADC2"]
#[doc = ""]
#[doc = " @param raw_out the variable to hold the output data."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK if success"]
#[doc = " - ESP_ERR_TIMEOUT the WIFI is started, using the ADC2"]
pub fn adc2_get_raw(
channel: adc2_channel_t,
width_bit: adc_bits_width_t,
raw_out: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Output ADC2 reference voltage to gpio 25 or 26 or 27"]
#[doc = ""]
#[doc = " This function utilizes the testing mux exclusive to ADC 2 to route the"]
#[doc = " reference voltage one of ADC2's channels. Supported gpios are gpios"]
#[doc = " 25, 26, and 27. This refernce voltage can be manually read from the pin"]
#[doc = " and used in the esp_adc_cal component."]
#[doc = ""]
#[doc = " @param[in] gpio GPIO number (gpios 25,26,27 supported)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: v_ref successfully routed to selected gpio"]
#[doc = " - ESP_ERR_INVALID_ARG: Unsupported gpio"]
pub fn adc2_vref_to_gpio(gpio: gpio_num_t) -> esp_err_t;
}
#[doc = "< Normal operating mode where CAN controller can send/receive/acknowledge messages"]
pub const can_mode_t_CAN_MODE_NORMAL: can_mode_t = 0;
#[doc = "< Transmission does not require acknowledgment. Use this mode for self testing"]
pub const can_mode_t_CAN_MODE_NO_ACK: can_mode_t = 1;
#[doc = "< The CAN controller will not influence the bus (No transmissions or acknowledgments) but can receive messages"]
pub const can_mode_t_CAN_MODE_LISTEN_ONLY: can_mode_t = 2;
#[doc = " @brief CAN driver operating modes"]
pub type can_mode_t = u32;
#[doc = "< Stopped state. The CAN controller will not participate in any CAN bus activities"]
pub const can_state_t_CAN_STATE_STOPPED: can_state_t = 0;
#[doc = "< Running state. The CAN controller can transmit and receive messages"]
pub const can_state_t_CAN_STATE_RUNNING: can_state_t = 1;
#[doc = "< Bus-off state. The CAN controller cannot participate in bus activities until it has recovered"]
pub const can_state_t_CAN_STATE_BUS_OFF: can_state_t = 2;
#[doc = "< Recovering state. The CAN controller is undergoing bus recovery"]
pub const can_state_t_CAN_STATE_RECOVERING: can_state_t = 3;
#[doc = " @brief CAN driver states"]
pub type can_state_t = u32;
#[doc = " @brief Structure for general configuration of the CAN driver"]
#[doc = ""]
#[doc = " @note Macro initializers are available for this structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct can_general_config_t {
#[doc = "< Mode of CAN controller"]
pub mode: can_mode_t,
#[doc = "< Transmit GPIO number"]
pub tx_io: gpio_num_t,
#[doc = "< Receive GPIO number"]
pub rx_io: gpio_num_t,
#[doc = "< CLKOUT GPIO number (optional, set to -1 if unused)"]
pub clkout_io: gpio_num_t,
#[doc = "< Bus off indicator GPIO number (optional, set to -1 if unused)"]
pub bus_off_io: gpio_num_t,
#[doc = "< Number of messages TX queue can hold (set to 0 to disable TX Queue)"]
pub tx_queue_len: u32,
#[doc = "< Number of messages RX queue can hold"]
pub rx_queue_len: u32,
#[doc = "< Bit field of alerts to enable (see documentation)"]
pub alerts_enabled: u32,
#[doc = "< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused)"]
pub clkout_divider: u32,
}
#[doc = " @brief Structure for bit timing configuration of the CAN driver"]
#[doc = ""]
#[doc = " @note Macro initializers are available for this structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct can_timing_config_t {
#[doc = "< Baudrate prescaler (APB clock divider, even number from 2 to 128)"]
pub brp: u8,
#[doc = "< Timing segment 1 (Number of time quanta, between 1 to 16)"]
pub tseg_1: u8,
#[doc = "< Timing segment 2 (Number of time quanta, 1 to 8)"]
pub tseg_2: u8,
#[doc = "< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4)"]
pub sjw: u8,
#[doc = "< Enables triple sampling when the CAN controller samples a bit"]
pub triple_sampling: bool,
}
#[doc = " @brief Structure for acceptance filter configuration of the CAN driver (see documentation)"]
#[doc = ""]
#[doc = " @note Macro initializers are available for this structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct can_filter_config_t {
#[doc = "< 32-bit acceptance code"]
pub acceptance_code: u32,
#[doc = "< 32-bit acceptance mask"]
pub acceptance_mask: u32,
#[doc = "< Use Single Filter Mode (see documentation)"]
pub single_filter: bool,
}
#[doc = " @brief Structure to store status information of CAN driver"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct can_status_info_t {
#[doc = "< Current state of CAN controller (Stopped/Running/Bus-Off/Recovery)"]
pub state: can_state_t,
#[doc = "< Number of messages queued for transmission or awaiting transmission completion"]
pub msgs_to_tx: u32,
#[doc = "< Number of messages in RX queue waiting to be read"]
pub msgs_to_rx: u32,
#[doc = "< Current value of Transmit Error Counter"]
pub tx_error_counter: u32,
#[doc = "< Current value of Receive Error Counter"]
pub rx_error_counter: u32,
#[doc = "< Number of messages that failed transmissions"]
pub tx_failed_count: u32,
#[doc = "< Number of messages that were lost due to a full RX queue"]
pub rx_missed_count: u32,
#[doc = "< Number of instances arbitration was lost"]
pub arb_lost_count: u32,
#[doc = "< Number of instances a bus error has occurred"]
pub bus_error_count: u32,
}
#[doc = " @brief Structure to store a CAN message"]
#[doc = ""]
#[doc = " @note The flags member is used to control the message type, and transmission"]
#[doc = " type (see documentation for message flags)"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct can_message_t {
#[doc = "< Bit field of message flags indicates frame/transmission type (see documentation)"]
pub flags: u32,
#[doc = "< 11 or 29 bit identifier"]
pub identifier: u32,
#[doc = "< Data length code"]
pub data_length_code: u8,
#[doc = "< Data bytes (not relevant in RTR frame)"]
pub data: [u8; 8usize],
}
extern "C" {
#[doc = " @brief Install CAN driver"]
#[doc = ""]
#[doc = " This function installs the CAN driver using three configuration structures."]
#[doc = " The required memory is allocated and the CAN driver is placed in the stopped"]
#[doc = " state after running this function."]
#[doc = ""]
#[doc = " @param[in] g_config General configuration structure"]
#[doc = " @param[in] t_config Timing configuration structure"]
#[doc = " @param[in] f_config Filter configuration structure"]
#[doc = ""]
#[doc = " @note Macro initializers are available for the configuration structures (see documentation)"]
#[doc = ""]
#[doc = " @note To reinstall the CAN driver, call can_driver_uninstall() first"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Successfully installed CAN driver"]
#[doc = " - ESP_ERR_INVALID_ARG: Arguments are invalid"]
#[doc = " - ESP_ERR_NO_MEM: Insufficient memory"]
#[doc = " - ESP_ERR_INVALID_STATE: Driver is already installed"]
pub fn can_driver_install(
g_config: *const can_general_config_t,
t_config: *const can_timing_config_t,
f_config: *const can_filter_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Uninstall the CAN driver"]
#[doc = ""]
#[doc = " This function uninstalls the CAN driver, freeing the memory utilized by the"]
#[doc = " driver. This function can only be called when the driver is in the stopped"]
#[doc = " state or the bus-off state."]
#[doc = ""]
#[doc = " @warning The application must ensure that no tasks are blocked on TX/RX"]
#[doc = " queues or alerts when this function is called."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Successfully uninstalled CAN driver"]
#[doc = " - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed"]
pub fn can_driver_uninstall() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start the CAN driver"]
#[doc = ""]
#[doc = " This function starts the CAN driver, putting the CAN driver into the running"]
#[doc = " state. This allows the CAN driver to participate in CAN bus activities such"]
#[doc = " as transmitting/receiving messages. The RX queue is reset in this function,"]
#[doc = " clearing any unread messages. This function can only be called when the CAN"]
#[doc = " driver is in the stopped state."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: CAN driver is now running"]
#[doc = " - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed"]
pub fn can_start() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Stop the CAN driver"]
#[doc = ""]
#[doc = " This function stops the CAN driver, preventing any further message from being"]
#[doc = " transmitted or received until can_start() is called. Any messages in the TX"]
#[doc = " queue are cleared. Any messages in the RX queue should be read by the"]
#[doc = " application after this function is called. This function can only be called"]
#[doc = " when the CAN driver is in the running state."]
#[doc = ""]
#[doc = " @warning A message currently being transmitted/received on the CAN bus will"]
#[doc = " be ceased immediately. This may lead to other CAN nodes interpreting"]
#[doc = " the unfinished message as an error."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: CAN driver is now Stopped"]
#[doc = " - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed"]
pub fn can_stop() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Transmit a CAN message"]
#[doc = ""]
#[doc = " This function queues a CAN message for transmission. Transmission will start"]
#[doc = " immediately if no other messages are queued for transmission. If the TX queue"]
#[doc = " is full, this function will block until more space becomes available or until"]
#[doc = " it timesout. If the TX queue is disabled (TX queue length = 0 in configuration),"]
#[doc = " this function will return immediately if another message is undergoing"]
#[doc = " transmission. This function can only be called when the CAN driver is in the"]
#[doc = " running state and cannot be called under Listen Only Mode."]
#[doc = ""]
#[doc = " @param[in] message Message to transmit"]
#[doc = " @param[in] ticks_to_wait Number of FreeRTOS ticks to block on the TX queue"]
#[doc = ""]
#[doc = " @note This function does not guarantee that the transmission is successful."]
#[doc = " The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application"]
#[doc = " upon the success/failure of a transmission."]
#[doc = ""]
#[doc = " @note The TX_IDLE alert can be used to alert the application when no other"]
#[doc = " messages are awaiting transmission."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Transmission successfully queued/initiated"]
#[doc = " - ESP_ERR_INVALID_ARG: Arguments are invalid"]
#[doc = " - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue"]
#[doc = " - ESP_FAIL: TX queue is disabled and another message is currently transmitting"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not in running state, or is not installed"]
#[doc = " - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions"]
pub fn can_transmit(message: *const can_message_t, ticks_to_wait: TickType_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Receive a CAN message"]
#[doc = ""]
#[doc = " This function receives a message from the RX queue. The flags field of the"]
#[doc = " message structure will indicate the type of message received. This function"]
#[doc = " will block if there are no messages in the RX queue"]
#[doc = ""]
#[doc = " @param[out] message Received message"]
#[doc = " @param[in] ticks_to_wait Number of FreeRTOS ticks to block on RX queue"]
#[doc = ""]
#[doc = " @warning The flags field of the received message should be checked to determine"]
#[doc = " if the received message contains any data bytes."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Message successfully received from RX queue"]
#[doc = " - ESP_ERR_TIMEOUT: Timed out waiting for message"]
#[doc = " - ESP_ERR_INVALID_ARG: Arguments are invalid"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not installed"]
pub fn can_receive(message: *mut can_message_t, ticks_to_wait: TickType_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read CAN driver alerts"]
#[doc = ""]
#[doc = " This function will read the alerts raised by the CAN driver. If no alert has"]
#[doc = " been when this function is called, this function will block until an alert"]
#[doc = " occurs or until it timeouts."]
#[doc = ""]
#[doc = " @param[out] alerts Bit field of raised alerts (see documentation for alert flags)"]
#[doc = " @param[in] ticks_to_wait Number of FreeRTOS ticks to block for alert"]
#[doc = ""]
#[doc = " @note Multiple alerts can be raised simultaneously. The application should"]
#[doc = " check for all alerts that have been enabled."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Alerts read"]
#[doc = " - ESP_ERR_TIMEOUT: Timed out waiting for alerts"]
#[doc = " - ESP_ERR_INVALID_ARG: Arguments are invalid"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not installed"]
pub fn can_read_alerts(alerts: *mut u32, ticks_to_wait: TickType_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Reconfigure which alerts are enabled"]
#[doc = ""]
#[doc = " This function reconfigures which alerts are enabled. If there are alerts"]
#[doc = " which have not been read whilst reconfiguring, this function can read those"]
#[doc = " alerts."]
#[doc = ""]
#[doc = " @param[in] alerts_enabled Bit field of alerts to enable (see documentation for alert flags)"]
#[doc = " @param[out] current_alerts Bit field of currently raised alerts. Set to NULL if unused"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Alerts reconfigured"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not installed"]
pub fn can_reconfigure_alerts(alerts_enabled: u32, current_alerts: *mut u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start the bus recovery process"]
#[doc = ""]
#[doc = " This function initiates the bus recovery process when the CAN driver is in"]
#[doc = " the bus-off state. Once initiated, the CAN driver will enter the recovering"]
#[doc = " state and wait for 128 occurrences of the bus-free signal on the CAN bus"]
#[doc = " before returning to the stopped state. This function will reset the TX queue,"]
#[doc = " clearing any messages pending transmission."]
#[doc = ""]
#[doc = " @note The BUS_RECOVERED alert can be enabled to alert the application when"]
#[doc = " the bus recovery process completes."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Bus recovery started"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not in the bus-off state, or is not installed"]
pub fn can_initiate_recovery() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get current status information of the CAN driver"]
#[doc = ""]
#[doc = " @param[out] status_info Status information"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK: Status information retrieved"]
#[doc = " - ESP_ERR_INVALID_ARG: Arguments are invalid"]
#[doc = " - ESP_ERR_INVALID_STATE: CAN driver is not installed"]
pub fn can_get_status_info(status_info: *mut can_status_info_t) -> esp_err_t;
}
#[doc = "< DAC channel 1 is GPIO25"]
pub const dac_channel_t_DAC_CHANNEL_1: dac_channel_t = 1;
#[doc = "< DAC channel 2 is GPIO26"]
pub const dac_channel_t_DAC_CHANNEL_2: dac_channel_t = 2;
pub const dac_channel_t_DAC_CHANNEL_MAX: dac_channel_t = 3;
pub type dac_channel_t = u32;
extern "C" {
#[doc = " @brief Get the gpio number of a specific DAC channel."]
#[doc = ""]
#[doc = " @param channel Channel to get the gpio number"]
#[doc = ""]
#[doc = " @param gpio_num output buffer to hold the gpio number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK if success"]
#[doc = " - ESP_ERR_INVALID_ARG if channal not valid"]
pub fn dac_pad_get_io_num(channel: dac_channel_t, gpio_num: *mut gpio_num_t) -> esp_err_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " @brief Set DAC output voltage."]
#[doc = ""]
#[doc = " @note Function has been deprecated, please use dac_output_voltage instead."]
#[doc = " This name will be removed in a future release."]
#[doc = " The difference is that before calling dac_output_voltage, we need to initialize the dac pad by dac_output_enable"]
#[doc = ""]
#[doc = ""]
#[doc = " @param channel DAC channel"]
#[doc = " @param dac_value DAC output value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn dac_out_voltage(channel: dac_channel_t, dac_value: u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set DAC output voltage."]
#[doc = ""]
#[doc = " DAC output is 8-bit. Maximum (255) corresponds to VDD."]
#[doc = ""]
#[doc = " @note Need to configure DAC pad before calling this function."]
#[doc = " DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26"]
#[doc = ""]
#[doc = " @param channel DAC channel"]
#[doc = " @param dac_value DAC output value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn dac_output_voltage(channel: dac_channel_t, dac_value: u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief DAC pad output enable"]
#[doc = ""]
#[doc = " @param channel DAC channel"]
#[doc = " @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26"]
#[doc = " I2S left channel will be mapped to DAC channel 2"]
#[doc = " I2S right channel will be mapped to DAC channel 1"]
pub fn dac_output_enable(channel: dac_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief DAC pad output disable"]
#[doc = ""]
#[doc = " @param channel DAC channel"]
#[doc = " @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26"]
pub fn dac_output_disable(channel: dac_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable DAC output data from I2S"]
pub fn dac_i2s_enable() -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable DAC output data from I2S"]
pub fn dac_i2s_disable() -> esp_err_t;
}
#[doc = " Type by which queues are referenced. For example, a call to xQueueCreate()"]
#[doc = " returns an QueueHandle_t variable that can then be used as a parameter to"]
#[doc = " xQueueSend(), xQueueReceive(), etc."]
pub type QueueHandle_t = *mut ::std::os::raw::c_void;
#[doc = " Type by which queue sets are referenced. For example, a call to"]
#[doc = " xQueueCreateSet() returns an xQueueSet variable that can then be used as a"]
#[doc = " parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc."]
pub type QueueSetHandle_t = *mut ::std::os::raw::c_void;
#[doc = " Queue sets can contain both queues and semaphores, so the"]
#[doc = " QueueSetMemberHandle_t is defined as a type to be used where a parameter or"]
#[doc = " return value can be either an QueueHandle_t or an SemaphoreHandle_t."]
pub type QueueSetMemberHandle_t = *mut ::std::os::raw::c_void;
extern "C" {
#[doc = " It is preferred that the macros xQueueSend(), xQueueSendToFront() and"]
#[doc = " xQueueSendToBack() are used in place of calling this function directly."]
#[doc = ""]
#[doc = " Post an item on a queue. The item is queued by copy, not by reference."]
#[doc = " This function must not be called from an interrupt service routine."]
#[doc = " See xQueueSendFromISR () for an alternative which may be used in an ISR."]
#[doc = ""]
#[doc = " @param xQueue The handle to the queue on which the item is to be posted."]
#[doc = ""]
#[doc = " @param pvItemToQueue A pointer to the item that is to be placed on the"]
#[doc = " queue. The size of the items the queue will hold was defined when the"]
#[doc = " queue was created, so this many bytes will be copied from pvItemToQueue"]
#[doc = " into the queue storage area."]
#[doc = ""]
#[doc = " @param xTicksToWait The maximum amount of time the task should block"]
#[doc = " waiting for space to become available on the queue, should it already"]
#[doc = " be full. The call will return immediately if this is set to 0 and the"]
#[doc = " queue is full. The time is defined in tick periods so the constant"]
#[doc = " portTICK_PERIOD_MS should be used to convert to real time if this is required."]
#[doc = ""]
#[doc = " @param xCopyPosition Can take the value queueSEND_TO_BACK to place the"]
#[doc = " item at the back of the queue, or queueSEND_TO_FRONT to place the item"]
#[doc = " at the front of the queue (for high priority messages)."]
#[doc = ""]
#[doc = " @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " struct AMessage"]
#[doc = " {"]
#[doc = " char ucMessageID;"]
#[doc = " char ucData[ 20 ];"]
#[doc = " } xMessage;"]
#[doc = ""]
#[doc = " uint32_t ulVar = 10UL;"]
#[doc = ""]
#[doc = " void vATask( void *pvParameters )"]
#[doc = " {"]
#[doc = " QueueHandle_t xQueue1, xQueue2;"]
#[doc = " struct AMessage *pxMessage;"]
#[doc = ""]
#[doc = " // Create a queue capable of containing 10 uint32_t values."]
#[doc = " xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );"]
#[doc = ""]
#[doc = " // Create a queue capable of containing 10 pointers to AMessage structures."]
#[doc = " // These should be passed by pointer as they contain a lot of data."]
#[doc = " xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );"]
#[doc = ""]
#[doc = " // ..."]
#[doc = ""]
#[doc = " if( xQueue1 != 0 )"]
#[doc = " {"]
#[doc = " // Send an uint32_t. Wait for 10 ticks for space to become"]
#[doc = " // available if necessary."]
#[doc = " if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )"]
#[doc = " {"]
#[doc = " // Failed to post the message, even after 10 ticks."]
#[doc = " }"]
#[doc = " }"]
#[doc = ""]
#[doc = " if( xQueue2 != 0 )"]
#[doc = " {"]
#[doc = " // Send a pointer to a struct AMessage object. Don't block if the"]
#[doc = " // queue is already full."]
#[doc = " pxMessage = & xMessage;"]
#[doc = " xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );"]
#[doc = " }"]
#[doc = ""]
#[doc = " // ... Rest of task code."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup QueueManagement"]
pub fn xQueueGenericSend(
xQueue: QueueHandle_t,
pvItemToQueue: *const ::std::os::raw::c_void,
xTicksToWait: TickType_t,
xCopyPosition: BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " A version of xQueuePeek() that can be called from an interrupt service"]
#[doc = " routine (ISR)."]
#[doc = ""]
#[doc = " Receive an item from a queue without removing the item from the queue."]
#[doc = " The item is received by copy so a buffer of adequate size must be"]
#[doc = " provided. The number of bytes copied into the buffer was defined when"]
#[doc = " the queue was created."]
#[doc = ""]
#[doc = " Successfully received items remain on the queue so will be returned again"]
#[doc = " by the next call, or a call to xQueueReceive()."]
#[doc = ""]
#[doc = " @param xQueue The handle to the queue from which the item is to be"]
#[doc = " received."]
#[doc = ""]
#[doc = " @param pvBuffer Pointer to the buffer into which the received item will"]
#[doc = " be copied."]
#[doc = ""]
#[doc = " @return pdTRUE if an item was successfully received from the queue,"]
#[doc = " otherwise pdFALSE."]
#[doc = ""]
#[doc = " \\ingroup QueueManagement"]
pub fn xQueuePeekFromISR(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
) -> BaseType_t;
}
extern "C" {
#[doc = " It is preferred that the macro xQueueReceive() be used rather than calling"]
#[doc = " this function directly."]
#[doc = ""]
#[doc = " Receive an item from a queue. The item is received by copy so a buffer of"]
#[doc = " adequate size must be provided. The number of bytes copied into the buffer"]
#[doc = " was defined when the queue was created."]
#[doc = ""]
#[doc = " This function must not be used in an interrupt service routine. See"]
#[doc = " xQueueReceiveFromISR for an alternative that can."]
#[doc = ""]
#[doc = " @param xQueue The handle to the queue from which the item is to be"]
#[doc = " received."]
#[doc = ""]
#[doc = " @param pvBuffer Pointer to the buffer into which the received item will"]
#[doc = " be copied."]
#[doc = ""]
#[doc = " @param xTicksToWait The maximum amount of time the task should block"]
#[doc = " waiting for an item to receive should the queue be empty at the time"]
#[doc = " of the call.\t The time is defined in tick periods so the constant"]
#[doc = " portTICK_PERIOD_MS should be used to convert to real time if this is required."]
#[doc = " xQueueGenericReceive() will return immediately if the queue is empty and"]
#[doc = " xTicksToWait is 0."]
#[doc = ""]
#[doc = " @param xJustPeek When set to true, the item received from the queue is not"]
#[doc = " actually removed from the queue - meaning a subsequent call to"]
#[doc = " xQueueReceive() will return the same item. When set to false, the item"]
#[doc = " being received from the queue is also removed from the queue."]
#[doc = ""]
#[doc = " @return pdTRUE if an item was successfully received from the queue,"]
#[doc = " otherwise pdFALSE."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " struct AMessage"]
#[doc = " {"]
#[doc = " \tchar ucMessageID;"]
#[doc = " \tchar ucData[ 20 ];"]
#[doc = " } xMessage;"]
#[doc = ""]
#[doc = " QueueHandle_t xQueue;"]
#[doc = ""]
#[doc = " // Task to create a queue and post a value."]
#[doc = " void vATask( void *pvParameters )"]
#[doc = " {"]
#[doc = " struct AMessage *pxMessage;"]
#[doc = ""]
#[doc = " \t// Create a queue capable of containing 10 pointers to AMessage structures."]
#[doc = " \t// These should be passed by pointer as they contain a lot of data."]
#[doc = " \txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );"]
#[doc = " \tif( xQueue == 0 )"]
#[doc = " \t{"]
#[doc = " \t\t// Failed to create the queue."]
#[doc = " \t}"]
#[doc = ""]
#[doc = " \t// ..."]
#[doc = ""]
#[doc = " \t// Send a pointer to a struct AMessage object. Don't block if the"]
#[doc = " \t// queue is already full."]
#[doc = " \tpxMessage = & xMessage;"]
#[doc = " \txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );"]
#[doc = ""]
#[doc = " \t// ... Rest of task code."]
#[doc = " }"]
#[doc = ""]
#[doc = " // Task to receive from the queue."]
#[doc = " void vADifferentTask( void *pvParameters )"]
#[doc = " {"]
#[doc = " struct AMessage *pxRxedMessage;"]
#[doc = ""]
#[doc = " \tif( xQueue != 0 )"]
#[doc = " \t{"]
#[doc = " \t\t// Receive a message on the created queue. Block for 10 ticks if a"]
#[doc = " \t\t// message is not immediately available."]
#[doc = " \t\tif( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )"]
#[doc = " \t\t{"]
#[doc = " \t\t\t// pcRxedMessage now points to the struct AMessage variable posted"]
#[doc = " \t\t\t// by vATask."]
#[doc = " \t\t}"]
#[doc = " \t}"]
#[doc = ""]
#[doc = " \t// ... Rest of task code."]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup QueueManagement"]
pub fn xQueueGenericReceive(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
xTicksToWait: TickType_t,
xJustPeek: BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Return the number of messages stored in a queue."]
#[doc = ""]
#[doc = " @param xQueue A handle to the queue being queried."]
#[doc = ""]
#[doc = " @return The number of messages available in the queue."]
#[doc = ""]
#[doc = " \\ingroup QueueManagement"]
pub fn uxQueueMessagesWaiting(xQueue: QueueHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " Return the number of free spaces available in a queue. This is equal to the"]
#[doc = " number of items that can be sent to the queue before the queue becomes full"]
#[doc = " if no items are removed."]
#[doc = ""]
#[doc = " @param xQueue A handle to the queue being queried."]
#[doc = ""]
#[doc = " @return The number of spaces available in the queue."]
#[doc = ""]
#[doc = " \\ingroup QueueManagement"]
pub fn uxQueueSpacesAvailable(xQueue: QueueHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " Delete a queue - freeing all the memory allocated for storing of items"]
#[doc = " placed on the queue."]
#[doc = ""]
#[doc = " @param xQueue A handle to the queue to be deleted."]
#[doc = ""]
#[doc = " \\ingroup QueueManagement"]
pub fn vQueueDelete(xQueue: QueueHandle_t);
}
extern "C" {
#[doc = "@{*/"]
#[doc = " It is preferred that the macros xQueueSendFromISR(),"]
#[doc = " xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place"]
#[doc = " of calling this function directly. xQueueGiveFromISR() is an"]
#[doc = " equivalent for use by semaphores that don't actually copy any data."]
#[doc = ""]
#[doc = " Post an item on a queue. It is safe to use this function from within an"]
#[doc = " interrupt service routine."]
#[doc = ""]
#[doc = " Items are queued by copy not reference so it is preferable to only"]
#[doc = " queue small items, especially when called from an ISR. In most cases"]
#[doc = " it would be preferable to store a pointer to the item being queued."]
#[doc = ""]
#[doc = " @param xQueue The handle to the queue on which the item is to be posted."]
#[doc = ""]
#[doc = " @param pvItemToQueue A pointer to the item that is to be placed on the"]
#[doc = " queue. The size of the items the queue will hold was defined when the"]
#[doc = " queue was created, so this many bytes will be copied from pvItemToQueue"]
#[doc = " into the queue storage area."]
#[doc = ""]
#[doc = " @param[out] pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set"]
#[doc = " *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task"]
#[doc = " to unblock, and the unblocked task has a priority higher than the currently"]
#[doc = " running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then"]
#[doc = " a context switch should be requested before the interrupt is exited."]
#[doc = ""]
#[doc = " @param xCopyPosition Can take the value queueSEND_TO_BACK to place the"]
#[doc = " item at the back of the queue, or queueSEND_TO_FRONT to place the item"]
#[doc = " at the front of the queue (for high priority messages)."]
#[doc = ""]
#[doc = " @return pdTRUE if the data was successfully sent to the queue, otherwise"]
#[doc = " errQUEUE_FULL."]
#[doc = ""]
#[doc = " Example usage for buffered IO (where the ISR can obtain more than one value"]
#[doc = " per call):"]
#[doc = " @code{c}"]
#[doc = " void vBufferISR( void )"]
#[doc = " {"]
#[doc = " char cIn;"]
#[doc = " BaseType_t xHigherPriorityTaskWokenByPost;"]
#[doc = ""]
#[doc = " \t// We have not woken a task at the start of the ISR."]
#[doc = " \txHigherPriorityTaskWokenByPost = pdFALSE;"]
#[doc = ""]
#[doc = " \t// Loop until the buffer is empty."]
#[doc = " \tdo"]
#[doc = " \t{"]
#[doc = " \t\t// Obtain a byte from the buffer."]
#[doc = " \t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );"]
#[doc = ""]
#[doc = " \t\t// Post each byte."]
#[doc = " \t\txQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );"]
#[doc = ""]
#[doc = " \t} while( portINPUT_BYTE( BUFFER_COUNT ) );"]
#[doc = ""]
#[doc = " \t// Now the buffer is empty we can switch context if necessary. Note that the"]
#[doc = " \t// name of the yield function required is port specific."]
#[doc = " \tif( xHigherPriorityTaskWokenByPost )"]
#[doc = " \t{"]
#[doc = " \t\ttaskYIELD_YIELD_FROM_ISR();"]
#[doc = " \t}"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup QueueManagement"]
pub fn xQueueGenericSendFromISR(
xQueue: QueueHandle_t,
pvItemToQueue: *const ::std::os::raw::c_void,
pxHigherPriorityTaskWoken: *mut BaseType_t,
xCopyPosition: BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueGiveFromISR(
xQueue: QueueHandle_t,
pxHigherPriorityTaskWoken: *mut BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Receive an item from a queue. It is safe to use this function from within an"]
#[doc = " interrupt service routine."]
#[doc = ""]
#[doc = " @param xQueue The handle to the queue from which the item is to be"]
#[doc = " received."]
#[doc = ""]
#[doc = " @param pvBuffer Pointer to the buffer into which the received item will"]
#[doc = " be copied."]
#[doc = ""]
#[doc = " @param[out] pxHigherPriorityTaskWoken A task may be blocked waiting for space to become"]
#[doc = " available on the queue. If xQueueReceiveFromISR causes such a task to"]
#[doc = " unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will"]
#[doc = " remain unchanged."]
#[doc = ""]
#[doc = " @return pdTRUE if an item was successfully received from the queue,"]
#[doc = " otherwise pdFALSE."]
#[doc = ""]
#[doc = " Example usage:"]
#[doc = " @code{c}"]
#[doc = " QueueHandle_t xQueue;"]
#[doc = ""]
#[doc = " // Function to create a queue and post some values."]
#[doc = " void vAFunction( void *pvParameters )"]
#[doc = " {"]
#[doc = " char cValueToPost;"]
#[doc = " const TickType_t xTicksToWait = ( TickType_t )0xff;"]
#[doc = ""]
#[doc = " \t// Create a queue capable of containing 10 characters."]
#[doc = " \txQueue = xQueueCreate( 10, sizeof( char ) );"]
#[doc = " \tif( xQueue == 0 )"]
#[doc = " \t{"]
#[doc = " \t\t// Failed to create the queue."]
#[doc = " \t}"]
#[doc = ""]
#[doc = " \t// ..."]
#[doc = ""]
#[doc = " \t// Post some characters that will be used within an ISR. If the queue"]
#[doc = " \t// is full then this task will block for xTicksToWait ticks."]
#[doc = " \tcValueToPost = 'a';"]
#[doc = " \txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );"]
#[doc = " \tcValueToPost = 'b';"]
#[doc = " \txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );"]
#[doc = ""]
#[doc = " \t// ... keep posting characters ... this task may block when the queue"]
#[doc = " \t// becomes full."]
#[doc = ""]
#[doc = " \tcValueToPost = 'c';"]
#[doc = " \txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );"]
#[doc = " }"]
#[doc = ""]
#[doc = " // ISR that outputs all the characters received on the queue."]
#[doc = " void vISR_Routine( void )"]
#[doc = " {"]
#[doc = " BaseType_t xTaskWokenByReceive = pdFALSE;"]
#[doc = " char cRxedChar;"]
#[doc = ""]
#[doc = " \twhile( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )"]
#[doc = " \t{"]
#[doc = " \t\t// A character was received. Output the character now."]
#[doc = " \t\tvOutputCharacter( cRxedChar );"]
#[doc = ""]
#[doc = " \t\t// If removing the character from the queue woke the task that was"]
#[doc = " \t\t// posting onto the queue cTaskWokenByReceive will have been set to"]
#[doc = " \t\t// pdTRUE. No matter how many times this loop iterates only one"]
#[doc = " \t\t// task will be woken."]
#[doc = " \t}"]
#[doc = ""]
#[doc = " \tif( cTaskWokenByPost != ( char ) pdFALSE;"]
#[doc = " \t{"]
#[doc = " \t\ttaskYIELD ();"]
#[doc = " \t}"]
#[doc = " }"]
#[doc = " @endcode"]
#[doc = " \\ingroup QueueManagement"]
pub fn xQueueReceiveFromISR(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
pxHigherPriorityTaskWoken: *mut BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = "@{*/"]
#[doc = " Utilities to query queues that are safe to use from an ISR. These utilities"]
#[doc = " should be used only from witin an ISR, or within a critical section."]
pub fn xQueueIsQueueEmptyFromISR(xQueue: QueueHandle_t) -> BaseType_t;
}
extern "C" {
pub fn xQueueIsQueueFullFromISR(xQueue: QueueHandle_t) -> BaseType_t;
}
extern "C" {
pub fn uxQueueMessagesWaitingFromISR(xQueue: QueueHandle_t) -> UBaseType_t;
}
extern "C" {
#[doc = " @cond */"]
#[doc = " xQueueAltGenericSend() is an alternative version of xQueueGenericSend()."]
#[doc = " Likewise xQueueAltGenericReceive() is an alternative version of"]
#[doc = " xQueueGenericReceive()."]
#[doc = ""]
#[doc = " The source code that implements the alternative (Alt) API is much"]
#[doc = " simpler\tbecause it executes everything from within a critical section."]
#[doc = " This is\tthe approach taken by many other RTOSes, but FreeRTOS.org has the"]
#[doc = " preferred fully featured API too. The fully featured API has more"]
#[doc = " complex\tcode that takes longer to execute, but makes much less use of"]
#[doc = " critical sections. Therefore the alternative API sacrifices interrupt"]
#[doc = " responsiveness to gain execution speed, whereas the fully featured API"]
#[doc = " sacrifices execution speed to ensure better interrupt responsiveness."]
pub fn xQueueAltGenericSend(
xQueue: QueueHandle_t,
pvItemToQueue: *const ::std::os::raw::c_void,
xTicksToWait: TickType_t,
xCopyPosition: BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueAltGenericReceive(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
xTicksToWait: TickType_t,
xJustPeeking: BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueCRSendFromISR(
xQueue: QueueHandle_t,
pvItemToQueue: *const ::std::os::raw::c_void,
xCoRoutinePreviouslyWoken: BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueCRReceiveFromISR(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
pxTaskWoken: *mut BaseType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueCRSend(
xQueue: QueueHandle_t,
pvItemToQueue: *const ::std::os::raw::c_void,
xTicksToWait: TickType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueCRReceive(
xQueue: QueueHandle_t,
pvBuffer: *mut ::std::os::raw::c_void,
xTicksToWait: TickType_t,
) -> BaseType_t;
}
extern "C" {
pub fn xQueueCreateMutex(ucQueueType: u8) -> QueueHandle_t;
}
extern "C" {
pub fn xQueueCreateMutexStatic(
ucQueueType: u8,
pxStaticQueue: *mut StaticQueue_t,
) -> QueueHandle_t;
}
extern "C" {
pub fn xQueueCreateCountingSemaphore(
uxMaxCount: UBaseType_t,
uxInitialCount: UBaseType_t,
) -> QueueHandle_t;
}
extern "C" {
pub fn xQueueCreateCountingSemaphoreStatic(
uxMaxCount: UBaseType_t,
uxInitialCount: UBaseType_t,
pxStaticQueue: *mut StaticQueue_t,
) -> QueueHandle_t;
}
extern "C" {
pub fn xQueueGetMutexHolder(xSemaphore: QueueHandle_t) -> *mut ::std::os::raw::c_void;
}
extern "C" {
pub fn xQueueTakeMutexRecursive(xMutex: QueueHandle_t, xTicksToWait: TickType_t) -> BaseType_t;
}
extern "C" {
pub fn xQueueGiveMutexRecursive(pxMutex: QueueHandle_t) -> BaseType_t;
}
extern "C" {
pub fn xQueueGenericCreate(
uxQueueLength: UBaseType_t,
uxItemSize: UBaseType_t,
ucQueueType: u8,
) -> QueueHandle_t;
}
extern "C" {
#[doc = " Queue sets provide a mechanism to allow a task to block (pend) on a read"]
#[doc = " operation from multiple queues or semaphores simultaneously."]
#[doc = ""]
#[doc = " See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this"]
#[doc = " function."]
#[doc = ""]
#[doc = " A queue set must be explicitly created using a call to xQueueCreateSet()"]
#[doc = " before it can be used. Once created, standard FreeRTOS queues and semaphores"]
#[doc = " can be added to the set using calls to xQueueAddToSet()."]
#[doc = " xQueueSelectFromSet() is then used to determine which, if any, of the queues"]
#[doc = " or semaphores contained in the set is in a state where a queue read or"]
#[doc = " semaphore take operation would be successful."]
#[doc = ""]
#[doc = " Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html"]
#[doc = " for reasons why queue sets are very rarely needed in practice as there are"]
#[doc = " simpler methods of blocking on multiple objects."]
#[doc = ""]
#[doc = " Note 2: Blocking on a queue set that contains a mutex will not cause the"]
#[doc = " mutex holder to inherit the priority of the blocked task."]
#[doc = ""]
#[doc = " Note 3: An additional 4 bytes of RAM is required for each space in a every"]
#[doc = " queue added to a queue set. Therefore counting semaphores that have a high"]
#[doc = " maximum count value should not be added to a queue set."]
#[doc = ""]
#[doc = " Note 4: A receive (in the case of a queue) or take (in the case of a"]
#[doc = " semaphore) operation must not be performed on a member of a queue set unless"]
#[doc = " a call to xQueueSelectFromSet() has first returned a handle to that set member."]
#[doc = ""]
#[doc = " @param uxEventQueueLength Queue sets store events that occur on"]
#[doc = " the queues and semaphores contained in the set. uxEventQueueLength specifies"]
#[doc = " the maximum number of events that can be queued at once. To be absolutely"]
#[doc = " certain that events are not lost uxEventQueueLength should be set to the"]
#[doc = " total sum of the length of the queues added to the set, where binary"]
#[doc = " semaphores and mutexes have a length of 1, and counting semaphores have a"]
#[doc = " length set by their maximum count value. Examples:"]
#[doc = " + If a queue set is to hold a queue of length 5, another queue of length 12,"]
#[doc = " and a binary semaphore, then uxEventQueueLength should be set to"]
#[doc = " (5 + 12 + 1), or 18."]
#[doc = " + If a queue set is to hold three binary semaphores then uxEventQueueLength"]
#[doc = " should be set to (1 + 1 + 1 ), or 3."]
#[doc = " + If a queue set is to hold a counting semaphore that has a maximum count of"]
#[doc = " 5, and a counting semaphore that has a maximum count of 3, then"]
#[doc = " uxEventQueueLength should be set to (5 + 3), or 8."]
#[doc = ""]
#[doc = " @return If the queue set is created successfully then a handle to the created"]
#[doc = " queue set is returned. Otherwise NULL is returned."]
pub fn xQueueCreateSet(uxEventQueueLength: UBaseType_t) -> QueueSetHandle_t;
}
extern "C" {
#[doc = " Adds a queue or semaphore to a queue set that was previously created by a"]
#[doc = " call to xQueueCreateSet()."]
#[doc = ""]
#[doc = " See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this"]
#[doc = " function."]
#[doc = ""]
#[doc = " Note 1: A receive (in the case of a queue) or take (in the case of a"]
#[doc = " semaphore) operation must not be performed on a member of a queue set unless"]
#[doc = " a call to xQueueSelectFromSet() has first returned a handle to that set member."]
#[doc = ""]
#[doc = " @param xQueueOrSemaphore The handle of the queue or semaphore being added to"]
#[doc = " the queue set (cast to an QueueSetMemberHandle_t type)."]
#[doc = ""]
#[doc = " @param xQueueSet The handle of the queue set to which the queue or semaphore"]
#[doc = " is being added."]
#[doc = ""]
#[doc = " @return If the queue or semaphore was successfully added to the queue set"]
#[doc = " then pdPASS is returned. If the queue could not be successfully added to the"]
#[doc = " queue set because it is already a member of a different queue set then pdFAIL"]
#[doc = " is returned."]
pub fn xQueueAddToSet(
xQueueOrSemaphore: QueueSetMemberHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " Removes a queue or semaphore from a queue set. A queue or semaphore can only"]
#[doc = " be removed from a set if the queue or semaphore is empty."]
#[doc = ""]
#[doc = " See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this"]
#[doc = " function."]
#[doc = ""]
#[doc = " @param xQueueOrSemaphore The handle of the queue or semaphore being removed"]
#[doc = " from the queue set (cast to an QueueSetMemberHandle_t type)."]
#[doc = ""]
#[doc = " @param xQueueSet The handle of the queue set in which the queue or semaphore"]
#[doc = " is included."]
#[doc = ""]
#[doc = " @return If the queue or semaphore was successfully removed from the queue set"]
#[doc = " then pdPASS is returned. If the queue was not in the queue set, or the"]
#[doc = " queue (or semaphore) was not empty, then pdFAIL is returned."]
pub fn xQueueRemoveFromSet(
xQueueOrSemaphore: QueueSetMemberHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " xQueueSelectFromSet() selects from the members of a queue set a queue or"]
#[doc = " semaphore that either contains data (in the case of a queue) or is available"]
#[doc = " to take (in the case of a semaphore). xQueueSelectFromSet() effectively"]
#[doc = " allows a task to block (pend) on a read operation on all the queues and"]
#[doc = " semaphores in a queue set simultaneously."]
#[doc = ""]
#[doc = " See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this"]
#[doc = " function."]
#[doc = ""]
#[doc = " Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html"]
#[doc = " for reasons why queue sets are very rarely needed in practice as there are"]
#[doc = " simpler methods of blocking on multiple objects."]
#[doc = ""]
#[doc = " Note 2: Blocking on a queue set that contains a mutex will not cause the"]
#[doc = " mutex holder to inherit the priority of the blocked task."]
#[doc = ""]
#[doc = " Note 3: A receive (in the case of a queue) or take (in the case of a"]
#[doc = " semaphore) operation must not be performed on a member of a queue set unless"]
#[doc = " a call to xQueueSelectFromSet() has first returned a handle to that set member."]
#[doc = ""]
#[doc = " @param xQueueSet The queue set on which the task will (potentially) block."]
#[doc = ""]
#[doc = " @param xTicksToWait The maximum time, in ticks, that the calling task will"]
#[doc = " remain in the Blocked state (with other tasks executing) to wait for a member"]
#[doc = " of the queue set to be ready for a successful queue read or semaphore take"]
#[doc = " operation."]
#[doc = ""]
#[doc = " @return xQueueSelectFromSet() will return the handle of a queue (cast to"]
#[doc = " a QueueSetMemberHandle_t type) contained in the queue set that contains data,"]
#[doc = " or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained"]
#[doc = " in the queue set that is available, or NULL if no such queue or semaphore"]
#[doc = " exists before before the specified block time expires."]
pub fn xQueueSelectFromSet(
xQueueSet: QueueSetHandle_t,
xTicksToWait: TickType_t,
) -> QueueSetMemberHandle_t;
}
extern "C" {
#[doc = " A version of xQueueSelectFromSet() that can be used from an ISR."]
pub fn xQueueSelectFromSetFromISR(xQueueSet: QueueSetHandle_t) -> QueueSetMemberHandle_t;
}
extern "C" {
#[doc = " @cond"]
pub fn vQueueWaitForMessageRestricted(xQueue: QueueHandle_t, xTicksToWait: TickType_t);
}
extern "C" {
pub fn xQueueGenericReset(xQueue: QueueHandle_t, xNewQueue: BaseType_t) -> BaseType_t;
}
extern "C" {
pub fn vQueueSetQueueNumber(xQueue: QueueHandle_t, uxQueueNumber: UBaseType_t);
}
extern "C" {
pub fn uxQueueGetQueueNumber(xQueue: QueueHandle_t) -> UBaseType_t;
}
extern "C" {
pub fn ucQueueGetQueueType(xQueue: QueueHandle_t) -> u8;
}
pub type SemaphoreHandle_t = QueueHandle_t;
#[doc = " Type by which ring buffers are referenced. For example, a call to xRingbufferCreate()"]
#[doc = " returns a RingbufHandle_t variable that can then be used as a parameter to"]
#[doc = " xRingbufferSend(), xRingbufferReceive(), etc."]
pub type RingbufHandle_t = *mut ::std::os::raw::c_void;
#[doc = " No-split buffers will only store an item in contiguous memory and will"]
#[doc = " never split an item. Each item requires an 8 byte overhead for a header"]
#[doc = " and will always internally occupy a 32-bit aligned size of space."]
pub const ringbuf_type_t_RINGBUF_TYPE_NOSPLIT: ringbuf_type_t = 0;
#[doc = " Allow-split buffers will split an item into two parts if necessary in"]
#[doc = " order to store it. Each item requires an 8 byte overhead for a header,"]
#[doc = " splitting incurs an extra header. Each item will always internally occupy"]
#[doc = " a 32-bit aligned size of space."]
pub const ringbuf_type_t_RINGBUF_TYPE_ALLOWSPLIT: ringbuf_type_t = 1;
#[doc = " Byte buffers store data as a sequence of bytes and do not maintain separate"]
#[doc = " items, therefore byte buffers have no overhead. All data is stored as a"]
#[doc = " sequence of byte and any number of bytes can be sent or retrieved each"]
#[doc = " time."]
pub const ringbuf_type_t_RINGBUF_TYPE_BYTEBUF: ringbuf_type_t = 2;
pub type ringbuf_type_t = u32;
extern "C" {
#[doc = " @brief Create a ring buffer"]
#[doc = ""]
#[doc = " @param[in] xBufferSize Size of the buffer in bytes. Note that items require"]
#[doc = " space for overhead in no-split/allow-split buffers"]
#[doc = " @param[in] xBufferType Type of ring buffer, see documentation."]
#[doc = ""]
#[doc = " @note xBufferSize of no-split/allow-split buffers will be rounded up to the nearest 32-bit aligned size."]
#[doc = ""]
#[doc = " @return A handle to the created ring buffer, or NULL in case of error."]
pub fn xRingbufferCreate(xBufferSize: usize, xBufferType: ringbuf_type_t) -> RingbufHandle_t;
}
extern "C" {
#[doc = " @brief Create a ring buffer of type RINGBUF_TYPE_NOSPLIT for a fixed item_size"]
#[doc = ""]
#[doc = " This API is similar to xRingbufferCreate(), but it will internally allocate"]
#[doc = " additional space for the headers."]
#[doc = ""]
#[doc = " @param[in] xItemSize Size of each item to be put into the ring buffer"]
#[doc = " @param[in] xItemNum Maximum number of items the buffer needs to hold simultaneously"]
#[doc = ""]
#[doc = " @return A RingbufHandle_t handle to the created ring buffer, or NULL in case of error."]
pub fn xRingbufferCreateNoSplit(xItemSize: usize, xItemNum: usize) -> RingbufHandle_t;
}
extern "C" {
#[doc = " @brief Insert an item into the ring buffer"]
#[doc = ""]
#[doc = " Attempt to insert an item into the ring buffer. This function will block until"]
#[doc = " enough free space is available or until it timesout."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to insert the item into"]
#[doc = " @param[in] pvItem Pointer to data to insert. NULL is allowed if xItemSize is 0."]
#[doc = " @param[in] xItemSize Size of data to insert."]
#[doc = " @param[in] xTicksToWait Ticks to wait for room in the ring buffer."]
#[doc = ""]
#[doc = " @note For no-split/allow-split ring buffers, the actual size of memory that"]
#[doc = " the item will occupy will be rounded up to the nearest 32-bit aligned"]
#[doc = " size. This is done to ensure all items are always stored in 32-bit"]
#[doc = " aligned fashion."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE if succeeded"]
#[doc = " - pdFALSE on time-out or when the data is larger than the maximum permissible size of the buffer"]
pub fn xRingbufferSend(
xRingbuffer: RingbufHandle_t,
pvItem: *const ::std::os::raw::c_void,
xItemSize: usize,
xTicksToWait: TickType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Insert an item into the ring buffer in an ISR"]
#[doc = ""]
#[doc = " Attempt to insert an item into the ring buffer from an ISR. This function"]
#[doc = " will return immediately if there is insufficient free space in the buffer."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to insert the item into"]
#[doc = " @param[in] pvItem Pointer to data to insert. NULL is allowed if xItemSize is 0."]
#[doc = " @param[in] xItemSize Size of data to insert."]
#[doc = " @param[out] pxHigherPriorityTaskWoken Value pointed to will be set to pdTRUE if the function woke up a higher priority task."]
#[doc = ""]
#[doc = " @note For no-split/allow-split ring buffers, the actual size of memory that"]
#[doc = " the item will occupy will be rounded up to the nearest 32-bit aligned"]
#[doc = " size. This is done to ensure all items are always stored in 32-bit"]
#[doc = " aligned fashion."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE if succeeded"]
#[doc = " - pdFALSE when the ring buffer does not have space."]
pub fn xRingbufferSendFromISR(
xRingbuffer: RingbufHandle_t,
pvItem: *const ::std::os::raw::c_void,
xItemSize: usize,
pxHigherPriorityTaskWoken: *mut BaseType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Retrieve an item from the ring buffer"]
#[doc = ""]
#[doc = " Attempt to retrieve an item from the ring buffer. This function will block"]
#[doc = " until an item is available or until it timesout."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] pxItemSize Pointer to a variable to which the size of the retrieved item will be written."]
#[doc = " @param[in] xTicksToWait Ticks to wait for items in the ring buffer."]
#[doc = ""]
#[doc = " @note A call to vRingbufferReturnItem() is required after this to free the item retrieved."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item."]
#[doc = " - NULL on timeout, *pxItemSize is untouched in that case."]
pub fn xRingbufferReceive(
xRingbuffer: RingbufHandle_t,
pxItemSize: *mut usize,
xTicksToWait: TickType_t,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Retrieve an item from the ring buffer in an ISR"]
#[doc = ""]
#[doc = " Attempt to retrieve an item from the ring buffer. This function returns immediately"]
#[doc = " if there are no items available for retrieval"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] pxItemSize Pointer to a variable to which the size of the"]
#[doc = " retrieved item will be written."]
#[doc = ""]
#[doc = " @note A call to vRingbufferReturnItemFromISR() is required after this to free the item retrieved."]
#[doc = " @note Byte buffers do not allow multiple retrievals before returning an item"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item."]
#[doc = " - NULL when the ring buffer is empty, *pxItemSize is untouched in that case."]
pub fn xRingbufferReceiveFromISR(
xRingbuffer: RingbufHandle_t,
pxItemSize: *mut usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Retrieve a split item from an allow-split ring buffer"]
#[doc = ""]
#[doc = " Attempt to retrieve a split item from an allow-split ring buffer. If the item"]
#[doc = " is not split, only a single item is retried. If the item is split, both parts"]
#[doc = " will be retrieved. This function will block until an item is available or"]
#[doc = " until it timesout."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] ppvHeadItem Double pointer to first part (set to NULL if no items were retrieved)"]
#[doc = " @param[out] ppvTailItem Double pointer to second part (set to NULL if item is not split)"]
#[doc = " @param[out] pxHeadItemSize Pointer to size of first part (unmodified if no items were retrieved)"]
#[doc = " @param[out] pxTailItemSize Pointer to size of second part (unmodified if item is not split)"]
#[doc = " @param[in] xTicksToWait Ticks to wait for items in the ring buffer."]
#[doc = ""]
#[doc = " @note Call(s) to vRingbufferReturnItem() is required after this to free up the item(s) retrieved."]
#[doc = " @note This function should only be called on allow-split buffers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE if an item (split or unsplit) was retrieved"]
#[doc = " - pdFALSE when no item was retrieved"]
pub fn xRingbufferReceiveSplit(
xRingbuffer: RingbufHandle_t,
ppvHeadItem: *mut *mut ::std::os::raw::c_void,
ppvTailItem: *mut *mut ::std::os::raw::c_void,
pxHeadItemSize: *mut usize,
pxTailItemSize: *mut usize,
xTicksToWait: TickType_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Retrieve a split item from an allow-split ring buffer in an ISR"]
#[doc = ""]
#[doc = " Attempt to retrieve a split item from an allow-split ring buffer. If the item"]
#[doc = " is not split, only a single item is retried. If the item is split, both parts"]
#[doc = " will be retrieved. This function returns immediately if there are no items"]
#[doc = " available for retrieval"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] ppvHeadItem Double pointer to first part (set to NULL if no items were retrieved)"]
#[doc = " @param[out] ppvTailItem Double pointer to second part (set to NULL if item is not split)"]
#[doc = " @param[out] pxHeadItemSize Pointer to size of first part (unmodified if no items were retrieved)"]
#[doc = " @param[out] pxTailItemSize Pointer to size of second part (unmodified if item is not split)"]
#[doc = ""]
#[doc = " @note Calls to vRingbufferReturnItemFromISR() is required after this to free up the item(s) retrieved."]
#[doc = " @note This function should only be called on allow-split buffers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE if an item (split or unsplit) was retrieved"]
#[doc = " - pdFALSE when no item was retrieved"]
pub fn xRingbufferReceiveSplitFromISR(
xRingbuffer: RingbufHandle_t,
ppvHeadItem: *mut *mut ::std::os::raw::c_void,
ppvTailItem: *mut *mut ::std::os::raw::c_void,
pxHeadItemSize: *mut usize,
pxTailItemSize: *mut usize,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Retrieve bytes from a byte buffer, specifying the maximum amount of bytes to retrieve"]
#[doc = ""]
#[doc = " Attempt to retrieve data from a byte buffer whilst specifying a maximum number"]
#[doc = " of bytes to retrieve. This function will block until there is data available"]
#[doc = " for retrieval or until it timesout."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] pxItemSize Pointer to a variable to which the size of the retrieved item will be written."]
#[doc = " @param[in] xTicksToWait Ticks to wait for items in the ring buffer."]
#[doc = " @param[in] xMaxSize Maximum number of bytes to return."]
#[doc = ""]
#[doc = " @note A call to vRingbufferReturnItem() is required after this to free up the data retrieved."]
#[doc = " @note This function should only be called on byte buffers"]
#[doc = " @note Byte buffers do not allow multiple retrievals before returning an item"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Pointer to the retrieved item on success; *pxItemSize filled with"]
#[doc = " the length of the item."]
#[doc = " - NULL on timeout, *pxItemSize is untouched in that case."]
pub fn xRingbufferReceiveUpTo(
xRingbuffer: RingbufHandle_t,
pxItemSize: *mut usize,
xTicksToWait: TickType_t,
xMaxSize: usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Retrieve bytes from a byte buffer, specifying the maximum amount of"]
#[doc = " bytes to retrieve. Call this from an ISR."]
#[doc = ""]
#[doc = " Attempt to retrieve bytes from a byte buffer whilst specifying a maximum number"]
#[doc = " of bytes to retrieve. This function will return immediately if there is no data"]
#[doc = " available for retrieval."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to retrieve the item from"]
#[doc = " @param[out] pxItemSize Pointer to a variable to which the size of the retrieved item will be written."]
#[doc = " @param[in] xMaxSize Maximum number of bytes to return."]
#[doc = ""]
#[doc = " @note A call to vRingbufferReturnItemFromISR() is required after this to free up the data received."]
#[doc = " @note This function should only be called on byte buffers"]
#[doc = " @note Byte buffers do not allow multiple retrievals before returning an item"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Pointer to the retrieved item on success; *pxItemSize filled with"]
#[doc = " the length of the item."]
#[doc = " - NULL when the ring buffer is empty, *pxItemSize is untouched in that case."]
pub fn xRingbufferReceiveUpToFromISR(
xRingbuffer: RingbufHandle_t,
pxItemSize: *mut usize,
xMaxSize: usize,
) -> *mut ::std::os::raw::c_void;
}
extern "C" {
#[doc = " @brief Return a previously-retrieved item to the ring buffer"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer the item was retrieved from"]
#[doc = " @param[in] pvItem Item that was received earlier"]
#[doc = ""]
#[doc = " @note If a split item is retrieved, both parts should be returned by calling this function twice"]
pub fn vRingbufferReturnItem(xRingbuffer: RingbufHandle_t, pvItem: *mut ::std::os::raw::c_void);
}
extern "C" {
#[doc = " @brief Return a previously-retrieved item to the ring buffer from an ISR"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer the item was retrieved from"]
#[doc = " @param[in] pvItem Item that was received earlier"]
#[doc = " @param[out] pxHigherPriorityTaskWoken Value pointed to will be set to pdTRUE"]
#[doc = " if the function woke up a higher priority task."]
#[doc = ""]
#[doc = " @note If a split item is retrieved, both parts should be returned by calling this function twice"]
pub fn vRingbufferReturnItemFromISR(
xRingbuffer: RingbufHandle_t,
pvItem: *mut ::std::os::raw::c_void,
pxHigherPriorityTaskWoken: *mut BaseType_t,
);
}
extern "C" {
#[doc = " @brief Delete a ring buffer"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to delete"]
pub fn vRingbufferDelete(xRingbuffer: RingbufHandle_t);
}
extern "C" {
#[doc = " @brief Get maximum size of an item that can be placed in the ring buffer"]
#[doc = ""]
#[doc = " This function returns the maximum size an item can have if it was placed in"]
#[doc = " an empty ring buffer."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to query"]
#[doc = ""]
#[doc = " @return Maximum size, in bytes, of an item that can be placed in a ring buffer."]
pub fn xRingbufferGetMaxItemSize(xRingbuffer: RingbufHandle_t) -> usize;
}
extern "C" {
#[doc = " @brief Get current free size available for an item/data in the buffer"]
#[doc = ""]
#[doc = " This gives the real time free space available for an item/data in the ring"]
#[doc = " buffer. This represents the maximum size an item/data can have if it was"]
#[doc = " currently sent to the ring buffer."]
#[doc = ""]
#[doc = " @warning This API is not thread safe. So, if multiple threads are accessing"]
#[doc = " the same ring buffer, it is the application's responsibility to"]
#[doc = " ensure atomic access to this API and the subsequent Send"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to query"]
#[doc = ""]
#[doc = " @return Current free size, in bytes, available for an entry"]
pub fn xRingbufferGetCurFreeSize(xRingbuffer: RingbufHandle_t) -> usize;
}
extern "C" {
#[doc = " @brief Add the ring buffer's read semaphore to a queue set."]
#[doc = ""]
#[doc = " The ring buffer's read semaphore indicates that data has been written"]
#[doc = " to the ring buffer. This function adds the ring buffer's read semaphore to"]
#[doc = " a queue set."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to add to the queue set"]
#[doc = " @param[in] xQueueSet Queue set to add the ring buffer's read semaphore to"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE on success, pdFALSE otherwise"]
pub fn xRingbufferAddToQueueSetRead(
xRingbuffer: RingbufHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Check if the selected queue set member is the ring buffer's read semaphore"]
#[doc = ""]
#[doc = " This API checks if queue set member returned from xQueueSelectFromSet()"]
#[doc = " is the read semaphore of this ring buffer. If so, this indicates the ring buffer"]
#[doc = " has items waiting to be retrieved."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer which should be checked"]
#[doc = " @param[in] xMember Member returned from xQueueSelectFromSet"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE when semaphore belongs to ring buffer"]
#[doc = " - pdFALSE otherwise."]
pub fn xRingbufferCanRead(
xRingbuffer: RingbufHandle_t,
xMember: QueueSetMemberHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Remove the ring buffer's read semaphore from a queue set."]
#[doc = ""]
#[doc = " This specifically removes a ring buffer's read semaphore from a queue set. The"]
#[doc = " read semaphore is used to indicate when data has been written to the ring buffer"]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to remove from the queue set"]
#[doc = " @param[in] xQueueSet Queue set to remove the ring buffer's read semaphore from"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - pdTRUE on success"]
#[doc = " - pdFALSE otherwise"]
pub fn xRingbufferRemoveFromQueueSetRead(
xRingbuffer: RingbufHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
extern "C" {
#[doc = " @brief Get information about ring buffer status"]
#[doc = ""]
#[doc = " Get information of the a ring buffer's current status such as"]
#[doc = " free/read/write pointer positions, and number of items waiting to be retrieved."]
#[doc = " Arguments can be set to NULL if they are not required."]
#[doc = ""]
#[doc = " @param[in] xRingbuffer Ring buffer to remove from the queue set"]
#[doc = " @param[out] uxFree Pointer use to store free pointer position"]
#[doc = " @param[out] uxRead Pointer use to store read pointer position"]
#[doc = " @param[out] uxWrite Pointer use to store write pointer position"]
#[doc = " @param[out] uxItemsWaiting Pointer use to store number of items (bytes for byte buffer) waiting to be retrieved"]
pub fn vRingbufferGetInfo(
xRingbuffer: RingbufHandle_t,
uxFree: *mut UBaseType_t,
uxRead: *mut UBaseType_t,
uxWrite: *mut UBaseType_t,
uxItemsWaiting: *mut UBaseType_t,
);
}
extern "C" {
#[doc = " @brief Debugging function to print the internal pointers in the ring buffer"]
#[doc = ""]
#[doc = " @param xRingbuffer Ring buffer to show"]
pub fn xRingbufferPrintInfo(xRingbuffer: RingbufHandle_t);
}
extern "C" {
#[doc = " @cond"]
pub fn xRingbufferIsNextItemWrapped(xRingbuffer: RingbufHandle_t) -> bool;
}
extern "C" {
pub fn xRingbufferAddToQueueSetWrite(
xRingbuffer: RingbufHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
extern "C" {
pub fn xRingbufferRemoveFromQueueSetWrite(
xRingbuffer: RingbufHandle_t,
xQueueSet: QueueSetHandle_t,
) -> BaseType_t;
}
#[doc = "< I2C slave mode"]
pub const i2c_mode_t_I2C_MODE_SLAVE: i2c_mode_t = 0;
#[doc = "< I2C master mode"]
pub const i2c_mode_t_I2C_MODE_MASTER: i2c_mode_t = 1;
pub const i2c_mode_t_I2C_MODE_MAX: i2c_mode_t = 2;
pub type i2c_mode_t = u32;
#[doc = "< I2C write data"]
pub const i2c_rw_t_I2C_MASTER_WRITE: i2c_rw_t = 0;
#[doc = "< I2C read data"]
pub const i2c_rw_t_I2C_MASTER_READ: i2c_rw_t = 1;
pub type i2c_rw_t = u32;
#[doc = "< I2C data msb first"]
pub const i2c_trans_mode_t_I2C_DATA_MODE_MSB_FIRST: i2c_trans_mode_t = 0;
#[doc = "< I2C data lsb first"]
pub const i2c_trans_mode_t_I2C_DATA_MODE_LSB_FIRST: i2c_trans_mode_t = 1;
pub const i2c_trans_mode_t_I2C_DATA_MODE_MAX: i2c_trans_mode_t = 2;
pub type i2c_trans_mode_t = u32;
#[doc = "<I2C restart command"]
pub const i2c_opmode_t_I2C_CMD_RESTART: i2c_opmode_t = 0;
#[doc = "<I2C write command"]
pub const i2c_opmode_t_I2C_CMD_WRITE: i2c_opmode_t = 1;
#[doc = "<I2C read command"]
pub const i2c_opmode_t_I2C_CMD_READ: i2c_opmode_t = 2;
#[doc = "<I2C stop command"]
pub const i2c_opmode_t_I2C_CMD_STOP: i2c_opmode_t = 3;
#[doc = "<I2C end command"]
pub const i2c_opmode_t_I2C_CMD_END: i2c_opmode_t = 4;
pub type i2c_opmode_t = u32;
#[doc = "< I2C port 0"]
pub const i2c_port_t_I2C_NUM_0: i2c_port_t = 0;
#[doc = "< I2C port 1"]
pub const i2c_port_t_I2C_NUM_1: i2c_port_t = 1;
pub const i2c_port_t_I2C_NUM_MAX: i2c_port_t = 2;
pub type i2c_port_t = u32;
#[doc = "< I2C 7bit address for slave mode"]
pub const i2c_addr_mode_t_I2C_ADDR_BIT_7: i2c_addr_mode_t = 0;
#[doc = "< I2C 10bit address for slave mode"]
pub const i2c_addr_mode_t_I2C_ADDR_BIT_10: i2c_addr_mode_t = 1;
pub const i2c_addr_mode_t_I2C_ADDR_BIT_MAX: i2c_addr_mode_t = 2;
pub type i2c_addr_mode_t = u32;
#[doc = "< I2C ack for each byte read"]
pub const i2c_ack_type_t_I2C_MASTER_ACK: i2c_ack_type_t = 0;
#[doc = "< I2C nack for each byte read"]
pub const i2c_ack_type_t_I2C_MASTER_NACK: i2c_ack_type_t = 1;
#[doc = "< I2C nack for the last byte"]
pub const i2c_ack_type_t_I2C_MASTER_LAST_NACK: i2c_ack_type_t = 2;
pub const i2c_ack_type_t_I2C_MASTER_ACK_MAX: i2c_ack_type_t = 3;
pub type i2c_ack_type_t = u32;
#[doc = " @brief I2C initialization parameters"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct i2c_config_t {
#[doc = "< I2C mode"]
pub mode: i2c_mode_t,
#[doc = "< GPIO number for I2C sda signal"]
pub sda_io_num: gpio_num_t,
#[doc = "< Internal GPIO pull mode for I2C sda signal"]
pub sda_pullup_en: gpio_pullup_t,
#[doc = "< GPIO number for I2C scl signal"]
pub scl_io_num: gpio_num_t,
#[doc = "< Internal GPIO pull mode for I2C scl signal"]
pub scl_pullup_en: gpio_pullup_t,
pub __bindgen_anon_1: i2c_config_t__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union i2c_config_t__bindgen_ty_1 {
pub master: i2c_config_t__bindgen_ty_1__bindgen_ty_1,
pub slave: i2c_config_t__bindgen_ty_1__bindgen_ty_2,
_bindgen_union_align: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct i2c_config_t__bindgen_ty_1__bindgen_ty_1 {
#[doc = "< I2C clock frequency for master mode, (no higher than 1MHz for now)"]
pub clk_speed: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct i2c_config_t__bindgen_ty_1__bindgen_ty_2 {
#[doc = "< I2C 10bit address mode enable for slave mode"]
pub addr_10bit_en: u8,
#[doc = "< I2C address for slave mode"]
pub slave_addr: u16,
}
pub type i2c_cmd_handle_t = *mut ::std::os::raw::c_void;
extern "C" {
#[doc = " @brief I2C driver install"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param mode I2C mode( master or slave )"]
#[doc = " @param slv_rx_buf_len receiving buffer size for slave mode"]
#[doc = " @note"]
#[doc = " Only slave mode will use this value, driver will ignore this value in master mode."]
#[doc = " @param slv_tx_buf_len sending buffer size for slave mode"]
#[doc = " @note"]
#[doc = " Only slave mode will use this value, driver will ignore this value in master mode."]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @note"]
#[doc = " In master mode, if the cache is likely to be disabled(such as write flash) and the slave is time-sensitive,"]
#[doc = " `ESP_INTR_FLAG_IRAM` is suggested to be used. In this case, please use the memory allocated from internal RAM in i2c read and write function,"]
#[doc = " because we can not access the psram(if psram is enabled) in interrupt handle function when cache is disabled."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_FAIL Driver install error"]
pub fn i2c_driver_install(
i2c_num: i2c_port_t,
mode: i2c_mode_t,
slv_rx_buf_len: usize,
slv_tx_buf_len: usize,
intr_alloc_flags: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief I2C driver delete"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_driver_delete(i2c_num: i2c_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief I2C parameter initialization"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param i2c_conf pointer to I2C parameter settings"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_param_config(i2c_num: i2c_port_t, i2c_conf: *const i2c_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief reset I2C tx hardware fifo"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_reset_tx_fifo(i2c_num: i2c_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief reset I2C rx fifo"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_reset_rx_fifo(i2c_num: i2c_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief I2C isr handler register"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param fn isr handler function"]
#[doc = " @param arg parameter for isr handler function"]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @param handle handle return from esp_intr_alloc."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_isr_register(
i2c_num: i2c_port_t,
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut intr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief to delete and free I2C isr."]
#[doc = ""]
#[doc = " @param handle handle of isr."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_isr_free(handle: intr_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure GPIO signal for I2C sck and sda"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param sda_io_num GPIO number for I2C sda signal"]
#[doc = " @param scl_io_num GPIO number for I2C scl signal"]
#[doc = " @param sda_pullup_en Whether to enable the internal pullup for sda pin"]
#[doc = " @param scl_pullup_en Whether to enable the internal pullup for scl pin"]
#[doc = " @param mode I2C mode"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_pin(
i2c_num: i2c_port_t,
sda_io_num: ::std::os::raw::c_int,
scl_io_num: ::std::os::raw::c_int,
sda_pullup_en: gpio_pullup_t,
scl_pullup_en: gpio_pullup_t,
mode: i2c_mode_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Create and init I2C command link"]
#[doc = " @note"]
#[doc = " Before we build I2C command link, we need to call i2c_cmd_link_create() to create"]
#[doc = " a command link."]
#[doc = " After we finish sending the commands, we need to call i2c_cmd_link_delete() to"]
#[doc = " release and return the resources."]
#[doc = ""]
#[doc = " @return i2c command link handler"]
pub fn i2c_cmd_link_create() -> i2c_cmd_handle_t;
}
extern "C" {
#[doc = " @brief Free I2C command link"]
#[doc = " @note"]
#[doc = " Before we build I2C command link, we need to call i2c_cmd_link_create() to create"]
#[doc = " a command link."]
#[doc = " After we finish sending the commands, we need to call i2c_cmd_link_delete() to"]
#[doc = " release and return the resources."]
#[doc = ""]
#[doc = " @param cmd_handle I2C command handle"]
pub fn i2c_cmd_link_delete(cmd_handle: i2c_cmd_handle_t);
}
extern "C" {
#[doc = " @brief Queue command for I2C master to generate a start signal"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_start(cmd_handle: i2c_cmd_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue command for I2C master to write one byte to I2C bus"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = " @param data I2C one byte command to write to bus"]
#[doc = " @param ack_en enable ack check for master"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_write_byte(cmd_handle: i2c_cmd_handle_t, data: u8, ack_en: bool)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue command for I2C master to write buffer to I2C bus"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = " @param data data to send"]
#[doc = " @note"]
#[doc = " If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM."]
#[doc = " @param data_len data length"]
#[doc = " @param ack_en enable ack check for master"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_write(
cmd_handle: i2c_cmd_handle_t,
data: *mut u8,
data_len: usize,
ack_en: bool,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue command for I2C master to read one byte from I2C bus"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = " @param data pointer accept the data byte"]
#[doc = " @note"]
#[doc = " If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM."]
#[doc = " @param ack ack value for read command"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_read_byte(
cmd_handle: i2c_cmd_handle_t,
data: *mut u8,
ack: i2c_ack_type_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue command for I2C master to read data from I2C bus"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = " @param data data buffer to accept the data from bus"]
#[doc = " @note"]
#[doc = " If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM."]
#[doc = " @param data_len read data length"]
#[doc = " @param ack ack value for read command"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_read(
cmd_handle: i2c_cmd_handle_t,
data: *mut u8,
data_len: usize,
ack: i2c_ack_type_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue command for I2C master to generate a stop signal"]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = " Call i2c_master_cmd_begin() to send all queued commands"]
#[doc = ""]
#[doc = " @param cmd_handle I2C cmd link"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_master_stop(cmd_handle: i2c_cmd_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief I2C master send queued commands."]
#[doc = " This function will trigger sending all queued commands."]
#[doc = " The task will be blocked until all the commands have been sent out."]
#[doc = " The I2C APIs are not thread-safe, if you want to use one I2C port in different tasks,"]
#[doc = " you need to take care of the multi-thread issue."]
#[doc = " @note"]
#[doc = " Only call this function in I2C master mode"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param cmd_handle I2C command handler"]
#[doc = " @param ticks_to_wait maximum wait ticks."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_FAIL Sending command error, slave doesn't ACK the transfer."]
#[doc = " - ESP_ERR_INVALID_STATE I2C driver not installed or not in master mode."]
#[doc = " - ESP_ERR_TIMEOUT Operation timeout because the bus is busy."]
pub fn i2c_master_cmd_begin(
i2c_num: i2c_port_t,
cmd_handle: i2c_cmd_handle_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief I2C slave write data to internal ringbuffer, when tx fifo empty, isr will fill the hardware"]
#[doc = " fifo from the internal ringbuffer"]
#[doc = " @note"]
#[doc = " Only call this function in I2C slave mode"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param data data pointer to write into internal buffer"]
#[doc = " @param size data size"]
#[doc = " @param ticks_to_wait Maximum waiting ticks"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL(-1) Parameter error"]
#[doc = " - Others(>=0) The number of data bytes that pushed to the I2C slave buffer."]
pub fn i2c_slave_write_buffer(
i2c_num: i2c_port_t,
data: *mut u8,
size: ::std::os::raw::c_int,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief I2C slave read data from internal buffer. When I2C slave receive data, isr will copy received data"]
#[doc = " from hardware rx fifo to internal ringbuffer. Then users can read from internal ringbuffer."]
#[doc = " @note"]
#[doc = " Only call this function in I2C slave mode"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param data data pointer to write into internal buffer"]
#[doc = " @param max_size Maximum data size to read"]
#[doc = " @param ticks_to_wait Maximum waiting ticks"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL(-1) Parameter error"]
#[doc = " - Others(>=0) The number of data bytes that read from I2C slave buffer."]
pub fn i2c_slave_read_buffer(
i2c_num: i2c_port_t,
data: *mut u8,
max_size: usize,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief set I2C master clock period"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param high_period clock cycle number during SCL is high level, high_period is a 14 bit value"]
#[doc = " @param low_period clock cycle number during SCL is low level, low_period is a 14 bit value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_period(
i2c_num: i2c_port_t,
high_period: ::std::os::raw::c_int,
low_period: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C master clock period"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param high_period pointer to get clock cycle number during SCL is high level, will get a 14 bit value"]
#[doc = " @param low_period pointer to get clock cycle number during SCL is low level, will get a 14 bit value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_period(
i2c_num: i2c_port_t,
high_period: *mut ::std::os::raw::c_int,
low_period: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief enable hardware filter on I2C bus"]
#[doc = " Sometimes the I2C bus is disturbed by high frequency noise(about 20ns), or the rising edge of"]
#[doc = " the SCL clock is very slow, these may cause the master state machine broken. enable hardware"]
#[doc = " filter can filter out high frequency interference and make the master more stable."]
#[doc = " @note"]
#[doc = " Enable filter will slow the SCL clock."]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param cyc_num the APB cycles need to be filtered(0<= cyc_num <=7)."]
#[doc = " When the period of a pulse is less than cyc_num * APB_cycle, the I2C controller will ignore this pulse."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_filter_enable(i2c_num: i2c_port_t, cyc_num: u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief disable filter on I2C bus"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_filter_disable(i2c_num: i2c_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief set I2C master start signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param setup_time clock number between the falling-edge of SDA and rising-edge of SCL for start mark, it's a 10-bit value."]
#[doc = " @param hold_time clock num between the falling-edge of SDA and falling-edge of SCL for start mark, it's a 10-bit value."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_start_timing(
i2c_num: i2c_port_t,
setup_time: ::std::os::raw::c_int,
hold_time: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C master start signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param setup_time pointer to get setup time"]
#[doc = " @param hold_time pointer to get hold time"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_start_timing(
i2c_num: i2c_port_t,
setup_time: *mut ::std::os::raw::c_int,
hold_time: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief set I2C master stop signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param setup_time clock num between the rising-edge of SCL and the rising-edge of SDA, it's a 10-bit value."]
#[doc = " @param hold_time clock number after the STOP bit's rising-edge, it's a 14-bit value."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_stop_timing(
i2c_num: i2c_port_t,
setup_time: ::std::os::raw::c_int,
hold_time: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C master stop signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param setup_time pointer to get setup time."]
#[doc = " @param hold_time pointer to get hold time."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_stop_timing(
i2c_num: i2c_port_t,
setup_time: *mut ::std::os::raw::c_int,
hold_time: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief set I2C data signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param sample_time clock number I2C used to sample data on SDA after the rising-edge of SCL, it's a 10-bit value"]
#[doc = " @param hold_time clock number I2C used to hold the data after the falling-edge of SCL, it's a 10-bit value"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_data_timing(
i2c_num: i2c_port_t,
sample_time: ::std::os::raw::c_int,
hold_time: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C data signal timing"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param sample_time pointer to get sample time"]
#[doc = " @param hold_time pointer to get hold time"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_data_timing(
i2c_num: i2c_port_t,
sample_time: *mut ::std::os::raw::c_int,
hold_time: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief set I2C timeout value"]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param timeout timeout value for I2C bus (unit: APB 80Mhz clock cycle)"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_timeout(i2c_num: i2c_port_t, timeout: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C timeout value"]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param timeout pointer to get timeout value"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_timeout(i2c_num: i2c_port_t, timeout: *mut ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief set I2C data transfer mode"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param tx_trans_mode I2C sending data mode"]
#[doc = " @param rx_trans_mode I2C receving data mode"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_set_data_mode(
i2c_num: i2c_port_t,
tx_trans_mode: i2c_trans_mode_t,
rx_trans_mode: i2c_trans_mode_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief get I2C data transfer mode"]
#[doc = ""]
#[doc = " @param i2c_num I2C port number"]
#[doc = " @param tx_trans_mode pointer to get I2C sending data mode"]
#[doc = " @param rx_trans_mode pointer to get I2C receiving data mode"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2c_get_data_mode(
i2c_num: i2c_port_t,
tx_trans_mode: *mut i2c_trans_mode_t,
rx_trans_mode: *mut i2c_trans_mode_t,
) -> esp_err_t;
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_2 {
pub reserved_0: u32,
pub reserved_4: u32,
pub conf: _bindgen_ty_2__bindgen_ty_1,
pub int_raw: _bindgen_ty_2__bindgen_ty_2,
pub int_st: _bindgen_ty_2__bindgen_ty_3,
pub int_ena: _bindgen_ty_2__bindgen_ty_4,
pub int_clr: _bindgen_ty_2__bindgen_ty_5,
pub timing: _bindgen_ty_2__bindgen_ty_6,
pub fifo_conf: _bindgen_ty_2__bindgen_ty_7,
pub rx_eof_num: u32,
pub conf_single_data: u32,
pub conf_chan: _bindgen_ty_2__bindgen_ty_8,
pub out_link: _bindgen_ty_2__bindgen_ty_9,
pub in_link: _bindgen_ty_2__bindgen_ty_10,
pub out_eof_des_addr: u32,
pub in_eof_des_addr: u32,
pub out_eof_bfr_des_addr: u32,
pub ahb_test: _bindgen_ty_2__bindgen_ty_11,
pub in_link_dscr: u32,
pub in_link_dscr_bf0: u32,
pub in_link_dscr_bf1: u32,
pub out_link_dscr: u32,
pub out_link_dscr_bf0: u32,
pub out_link_dscr_bf1: u32,
pub lc_conf: _bindgen_ty_2__bindgen_ty_12,
pub out_fifo_push: _bindgen_ty_2__bindgen_ty_13,
pub in_fifo_pop: _bindgen_ty_2__bindgen_ty_14,
pub lc_state0: u32,
pub lc_state1: u32,
pub lc_hung_conf: _bindgen_ty_2__bindgen_ty_15,
pub reserved_78: u32,
pub reserved_7c: u32,
pub cvsd_conf0: _bindgen_ty_2__bindgen_ty_16,
pub cvsd_conf1: _bindgen_ty_2__bindgen_ty_17,
pub cvsd_conf2: _bindgen_ty_2__bindgen_ty_18,
pub plc_conf0: _bindgen_ty_2__bindgen_ty_19,
pub plc_conf1: _bindgen_ty_2__bindgen_ty_20,
pub plc_conf2: _bindgen_ty_2__bindgen_ty_21,
pub esco_conf0: _bindgen_ty_2__bindgen_ty_22,
pub sco_conf0: _bindgen_ty_2__bindgen_ty_23,
pub conf1: _bindgen_ty_2__bindgen_ty_24,
pub pd_conf: _bindgen_ty_2__bindgen_ty_25,
pub conf2: _bindgen_ty_2__bindgen_ty_26,
pub clkm_conf: _bindgen_ty_2__bindgen_ty_27,
pub sample_rate_conf: _bindgen_ty_2__bindgen_ty_28,
pub pdm_conf: _bindgen_ty_2__bindgen_ty_29,
pub pdm_freq_conf: _bindgen_ty_2__bindgen_ty_30,
pub state: _bindgen_ty_2__bindgen_ty_31,
pub reserved_c0: u32,
pub reserved_c4: u32,
pub reserved_c8: u32,
pub reserved_cc: u32,
pub reserved_d0: u32,
pub reserved_d4: u32,
pub reserved_d8: u32,
pub reserved_dc: u32,
pub reserved_e0: u32,
pub reserved_e4: u32,
pub reserved_e8: u32,
pub reserved_ec: u32,
pub reserved_f0: u32,
pub reserved_f4: u32,
pub reserved_f8: u32,
pub date: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_1 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn tx_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_fifo_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_fifo_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_fifo_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_fifo_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_slave_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_slave_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_slave_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_slave_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_right_first(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_right_first(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_right_first(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_right_first(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_msb_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_msb_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_msb_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_msb_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_short_sync(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_short_sync(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_short_sync(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_short_sync(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_mono(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_mono(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_mono(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_mono(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_msb_right(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_msb_right(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_msb_right(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_msb_right(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn sig_loopback(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_sig_loopback(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_reset: u32,
rx_reset: u32,
tx_fifo_reset: u32,
rx_fifo_reset: u32,
tx_start: u32,
rx_start: u32,
tx_slave_mod: u32,
rx_slave_mod: u32,
tx_right_first: u32,
rx_right_first: u32,
tx_msb_shift: u32,
rx_msb_shift: u32,
tx_short_sync: u32,
rx_short_sync: u32,
tx_mono: u32,
rx_mono: u32,
tx_msb_right: u32,
rx_msb_right: u32,
sig_loopback: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let tx_reset: u32 = unsafe { ::core::mem::transmute(tx_reset) };
tx_reset as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let rx_reset: u32 = unsafe { ::core::mem::transmute(rx_reset) };
rx_reset as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let tx_fifo_reset: u32 = unsafe { ::core::mem::transmute(tx_fifo_reset) };
tx_fifo_reset as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let rx_fifo_reset: u32 = unsafe { ::core::mem::transmute(rx_fifo_reset) };
rx_fifo_reset as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let tx_start: u32 = unsafe { ::core::mem::transmute(tx_start) };
tx_start as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let rx_start: u32 = unsafe { ::core::mem::transmute(rx_start) };
rx_start as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let tx_slave_mod: u32 = unsafe { ::core::mem::transmute(tx_slave_mod) };
tx_slave_mod as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let rx_slave_mod: u32 = unsafe { ::core::mem::transmute(rx_slave_mod) };
rx_slave_mod as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let tx_right_first: u32 = unsafe { ::core::mem::transmute(tx_right_first) };
tx_right_first as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let rx_right_first: u32 = unsafe { ::core::mem::transmute(rx_right_first) };
rx_right_first as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let tx_msb_shift: u32 = unsafe { ::core::mem::transmute(tx_msb_shift) };
tx_msb_shift as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let rx_msb_shift: u32 = unsafe { ::core::mem::transmute(rx_msb_shift) };
rx_msb_shift as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let tx_short_sync: u32 = unsafe { ::core::mem::transmute(tx_short_sync) };
tx_short_sync as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let rx_short_sync: u32 = unsafe { ::core::mem::transmute(rx_short_sync) };
rx_short_sync as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let tx_mono: u32 = unsafe { ::core::mem::transmute(tx_mono) };
tx_mono as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rx_mono: u32 = unsafe { ::core::mem::transmute(rx_mono) };
rx_mono as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let tx_msb_right: u32 = unsafe { ::core::mem::transmute(tx_msb_right) };
tx_msb_right as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rx_msb_right: u32 = unsafe { ::core::mem::transmute(rx_msb_right) };
rx_msb_right as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let sig_loopback: u32 = unsafe { ::core::mem::transmute(sig_loopback) };
sig_loopback as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_2 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn rx_take_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_take_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_put_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_put_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_take_data: u32,
tx_put_data: u32,
rx_wfull: u32,
rx_rempty: u32,
tx_wfull: u32,
tx_rempty: u32,
rx_hung: u32,
tx_hung: u32,
in_done: u32,
in_suc_eof: u32,
in_err_eof: u32,
out_done: u32,
out_eof: u32,
in_dscr_err: u32,
out_dscr_err: u32,
in_dscr_empty: u32,
out_total_eof: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rx_take_data: u32 = unsafe { ::core::mem::transmute(rx_take_data) };
rx_take_data as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let tx_put_data: u32 = unsafe { ::core::mem::transmute(tx_put_data) };
tx_put_data as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rx_wfull: u32 = unsafe { ::core::mem::transmute(rx_wfull) };
rx_wfull as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let rx_rempty: u32 = unsafe { ::core::mem::transmute(rx_rempty) };
rx_rempty as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let tx_wfull: u32 = unsafe { ::core::mem::transmute(tx_wfull) };
tx_wfull as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let tx_rempty: u32 = unsafe { ::core::mem::transmute(tx_rempty) };
tx_rempty as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let rx_hung: u32 = unsafe { ::core::mem::transmute(rx_hung) };
rx_hung as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let tx_hung: u32 = unsafe { ::core::mem::transmute(tx_hung) };
tx_hung as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let in_dscr_err: u32 = unsafe { ::core::mem::transmute(in_dscr_err) };
in_dscr_err as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let out_dscr_err: u32 = unsafe { ::core::mem::transmute(out_dscr_err) };
out_dscr_err as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let in_dscr_empty: u32 = unsafe { ::core::mem::transmute(in_dscr_empty) };
in_dscr_empty as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_3 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn rx_take_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_take_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_put_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_put_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_take_data: u32,
tx_put_data: u32,
rx_wfull: u32,
rx_rempty: u32,
tx_wfull: u32,
tx_rempty: u32,
rx_hung: u32,
tx_hung: u32,
in_done: u32,
in_suc_eof: u32,
in_err_eof: u32,
out_done: u32,
out_eof: u32,
in_dscr_err: u32,
out_dscr_err: u32,
in_dscr_empty: u32,
out_total_eof: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rx_take_data: u32 = unsafe { ::core::mem::transmute(rx_take_data) };
rx_take_data as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let tx_put_data: u32 = unsafe { ::core::mem::transmute(tx_put_data) };
tx_put_data as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rx_wfull: u32 = unsafe { ::core::mem::transmute(rx_wfull) };
rx_wfull as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let rx_rempty: u32 = unsafe { ::core::mem::transmute(rx_rempty) };
rx_rempty as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let tx_wfull: u32 = unsafe { ::core::mem::transmute(tx_wfull) };
tx_wfull as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let tx_rempty: u32 = unsafe { ::core::mem::transmute(tx_rempty) };
tx_rempty as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let rx_hung: u32 = unsafe { ::core::mem::transmute(rx_hung) };
rx_hung as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let tx_hung: u32 = unsafe { ::core::mem::transmute(tx_hung) };
tx_hung as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let in_dscr_err: u32 = unsafe { ::core::mem::transmute(in_dscr_err) };
in_dscr_err as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let out_dscr_err: u32 = unsafe { ::core::mem::transmute(out_dscr_err) };
out_dscr_err as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let in_dscr_empty: u32 = unsafe { ::core::mem::transmute(in_dscr_empty) };
in_dscr_empty as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_4 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn rx_take_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_take_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_put_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_put_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_take_data: u32,
tx_put_data: u32,
rx_wfull: u32,
rx_rempty: u32,
tx_wfull: u32,
tx_rempty: u32,
rx_hung: u32,
tx_hung: u32,
in_done: u32,
in_suc_eof: u32,
in_err_eof: u32,
out_done: u32,
out_eof: u32,
in_dscr_err: u32,
out_dscr_err: u32,
in_dscr_empty: u32,
out_total_eof: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rx_take_data: u32 = unsafe { ::core::mem::transmute(rx_take_data) };
rx_take_data as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let tx_put_data: u32 = unsafe { ::core::mem::transmute(tx_put_data) };
tx_put_data as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rx_wfull: u32 = unsafe { ::core::mem::transmute(rx_wfull) };
rx_wfull as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let rx_rempty: u32 = unsafe { ::core::mem::transmute(rx_rempty) };
rx_rempty as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let tx_wfull: u32 = unsafe { ::core::mem::transmute(tx_wfull) };
tx_wfull as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let tx_rempty: u32 = unsafe { ::core::mem::transmute(tx_rempty) };
tx_rempty as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let rx_hung: u32 = unsafe { ::core::mem::transmute(rx_hung) };
rx_hung as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let tx_hung: u32 = unsafe { ::core::mem::transmute(tx_hung) };
tx_hung as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let in_dscr_err: u32 = unsafe { ::core::mem::transmute(in_dscr_err) };
in_dscr_err as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let out_dscr_err: u32 = unsafe { ::core::mem::transmute(out_dscr_err) };
out_dscr_err as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let in_dscr_empty: u32 = unsafe { ::core::mem::transmute(in_dscr_empty) };
in_dscr_empty as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_5 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn take_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_take_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn put_data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_put_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_wfull(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_wfull(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_rempty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_rempty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_hung(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_hung(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_dscr_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_dscr_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
take_data: u32,
put_data: u32,
rx_wfull: u32,
rx_rempty: u32,
tx_wfull: u32,
tx_rempty: u32,
rx_hung: u32,
tx_hung: u32,
in_done: u32,
in_suc_eof: u32,
in_err_eof: u32,
out_done: u32,
out_eof: u32,
in_dscr_err: u32,
out_dscr_err: u32,
in_dscr_empty: u32,
out_total_eof: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let take_data: u32 = unsafe { ::core::mem::transmute(take_data) };
take_data as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let put_data: u32 = unsafe { ::core::mem::transmute(put_data) };
put_data as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rx_wfull: u32 = unsafe { ::core::mem::transmute(rx_wfull) };
rx_wfull as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let rx_rempty: u32 = unsafe { ::core::mem::transmute(rx_rempty) };
rx_rempty as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let tx_wfull: u32 = unsafe { ::core::mem::transmute(tx_wfull) };
tx_wfull as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let tx_rempty: u32 = unsafe { ::core::mem::transmute(tx_rempty) };
tx_rempty as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let rx_hung: u32 = unsafe { ::core::mem::transmute(rx_hung) };
rx_hung as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let tx_hung: u32 = unsafe { ::core::mem::transmute(tx_hung) };
tx_hung as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let in_dscr_err: u32 = unsafe { ::core::mem::transmute(in_dscr_err) };
in_dscr_err as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let out_dscr_err: u32 = unsafe { ::core::mem::transmute(out_dscr_err) };
out_dscr_err as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let in_dscr_empty: u32 = unsafe { ::core::mem::transmute(in_dscr_empty) };
in_dscr_empty as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_6 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_2__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn tx_bck_in_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_bck_in_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_ws_in_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_ws_in_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_bck_in_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_bck_in_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_ws_in_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_ws_in_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_sd_in_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_sd_in_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_bck_out_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_bck_out_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_ws_out_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_ws_out_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_sd_out_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_sd_out_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_ws_out_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_ws_out_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_bck_out_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_bck_out_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_dsync_sw(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_dsync_sw(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_dsync_sw(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_dsync_sw(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn data_enable_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 2u8) as u32) }
}
#[inline]
pub fn set_data_enable_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_bck_in_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_bck_in_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved25(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved25(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 7u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_bck_in_delay: u32,
tx_ws_in_delay: u32,
rx_bck_in_delay: u32,
rx_ws_in_delay: u32,
rx_sd_in_delay: u32,
tx_bck_out_delay: u32,
tx_ws_out_delay: u32,
tx_sd_out_delay: u32,
rx_ws_out_delay: u32,
rx_bck_out_delay: u32,
tx_dsync_sw: u32,
rx_dsync_sw: u32,
data_enable_delay: u32,
tx_bck_in_inv: u32,
reserved25: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let tx_bck_in_delay: u32 = unsafe { ::core::mem::transmute(tx_bck_in_delay) };
tx_bck_in_delay as u64
});
__bindgen_bitfield_unit.set(2usize, 2u8, {
let tx_ws_in_delay: u32 = unsafe { ::core::mem::transmute(tx_ws_in_delay) };
tx_ws_in_delay as u64
});
__bindgen_bitfield_unit.set(4usize, 2u8, {
let rx_bck_in_delay: u32 = unsafe { ::core::mem::transmute(rx_bck_in_delay) };
rx_bck_in_delay as u64
});
__bindgen_bitfield_unit.set(6usize, 2u8, {
let rx_ws_in_delay: u32 = unsafe { ::core::mem::transmute(rx_ws_in_delay) };
rx_ws_in_delay as u64
});
__bindgen_bitfield_unit.set(8usize, 2u8, {
let rx_sd_in_delay: u32 = unsafe { ::core::mem::transmute(rx_sd_in_delay) };
rx_sd_in_delay as u64
});
__bindgen_bitfield_unit.set(10usize, 2u8, {
let tx_bck_out_delay: u32 = unsafe { ::core::mem::transmute(tx_bck_out_delay) };
tx_bck_out_delay as u64
});
__bindgen_bitfield_unit.set(12usize, 2u8, {
let tx_ws_out_delay: u32 = unsafe { ::core::mem::transmute(tx_ws_out_delay) };
tx_ws_out_delay as u64
});
__bindgen_bitfield_unit.set(14usize, 2u8, {
let tx_sd_out_delay: u32 = unsafe { ::core::mem::transmute(tx_sd_out_delay) };
tx_sd_out_delay as u64
});
__bindgen_bitfield_unit.set(16usize, 2u8, {
let rx_ws_out_delay: u32 = unsafe { ::core::mem::transmute(rx_ws_out_delay) };
rx_ws_out_delay as u64
});
__bindgen_bitfield_unit.set(18usize, 2u8, {
let rx_bck_out_delay: u32 = unsafe { ::core::mem::transmute(rx_bck_out_delay) };
rx_bck_out_delay as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let tx_dsync_sw: u32 = unsafe { ::core::mem::transmute(tx_dsync_sw) };
tx_dsync_sw as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let rx_dsync_sw: u32 = unsafe { ::core::mem::transmute(rx_dsync_sw) };
rx_dsync_sw as u64
});
__bindgen_bitfield_unit.set(22usize, 2u8, {
let data_enable_delay: u32 = unsafe { ::core::mem::transmute(data_enable_delay) };
data_enable_delay as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let tx_bck_in_inv: u32 = unsafe { ::core::mem::transmute(tx_bck_in_inv) };
tx_bck_in_inv as u64
});
__bindgen_bitfield_unit.set(25usize, 7u8, {
let reserved25: u32 = unsafe { ::core::mem::transmute(reserved25) };
reserved25 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_7 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn rx_data_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_rx_data_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn tx_data_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 6u8) as u32) }
}
#[inline]
pub fn set_tx_data_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 6u8, val as u64)
}
}
#[inline]
pub fn dscr_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_dscr_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_fifo_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 3u8) as u32) }
}
#[inline]
pub fn set_tx_fifo_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 3u8, val as u64)
}
}
#[inline]
pub fn rx_fifo_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_fifo_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 3u8, val as u64)
}
}
#[inline]
pub fn tx_fifo_mod_force_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_fifo_mod_force_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_fifo_mod_force_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_fifo_mod_force_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved21(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 11u8) as u32) }
}
#[inline]
pub fn set_reserved21(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 11u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_data_num: u32,
tx_data_num: u32,
dscr_en: u32,
tx_fifo_mod: u32,
rx_fifo_mod: u32,
tx_fifo_mod_force_en: u32,
rx_fifo_mod_force_en: u32,
reserved21: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let rx_data_num: u32 = unsafe { ::core::mem::transmute(rx_data_num) };
rx_data_num as u64
});
__bindgen_bitfield_unit.set(6usize, 6u8, {
let tx_data_num: u32 = unsafe { ::core::mem::transmute(tx_data_num) };
tx_data_num as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let dscr_en: u32 = unsafe { ::core::mem::transmute(dscr_en) };
dscr_en as u64
});
__bindgen_bitfield_unit.set(13usize, 3u8, {
let tx_fifo_mod: u32 = unsafe { ::core::mem::transmute(tx_fifo_mod) };
tx_fifo_mod as u64
});
__bindgen_bitfield_unit.set(16usize, 3u8, {
let rx_fifo_mod: u32 = unsafe { ::core::mem::transmute(rx_fifo_mod) };
rx_fifo_mod as u64
});
__bindgen_bitfield_unit.set(19usize, 1u8, {
let tx_fifo_mod_force_en: u32 = unsafe { ::core::mem::transmute(tx_fifo_mod_force_en) };
tx_fifo_mod_force_en as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let rx_fifo_mod_force_en: u32 = unsafe { ::core::mem::transmute(rx_fifo_mod_force_en) };
rx_fifo_mod_force_en as u64
});
__bindgen_bitfield_unit.set(21usize, 11u8, {
let reserved21: u32 = unsafe { ::core::mem::transmute(reserved21) };
reserved21 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_8 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn tx_chan_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_tx_chan_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn rx_chan_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 2u8) as u32) }
}
#[inline]
pub fn set_rx_chan_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved5(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 27u8) as u32) }
}
#[inline]
pub fn set_reserved5(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 27u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_chan_mod: u32,
rx_chan_mod: u32,
reserved5: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let tx_chan_mod: u32 = unsafe { ::core::mem::transmute(tx_chan_mod) };
tx_chan_mod as u64
});
__bindgen_bitfield_unit.set(3usize, 2u8, {
let rx_chan_mod: u32 = unsafe { ::core::mem::transmute(rx_chan_mod) };
rx_chan_mod as u64
});
__bindgen_bitfield_unit.set(5usize, 27u8, {
let reserved5: u32 = unsafe { ::core::mem::transmute(reserved5) };
reserved5 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_9 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 8u8, val as u64)
}
}
#[inline]
pub fn stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn restart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_restart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn park(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_park(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
addr: u32,
reserved20: u32,
stop: u32,
start: u32,
restart: u32,
park: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let addr: u32 = unsafe { ::core::mem::transmute(addr) };
addr as u64
});
__bindgen_bitfield_unit.set(20usize, 8u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let stop: u32 = unsafe { ::core::mem::transmute(stop) };
stop as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let restart: u32 = unsafe { ::core::mem::transmute(restart) };
restart as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let park: u32 = unsafe { ::core::mem::transmute(park) };
park as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_10 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 8u8, val as u64)
}
}
#[inline]
pub fn stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn restart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_restart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn park(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_park(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
addr: u32,
reserved20: u32,
stop: u32,
start: u32,
restart: u32,
park: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let addr: u32 = unsafe { ::core::mem::transmute(addr) };
addr as u64
});
__bindgen_bitfield_unit.set(20usize, 8u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let stop: u32 = unsafe { ::core::mem::transmute(stop) };
stop as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let restart: u32 = unsafe { ::core::mem::transmute(restart) };
restart as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let park: u32 = unsafe { ::core::mem::transmute(park) };
park as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_11 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 2u8) as u32) }
}
#[inline]
pub fn set_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved6(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 26u8) as u32) }
}
#[inline]
pub fn set_reserved6(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 26u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
mode: u32,
reserved3: u32,
addr: u32,
reserved6: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let mode: u32 = unsafe { ::core::mem::transmute(mode) };
mode as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let reserved3: u32 = unsafe { ::core::mem::transmute(reserved3) };
reserved3 as u64
});
__bindgen_bitfield_unit.set(4usize, 2u8, {
let addr: u32 = unsafe { ::core::mem::transmute(addr) };
addr as u64
});
__bindgen_bitfield_unit.set(6usize, 26u8, {
let reserved6: u32 = unsafe { ::core::mem::transmute(reserved6) };
reserved6 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_12 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn in_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn ahbm_fifo_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_ahbm_fifo_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn ahbm_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_ahbm_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_loop_test(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_loop_test(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_loop_test(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_loop_test(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_auto_wrback(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_auto_wrback(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_no_restart_clr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_no_restart_clr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn outdscr_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_outdscr_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn indscr_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_indscr_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_data_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_data_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn check_owner(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_check_owner(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn mem_trans_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_mem_trans_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved14(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 18u8) as u32) }
}
#[inline]
pub fn set_reserved14(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 18u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
in_rst: u32,
out_rst: u32,
ahbm_fifo_rst: u32,
ahbm_rst: u32,
out_loop_test: u32,
in_loop_test: u32,
out_auto_wrback: u32,
out_no_restart_clr: u32,
out_eof_mode: u32,
outdscr_burst_en: u32,
indscr_burst_en: u32,
out_data_burst_en: u32,
check_owner: u32,
mem_trans_en: u32,
reserved14: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let in_rst: u32 = unsafe { ::core::mem::transmute(in_rst) };
in_rst as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let out_rst: u32 = unsafe { ::core::mem::transmute(out_rst) };
out_rst as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let ahbm_fifo_rst: u32 = unsafe { ::core::mem::transmute(ahbm_fifo_rst) };
ahbm_fifo_rst as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let ahbm_rst: u32 = unsafe { ::core::mem::transmute(ahbm_rst) };
ahbm_rst as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let out_loop_test: u32 = unsafe { ::core::mem::transmute(out_loop_test) };
out_loop_test as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let in_loop_test: u32 = unsafe { ::core::mem::transmute(in_loop_test) };
in_loop_test as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let out_auto_wrback: u32 = unsafe { ::core::mem::transmute(out_auto_wrback) };
out_auto_wrback as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_no_restart_clr: u32 = unsafe { ::core::mem::transmute(out_no_restart_clr) };
out_no_restart_clr as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_eof_mode: u32 = unsafe { ::core::mem::transmute(out_eof_mode) };
out_eof_mode as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let outdscr_burst_en: u32 = unsafe { ::core::mem::transmute(outdscr_burst_en) };
outdscr_burst_en as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let indscr_burst_en: u32 = unsafe { ::core::mem::transmute(indscr_burst_en) };
indscr_burst_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let out_data_burst_en: u32 = unsafe { ::core::mem::transmute(out_data_burst_en) };
out_data_burst_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let check_owner: u32 = unsafe { ::core::mem::transmute(check_owner) };
check_owner as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let mem_trans_en: u32 = unsafe { ::core::mem::transmute(mem_trans_en) };
mem_trans_en as u64
});
__bindgen_bitfield_unit.set(14usize, 18u8, {
let reserved14: u32 = unsafe { ::core::mem::transmute(reserved14) };
reserved14 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_13 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn wdata(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 9u8) as u32) }
}
#[inline]
pub fn set_wdata(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 9u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 7u8, val as u64)
}
}
#[inline]
pub fn push(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_push(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
wdata: u32,
reserved9: u32,
push: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 9u8, {
let wdata: u32 = unsafe { ::core::mem::transmute(wdata) };
wdata as u64
});
__bindgen_bitfield_unit.set(9usize, 7u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let push: u32 = unsafe { ::core::mem::transmute(push) };
push as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_14 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_14__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_14__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_14__bindgen_ty_1 {
#[inline]
pub fn rdata(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_rdata(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn pop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_pop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rdata: u32,
reserved12: u32,
pop: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let rdata: u32 = unsafe { ::core::mem::transmute(rdata) };
rdata as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let pop: u32 = unsafe { ::core::mem::transmute(pop) };
pop as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_15 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_15__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_15__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_15__bindgen_ty_1 {
#[inline]
pub fn fifo_timeout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_fifo_timeout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn fifo_timeout_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
}
#[inline]
pub fn set_fifo_timeout_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 3u8, val as u64)
}
}
#[inline]
pub fn fifo_timeout_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_fifo_timeout_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 20u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 20u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
fifo_timeout: u32,
fifo_timeout_shift: u32,
fifo_timeout_ena: u32,
reserved12: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let fifo_timeout: u32 = unsafe { ::core::mem::transmute(fifo_timeout) };
fifo_timeout as u64
});
__bindgen_bitfield_unit.set(8usize, 3u8, {
let fifo_timeout_shift: u32 = unsafe { ::core::mem::transmute(fifo_timeout_shift) };
fifo_timeout_shift as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let fifo_timeout_ena: u32 = unsafe { ::core::mem::transmute(fifo_timeout_ena) };
fifo_timeout_ena as u64
});
__bindgen_bitfield_unit.set(12usize, 20u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_16 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_16__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_16__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_16__bindgen_ty_1 {
#[inline]
pub fn y_max(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_y_max(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn y_min(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_y_min(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(y_max: u32, y_min: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let y_max: u32 = unsafe { ::core::mem::transmute(y_max) };
y_max as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let y_min: u32 = unsafe { ::core::mem::transmute(y_min) };
y_min as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_17 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_17__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_17__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_17__bindgen_ty_1 {
#[inline]
pub fn sigma_max(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_sigma_max(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn sigma_min(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_sigma_min(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
sigma_max: u32,
sigma_min: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let sigma_max: u32 = unsafe { ::core::mem::transmute(sigma_max) };
sigma_max as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let sigma_min: u32 = unsafe { ::core::mem::transmute(sigma_min) };
sigma_min as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_18 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_18__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_18__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_18__bindgen_ty_1 {
#[inline]
pub fn cvsd_k(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_cvsd_k(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn cvsd_j(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 3u8) as u32) }
}
#[inline]
pub fn set_cvsd_j(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 3u8, val as u64)
}
}
#[inline]
pub fn cvsd_beta(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 10u8) as u32) }
}
#[inline]
pub fn set_cvsd_beta(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 10u8, val as u64)
}
}
#[inline]
pub fn cvsd_h(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 3u8) as u32) }
}
#[inline]
pub fn set_cvsd_h(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cvsd_k: u32,
cvsd_j: u32,
cvsd_beta: u32,
cvsd_h: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let cvsd_k: u32 = unsafe { ::core::mem::transmute(cvsd_k) };
cvsd_k as u64
});
__bindgen_bitfield_unit.set(3usize, 3u8, {
let cvsd_j: u32 = unsafe { ::core::mem::transmute(cvsd_j) };
cvsd_j as u64
});
__bindgen_bitfield_unit.set(6usize, 10u8, {
let cvsd_beta: u32 = unsafe { ::core::mem::transmute(cvsd_beta) };
cvsd_beta as u64
});
__bindgen_bitfield_unit.set(16usize, 3u8, {
let cvsd_h: u32 = unsafe { ::core::mem::transmute(cvsd_h) };
cvsd_h as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_19 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_19__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_19__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_2__bindgen_ty_19__bindgen_ty_1 {
#[inline]
pub fn good_pack_max(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_good_pack_max(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn n_err_seg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 3u8) as u32) }
}
#[inline]
pub fn set_n_err_seg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 3u8, val as u64)
}
}
#[inline]
pub fn shift_rate(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 3u8) as u32) }
}
#[inline]
pub fn set_shift_rate(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 3u8, val as u64)
}
}
#[inline]
pub fn max_slide_sample(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 8u8) as u32) }
}
#[inline]
pub fn set_max_slide_sample(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 8u8, val as u64)
}
}
#[inline]
pub fn pack_len_8k(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 5u8) as u32) }
}
#[inline]
pub fn set_pack_len_8k(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 5u8, val as u64)
}
}
#[inline]
pub fn n_min_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 3u8) as u32) }
}
#[inline]
pub fn set_n_min_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
good_pack_max: u32,
n_err_seg: u32,
shift_rate: u32,
max_slide_sample: u32,
pack_len_8k: u32,
n_min_err: u32,
reserved28: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let good_pack_max: u32 = unsafe { ::core::mem::transmute(good_pack_max) };
good_pack_max as u64
});
__bindgen_bitfield_unit.set(6usize, 3u8, {
let n_err_seg: u32 = unsafe { ::core::mem::transmute(n_err_seg) };
n_err_seg as u64
});
__bindgen_bitfield_unit.set(9usize, 3u8, {
let shift_rate: u32 = unsafe { ::core::mem::transmute(shift_rate) };
shift_rate as u64
});
__bindgen_bitfield_unit.set(12usize, 8u8, {
let max_slide_sample: u32 = unsafe { ::core::mem::transmute(max_slide_sample) };
max_slide_sample as u64
});
__bindgen_bitfield_unit.set(20usize, 5u8, {
let pack_len_8k: u32 = unsafe { ::core::mem::transmute(pack_len_8k) };
pack_len_8k as u64
});
__bindgen_bitfield_unit.set(25usize, 3u8, {
let n_min_err: u32 = unsafe { ::core::mem::transmute(n_min_err) };
n_min_err as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_20 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_20__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_20__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_2__bindgen_ty_20__bindgen_ty_1 {
#[inline]
pub fn bad_cef_atten_para(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_bad_cef_atten_para(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn bad_cef_atten_para_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 4u8) as u32) }
}
#[inline]
pub fn set_bad_cef_atten_para_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 4u8, val as u64)
}
}
#[inline]
pub fn bad_ola_win2_para_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_bad_ola_win2_para_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn bad_ola_win2_para(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_bad_ola_win2_para(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn slide_win_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_slide_win_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
bad_cef_atten_para: u32,
bad_cef_atten_para_shift: u32,
bad_ola_win2_para_shift: u32,
bad_ola_win2_para: u32,
slide_win_len: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let bad_cef_atten_para: u32 = unsafe { ::core::mem::transmute(bad_cef_atten_para) };
bad_cef_atten_para as u64
});
__bindgen_bitfield_unit.set(8usize, 4u8, {
let bad_cef_atten_para_shift: u32 =
unsafe { ::core::mem::transmute(bad_cef_atten_para_shift) };
bad_cef_atten_para_shift as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let bad_ola_win2_para_shift: u32 =
unsafe { ::core::mem::transmute(bad_ola_win2_para_shift) };
bad_ola_win2_para_shift as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let bad_ola_win2_para: u32 = unsafe { ::core::mem::transmute(bad_ola_win2_para) };
bad_ola_win2_para as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let slide_win_len: u32 = unsafe { ::core::mem::transmute(slide_win_len) };
slide_win_len as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_21 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_21__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_21__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_21__bindgen_ty_1 {
#[inline]
pub fn cvsd_seg_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_cvsd_seg_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn min_period(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 5u8) as u32) }
}
#[inline]
pub fn set_min_period(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 5u8, val as u64)
}
}
#[inline]
pub fn reserved7(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 25u8) as u32) }
}
#[inline]
pub fn set_reserved7(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 25u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cvsd_seg_mod: u32,
min_period: u32,
reserved7: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let cvsd_seg_mod: u32 = unsafe { ::core::mem::transmute(cvsd_seg_mod) };
cvsd_seg_mod as u64
});
__bindgen_bitfield_unit.set(2usize, 5u8, {
let min_period: u32 = unsafe { ::core::mem::transmute(min_period) };
min_period as u64
});
__bindgen_bitfield_unit.set(7usize, 25u8, {
let reserved7: u32 = unsafe { ::core::mem::transmute(reserved7) };
reserved7 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_22 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_22__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_22__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_22__bindgen_ty_1 {
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn chan_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_chan_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_dec_pack_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_dec_pack_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_pack_len_8k(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 5u8) as u32) }
}
#[inline]
pub fn set_cvsd_pack_len_8k(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 5u8, val as u64)
}
}
#[inline]
pub fn cvsd_inf_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_inf_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_dec_start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_dec_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_dec_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_dec_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn plc_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_plc_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn plc2dma_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_plc2dma_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved13(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 19u8) as u32) }
}
#[inline]
pub fn set_reserved13(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 19u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
en: u32,
chan_mod: u32,
cvsd_dec_pack_err: u32,
cvsd_pack_len_8k: u32,
cvsd_inf_en: u32,
cvsd_dec_start: u32,
cvsd_dec_reset: u32,
plc_en: u32,
plc2dma_en: u32,
reserved13: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let chan_mod: u32 = unsafe { ::core::mem::transmute(chan_mod) };
chan_mod as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let cvsd_dec_pack_err: u32 = unsafe { ::core::mem::transmute(cvsd_dec_pack_err) };
cvsd_dec_pack_err as u64
});
__bindgen_bitfield_unit.set(3usize, 5u8, {
let cvsd_pack_len_8k: u32 = unsafe { ::core::mem::transmute(cvsd_pack_len_8k) };
cvsd_pack_len_8k as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let cvsd_inf_en: u32 = unsafe { ::core::mem::transmute(cvsd_inf_en) };
cvsd_inf_en as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let cvsd_dec_start: u32 = unsafe { ::core::mem::transmute(cvsd_dec_start) };
cvsd_dec_start as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let cvsd_dec_reset: u32 = unsafe { ::core::mem::transmute(cvsd_dec_reset) };
cvsd_dec_reset as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let plc_en: u32 = unsafe { ::core::mem::transmute(plc_en) };
plc_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let plc2dma_en: u32 = unsafe { ::core::mem::transmute(plc2dma_en) };
plc2dma_en as u64
});
__bindgen_bitfield_unit.set(13usize, 19u8, {
let reserved13: u32 = unsafe { ::core::mem::transmute(reserved13) };
reserved13 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_23 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_23__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_23__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_23__bindgen_ty_1 {
#[inline]
pub fn with_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_with_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn no_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_no_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_enc_start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_enc_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn cvsd_enc_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_cvsd_enc_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
with_en: u32,
no_en: u32,
cvsd_enc_start: u32,
cvsd_enc_reset: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let with_en: u32 = unsafe { ::core::mem::transmute(with_en) };
with_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let no_en: u32 = unsafe { ::core::mem::transmute(no_en) };
no_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let cvsd_enc_start: u32 = unsafe { ::core::mem::transmute(cvsd_enc_start) };
cvsd_enc_start as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let cvsd_enc_reset: u32 = unsafe { ::core::mem::transmute(cvsd_enc_reset) };
cvsd_enc_reset as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_24 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_24__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_24__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_24__bindgen_ty_1 {
#[inline]
pub fn tx_pcm_conf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_tx_pcm_conf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn tx_pcm_bypass(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_pcm_bypass(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_pcm_conf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_pcm_conf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 3u8, val as u64)
}
}
#[inline]
pub fn rx_pcm_bypass(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_pcm_bypass(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_stop_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_stop_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_zeros_rm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_zeros_rm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved10(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 22u8) as u32) }
}
#[inline]
pub fn set_reserved10(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 22u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_pcm_conf: u32,
tx_pcm_bypass: u32,
rx_pcm_conf: u32,
rx_pcm_bypass: u32,
tx_stop_en: u32,
tx_zeros_rm_en: u32,
reserved10: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let tx_pcm_conf: u32 = unsafe { ::core::mem::transmute(tx_pcm_conf) };
tx_pcm_conf as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let tx_pcm_bypass: u32 = unsafe { ::core::mem::transmute(tx_pcm_bypass) };
tx_pcm_bypass as u64
});
__bindgen_bitfield_unit.set(4usize, 3u8, {
let rx_pcm_conf: u32 = unsafe { ::core::mem::transmute(rx_pcm_conf) };
rx_pcm_conf as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let rx_pcm_bypass: u32 = unsafe { ::core::mem::transmute(rx_pcm_bypass) };
rx_pcm_bypass as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let tx_stop_en: u32 = unsafe { ::core::mem::transmute(tx_stop_en) };
tx_stop_en as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let tx_zeros_rm_en: u32 = unsafe { ::core::mem::transmute(tx_zeros_rm_en) };
tx_zeros_rm_en as u64
});
__bindgen_bitfield_unit.set(10usize, 22u8, {
let reserved10: u32 = unsafe { ::core::mem::transmute(reserved10) };
reserved10 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_25 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_25__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_25__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_25__bindgen_ty_1 {
#[inline]
pub fn fifo_force_pd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_fifo_force_pd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn fifo_force_pu(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_fifo_force_pu(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn plc_mem_force_pd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_plc_mem_force_pd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn plc_mem_force_pu(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_plc_mem_force_pu(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
fifo_force_pd: u32,
fifo_force_pu: u32,
plc_mem_force_pd: u32,
plc_mem_force_pu: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let fifo_force_pd: u32 = unsafe { ::core::mem::transmute(fifo_force_pd) };
fifo_force_pd as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let fifo_force_pu: u32 = unsafe { ::core::mem::transmute(fifo_force_pu) };
fifo_force_pu as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let plc_mem_force_pd: u32 = unsafe { ::core::mem::transmute(plc_mem_force_pd) };
plc_mem_force_pd as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let plc_mem_force_pu: u32 = unsafe { ::core::mem::transmute(plc_mem_force_pu) };
plc_mem_force_pu as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_26 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_26__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_26__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_26__bindgen_ty_1 {
#[inline]
pub fn camera_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_camera_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn lcd_tx_wrx2_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_lcd_tx_wrx2_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn lcd_tx_sdx2_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_lcd_tx_sdx2_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn data_enable_test_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_data_enable_test_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn data_enable(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_data_enable(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn lcd_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_lcd_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn ext_adc_start_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_ext_adc_start_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn inter_valid_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_inter_valid_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 24u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
camera_en: u32,
lcd_tx_wrx2_en: u32,
lcd_tx_sdx2_en: u32,
data_enable_test_en: u32,
data_enable: u32,
lcd_en: u32,
ext_adc_start_en: u32,
inter_valid_en: u32,
reserved8: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let camera_en: u32 = unsafe { ::core::mem::transmute(camera_en) };
camera_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let lcd_tx_wrx2_en: u32 = unsafe { ::core::mem::transmute(lcd_tx_wrx2_en) };
lcd_tx_wrx2_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let lcd_tx_sdx2_en: u32 = unsafe { ::core::mem::transmute(lcd_tx_sdx2_en) };
lcd_tx_sdx2_en as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let data_enable_test_en: u32 = unsafe { ::core::mem::transmute(data_enable_test_en) };
data_enable_test_en as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let data_enable: u32 = unsafe { ::core::mem::transmute(data_enable) };
data_enable as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let lcd_en: u32 = unsafe { ::core::mem::transmute(lcd_en) };
lcd_en as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let ext_adc_start_en: u32 = unsafe { ::core::mem::transmute(ext_adc_start_en) };
ext_adc_start_en as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let inter_valid_en: u32 = unsafe { ::core::mem::transmute(inter_valid_en) };
inter_valid_en as u64
});
__bindgen_bitfield_unit.set(8usize, 24u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_27 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_27__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_27__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_27__bindgen_ty_1 {
#[inline]
pub fn clkm_div_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_clkm_div_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn clkm_div_b(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 6u8) as u32) }
}
#[inline]
pub fn set_clkm_div_b(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 6u8, val as u64)
}
}
#[inline]
pub fn clkm_div_a(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 6u8) as u32) }
}
#[inline]
pub fn set_clkm_div_a(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 6u8, val as u64)
}
}
#[inline]
pub fn clk_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_clk_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn clka_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_clka_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved22(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved22(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 10u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
clkm_div_num: u32,
clkm_div_b: u32,
clkm_div_a: u32,
clk_en: u32,
clka_en: u32,
reserved22: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let clkm_div_num: u32 = unsafe { ::core::mem::transmute(clkm_div_num) };
clkm_div_num as u64
});
__bindgen_bitfield_unit.set(8usize, 6u8, {
let clkm_div_b: u32 = unsafe { ::core::mem::transmute(clkm_div_b) };
clkm_div_b as u64
});
__bindgen_bitfield_unit.set(14usize, 6u8, {
let clkm_div_a: u32 = unsafe { ::core::mem::transmute(clkm_div_a) };
clkm_div_a as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let clk_en: u32 = unsafe { ::core::mem::transmute(clk_en) };
clk_en as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let clka_en: u32 = unsafe { ::core::mem::transmute(clka_en) };
clka_en as u64
});
__bindgen_bitfield_unit.set(22usize, 10u8, {
let reserved22: u32 = unsafe { ::core::mem::transmute(reserved22) };
reserved22 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_28 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_28__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_28__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_2__bindgen_ty_28__bindgen_ty_1 {
#[inline]
pub fn tx_bck_div_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_tx_bck_div_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn rx_bck_div_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 6u8) as u32) }
}
#[inline]
pub fn set_rx_bck_div_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 6u8, val as u64)
}
}
#[inline]
pub fn tx_bits_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 6u8) as u32) }
}
#[inline]
pub fn set_tx_bits_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 6u8, val as u64)
}
}
#[inline]
pub fn rx_bits_mod(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 6u8) as u32) }
}
#[inline]
pub fn set_rx_bits_mod(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 6u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_bck_div_num: u32,
rx_bck_div_num: u32,
tx_bits_mod: u32,
rx_bits_mod: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let tx_bck_div_num: u32 = unsafe { ::core::mem::transmute(tx_bck_div_num) };
tx_bck_div_num as u64
});
__bindgen_bitfield_unit.set(6usize, 6u8, {
let rx_bck_div_num: u32 = unsafe { ::core::mem::transmute(rx_bck_div_num) };
rx_bck_div_num as u64
});
__bindgen_bitfield_unit.set(12usize, 6u8, {
let tx_bits_mod: u32 = unsafe { ::core::mem::transmute(tx_bits_mod) };
tx_bits_mod as u64
});
__bindgen_bitfield_unit.set(18usize, 6u8, {
let rx_bits_mod: u32 = unsafe { ::core::mem::transmute(rx_bits_mod) };
rx_bits_mod as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_29 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_29__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_29__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_2__bindgen_ty_29__bindgen_ty_1 {
#[inline]
pub fn tx_pdm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_pdm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_pdm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_pdm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn pcm2pdm_conv_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_pcm2pdm_conv_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn pdm2pcm_conv_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_pdm2pcm_conv_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_sinc_osr2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 4u8) as u32) }
}
#[inline]
pub fn set_tx_sinc_osr2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 4u8, val as u64)
}
}
#[inline]
pub fn tx_prescale(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_tx_prescale(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn tx_hp_in_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_hp_in_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_lp_in_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_lp_in_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_sinc_in_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_sinc_in_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 2u8, val as u64)
}
}
#[inline]
pub fn tx_sigmadelta_in_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 2u8) as u32) }
}
#[inline]
pub fn set_tx_sigmadelta_in_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_sinc_dsr_16_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_sinc_dsr_16_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn txhp_bypass(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_txhp_bypass(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved26(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 6u8) as u32) }
}
#[inline]
pub fn set_reserved26(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 6u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_pdm_en: u32,
rx_pdm_en: u32,
pcm2pdm_conv_en: u32,
pdm2pcm_conv_en: u32,
tx_sinc_osr2: u32,
tx_prescale: u32,
tx_hp_in_shift: u32,
tx_lp_in_shift: u32,
tx_sinc_in_shift: u32,
tx_sigmadelta_in_shift: u32,
rx_sinc_dsr_16_en: u32,
txhp_bypass: u32,
reserved26: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let tx_pdm_en: u32 = unsafe { ::core::mem::transmute(tx_pdm_en) };
tx_pdm_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let rx_pdm_en: u32 = unsafe { ::core::mem::transmute(rx_pdm_en) };
rx_pdm_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let pcm2pdm_conv_en: u32 = unsafe { ::core::mem::transmute(pcm2pdm_conv_en) };
pcm2pdm_conv_en as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let pdm2pcm_conv_en: u32 = unsafe { ::core::mem::transmute(pdm2pcm_conv_en) };
pdm2pcm_conv_en as u64
});
__bindgen_bitfield_unit.set(4usize, 4u8, {
let tx_sinc_osr2: u32 = unsafe { ::core::mem::transmute(tx_sinc_osr2) };
tx_sinc_osr2 as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let tx_prescale: u32 = unsafe { ::core::mem::transmute(tx_prescale) };
tx_prescale as u64
});
__bindgen_bitfield_unit.set(16usize, 2u8, {
let tx_hp_in_shift: u32 = unsafe { ::core::mem::transmute(tx_hp_in_shift) };
tx_hp_in_shift as u64
});
__bindgen_bitfield_unit.set(18usize, 2u8, {
let tx_lp_in_shift: u32 = unsafe { ::core::mem::transmute(tx_lp_in_shift) };
tx_lp_in_shift as u64
});
__bindgen_bitfield_unit.set(20usize, 2u8, {
let tx_sinc_in_shift: u32 = unsafe { ::core::mem::transmute(tx_sinc_in_shift) };
tx_sinc_in_shift as u64
});
__bindgen_bitfield_unit.set(22usize, 2u8, {
let tx_sigmadelta_in_shift: u32 =
unsafe { ::core::mem::transmute(tx_sigmadelta_in_shift) };
tx_sigmadelta_in_shift as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let rx_sinc_dsr_16_en: u32 = unsafe { ::core::mem::transmute(rx_sinc_dsr_16_en) };
rx_sinc_dsr_16_en as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let txhp_bypass: u32 = unsafe { ::core::mem::transmute(txhp_bypass) };
txhp_bypass as u64
});
__bindgen_bitfield_unit.set(26usize, 6u8, {
let reserved26: u32 = unsafe { ::core::mem::transmute(reserved26) };
reserved26 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_30 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_30__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_30__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_2__bindgen_ty_30__bindgen_ty_1 {
#[inline]
pub fn tx_pdm_fs(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_tx_pdm_fs(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn tx_pdm_fp(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 10u8) as u32) }
}
#[inline]
pub fn set_tx_pdm_fp(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 10u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 12u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_pdm_fs: u32,
tx_pdm_fp: u32,
reserved20: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let tx_pdm_fs: u32 = unsafe { ::core::mem::transmute(tx_pdm_fs) };
tx_pdm_fs as u64
});
__bindgen_bitfield_unit.set(10usize, 10u8, {
let tx_pdm_fp: u32 = unsafe { ::core::mem::transmute(tx_pdm_fp) };
tx_pdm_fp as u64
});
__bindgen_bitfield_unit.set(20usize, 12u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_2__bindgen_ty_31 {
pub __bindgen_anon_1: _bindgen_ty_2__bindgen_ty_31__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_2__bindgen_ty_31__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_2__bindgen_ty_31__bindgen_ty_1 {
#[inline]
pub fn tx_idle(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_idle(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_fifo_reset_back(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_fifo_reset_back(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_fifo_reset_back(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_fifo_reset_back(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 29u8) as u32) }
}
#[inline]
pub fn set_reserved3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 29u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
tx_idle: u32,
tx_fifo_reset_back: u32,
rx_fifo_reset_back: u32,
reserved3: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let tx_idle: u32 = unsafe { ::core::mem::transmute(tx_idle) };
tx_idle as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let tx_fifo_reset_back: u32 = unsafe { ::core::mem::transmute(tx_fifo_reset_back) };
tx_fifo_reset_back as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rx_fifo_reset_back: u32 = unsafe { ::core::mem::transmute(rx_fifo_reset_back) };
rx_fifo_reset_back as u64
});
__bindgen_bitfield_unit.set(3usize, 29u8, {
let reserved3: u32 = unsafe { ::core::mem::transmute(reserved3) };
reserved3 as u64
});
__bindgen_bitfield_unit
}
}
pub type i2s_dev_t = _bindgen_ty_2;
extern "C" {
pub static mut I2S0: i2s_dev_t;
}
extern "C" {
pub static mut I2S1: i2s_dev_t;
}
extern "C" {
pub fn esp_dport_access_stall_other_cpu_start();
}
extern "C" {
pub fn esp_dport_access_stall_other_cpu_end();
}
extern "C" {
pub fn esp_dport_access_int_init();
}
extern "C" {
pub fn esp_dport_access_int_pause();
}
extern "C" {
pub fn esp_dport_access_int_resume();
}
extern "C" {
pub fn esp_dport_access_read_buffer(buff_out: *mut u32, address: u32, num_words: u32);
}
extern "C" {
pub fn esp_dport_access_reg_read(reg: u32) -> u32;
}
extern "C" {
pub fn esp_dport_access_sequence_reg_read(reg: u32) -> u32;
}
extern "C" {
pub fn esp_dport_access_int_abort();
}
pub const periph_module_t_PERIPH_LEDC_MODULE: periph_module_t = 0;
pub const periph_module_t_PERIPH_UART0_MODULE: periph_module_t = 1;
pub const periph_module_t_PERIPH_UART1_MODULE: periph_module_t = 2;
pub const periph_module_t_PERIPH_UART2_MODULE: periph_module_t = 3;
pub const periph_module_t_PERIPH_I2C0_MODULE: periph_module_t = 4;
pub const periph_module_t_PERIPH_I2C1_MODULE: periph_module_t = 5;
pub const periph_module_t_PERIPH_I2S0_MODULE: periph_module_t = 6;
pub const periph_module_t_PERIPH_I2S1_MODULE: periph_module_t = 7;
pub const periph_module_t_PERIPH_TIMG0_MODULE: periph_module_t = 8;
pub const periph_module_t_PERIPH_TIMG1_MODULE: periph_module_t = 9;
pub const periph_module_t_PERIPH_PWM0_MODULE: periph_module_t = 10;
pub const periph_module_t_PERIPH_PWM1_MODULE: periph_module_t = 11;
pub const periph_module_t_PERIPH_PWM2_MODULE: periph_module_t = 12;
pub const periph_module_t_PERIPH_PWM3_MODULE: periph_module_t = 13;
pub const periph_module_t_PERIPH_UHCI0_MODULE: periph_module_t = 14;
pub const periph_module_t_PERIPH_UHCI1_MODULE: periph_module_t = 15;
pub const periph_module_t_PERIPH_RMT_MODULE: periph_module_t = 16;
pub const periph_module_t_PERIPH_PCNT_MODULE: periph_module_t = 17;
pub const periph_module_t_PERIPH_SPI_MODULE: periph_module_t = 18;
pub const periph_module_t_PERIPH_HSPI_MODULE: periph_module_t = 19;
pub const periph_module_t_PERIPH_VSPI_MODULE: periph_module_t = 20;
pub const periph_module_t_PERIPH_SPI_DMA_MODULE: periph_module_t = 21;
pub const periph_module_t_PERIPH_SDMMC_MODULE: periph_module_t = 22;
pub const periph_module_t_PERIPH_SDIO_SLAVE_MODULE: periph_module_t = 23;
pub const periph_module_t_PERIPH_CAN_MODULE: periph_module_t = 24;
pub const periph_module_t_PERIPH_EMAC_MODULE: periph_module_t = 25;
pub const periph_module_t_PERIPH_RNG_MODULE: periph_module_t = 26;
pub const periph_module_t_PERIPH_WIFI_MODULE: periph_module_t = 27;
pub const periph_module_t_PERIPH_BT_MODULE: periph_module_t = 28;
pub const periph_module_t_PERIPH_WIFI_BT_COMMON_MODULE: periph_module_t = 29;
pub const periph_module_t_PERIPH_BT_BASEBAND_MODULE: periph_module_t = 30;
pub const periph_module_t_PERIPH_BT_LC_MODULE: periph_module_t = 31;
pub const periph_module_t_PERIPH_AES_MODULE: periph_module_t = 32;
pub const periph_module_t_PERIPH_SHA_MODULE: periph_module_t = 33;
pub const periph_module_t_PERIPH_RSA_MODULE: periph_module_t = 34;
pub type periph_module_t = u32;
extern "C" {
#[doc = " @brief enable peripheral module"]
#[doc = ""]
#[doc = " @param[in] periph : Peripheral module name"]
#[doc = ""]
#[doc = " Clock for the module will be ungated, and reset de-asserted."]
#[doc = ""]
#[doc = " @return NULL"]
#[doc = ""]
pub fn periph_module_enable(periph: periph_module_t);
}
extern "C" {
#[doc = " @brief disable peripheral module"]
#[doc = ""]
#[doc = " @param[in] periph : Peripheral module name"]
#[doc = ""]
#[doc = " Clock for the module will be gated, reset asserted."]
#[doc = ""]
#[doc = " @return NULL"]
#[doc = ""]
pub fn periph_module_disable(periph: periph_module_t);
}
extern "C" {
#[doc = " @brief reset peripheral module"]
#[doc = ""]
#[doc = " @param[in] periph : Peripheral module name"]
#[doc = ""]
#[doc = " Reset will asserted then de-assrted for the peripheral."]
#[doc = ""]
#[doc = " Calling this function does not enable or disable the clock for the module."]
#[doc = ""]
#[doc = " @return NULL"]
#[doc = ""]
pub fn periph_module_reset(periph: periph_module_t);
}
#[doc = "< I2S bits per sample: 8-bits"]
pub const i2s_bits_per_sample_t_I2S_BITS_PER_SAMPLE_8BIT: i2s_bits_per_sample_t = 8;
#[doc = "< I2S bits per sample: 16-bits"]
pub const i2s_bits_per_sample_t_I2S_BITS_PER_SAMPLE_16BIT: i2s_bits_per_sample_t = 16;
#[doc = "< I2S bits per sample: 24-bits"]
pub const i2s_bits_per_sample_t_I2S_BITS_PER_SAMPLE_24BIT: i2s_bits_per_sample_t = 24;
#[doc = "< I2S bits per sample: 32-bits"]
pub const i2s_bits_per_sample_t_I2S_BITS_PER_SAMPLE_32BIT: i2s_bits_per_sample_t = 32;
#[doc = " @brief I2S bit width per sample."]
#[doc = ""]
pub type i2s_bits_per_sample_t = u32;
#[doc = "< I2S 1 channel (mono)"]
pub const i2s_channel_t_I2S_CHANNEL_MONO: i2s_channel_t = 1;
#[doc = "< I2S 2 channel (stereo)"]
pub const i2s_channel_t_I2S_CHANNEL_STEREO: i2s_channel_t = 2;
#[doc = " @brief I2S channel."]
#[doc = ""]
pub type i2s_channel_t = u32;
#[doc = "< I2S communication format I2S"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_I2S: i2s_comm_format_t = 1;
#[doc = "< I2S format MSB"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_I2S_MSB: i2s_comm_format_t = 2;
#[doc = "< I2S format LSB"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_I2S_LSB: i2s_comm_format_t = 4;
#[doc = "< I2S communication format PCM"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_PCM: i2s_comm_format_t = 8;
#[doc = "< PCM Short"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_PCM_SHORT: i2s_comm_format_t = 16;
#[doc = "< PCM Long"]
pub const i2s_comm_format_t_I2S_COMM_FORMAT_PCM_LONG: i2s_comm_format_t = 32;
#[doc = " @brief I2S communication standard format"]
#[doc = ""]
pub type i2s_comm_format_t = u32;
pub const i2s_channel_fmt_t_I2S_CHANNEL_FMT_RIGHT_LEFT: i2s_channel_fmt_t = 0;
pub const i2s_channel_fmt_t_I2S_CHANNEL_FMT_ALL_RIGHT: i2s_channel_fmt_t = 1;
pub const i2s_channel_fmt_t_I2S_CHANNEL_FMT_ALL_LEFT: i2s_channel_fmt_t = 2;
pub const i2s_channel_fmt_t_I2S_CHANNEL_FMT_ONLY_RIGHT: i2s_channel_fmt_t = 3;
pub const i2s_channel_fmt_t_I2S_CHANNEL_FMT_ONLY_LEFT: i2s_channel_fmt_t = 4;
#[doc = " @brief I2S channel format type"]
pub type i2s_channel_fmt_t = u32;
pub const pdm_sample_rate_ratio_t_PDM_SAMPLE_RATE_RATIO_64: pdm_sample_rate_ratio_t = 0;
pub const pdm_sample_rate_ratio_t_PDM_SAMPLE_RATE_RATIO_128: pdm_sample_rate_ratio_t = 1;
#[doc = " @brief PDM sample rate ratio, measured in Hz."]
#[doc = ""]
pub type pdm_sample_rate_ratio_t = u32;
pub const pdm_pcm_conv_t_PDM_PCM_CONV_ENABLE: pdm_pcm_conv_t = 0;
pub const pdm_pcm_conv_t_PDM_PCM_CONV_DISABLE: pdm_pcm_conv_t = 1;
#[doc = " @brief PDM PCM convter enable/disable."]
#[doc = ""]
pub type pdm_pcm_conv_t = u32;
#[doc = "< I2S 0"]
pub const i2s_port_t_I2S_NUM_0: i2s_port_t = 0;
#[doc = "< I2S 1"]
pub const i2s_port_t_I2S_NUM_1: i2s_port_t = 1;
pub const i2s_port_t_I2S_NUM_MAX: i2s_port_t = 2;
#[doc = " @brief I2S Peripheral, 0 & 1."]
#[doc = ""]
pub type i2s_port_t = u32;
pub const i2s_mode_t_I2S_MODE_MASTER: i2s_mode_t = 1;
pub const i2s_mode_t_I2S_MODE_SLAVE: i2s_mode_t = 2;
pub const i2s_mode_t_I2S_MODE_TX: i2s_mode_t = 4;
pub const i2s_mode_t_I2S_MODE_RX: i2s_mode_t = 8;
#[doc = "< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB"]
pub const i2s_mode_t_I2S_MODE_DAC_BUILT_IN: i2s_mode_t = 16;
#[doc = "< Input I2S data from built-in ADC, each data can be 12-bit width at most"]
pub const i2s_mode_t_I2S_MODE_ADC_BUILT_IN: i2s_mode_t = 32;
pub const i2s_mode_t_I2S_MODE_PDM: i2s_mode_t = 64;
#[doc = " @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX"]
#[doc = ""]
#[doc = " @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip."]
#[doc = ""]
pub type i2s_mode_t = u32;
#[doc = " @brief I2S configuration parameters for i2s_param_config function"]
#[doc = ""]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct i2s_config_t {
#[doc = "< I2S work mode"]
pub mode: i2s_mode_t,
#[doc = "< I2S sample rate"]
pub sample_rate: ::std::os::raw::c_int,
#[doc = "< I2S bits per sample"]
pub bits_per_sample: i2s_bits_per_sample_t,
#[doc = "< I2S channel format"]
pub channel_format: i2s_channel_fmt_t,
#[doc = "< I2S communication format"]
pub communication_format: i2s_comm_format_t,
#[doc = "< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info"]
pub intr_alloc_flags: ::std::os::raw::c_int,
#[doc = "< I2S DMA Buffer Count"]
pub dma_buf_count: ::std::os::raw::c_int,
#[doc = "< I2S DMA Buffer Length"]
pub dma_buf_len: ::std::os::raw::c_int,
#[doc = "< I2S using APLL as main I2S clock, enable it to get accurate clock"]
pub use_apll: bool,
#[doc = "< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability)"]
pub tx_desc_auto_clear: bool,
#[doc = "< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value."]
pub fixed_mclk: ::std::os::raw::c_int,
}
pub const i2s_event_type_t_I2S_EVENT_DMA_ERROR: i2s_event_type_t = 0;
#[doc = "< I2S DMA finish sent 1 buffer"]
pub const i2s_event_type_t_I2S_EVENT_TX_DONE: i2s_event_type_t = 1;
#[doc = "< I2S DMA finish received 1 buffer"]
pub const i2s_event_type_t_I2S_EVENT_RX_DONE: i2s_event_type_t = 2;
#[doc = "< I2S event max index"]
pub const i2s_event_type_t_I2S_EVENT_MAX: i2s_event_type_t = 3;
#[doc = " @brief I2S event types"]
#[doc = ""]
pub type i2s_event_type_t = u32;
#[doc = "< Disable I2S built-in DAC signals"]
pub const i2s_dac_mode_t_I2S_DAC_CHANNEL_DISABLE: i2s_dac_mode_t = 0;
#[doc = "< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25"]
pub const i2s_dac_mode_t_I2S_DAC_CHANNEL_RIGHT_EN: i2s_dac_mode_t = 1;
#[doc = "< Enable I2S built-in DAC left channel, maps to DAC channel 2 on GPIO26"]
pub const i2s_dac_mode_t_I2S_DAC_CHANNEL_LEFT_EN: i2s_dac_mode_t = 2;
#[doc = "< Enable both of the I2S built-in DAC channels."]
pub const i2s_dac_mode_t_I2S_DAC_CHANNEL_BOTH_EN: i2s_dac_mode_t = 3;
#[doc = "< I2S built-in DAC mode max index"]
pub const i2s_dac_mode_t_I2S_DAC_CHANNEL_MAX: i2s_dac_mode_t = 4;
#[doc = " @brief I2S DAC mode for i2s_set_dac_mode."]
#[doc = ""]
#[doc = " @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip."]
pub type i2s_dac_mode_t = u32;
#[doc = " @brief Event structure used in I2S event queue"]
#[doc = ""]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct i2s_event_t {
#[doc = "< I2S event type"]
pub type_: i2s_event_type_t,
#[doc = "< I2S data size for I2S_DATA event"]
pub size: usize,
}
#[doc = " @brief I2S pin number for i2s_set_pin"]
#[doc = ""]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct i2s_pin_config_t {
#[doc = "< BCK in out pin"]
pub bck_io_num: ::std::os::raw::c_int,
#[doc = "< WS in out pin"]
pub ws_io_num: ::std::os::raw::c_int,
#[doc = "< DATA out pin"]
pub data_out_num: ::std::os::raw::c_int,
#[doc = "< DATA in pin"]
pub data_in_num: ::std::os::raw::c_int,
}
pub type i2s_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief Set I2S pin number"]
#[doc = ""]
#[doc = " @note"]
#[doc = " The I2S peripheral output signals can be connected to multiple GPIO pads."]
#[doc = " However, the I2S peripheral input signal can only be connected to one GPIO pad."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0 or I2S_NUM_1"]
#[doc = ""]
#[doc = " @param pin I2S Pin structure, or NULL to set 2-channel 8-bit internal DAC pin configuration (GPIO25 & GPIO26)"]
#[doc = ""]
#[doc = " Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where"]
#[doc = " the current configuration should not be changed."]
#[doc = ""]
#[doc = " @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default."]
#[doc = " if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_FAIL IO error"]
pub fn i2s_set_pin(i2s_num: i2s_port_t, pin: *const i2s_pin_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set I2S dac mode, I2S built-in DAC is disabled by default"]
#[doc = ""]
#[doc = " @param dac_mode DAC mode configurations - see i2s_dac_mode_t"]
#[doc = ""]
#[doc = " @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip."]
#[doc = " If either of the built-in DAC channel are enabled, the other one can not"]
#[doc = " be used as RTC DAC function at the same time."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_set_dac_mode(dac_mode: i2s_dac_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Install and start I2S driver."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param i2s_config I2S configurations - see i2s_config_t struct"]
#[doc = ""]
#[doc = " @param queue_size I2S event queue size/depth."]
#[doc = ""]
#[doc = " @param i2s_queue I2S event queue handle, if set NULL, driver will not use an event queue."]
#[doc = ""]
#[doc = " This function must be called before any I2S driver read/write operations."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_NO_MEM Out of memory"]
pub fn i2s_driver_install(
i2s_num: i2s_port_t,
i2s_config: *const i2s_config_t,
queue_size: ::std::os::raw::c_int,
i2s_queue: *mut ::std::os::raw::c_void,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Uninstall I2S driver."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_driver_uninstall(i2s_num: i2s_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Write data to I2S DMA transmit buffer."]
#[doc = ""]
#[doc = " This function is deprecated. Use 'i2s_write' instead."]
#[doc = " This definition will be removed in a future release."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - The amount of bytes written, if timeout, the result will be less than the size passed in."]
#[doc = " - ESP_FAIL Parameter error"]
pub fn i2s_write_bytes(
i2s_num: i2s_port_t,
src: *const ::std::os::raw::c_void,
size: usize,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Write data to I2S DMA transmit buffer."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param src Source address to write from"]
#[doc = ""]
#[doc = " @param size Size of data in bytes"]
#[doc = ""]
#[doc = " @param[out] bytes_written Number of bytes written, if timeout, the result will be less than the size passed in."]
#[doc = ""]
#[doc = " @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this"]
#[doc = " many ticks pass without space becoming available in the DMA"]
#[doc = " transmit buffer, then the function will return (note that if the"]
#[doc = " data is written to the DMA buffer in pieces, the overall operation"]
#[doc = " may still take longer than this timeout.) Pass portMAX_DELAY for no"]
#[doc = " timeout."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_write(
i2s_num: i2s_port_t,
src: *const ::std::os::raw::c_void,
size: usize,
bytes_written: *mut usize,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Write data to I2S DMA transmit buffer while expanding the number of bits per sample. For example, expanding 16-bit PCM to 32-bit PCM."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param src Source address to write from"]
#[doc = ""]
#[doc = " @param size Size of data in bytes"]
#[doc = ""]
#[doc = " @param src_bits Source audio bit"]
#[doc = ""]
#[doc = " @param aim_bits Bit wanted, no more than 32, and must be greater than src_bits"]
#[doc = ""]
#[doc = " @param[out] bytes_written Number of bytes written, if timeout, the result will be less than the size passed in."]
#[doc = ""]
#[doc = " @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this"]
#[doc = " many ticks pass without space becoming available in the DMA"]
#[doc = " transmit buffer, then the function will return (note that if the"]
#[doc = " data is written to the DMA buffer in pieces, the overall operation"]
#[doc = " may still take longer than this timeout.) Pass portMAX_DELAY for no"]
#[doc = " timeout."]
#[doc = ""]
#[doc = " Format of the data in source buffer is determined by the I2S"]
#[doc = " configuration (see i2s_config_t)."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_write_expand(
i2s_num: i2s_port_t,
src: *const ::std::os::raw::c_void,
size: usize,
src_bits: usize,
aim_bits: usize,
bytes_written: *mut usize,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read data from I2S DMA receive buffer"]
#[doc = ""]
#[doc = " This function is deprecated. Use 'i2s_read' instead."]
#[doc = " This definition will be removed in a future release."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - The amount of bytes read, if timeout, bytes read will be less than the size passed in"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn i2s_read_bytes(
i2s_num: i2s_port_t,
dest: *mut ::std::os::raw::c_void,
size: usize,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Read data from I2S DMA receive buffer"]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param dest Destination address to read into"]
#[doc = ""]
#[doc = " @param size Size of data in bytes"]
#[doc = ""]
#[doc = " @param[out] bytes_read Number of bytes read, if timeout, bytes read will be less than the size passed in."]
#[doc = ""]
#[doc = " @param ticks_to_wait RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout."]
#[doc = ""]
#[doc = " @note If the built-in ADC mode is enabled, we should call i2s_adc_start and i2s_adc_stop around the whole reading process,"]
#[doc = " to prevent the data getting corrupted."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_read(
i2s_num: i2s_port_t,
dest: *mut ::std::os::raw::c_void,
size: usize,
bytes_read: *mut usize,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Write a single sample to the I2S DMA TX buffer."]
#[doc = ""]
#[doc = " This function is deprecated. Use 'i2s_write' instead."]
#[doc = " This definition will be removed in a future release."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param sample Buffer to read data. Size of buffer (in bytes) = bits_per_sample / 8."]
#[doc = ""]
#[doc = " @param ticks_to_wait Timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Number of bytes successfully pushed to DMA buffer, will be either zero or the size of configured sample buffer (in bytes)."]
#[doc = " - ESP_FAIL Parameter error"]
pub fn i2s_push_sample(
i2s_num: i2s_port_t,
sample: *const ::std::os::raw::c_void,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Read a single sample from the I2S DMA RX buffer."]
#[doc = ""]
#[doc = " This function is deprecated. Use 'i2s_read' instead."]
#[doc = " This definition will be removed in a future release."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param sample Buffer to write data. Size of buffer (in bytes) = bits_per_sample / 8."]
#[doc = ""]
#[doc = " @param ticks_to_wait Timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - Number of bytes successfully read from DMA buffer, will be either zero or the size of configured sample buffer (in bytes)."]
#[doc = " - ESP_FAIL Parameter error"]
pub fn i2s_pop_sample(
i2s_num: i2s_port_t,
sample: *mut ::std::os::raw::c_void,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Set sample rate used for I2S RX and TX."]
#[doc = ""]
#[doc = " The bit clock rate is determined by the sample rate and i2s_config_t configuration parameters (number of channels, bits_per_sample)."]
#[doc = ""]
#[doc = " `bit_clock = rate * (number of channels) * bits_per_sample`"]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param rate I2S sample rate (ex: 8000, 44100...)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_NO_MEM Out of memory"]
pub fn i2s_set_sample_rates(i2s_num: i2s_port_t, rate: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Stop I2S driver"]
#[doc = ""]
#[doc = " Disables I2S TX/RX, until i2s_start() is called."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_stop(i2s_num: i2s_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start I2S driver"]
#[doc = ""]
#[doc = " It is not necessary to call this function after i2s_driver_install() (it is started automatically), however it is necessary to call it after i2s_stop()."]
#[doc = ""]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_start(i2s_num: i2s_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Zero the contents of the TX DMA buffer."]
#[doc = ""]
#[doc = " Pushes zero-byte samples into the TX DMA buffer, until it is full."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_zero_dma_buffer(i2s_num: i2s_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set clock & bit width used for I2S RX and TX."]
#[doc = ""]
#[doc = " Similar to i2s_set_sample_rates(), but also sets bit width."]
#[doc = ""]
#[doc = " @param i2s_num I2S_NUM_0, I2S_NUM_1"]
#[doc = ""]
#[doc = " @param rate I2S sample rate (ex: 8000, 44100...)"]
#[doc = ""]
#[doc = " @param bits I2S bit width (I2S_BITS_PER_SAMPLE_16BIT, I2S_BITS_PER_SAMPLE_24BIT, I2S_BITS_PER_SAMPLE_32BIT)"]
#[doc = ""]
#[doc = " @param ch I2S channel, (I2S_CHANNEL_MONO, I2S_CHANNEL_STEREO)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_NO_MEM Out of memory"]
pub fn i2s_set_clk(
i2s_num: i2s_port_t,
rate: u32,
bits: i2s_bits_per_sample_t,
ch: i2s_channel_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,"]
#[doc = " and set ADC parameters."]
#[doc = " @param adc_unit SAR ADC unit index"]
#[doc = " @param adc_channel ADC channel index"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn i2s_set_adc_mode(adc_unit: adc_unit_t, adc_channel: adc1_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start to use I2S built-in ADC mode"]
#[doc = " @note This function would acquire the lock of ADC to prevent the data getting corrupted"]
#[doc = " during the I2S peripheral is being used to do fully continuous ADC sampling."]
#[doc = ""]
#[doc = " @param i2s_num i2s port index"]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE Driver state error"]
pub fn i2s_adc_enable(i2s_num: i2s_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Stop to use I2S built-in ADC mode"]
#[doc = " @param i2s_num i2s port index"]
#[doc = " @note This function would release the lock of ADC so that other tasks can use ADC."]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE Driver state error"]
pub fn i2s_adc_disable(i2s_num: i2s_port_t) -> esp_err_t;
}
#[doc = "< LEDC high speed speed_mode"]
pub const ledc_mode_t_LEDC_HIGH_SPEED_MODE: ledc_mode_t = 0;
#[doc = "< LEDC low speed speed_mode"]
pub const ledc_mode_t_LEDC_LOW_SPEED_MODE: ledc_mode_t = 1;
#[doc = "< LEDC speed limit"]
pub const ledc_mode_t_LEDC_SPEED_MODE_MAX: ledc_mode_t = 2;
pub type ledc_mode_t = u32;
#[doc = "< Disable LEDC interrupt"]
pub const ledc_intr_type_t_LEDC_INTR_DISABLE: ledc_intr_type_t = 0;
#[doc = "< Enable LEDC interrupt"]
pub const ledc_intr_type_t_LEDC_INTR_FADE_END: ledc_intr_type_t = 1;
pub type ledc_intr_type_t = u32;
#[doc = "< LEDC duty decrease direction"]
pub const ledc_duty_direction_t_LEDC_DUTY_DIR_DECREASE: ledc_duty_direction_t = 0;
#[doc = "< LEDC duty increase direction"]
pub const ledc_duty_direction_t_LEDC_DUTY_DIR_INCREASE: ledc_duty_direction_t = 1;
pub const ledc_duty_direction_t_LEDC_DUTY_DIR_MAX: ledc_duty_direction_t = 2;
pub type ledc_duty_direction_t = u32;
#[doc = "< LEDC timer clock divided from reference tick (1Mhz)"]
pub const ledc_clk_src_t_LEDC_REF_TICK: ledc_clk_src_t = 0;
#[doc = "< LEDC timer clock divided from APB clock (80Mhz)"]
pub const ledc_clk_src_t_LEDC_APB_CLK: ledc_clk_src_t = 1;
pub type ledc_clk_src_t = u32;
#[doc = "< LEDC timer 0"]
pub const ledc_timer_t_LEDC_TIMER_0: ledc_timer_t = 0;
#[doc = "< LEDC timer 1"]
pub const ledc_timer_t_LEDC_TIMER_1: ledc_timer_t = 1;
#[doc = "< LEDC timer 2"]
pub const ledc_timer_t_LEDC_TIMER_2: ledc_timer_t = 2;
#[doc = "< LEDC timer 3"]
pub const ledc_timer_t_LEDC_TIMER_3: ledc_timer_t = 3;
pub const ledc_timer_t_LEDC_TIMER_MAX: ledc_timer_t = 4;
pub type ledc_timer_t = u32;
#[doc = "< LEDC channel 0"]
pub const ledc_channel_t_LEDC_CHANNEL_0: ledc_channel_t = 0;
#[doc = "< LEDC channel 1"]
pub const ledc_channel_t_LEDC_CHANNEL_1: ledc_channel_t = 1;
#[doc = "< LEDC channel 2"]
pub const ledc_channel_t_LEDC_CHANNEL_2: ledc_channel_t = 2;
#[doc = "< LEDC channel 3"]
pub const ledc_channel_t_LEDC_CHANNEL_3: ledc_channel_t = 3;
#[doc = "< LEDC channel 4"]
pub const ledc_channel_t_LEDC_CHANNEL_4: ledc_channel_t = 4;
#[doc = "< LEDC channel 5"]
pub const ledc_channel_t_LEDC_CHANNEL_5: ledc_channel_t = 5;
#[doc = "< LEDC channel 6"]
pub const ledc_channel_t_LEDC_CHANNEL_6: ledc_channel_t = 6;
#[doc = "< LEDC channel 7"]
pub const ledc_channel_t_LEDC_CHANNEL_7: ledc_channel_t = 7;
pub const ledc_channel_t_LEDC_CHANNEL_MAX: ledc_channel_t = 8;
pub type ledc_channel_t = u32;
#[doc = "< LEDC PWM duty resolution of 1 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_1_BIT: ledc_timer_bit_t = 1;
#[doc = "< LEDC PWM duty resolution of 2 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_2_BIT: ledc_timer_bit_t = 2;
#[doc = "< LEDC PWM duty resolution of 3 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_3_BIT: ledc_timer_bit_t = 3;
#[doc = "< LEDC PWM duty resolution of 4 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_4_BIT: ledc_timer_bit_t = 4;
#[doc = "< LEDC PWM duty resolution of 5 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_5_BIT: ledc_timer_bit_t = 5;
#[doc = "< LEDC PWM duty resolution of 6 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_6_BIT: ledc_timer_bit_t = 6;
#[doc = "< LEDC PWM duty resolution of 7 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_7_BIT: ledc_timer_bit_t = 7;
#[doc = "< LEDC PWM duty resolution of 8 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_8_BIT: ledc_timer_bit_t = 8;
#[doc = "< LEDC PWM duty resolution of 9 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_9_BIT: ledc_timer_bit_t = 9;
#[doc = "< LEDC PWM duty resolution of 10 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_10_BIT: ledc_timer_bit_t = 10;
#[doc = "< LEDC PWM duty resolution of 11 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_11_BIT: ledc_timer_bit_t = 11;
#[doc = "< LEDC PWM duty resolution of 12 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_12_BIT: ledc_timer_bit_t = 12;
#[doc = "< LEDC PWM duty resolution of 13 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_13_BIT: ledc_timer_bit_t = 13;
#[doc = "< LEDC PWM duty resolution of 14 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_14_BIT: ledc_timer_bit_t = 14;
#[doc = "< LEDC PWM duty resolution of 15 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_15_BIT: ledc_timer_bit_t = 15;
#[doc = "< LEDC PWM duty resolution of 16 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_16_BIT: ledc_timer_bit_t = 16;
#[doc = "< LEDC PWM duty resolution of 17 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_17_BIT: ledc_timer_bit_t = 17;
#[doc = "< LEDC PWM duty resolution of 18 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_18_BIT: ledc_timer_bit_t = 18;
#[doc = "< LEDC PWM duty resolution of 19 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_19_BIT: ledc_timer_bit_t = 19;
#[doc = "< LEDC PWM duty resolution of 20 bits"]
pub const ledc_timer_bit_t_LEDC_TIMER_20_BIT: ledc_timer_bit_t = 20;
pub const ledc_timer_bit_t_LEDC_TIMER_BIT_MAX: ledc_timer_bit_t = 21;
pub type ledc_timer_bit_t = u32;
#[doc = "< LEDC fade function will return immediately"]
pub const ledc_fade_mode_t_LEDC_FADE_NO_WAIT: ledc_fade_mode_t = 0;
#[doc = "< LEDC fade function will block until fading to the target duty"]
pub const ledc_fade_mode_t_LEDC_FADE_WAIT_DONE: ledc_fade_mode_t = 1;
pub const ledc_fade_mode_t_LEDC_FADE_MAX: ledc_fade_mode_t = 2;
pub type ledc_fade_mode_t = u32;
#[doc = " @brief Configuration parameters of LEDC channel for ledc_channel_config function"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct ledc_channel_config_t {
#[doc = "< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16"]
pub gpio_num: ::std::os::raw::c_int,
#[doc = "< LEDC speed speed_mode, high-speed mode or low-speed mode"]
pub speed_mode: ledc_mode_t,
#[doc = "< LEDC channel (0 - 7)"]
pub channel: ledc_channel_t,
#[doc = "< configure interrupt, Fade interrupt enable or Fade interrupt disable"]
pub intr_type: ledc_intr_type_t,
#[doc = "< Select the timer source of channel (0 - 3)"]
pub timer_sel: ledc_timer_t,
#[doc = "< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)]"]
pub duty: u32,
#[doc = "< LEDC channel hpoint value, the max value is 0xfffff"]
pub hpoint: ::std::os::raw::c_int,
}
#[doc = " @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function"]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct ledc_timer_config_t {
#[doc = "< LEDC speed speed_mode, high-speed mode or low-speed mode"]
pub speed_mode: ledc_mode_t,
pub __bindgen_anon_1: ledc_timer_config_t__bindgen_ty_1,
#[doc = "< The timer source of channel (0 - 3)"]
pub timer_num: ledc_timer_t,
#[doc = "< LEDC timer frequency (Hz)"]
pub freq_hz: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union ledc_timer_config_t__bindgen_ty_1 {
#[doc = "< LEDC channel duty resolution"]
pub duty_resolution: ledc_timer_bit_t,
#[doc = "< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1"]
pub bit_num: ledc_timer_bit_t,
_bindgen_union_align: u32,
}
pub type ledc_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief LEDC channel configuration"]
#[doc = " Configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC duty resolution"]
#[doc = ""]
#[doc = " @param ledc_conf Pointer of LEDC channel configure struct"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn ledc_channel_config(ledc_conf: *const ledc_channel_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC timer configuration"]
#[doc = " Configure LEDC timer with the given source timer/frequency(Hz)/duty_resolution"]
#[doc = ""]
#[doc = " @param timer_conf Pointer of LEDC timer configure struct"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current duty_resolution."]
pub fn ledc_timer_config(timer_conf: *const ledc_timer_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC update channel parameters"]
#[doc = " @note Call this function to activate the LEDC updated parameters."]
#[doc = " After ledc_set_duty, we need to call this function to update the settings."]
#[doc = " @note ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to"]
#[doc = " control one LEDC channel in different tasks at the same time."]
#[doc = " A thread-safe version of API is ledc_set_duty_and_update"]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = ""]
pub fn ledc_update_duty(speed_mode: ledc_mode_t, channel: ledc_channel_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC stop."]
#[doc = " Disable LEDC output, and set idle level"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @param idle_level Set output idle level after LEDC stops."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn ledc_stop(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
idle_level: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC set channel frequency (Hz)"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_num LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = " @param freq_hz Set the LEDC frequency"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current duty_resolution."]
pub fn ledc_set_freq(
speed_mode: ledc_mode_t,
timer_num: ledc_timer_t,
freq_hz: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC get channel frequency (Hz)"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_num LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - 0 error"]
#[doc = " - Others Current LEDC frequency"]
pub fn ledc_get_freq(speed_mode: ledc_mode_t, timer_num: ledc_timer_t) -> u32;
}
extern "C" {
#[doc = " @brief LEDC set duty and hpoint value"]
#[doc = " Only after calling ledc_update_duty will the duty update."]
#[doc = " @note ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to"]
#[doc = " control one LEDC channel in different tasks at the same time."]
#[doc = " A thread-safe version of API is ledc_set_duty_and_update"]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]"]
#[doc = " @param hpoint Set the LEDC hpoint value(max: 0xfffff)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn ledc_set_duty_with_hpoint(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
duty: u32,
hpoint: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC get hpoint value, the counter value when the output is set high level."]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @return"]
#[doc = " - LEDC_ERR_VAL if parameter error"]
#[doc = " - Others Current hpoint value of LEDC channel"]
pub fn ledc_get_hpoint(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief LEDC set duty"]
#[doc = " This function do not change the hpoint value of this channel. if needed, please call ledc_set_duty_with_hpoint."]
#[doc = " only after calling ledc_update_duty will the duty update."]
#[doc = " @note ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to"]
#[doc = " control one LEDC channel in different tasks at the same time."]
#[doc = " A thread-safe version of API is ledc_set_duty_and_update."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn ledc_set_duty(speed_mode: ledc_mode_t, channel: ledc_channel_t, duty: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief LEDC get duty"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - LEDC_ERR_DUTY if parameter error"]
#[doc = " - Others Current LEDC duty"]
pub fn ledc_get_duty(speed_mode: ledc_mode_t, channel: ledc_channel_t) -> u32;
}
extern "C" {
#[doc = " @brief LEDC set gradient"]
#[doc = " Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @param duty Set the start of the gradient duty, the range of duty setting is [0, (2**duty_resolution)]"]
#[doc = " @param fade_direction Set the direction of the gradient"]
#[doc = " @param step_num Set the number of the gradient"]
#[doc = " @param duty_cyle_num Set how many LEDC tick each time the gradient lasts"]
#[doc = " @param duty_scale Set gradient change amplitude"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn ledc_set_fade(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
duty: u32,
fade_direction: ledc_duty_direction_t,
step_num: u32,
duty_cyle_num: u32,
duty_scale: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register LEDC interrupt handler, the handler is an ISR."]
#[doc = " The handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " @param fn Interrupt handler function."]
#[doc = " @param arg User-supplied argument passed to the handler function."]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @param arg Parameter for handler function"]
#[doc = " @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will"]
#[doc = " be returned here."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Function pointer error."]
pub fn ledc_isr_register(
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut ledc_isr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure LEDC settings"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_sel Timer index (0-3), there are 4 timers in LEDC module"]
#[doc = " @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source"]
#[doc = " @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)]"]
#[doc = " @param clk_src Select LEDC source clock."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - (-1) Parameter error"]
#[doc = " - Other Current LEDC duty"]
pub fn ledc_timer_set(
speed_mode: ledc_mode_t,
timer_sel: ledc_timer_t,
clock_divider: u32,
duty_resolution: u32,
clk_src: ledc_clk_src_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Reset LEDC timer"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_sel LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn ledc_timer_rst(speed_mode: ledc_mode_t, timer_sel: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Pause LEDC timer counter"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_sel LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
#[doc = ""]
pub fn ledc_timer_pause(speed_mode: ledc_mode_t, timer_sel: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Resume LEDC timer"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param timer_sel LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn ledc_timer_resume(speed_mode: ledc_mode_t, timer_sel: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Bind LEDC channel with the selected timer"]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel index (0-7), select from ledc_channel_t"]
#[doc = " @param timer_idx LEDC timer index (0-3), select from ledc_timer_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn ledc_bind_channel_timer(
speed_mode: ledc_mode_t,
channel: u32,
timer_idx: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set LEDC fade function."]
#[doc = " @note Call ledc_fade_func_install() once before calling this function."]
#[doc = " Call ledc_fade_start() after this to start fading."]
#[doc = " @note ledc_set_fade_with_step, ledc_set_fade_with_time and ledc_fade_start are not thread-safe, do not call these functions to"]
#[doc = " control one LEDC channel in different tasks at the same time."]
#[doc = " A thread-safe version of API is ledc_set_fade_step_and_start"]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,"]
#[doc = " @param channel LEDC channel index (0-7), select from ledc_channel_t"]
#[doc = " @param target_duty Target duty of fading [0, (2**duty_resolution) - 1]"]
#[doc = " @param scale Controls the increase or decrease step scale."]
#[doc = " @param cycle_num increase or decrease the duty every cycle_num cycles"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function not installed."]
#[doc = " - ESP_FAIL Fade function init error"]
pub fn ledc_set_fade_with_step(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
target_duty: u32,
scale: u32,
cycle_num: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set LEDC fade function, with a limited time."]
#[doc = " @note Call ledc_fade_func_install() once before calling this function."]
#[doc = " Call ledc_fade_start() after this to start fading."]
#[doc = " @note ledc_set_fade_with_step, ledc_set_fade_with_time and ledc_fade_start are not thread-safe, do not call these functions to"]
#[doc = " control one LEDC channel in different tasks at the same time."]
#[doc = " A thread-safe version of API is ledc_set_fade_step_and_start"]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,"]
#[doc = " @param channel LEDC channel index (0-7), select from ledc_channel_t"]
#[doc = " @param target_duty Target duty of fading.( 0 - (2 ** duty_resolution - 1)))"]
#[doc = " @param max_fade_time_ms The maximum time of the fading ( ms )."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function not installed."]
#[doc = " - ESP_FAIL Fade function init error"]
pub fn ledc_set_fade_with_time(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
target_duty: u32,
max_fade_time_ms: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Install LEDC fade function. This function will occupy interrupt of LEDC module."]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function already installed."]
pub fn ledc_fade_func_install(intr_alloc_flags: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Uninstall LEDC fade function."]
#[doc = ""]
pub fn ledc_fade_func_uninstall();
}
extern "C" {
#[doc = " @brief Start LEDC fading."]
#[doc = " @note Call ledc_fade_func_install() once before calling this function."]
#[doc = " Call this API right after ledc_set_fade_with_time or ledc_set_fade_with_step before to start fading."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel number"]
#[doc = " @param fade_mode Whether to block until fading done."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function not installed."]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error."]
pub fn ledc_fade_start(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
fade_mode: ledc_fade_mode_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief A thread-safe API to set duty for LEDC channel and return when duty updated."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = ""]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode"]
#[doc = " @param channel LEDC channel (0-7), select from ledc_channel_t"]
#[doc = " @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]"]
#[doc = " @param hpoint Set the LEDC hpoint value(max: 0xfffff)"]
#[doc = ""]
pub fn ledc_set_duty_and_update(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
duty: u32,
hpoint: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief A thread-safe API to set and start LEDC fade function, with a limited time."]
#[doc = " @note Call ledc_fade_func_install() once, before calling this function."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,"]
#[doc = " @param channel LEDC channel index (0-7), select from ledc_channel_t"]
#[doc = " @param target_duty Target duty of fading.( 0 - (2 ** duty_resolution - 1)))"]
#[doc = " @param max_fade_time_ms The maximum time of the fading ( ms )."]
#[doc = " @param fade_mode choose blocking or non-blocking mode"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function not installed."]
#[doc = " - ESP_FAIL Fade function init error"]
pub fn ledc_set_fade_time_and_start(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
target_duty: u32,
max_fade_time_ms: u32,
fade_mode: ledc_fade_mode_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief A thread-safe API to set and start LEDC fade function."]
#[doc = " @note Call ledc_fade_func_install() once before calling this function."]
#[doc = " @note If a fade operation is running in progress on that channel, the driver would not allow it to be stopped."]
#[doc = " Other duty operations will have to wait until the fade operation has finished."]
#[doc = " @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,"]
#[doc = " @param channel LEDC channel index (0-7), select from ledc_channel_t"]
#[doc = " @param target_duty Target duty of fading [0, (2**duty_resolution) - 1]"]
#[doc = " @param scale Controls the increase or decrease step scale."]
#[doc = " @param cycle_num increase or decrease the duty every cycle_num cycles"]
#[doc = " @param fade_mode choose blocking or non-blocking mode"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_STATE Fade function not installed."]
#[doc = " - ESP_FAIL Fade function init error"]
pub fn ledc_set_fade_step_and_start(
speed_mode: ledc_mode_t,
channel: ledc_channel_t,
target_duty: u32,
scale: u32,
cycle_num: u32,
fade_mode: ledc_fade_mode_t,
) -> esp_err_t;
}
#[doc = "<PWM0A output pin"]
pub const mcpwm_io_signals_t_MCPWM0A: mcpwm_io_signals_t = 0;
#[doc = "<PWM0B output pin"]
pub const mcpwm_io_signals_t_MCPWM0B: mcpwm_io_signals_t = 1;
#[doc = "<PWM1A output pin"]
pub const mcpwm_io_signals_t_MCPWM1A: mcpwm_io_signals_t = 2;
#[doc = "<PWM1B output pin"]
pub const mcpwm_io_signals_t_MCPWM1B: mcpwm_io_signals_t = 3;
#[doc = "<PWM2A output pin"]
pub const mcpwm_io_signals_t_MCPWM2A: mcpwm_io_signals_t = 4;
#[doc = "<PWM2B output pin"]
pub const mcpwm_io_signals_t_MCPWM2B: mcpwm_io_signals_t = 5;
#[doc = "<SYNC0 input pin"]
pub const mcpwm_io_signals_t_MCPWM_SYNC_0: mcpwm_io_signals_t = 6;
#[doc = "<SYNC1 input pin"]
pub const mcpwm_io_signals_t_MCPWM_SYNC_1: mcpwm_io_signals_t = 7;
#[doc = "<SYNC2 input pin"]
pub const mcpwm_io_signals_t_MCPWM_SYNC_2: mcpwm_io_signals_t = 8;
#[doc = "<FAULT0 input pin"]
pub const mcpwm_io_signals_t_MCPWM_FAULT_0: mcpwm_io_signals_t = 9;
#[doc = "<FAULT1 input pin"]
pub const mcpwm_io_signals_t_MCPWM_FAULT_1: mcpwm_io_signals_t = 10;
#[doc = "<FAULT2 input pin"]
pub const mcpwm_io_signals_t_MCPWM_FAULT_2: mcpwm_io_signals_t = 11;
#[doc = "<CAP0 input pin"]
pub const mcpwm_io_signals_t_MCPWM_CAP_0: mcpwm_io_signals_t = 84;
#[doc = "<CAP1 input pin"]
pub const mcpwm_io_signals_t_MCPWM_CAP_1: mcpwm_io_signals_t = 85;
#[doc = "<CAP2 input pin"]
pub const mcpwm_io_signals_t_MCPWM_CAP_2: mcpwm_io_signals_t = 86;
#[doc = " @brief IO signals for the MCPWM"]
#[doc = ""]
#[doc = " - 6 MCPWM output pins that generate PWM signals"]
#[doc = " - 3 MCPWM fault input pins to detect faults like overcurrent, overvoltage, etc."]
#[doc = " - 3 MCPWM sync input pins to synchronize MCPWM outputs signals"]
#[doc = " - 3 MCPWM capture input pins to gather feedback from controlled motors, using e.g. hall sensors"]
pub type mcpwm_io_signals_t = u32;
#[doc = " @brief MCPWM pin number for"]
#[doc = ""]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct mcpwm_pin_config_t {
#[doc = "<MCPWM0A out pin"]
pub mcpwm0a_out_num: ::std::os::raw::c_int,
#[doc = "<MCPWM0A out pin"]
pub mcpwm0b_out_num: ::std::os::raw::c_int,
#[doc = "<MCPWM0A out pin"]
pub mcpwm1a_out_num: ::std::os::raw::c_int,
#[doc = "<MCPWM0A out pin"]
pub mcpwm1b_out_num: ::std::os::raw::c_int,
#[doc = "<MCPWM0A out pin"]
pub mcpwm2a_out_num: ::std::os::raw::c_int,
#[doc = "<MCPWM0A out pin"]
pub mcpwm2b_out_num: ::std::os::raw::c_int,
#[doc = "<SYNC0 in pin"]
pub mcpwm_sync0_in_num: ::std::os::raw::c_int,
#[doc = "<SYNC1 in pin"]
pub mcpwm_sync1_in_num: ::std::os::raw::c_int,
#[doc = "<SYNC2 in pin"]
pub mcpwm_sync2_in_num: ::std::os::raw::c_int,
#[doc = "<FAULT0 in pin"]
pub mcpwm_fault0_in_num: ::std::os::raw::c_int,
#[doc = "<FAULT1 in pin"]
pub mcpwm_fault1_in_num: ::std::os::raw::c_int,
#[doc = "<FAULT2 in pin"]
pub mcpwm_fault2_in_num: ::std::os::raw::c_int,
#[doc = "<CAP0 in pin"]
pub mcpwm_cap0_in_num: ::std::os::raw::c_int,
#[doc = "<CAP1 in pin"]
pub mcpwm_cap1_in_num: ::std::os::raw::c_int,
#[doc = "<CAP2 in pin"]
pub mcpwm_cap2_in_num: ::std::os::raw::c_int,
}
#[doc = "<MCPWM unit0 selected"]
pub const mcpwm_unit_t_MCPWM_UNIT_0: mcpwm_unit_t = 0;
#[doc = "<MCPWM unit1 selected"]
pub const mcpwm_unit_t_MCPWM_UNIT_1: mcpwm_unit_t = 1;
#[doc = "<Num of MCPWM units on ESP32"]
pub const mcpwm_unit_t_MCPWM_UNIT_MAX: mcpwm_unit_t = 2;
#[doc = " @brief Select MCPWM unit"]
pub type mcpwm_unit_t = u32;
#[doc = "<Select MCPWM timer0"]
pub const mcpwm_timer_t_MCPWM_TIMER_0: mcpwm_timer_t = 0;
#[doc = "<Select MCPWM timer1"]
pub const mcpwm_timer_t_MCPWM_TIMER_1: mcpwm_timer_t = 1;
#[doc = "<Select MCPWM timer2"]
pub const mcpwm_timer_t_MCPWM_TIMER_2: mcpwm_timer_t = 2;
#[doc = "<Num of MCPWM timers on ESP32"]
pub const mcpwm_timer_t_MCPWM_TIMER_MAX: mcpwm_timer_t = 3;
#[doc = " @brief Select MCPWM timer"]
pub type mcpwm_timer_t = u32;
#[doc = "<Select MCPWMXA, where 'X' is timer number"]
pub const mcpwm_operator_t_MCPWM_OPR_A: mcpwm_operator_t = 0;
#[doc = "<Select MCPWMXB, where 'X' is timer number"]
pub const mcpwm_operator_t_MCPWM_OPR_B: mcpwm_operator_t = 1;
#[doc = "<Num of operators to each timer of MCPWM"]
pub const mcpwm_operator_t_MCPWM_OPR_MAX: mcpwm_operator_t = 2;
#[doc = " @brief Select MCPWM operator"]
pub type mcpwm_operator_t = u32;
#[doc = "<For asymmetric MCPWM"]
pub const mcpwm_counter_type_t_MCPWM_UP_COUNTER: mcpwm_counter_type_t = 1;
#[doc = "<For asymmetric MCPWM"]
pub const mcpwm_counter_type_t_MCPWM_DOWN_COUNTER: mcpwm_counter_type_t = 2;
#[doc = "<For symmetric MCPWM, frequency is half of MCPWM frequency set"]
pub const mcpwm_counter_type_t_MCPWM_UP_DOWN_COUNTER: mcpwm_counter_type_t = 3;
#[doc = "<Maximum counter mode"]
pub const mcpwm_counter_type_t_MCPWM_COUNTER_MAX: mcpwm_counter_type_t = 4;
#[doc = " @brief Select type of MCPWM counter"]
pub type mcpwm_counter_type_t = u32;
#[doc = "<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM"]
pub const mcpwm_duty_type_t_MCPWM_DUTY_MODE_0: mcpwm_duty_type_t = 0;
#[doc = "<Active low duty, i.e. duty cycle proportional to low time for asymmetric MCPWM, out of phase(inverted) MCPWM"]
pub const mcpwm_duty_type_t_MCPWM_DUTY_MODE_1: mcpwm_duty_type_t = 1;
#[doc = "<Num of duty cycle modes"]
pub const mcpwm_duty_type_t_MCPWM_DUTY_MODE_MAX: mcpwm_duty_type_t = 2;
#[doc = " @brief Select type of MCPWM duty cycle mode"]
pub type mcpwm_duty_type_t = u32;
#[doc = "<Enable oneshot mode"]
pub const mcpwm_carrier_os_t_MCPWM_ONESHOT_MODE_DIS: mcpwm_carrier_os_t = 0;
#[doc = "<Disable oneshot mode"]
pub const mcpwm_carrier_os_t_MCPWM_ONESHOT_MODE_EN: mcpwm_carrier_os_t = 1;
#[doc = " @brief MCPWM carrier oneshot mode, in this mode the width of the first pulse of carrier can be programmed"]
pub type mcpwm_carrier_os_t = u32;
#[doc = "<Enable carrier output inversion"]
pub const mcpwm_carrier_out_ivt_t_MCPWM_CARRIER_OUT_IVT_DIS: mcpwm_carrier_out_ivt_t = 0;
#[doc = "<Disable carrier output inversion"]
pub const mcpwm_carrier_out_ivt_t_MCPWM_CARRIER_OUT_IVT_EN: mcpwm_carrier_out_ivt_t = 1;
#[doc = " @brief MCPWM carrier output inversion, high frequency carrier signal active with MCPWM signal is high"]
pub type mcpwm_carrier_out_ivt_t = u32;
#[doc = "<Select SYNC0 as input"]
pub const mcpwm_sync_signal_t_MCPWM_SELECT_SYNC0: mcpwm_sync_signal_t = 4;
#[doc = "<Select SYNC1 as input"]
pub const mcpwm_sync_signal_t_MCPWM_SELECT_SYNC1: mcpwm_sync_signal_t = 5;
#[doc = "<Select SYNC2 as input"]
pub const mcpwm_sync_signal_t_MCPWM_SELECT_SYNC2: mcpwm_sync_signal_t = 6;
#[doc = " @brief MCPWM select sync signal input"]
pub type mcpwm_sync_signal_t = u32;
#[doc = "<Select F0 as input"]
pub const mcpwm_fault_signal_t_MCPWM_SELECT_F0: mcpwm_fault_signal_t = 0;
#[doc = "<Select F1 as input"]
pub const mcpwm_fault_signal_t_MCPWM_SELECT_F1: mcpwm_fault_signal_t = 1;
#[doc = "<Select F2 as input"]
pub const mcpwm_fault_signal_t_MCPWM_SELECT_F2: mcpwm_fault_signal_t = 2;
#[doc = " @brief MCPWM select fault signal input"]
pub type mcpwm_fault_signal_t = u32;
#[doc = "<Fault condition occurs when fault input signal goes from high to low, currently not supported"]
pub const mcpwm_fault_input_level_t_MCPWM_LOW_LEVEL_TGR: mcpwm_fault_input_level_t = 0;
#[doc = "<Fault condition occurs when fault input signal goes low to high"]
pub const mcpwm_fault_input_level_t_MCPWM_HIGH_LEVEL_TGR: mcpwm_fault_input_level_t = 1;
#[doc = " @brief MCPWM select triggering level of fault signal"]
pub type mcpwm_fault_input_level_t = u32;
#[doc = "<No change in MCPWMXA output"]
pub const mcpwm_action_on_pwmxa_t_MCPWM_NO_CHANGE_IN_MCPWMXA: mcpwm_action_on_pwmxa_t = 0;
#[doc = "<Make MCPWMXA output low"]
pub const mcpwm_action_on_pwmxa_t_MCPWM_FORCE_MCPWMXA_LOW: mcpwm_action_on_pwmxa_t = 1;
#[doc = "<Make MCPWMXA output high"]
pub const mcpwm_action_on_pwmxa_t_MCPWM_FORCE_MCPWMXA_HIGH: mcpwm_action_on_pwmxa_t = 2;
#[doc = "<Make MCPWMXA output toggle"]
pub const mcpwm_action_on_pwmxa_t_MCPWM_TOG_MCPWMXA: mcpwm_action_on_pwmxa_t = 3;
#[doc = " @brief MCPWM select action to be taken on MCPWMXA when fault occurs"]
pub type mcpwm_action_on_pwmxa_t = u32;
#[doc = "<No change in MCPWMXB output"]
pub const mcpwm_action_on_pwmxb_t_MCPWM_NO_CHANGE_IN_MCPWMXB: mcpwm_action_on_pwmxb_t = 0;
#[doc = "<Make MCPWMXB output low"]
pub const mcpwm_action_on_pwmxb_t_MCPWM_FORCE_MCPWMXB_LOW: mcpwm_action_on_pwmxb_t = 1;
#[doc = "<Make MCPWMXB output high"]
pub const mcpwm_action_on_pwmxb_t_MCPWM_FORCE_MCPWMXB_HIGH: mcpwm_action_on_pwmxb_t = 2;
#[doc = "<Make MCPWMXB output toggle"]
pub const mcpwm_action_on_pwmxb_t_MCPWM_TOG_MCPWMXB: mcpwm_action_on_pwmxb_t = 3;
#[doc = " @brief MCPWM select action to be taken on MCPWMxB when fault occurs"]
pub type mcpwm_action_on_pwmxb_t = u32;
#[doc = "<Select CAP0 as input"]
pub const mcpwm_capture_signal_t_MCPWM_SELECT_CAP0: mcpwm_capture_signal_t = 0;
#[doc = "<Select CAP1 as input"]
pub const mcpwm_capture_signal_t_MCPWM_SELECT_CAP1: mcpwm_capture_signal_t = 1;
#[doc = "<Select CAP2 as input"]
pub const mcpwm_capture_signal_t_MCPWM_SELECT_CAP2: mcpwm_capture_signal_t = 2;
#[doc = " @brief MCPWM select capture signal input"]
pub type mcpwm_capture_signal_t = u32;
#[doc = "<Capture starts from negative edge"]
pub const mcpwm_capture_on_edge_t_MCPWM_NEG_EDGE: mcpwm_capture_on_edge_t = 0;
#[doc = "<Capture starts from positive edge"]
pub const mcpwm_capture_on_edge_t_MCPWM_POS_EDGE: mcpwm_capture_on_edge_t = 1;
#[doc = " @brief MCPWM select capture starts from which edge"]
pub type mcpwm_capture_on_edge_t = u32;
#[doc = "<MCPWMXA = no change, MCPWMXB = falling edge delay"]
pub const mcpwm_deadtime_type_t_MCPWM_BYPASS_RED: mcpwm_deadtime_type_t = 0;
#[doc = "<MCPWMXA = rising edge delay, MCPWMXB = no change"]
pub const mcpwm_deadtime_type_t_MCPWM_BYPASS_FED: mcpwm_deadtime_type_t = 1;
#[doc = "<MCPWMXA = rising edge delay, MCPWMXB = falling edge delay"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_HIGH_MODE: mcpwm_deadtime_type_t = 2;
#[doc = "<MCPWMXA = compliment of rising edge delay, MCPWMXB = compliment of falling edge delay"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_LOW_MODE: mcpwm_deadtime_type_t = 3;
#[doc = "<MCPWMXA = rising edge delay, MCPWMXB = compliment of falling edge delay"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE: mcpwm_deadtime_type_t = 4;
#[doc = "<MCPWMXA = compliment of rising edge delay, MCPWMXB = falling edge delay"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_LOW_COMPLIMENT_MODE: mcpwm_deadtime_type_t = 5;
#[doc = "<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_RED_FED_FROM_PWMXA: mcpwm_deadtime_type_t = 6;
#[doc = "<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB"]
pub const mcpwm_deadtime_type_t_MCPWM_ACTIVE_RED_FED_FROM_PWMXB: mcpwm_deadtime_type_t = 7;
pub const mcpwm_deadtime_type_t_MCPWM_DEADTIME_TYPE_MAX: mcpwm_deadtime_type_t = 8;
#[doc = " @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay"]
pub type mcpwm_deadtime_type_t = u32;
#[doc = " @brief MCPWM config structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct mcpwm_config_t {
#[doc = "<Set frequency of MCPWM in Hz"]
pub frequency: u32,
#[doc = "<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3"]
pub cmpr_a: f32,
#[doc = "<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0"]
pub cmpr_b: f32,
#[doc = "<Set type of duty cycle"]
pub duty_mode: mcpwm_duty_type_t,
#[doc = "<Set type of MCPWM counter"]
pub counter_mode: mcpwm_counter_type_t,
}
#[doc = " @brief MCPWM config carrier structure"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct mcpwm_carrier_config_t {
#[doc = "<Set carrier period = (carrier_period + 1)*800ns, carrier_period should be < 16"]
pub carrier_period: u8,
#[doc = "<Set carrier duty cycle, carrier_duty should be less than 8 (increment every 12.5%)"]
pub carrier_duty: u8,
#[doc = "<Set pulse width of first pulse in one shot mode = (carrier period)*(pulse_width_in_os + 1), should be less then 16"]
pub pulse_width_in_os: u8,
#[doc = "<Enable or disable carrier oneshot mode"]
pub carrier_os_mode: mcpwm_carrier_os_t,
#[doc = "<Invert output of carrier"]
pub carrier_ivt_mode: mcpwm_carrier_out_ivt_t,
}
extern "C" {
#[doc = " @brief This function initializes each gpio signal for MCPWM"]
#[doc = " @note"]
#[doc = " This function initializes one gpio at a time."]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)"]
#[doc = " 'X' is timer_num(0-2)"]
#[doc = " @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_gpio_init(
mcpwm_num: mcpwm_unit_t,
io_signal: mcpwm_io_signals_t,
gpio_num: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize MCPWM gpio structure"]
#[doc = " @note"]
#[doc = " This function can be used to initialize more then one gpio at a time."]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param mcpwm_pin MCPWM pin structure"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_pin(
mcpwm_num: mcpwm_unit_t,
mcpwm_pin: *const mcpwm_pin_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize MCPWM parameters"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param mcpwm_conf configure structure mcpwm_config_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_init(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
mcpwm_conf: *const mcpwm_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set frequency(in Hz) of MCPWM timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param frequency set the frequency in Hz of each timer"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_frequency(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
frequency: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'X' is timer number selected"]
#[doc = " @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_duty(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
duty: f32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected"]
#[doc = " @param duty set duty value in microseconds of each operator"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_duty_in_us(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
duty: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set duty either active high or active low(out of phase/inverted)"]
#[doc = " @note"]
#[doc = " Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected"]
#[doc = " @param duty_num set active low or active high duty type"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_duty_type(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
duty_num: mcpwm_duty_type_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get frequency of timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - frequency of timer"]
pub fn mcpwm_get_frequency(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> u32;
}
extern "C" {
#[doc = " @brief Get duty cycle of each operator"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - duty cycle in % of each operator(56.7 means duty is 56.7%)"]
pub fn mcpwm_get_duty(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
) -> f32;
}
extern "C" {
#[doc = " @brief Use this function to set MCPWM signal high"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected"]
#[doc = ""]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_signal_high(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Use this function to set MCPWM signal low"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected"]
#[doc = ""]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_set_signal_low(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
op_num: mcpwm_operator_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start MCPWM signal on timer 'x'"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_start(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start MCPWM signal on timer 'x'"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_stop(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize carrier configuration"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param carrier_conf configure structure mcpwm_carrier_config_t"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_init(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
carrier_conf: *const mcpwm_carrier_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable MCPWM carrier submodule, for respective timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_enable(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable MCPWM carrier submodule, for respective timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_disable(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set period of carrier"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns"]
#[doc = " (carrier_period <= 15)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_set_period(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
carrier_period: u8,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set duty_cycle of carrier"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%"]
#[doc = " (chop_duty <= 7)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_set_duty_cycle(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
carrier_duty: u8,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable and set width of first pulse in carrier oneshot mode"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)"]
#[doc = " (pulse_width <= 15)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_oneshot_mode_enable(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
pulse_width: u8,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable oneshot mode, width of first pulse = carrier period"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_oneshot_mode_disable(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable or disable carrier output inversion"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param carrier_ivt_mode enable or disable carrier output inversion"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_carrier_output_invert(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
carrier_ivt_mode: mcpwm_carrier_out_ivt_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable and initialize deadtime for each MCPWM timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param dt_mode set deadtime mode"]
#[doc = " @param red set rising edge delay = red*100ns"]
#[doc = " @param fed set rising edge delay = fed*100ns"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_deadtime_enable(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
dt_mode: mcpwm_deadtime_type_t,
red: u32,
fed: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable deadtime on MCPWM timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_deadtime_disable(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize fault submodule, currently low level triggering is not supported"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param intput_level set fault signal level, which will cause fault to occur"]
#[doc = " @param fault_sig set the fault pin, which needs to be enabled"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_fault_init(
mcpwm_num: mcpwm_unit_t,
intput_level: mcpwm_fault_input_level_t,
fault_sig: mcpwm_fault_signal_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set oneshot mode on fault detection, once fault occur in oneshot mode reset is required to resume MCPWM signals"]
#[doc = " @note"]
#[doc = " currently low level triggering is not supported"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param fault_sig set the fault pin, which needs to be enabled for oneshot mode"]
#[doc = " @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle"]
#[doc = " @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_fault_set_oneshot_mode(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
fault_sig: mcpwm_fault_signal_t,
action_on_pwmxa: mcpwm_action_on_pwmxa_t,
action_on_pwmxb: mcpwm_action_on_pwmxb_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set cycle-by-cycle mode on fault detection, once fault occur in cyc mode MCPWM signal resumes as soon as fault signal becomes inactive"]
#[doc = " @note"]
#[doc = " currently low level triggering is not supported"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param fault_sig set the fault pin, which needs to be enabled for cyc mode"]
#[doc = " @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle"]
#[doc = " @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_fault_set_cyc_mode(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
fault_sig: mcpwm_fault_signal_t,
action_on_pwmxa: mcpwm_action_on_pwmxa_t,
action_on_pwmxb: mcpwm_action_on_pwmxb_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable fault signal"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param fault_sig fault pin, which needs to be disabled"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_fault_deinit(
mcpwm_num: mcpwm_unit_t,
fault_sig: mcpwm_fault_signal_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize capture submodule"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge"]
#[doc = " @param cap_sig capture pin, which needs to be enabled"]
#[doc = " @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_capture_enable(
mcpwm_num: mcpwm_unit_t,
cap_sig: mcpwm_capture_signal_t,
cap_edge: mcpwm_capture_on_edge_t,
num_of_pulse: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable capture signal"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param cap_sig capture pin, which needs to be disabled"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_capture_disable(
mcpwm_num: mcpwm_unit_t,
cap_sig: mcpwm_capture_signal_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get capture value"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param cap_sig capture pin on which value is to be measured"]
#[doc = ""]
#[doc = " @return"]
#[doc = " Captured value"]
pub fn mcpwm_capture_signal_get_value(
mcpwm_num: mcpwm_unit_t,
cap_sig: mcpwm_capture_signal_t,
) -> u32;
}
extern "C" {
#[doc = " @brief Get edge of capture signal"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param cap_sig capture pin of whose edge is to be determined"]
#[doc = ""]
#[doc = " @return"]
#[doc = " Capture signal edge: 1 - positive edge, 2 - negtive edge"]
pub fn mcpwm_capture_signal_get_edge(
mcpwm_num: mcpwm_unit_t,
cap_sig: mcpwm_capture_signal_t,
) -> u32;
}
extern "C" {
#[doc = " @brief Initialize sync submodule"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = " @param sync_sig set the synchronization pin, which needs to be enabled"]
#[doc = " @param phase_val phase value in 1/1000 (for 86.7%, phase_val = 867) which timer moves to on sync signal"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_sync_enable(
mcpwm_num: mcpwm_unit_t,
timer_num: mcpwm_timer_t,
sync_sig: mcpwm_sync_signal_t,
phase_val: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable sync submodule on given timer"]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn mcpwm_sync_disable(mcpwm_num: mcpwm_unit_t, timer_num: mcpwm_timer_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register MCPWM interrupt handler, the handler is an ISR."]
#[doc = " the handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " @param mcpwm_num set MCPWM unit(0-1)"]
#[doc = " @param fn interrupt handler function."]
#[doc = " @param arg user-supplied argument passed to the handler function."]
#[doc = " @param intr_alloc_flags flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. see esp_intr_alloc.h for more info."]
#[doc = " @param arg parameter for handler function"]
#[doc = " @param handle pointer to return handle. If non-NULL, a handle for the interrupt will"]
#[doc = " be returned here."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Function pointer error."]
pub fn mcpwm_isr_register(
mcpwm_num: mcpwm_unit_t,
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut intr_handle_t,
) -> esp_err_t;
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct lldesc_s {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
pub buf: *mut u8,
pub __bindgen_anon_1: lldesc_s__bindgen_ty_1,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union lldesc_s__bindgen_ty_1 {
pub empty: u32,
pub qe: lldesc_s__bindgen_ty_1__bindgen_ty_1,
_bindgen_union_align: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct lldesc_s__bindgen_ty_1__bindgen_ty_1 {
pub stqe_next: *mut lldesc_s,
}
impl lldesc_s {
#[inline]
pub fn size(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_size(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn length(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 12u8) as u32) }
}
#[inline]
pub fn set_length(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 12u8, val as u64)
}
}
#[inline]
pub fn offset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 5u8) as u32) }
}
#[inline]
pub fn set_offset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 5u8, val as u64)
}
}
#[inline]
pub fn sosf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_sosf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn owner(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_owner(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
size: u32,
length: u32,
offset: u32,
sosf: u32,
eof: u32,
owner: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let size: u32 = unsafe { ::core::mem::transmute(size) };
size as u64
});
__bindgen_bitfield_unit.set(12usize, 12u8, {
let length: u32 = unsafe { ::core::mem::transmute(length) };
length as u64
});
__bindgen_bitfield_unit.set(24usize, 5u8, {
let offset: u32 = unsafe { ::core::mem::transmute(offset) };
offset as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let sosf: u32 = unsafe { ::core::mem::transmute(sosf) };
sosf as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let eof: u32 = unsafe { ::core::mem::transmute(eof) };
eof as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let owner: u32 = unsafe { ::core::mem::transmute(owner) };
owner as u64
});
__bindgen_bitfield_unit
}
}
pub type lldesc_t = lldesc_s;
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct tx_ampdu_entry_s {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl tx_ampdu_entry_s {
#[inline]
pub fn sub_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_sub_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn dili_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 7u8) as u32) }
}
#[inline]
pub fn set_dili_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 7u8, val as u64)
}
}
#[inline]
pub fn null_byte(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 2u8) as u32) }
}
#[inline]
pub fn set_null_byte(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 2u8, val as u64)
}
}
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn enc(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_enc(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn seq(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_seq(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
sub_len: u32,
dili_num: u32,
null_byte: u32,
data: u32,
enc: u32,
seq: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let sub_len: u32 = unsafe { ::core::mem::transmute(sub_len) };
sub_len as u64
});
__bindgen_bitfield_unit.set(12usize, 7u8, {
let dili_num: u32 = unsafe { ::core::mem::transmute(dili_num) };
dili_num as u64
});
__bindgen_bitfield_unit.set(20usize, 2u8, {
let null_byte: u32 = unsafe { ::core::mem::transmute(null_byte) };
null_byte as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let enc: u32 = unsafe { ::core::mem::transmute(enc) };
enc as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let seq: u32 = unsafe { ::core::mem::transmute(seq) };
seq as u64
});
__bindgen_bitfield_unit
}
}
pub type tx_ampdu_entry_t = tx_ampdu_entry_s;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct lldesc_chain_s {
pub head: *mut lldesc_t,
pub tail: *mut lldesc_t,
}
pub type lldesc_chain_t = lldesc_chain_s;
extern "C" {
pub fn lldesc_build_chain(
descptr: *mut u8,
desclen: u32,
mblkptr: *mut u8,
buflen: u32,
blksz: u32,
owner: u8,
head: *mut *mut lldesc_t,
tail: *mut *mut lldesc_t,
);
}
extern "C" {
pub fn lldesc_num2link(head: *mut lldesc_t, nblks: u16) -> *mut lldesc_t;
}
extern "C" {
pub fn lldesc_set_owner(head: *mut lldesc_t, nblks: u16, owner: u8) -> *mut lldesc_t;
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_3 {
pub cmd: _bindgen_ty_3__bindgen_ty_1,
pub addr: u32,
pub ctrl: _bindgen_ty_3__bindgen_ty_2,
pub ctrl1: _bindgen_ty_3__bindgen_ty_3,
pub rd_status: _bindgen_ty_3__bindgen_ty_4,
pub ctrl2: _bindgen_ty_3__bindgen_ty_5,
pub clock: _bindgen_ty_3__bindgen_ty_6,
pub user: _bindgen_ty_3__bindgen_ty_7,
pub user1: _bindgen_ty_3__bindgen_ty_8,
pub user2: _bindgen_ty_3__bindgen_ty_9,
pub mosi_dlen: _bindgen_ty_3__bindgen_ty_10,
pub miso_dlen: _bindgen_ty_3__bindgen_ty_11,
pub slv_wr_status: u32,
pub pin: _bindgen_ty_3__bindgen_ty_12,
pub slave: _bindgen_ty_3__bindgen_ty_13,
pub slave1: _bindgen_ty_3__bindgen_ty_14,
pub slave2: _bindgen_ty_3__bindgen_ty_15,
pub slave3: _bindgen_ty_3__bindgen_ty_16,
pub slv_wrbuf_dlen: _bindgen_ty_3__bindgen_ty_17,
pub slv_rdbuf_dlen: _bindgen_ty_3__bindgen_ty_18,
pub cache_fctrl: _bindgen_ty_3__bindgen_ty_19,
pub cache_sctrl: _bindgen_ty_3__bindgen_ty_20,
pub sram_cmd: _bindgen_ty_3__bindgen_ty_21,
pub sram_drd_cmd: _bindgen_ty_3__bindgen_ty_22,
pub sram_dwr_cmd: _bindgen_ty_3__bindgen_ty_23,
pub slv_rd_bit: _bindgen_ty_3__bindgen_ty_24,
pub reserved_68: u32,
pub reserved_6c: u32,
pub reserved_70: u32,
pub reserved_74: u32,
pub reserved_78: u32,
pub reserved_7c: u32,
pub data_buf: [u32; 16usize],
pub tx_crc: u32,
pub reserved_c4: u32,
pub reserved_c8: u32,
pub reserved_cc: u32,
pub reserved_d0: u32,
pub reserved_d4: u32,
pub reserved_d8: u32,
pub reserved_dc: u32,
pub reserved_e0: u32,
pub reserved_e4: u32,
pub reserved_e8: u32,
pub reserved_ec: u32,
pub ext0: _bindgen_ty_3__bindgen_ty_25,
pub ext1: _bindgen_ty_3__bindgen_ty_26,
pub ext2: _bindgen_ty_3__bindgen_ty_27,
pub ext3: _bindgen_ty_3__bindgen_ty_28,
pub dma_conf: _bindgen_ty_3__bindgen_ty_29,
pub dma_out_link: _bindgen_ty_3__bindgen_ty_30,
pub dma_in_link: _bindgen_ty_3__bindgen_ty_31,
pub dma_status: _bindgen_ty_3__bindgen_ty_32,
pub dma_int_ena: _bindgen_ty_3__bindgen_ty_33,
pub dma_int_raw: _bindgen_ty_3__bindgen_ty_34,
pub dma_int_st: _bindgen_ty_3__bindgen_ty_35,
pub dma_int_clr: _bindgen_ty_3__bindgen_ty_36,
pub dma_in_err_eof_des_addr: u32,
pub dma_in_suc_eof_des_addr: u32,
pub dma_inlink_dscr: u32,
pub dma_inlink_dscr_bf0: u32,
pub dma_inlink_dscr_bf1: u32,
pub dma_out_eof_bfr_des_addr: u32,
pub dma_out_eof_des_addr: u32,
pub dma_outlink_dscr: u32,
pub dma_outlink_dscr_bf0: u32,
pub dma_outlink_dscr_bf1: u32,
pub dma_rx_status: u32,
pub dma_tx_status: u32,
pub reserved_150: u32,
pub reserved_154: u32,
pub reserved_158: u32,
pub reserved_15c: u32,
pub reserved_160: u32,
pub reserved_164: u32,
pub reserved_168: u32,
pub reserved_16c: u32,
pub reserved_170: u32,
pub reserved_174: u32,
pub reserved_178: u32,
pub reserved_17c: u32,
pub reserved_180: u32,
pub reserved_184: u32,
pub reserved_188: u32,
pub reserved_18c: u32,
pub reserved_190: u32,
pub reserved_194: u32,
pub reserved_198: u32,
pub reserved_19c: u32,
pub reserved_1a0: u32,
pub reserved_1a4: u32,
pub reserved_1a8: u32,
pub reserved_1ac: u32,
pub reserved_1b0: u32,
pub reserved_1b4: u32,
pub reserved_1b8: u32,
pub reserved_1bc: u32,
pub reserved_1c0: u32,
pub reserved_1c4: u32,
pub reserved_1c8: u32,
pub reserved_1cc: u32,
pub reserved_1d0: u32,
pub reserved_1d4: u32,
pub reserved_1d8: u32,
pub reserved_1dc: u32,
pub reserved_1e0: u32,
pub reserved_1e4: u32,
pub reserved_1e8: u32,
pub reserved_1ec: u32,
pub reserved_1f0: u32,
pub reserved_1f4: u32,
pub reserved_1f8: u32,
pub reserved_1fc: u32,
pub reserved_200: u32,
pub reserved_204: u32,
pub reserved_208: u32,
pub reserved_20c: u32,
pub reserved_210: u32,
pub reserved_214: u32,
pub reserved_218: u32,
pub reserved_21c: u32,
pub reserved_220: u32,
pub reserved_224: u32,
pub reserved_228: u32,
pub reserved_22c: u32,
pub reserved_230: u32,
pub reserved_234: u32,
pub reserved_238: u32,
pub reserved_23c: u32,
pub reserved_240: u32,
pub reserved_244: u32,
pub reserved_248: u32,
pub reserved_24c: u32,
pub reserved_250: u32,
pub reserved_254: u32,
pub reserved_258: u32,
pub reserved_25c: u32,
pub reserved_260: u32,
pub reserved_264: u32,
pub reserved_268: u32,
pub reserved_26c: u32,
pub reserved_270: u32,
pub reserved_274: u32,
pub reserved_278: u32,
pub reserved_27c: u32,
pub reserved_280: u32,
pub reserved_284: u32,
pub reserved_288: u32,
pub reserved_28c: u32,
pub reserved_290: u32,
pub reserved_294: u32,
pub reserved_298: u32,
pub reserved_29c: u32,
pub reserved_2a0: u32,
pub reserved_2a4: u32,
pub reserved_2a8: u32,
pub reserved_2ac: u32,
pub reserved_2b0: u32,
pub reserved_2b4: u32,
pub reserved_2b8: u32,
pub reserved_2bc: u32,
pub reserved_2c0: u32,
pub reserved_2c4: u32,
pub reserved_2c8: u32,
pub reserved_2cc: u32,
pub reserved_2d0: u32,
pub reserved_2d4: u32,
pub reserved_2d8: u32,
pub reserved_2dc: u32,
pub reserved_2e0: u32,
pub reserved_2e4: u32,
pub reserved_2e8: u32,
pub reserved_2ec: u32,
pub reserved_2f0: u32,
pub reserved_2f4: u32,
pub reserved_2f8: u32,
pub reserved_2fc: u32,
pub reserved_300: u32,
pub reserved_304: u32,
pub reserved_308: u32,
pub reserved_30c: u32,
pub reserved_310: u32,
pub reserved_314: u32,
pub reserved_318: u32,
pub reserved_31c: u32,
pub reserved_320: u32,
pub reserved_324: u32,
pub reserved_328: u32,
pub reserved_32c: u32,
pub reserved_330: u32,
pub reserved_334: u32,
pub reserved_338: u32,
pub reserved_33c: u32,
pub reserved_340: u32,
pub reserved_344: u32,
pub reserved_348: u32,
pub reserved_34c: u32,
pub reserved_350: u32,
pub reserved_354: u32,
pub reserved_358: u32,
pub reserved_35c: u32,
pub reserved_360: u32,
pub reserved_364: u32,
pub reserved_368: u32,
pub reserved_36c: u32,
pub reserved_370: u32,
pub reserved_374: u32,
pub reserved_378: u32,
pub reserved_37c: u32,
pub reserved_380: u32,
pub reserved_384: u32,
pub reserved_388: u32,
pub reserved_38c: u32,
pub reserved_390: u32,
pub reserved_394: u32,
pub reserved_398: u32,
pub reserved_39c: u32,
pub reserved_3a0: u32,
pub reserved_3a4: u32,
pub reserved_3a8: u32,
pub reserved_3ac: u32,
pub reserved_3b0: u32,
pub reserved_3b4: u32,
pub reserved_3b8: u32,
pub reserved_3bc: u32,
pub reserved_3c0: u32,
pub reserved_3c4: u32,
pub reserved_3c8: u32,
pub reserved_3cc: u32,
pub reserved_3d0: u32,
pub reserved_3d4: u32,
pub reserved_3d8: u32,
pub reserved_3dc: u32,
pub reserved_3e0: u32,
pub reserved_3e4: u32,
pub reserved_3e8: u32,
pub reserved_3ec: u32,
pub reserved_3f0: u32,
pub reserved_3f4: u32,
pub reserved_3f8: u32,
pub date: _bindgen_ty_3__bindgen_ty_37,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_1 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn flash_per(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_per(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_pes(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_pes(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_hpm(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_hpm(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_res(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_res(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_dp(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_dp(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_ce(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_ce(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_be(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_be(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_se(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_se(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_pp(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_pp(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_wrsr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_wrsr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_rdsr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_rdsr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_rdid(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_rdid(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_wrdi(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_wrdi(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_wren(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_wren(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_read(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_read(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
flash_per: u32,
flash_pes: u32,
usr: u32,
flash_hpm: u32,
flash_res: u32,
flash_dp: u32,
flash_ce: u32,
flash_be: u32,
flash_se: u32,
flash_pp: u32,
flash_wrsr: u32,
flash_rdsr: u32,
flash_rdid: u32,
flash_wrdi: u32,
flash_wren: u32,
flash_read: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let flash_per: u32 = unsafe { ::core::mem::transmute(flash_per) };
flash_per as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let flash_pes: u32 = unsafe { ::core::mem::transmute(flash_pes) };
flash_pes as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let usr: u32 = unsafe { ::core::mem::transmute(usr) };
usr as u64
});
__bindgen_bitfield_unit.set(19usize, 1u8, {
let flash_hpm: u32 = unsafe { ::core::mem::transmute(flash_hpm) };
flash_hpm as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let flash_res: u32 = unsafe { ::core::mem::transmute(flash_res) };
flash_res as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let flash_dp: u32 = unsafe { ::core::mem::transmute(flash_dp) };
flash_dp as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let flash_ce: u32 = unsafe { ::core::mem::transmute(flash_ce) };
flash_ce as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let flash_be: u32 = unsafe { ::core::mem::transmute(flash_be) };
flash_be as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let flash_se: u32 = unsafe { ::core::mem::transmute(flash_se) };
flash_se as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let flash_pp: u32 = unsafe { ::core::mem::transmute(flash_pp) };
flash_pp as u64
});
__bindgen_bitfield_unit.set(26usize, 1u8, {
let flash_wrsr: u32 = unsafe { ::core::mem::transmute(flash_wrsr) };
flash_wrsr as u64
});
__bindgen_bitfield_unit.set(27usize, 1u8, {
let flash_rdsr: u32 = unsafe { ::core::mem::transmute(flash_rdsr) };
flash_rdsr as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let flash_rdid: u32 = unsafe { ::core::mem::transmute(flash_rdid) };
flash_rdid as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let flash_wrdi: u32 = unsafe { ::core::mem::transmute(flash_wrdi) };
flash_wrdi as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let flash_wren: u32 = unsafe { ::core::mem::transmute(flash_wren) };
flash_wren as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let flash_read: u32 = unsafe { ::core::mem::transmute(flash_read) };
flash_read as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_2 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn fcs_crc_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_fcs_crc_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_crc_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_crc_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn wait_flash_idle_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_wait_flash_idle_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn fastrd_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_fastrd_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn fread_dual(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_fread_dual(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn resandres(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_resandres(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 4u8, val as u64)
}
}
#[inline]
pub fn fread_quad(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_fread_quad(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn wp(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_wp(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn wrsr_2b(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_wrsr_2b(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn fread_dio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_fread_dio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn fread_qio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_fread_qio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn rd_bit_order(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_bit_order(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_bit_order(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_bit_order(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved27(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 5u8) as u32) }
}
#[inline]
pub fn set_reserved27(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 5u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
fcs_crc_en: u32,
tx_crc_en: u32,
wait_flash_idle_en: u32,
fastrd_mode: u32,
fread_dual: u32,
resandres: u32,
reserved16: u32,
fread_quad: u32,
wp: u32,
wrsr_2b: u32,
fread_dio: u32,
fread_qio: u32,
rd_bit_order: u32,
wr_bit_order: u32,
reserved27: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let fcs_crc_en: u32 = unsafe { ::core::mem::transmute(fcs_crc_en) };
fcs_crc_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let tx_crc_en: u32 = unsafe { ::core::mem::transmute(tx_crc_en) };
tx_crc_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let wait_flash_idle_en: u32 = unsafe { ::core::mem::transmute(wait_flash_idle_en) };
wait_flash_idle_en as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let fastrd_mode: u32 = unsafe { ::core::mem::transmute(fastrd_mode) };
fastrd_mode as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let fread_dual: u32 = unsafe { ::core::mem::transmute(fread_dual) };
fread_dual as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let resandres: u32 = unsafe { ::core::mem::transmute(resandres) };
resandres as u64
});
__bindgen_bitfield_unit.set(16usize, 4u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let fread_quad: u32 = unsafe { ::core::mem::transmute(fread_quad) };
fread_quad as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let wp: u32 = unsafe { ::core::mem::transmute(wp) };
wp as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let wrsr_2b: u32 = unsafe { ::core::mem::transmute(wrsr_2b) };
wrsr_2b as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let fread_dio: u32 = unsafe { ::core::mem::transmute(fread_dio) };
fread_dio as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let fread_qio: u32 = unsafe { ::core::mem::transmute(fread_qio) };
fread_qio as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let rd_bit_order: u32 = unsafe { ::core::mem::transmute(rd_bit_order) };
rd_bit_order as u64
});
__bindgen_bitfield_unit.set(26usize, 1u8, {
let wr_bit_order: u32 = unsafe { ::core::mem::transmute(wr_bit_order) };
wr_bit_order as u64
});
__bindgen_bitfield_unit.set(27usize, 5u8, {
let reserved27: u32 = unsafe { ::core::mem::transmute(reserved27) };
reserved27 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_3 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn cs_hold_delay_res(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 12u8) as u32) }
}
#[inline]
pub fn set_cs_hold_delay_res(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 12u8, val as u64)
}
}
#[inline]
pub fn cs_hold_delay(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_cs_hold_delay(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
cs_hold_delay_res: u32,
cs_hold_delay: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(16usize, 12u8, {
let cs_hold_delay_res: u32 = unsafe { ::core::mem::transmute(cs_hold_delay_res) };
cs_hold_delay_res as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let cs_hold_delay: u32 = unsafe { ::core::mem::transmute(cs_hold_delay) };
cs_hold_delay as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_4 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn status(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_status(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn wb_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_wb_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn status_ext(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_status_ext(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
status: u32,
wb_mode: u32,
status_ext: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let status: u32 = unsafe { ::core::mem::transmute(status) };
status as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let wb_mode: u32 = unsafe { ::core::mem::transmute(wb_mode) };
wb_mode as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let status_ext: u32 = unsafe { ::core::mem::transmute(status_ext) };
status_ext as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_5 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn setup_time(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 4u8) as u32) }
}
#[inline]
pub fn set_setup_time(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 4u8, val as u64)
}
}
#[inline]
pub fn hold_time(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 4u8) as u32) }
}
#[inline]
pub fn set_hold_time(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 4u8, val as u64)
}
}
#[inline]
pub fn ck_out_low_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 4u8) as u32) }
}
#[inline]
pub fn set_ck_out_low_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 4u8, val as u64)
}
}
#[inline]
pub fn ck_out_high_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_ck_out_high_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn miso_delay_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 2u8) as u32) }
}
#[inline]
pub fn set_miso_delay_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 2u8, val as u64)
}
}
#[inline]
pub fn miso_delay_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 3u8) as u32) }
}
#[inline]
pub fn set_miso_delay_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 3u8, val as u64)
}
}
#[inline]
pub fn mosi_delay_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 2u8) as u32) }
}
#[inline]
pub fn set_mosi_delay_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 2u8, val as u64)
}
}
#[inline]
pub fn mosi_delay_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 3u8) as u32) }
}
#[inline]
pub fn set_mosi_delay_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 3u8, val as u64)
}
}
#[inline]
pub fn cs_delay_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 2u8) as u32) }
}
#[inline]
pub fn set_cs_delay_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 2u8, val as u64)
}
}
#[inline]
pub fn cs_delay_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_cs_delay_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
setup_time: u32,
hold_time: u32,
ck_out_low_mode: u32,
ck_out_high_mode: u32,
miso_delay_mode: u32,
miso_delay_num: u32,
mosi_delay_mode: u32,
mosi_delay_num: u32,
cs_delay_mode: u32,
cs_delay_num: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 4u8, {
let setup_time: u32 = unsafe { ::core::mem::transmute(setup_time) };
setup_time as u64
});
__bindgen_bitfield_unit.set(4usize, 4u8, {
let hold_time: u32 = unsafe { ::core::mem::transmute(hold_time) };
hold_time as u64
});
__bindgen_bitfield_unit.set(8usize, 4u8, {
let ck_out_low_mode: u32 = unsafe { ::core::mem::transmute(ck_out_low_mode) };
ck_out_low_mode as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let ck_out_high_mode: u32 = unsafe { ::core::mem::transmute(ck_out_high_mode) };
ck_out_high_mode as u64
});
__bindgen_bitfield_unit.set(16usize, 2u8, {
let miso_delay_mode: u32 = unsafe { ::core::mem::transmute(miso_delay_mode) };
miso_delay_mode as u64
});
__bindgen_bitfield_unit.set(18usize, 3u8, {
let miso_delay_num: u32 = unsafe { ::core::mem::transmute(miso_delay_num) };
miso_delay_num as u64
});
__bindgen_bitfield_unit.set(21usize, 2u8, {
let mosi_delay_mode: u32 = unsafe { ::core::mem::transmute(mosi_delay_mode) };
mosi_delay_mode as u64
});
__bindgen_bitfield_unit.set(23usize, 3u8, {
let mosi_delay_num: u32 = unsafe { ::core::mem::transmute(mosi_delay_num) };
mosi_delay_num as u64
});
__bindgen_bitfield_unit.set(26usize, 2u8, {
let cs_delay_mode: u32 = unsafe { ::core::mem::transmute(cs_delay_mode) };
cs_delay_mode as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let cs_delay_num: u32 = unsafe { ::core::mem::transmute(cs_delay_num) };
cs_delay_num as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_6 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn clkcnt_l(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_clkcnt_l(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn clkcnt_h(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 6u8) as u32) }
}
#[inline]
pub fn set_clkcnt_h(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 6u8, val as u64)
}
}
#[inline]
pub fn clkcnt_n(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 6u8) as u32) }
}
#[inline]
pub fn set_clkcnt_n(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 6u8, val as u64)
}
}
#[inline]
pub fn clkdiv_pre(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 13u8) as u32) }
}
#[inline]
pub fn set_clkdiv_pre(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 13u8, val as u64)
}
}
#[inline]
pub fn clk_equ_sysclk(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_clk_equ_sysclk(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
clkcnt_l: u32,
clkcnt_h: u32,
clkcnt_n: u32,
clkdiv_pre: u32,
clk_equ_sysclk: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let clkcnt_l: u32 = unsafe { ::core::mem::transmute(clkcnt_l) };
clkcnt_l as u64
});
__bindgen_bitfield_unit.set(6usize, 6u8, {
let clkcnt_h: u32 = unsafe { ::core::mem::transmute(clkcnt_h) };
clkcnt_h as u64
});
__bindgen_bitfield_unit.set(12usize, 6u8, {
let clkcnt_n: u32 = unsafe { ::core::mem::transmute(clkcnt_n) };
clkcnt_n as u64
});
__bindgen_bitfield_unit.set(18usize, 13u8, {
let clkdiv_pre: u32 = unsafe { ::core::mem::transmute(clkdiv_pre) };
clkdiv_pre as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let clk_equ_sysclk: u32 = unsafe { ::core::mem::transmute(clk_equ_sysclk) };
clk_equ_sysclk as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_7 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn doutdin(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_doutdin(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 3u8) as u32) }
}
#[inline]
pub fn set_reserved1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 3u8, val as u64)
}
}
#[inline]
pub fn cs_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn cs_setup(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs_setup(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn ck_i_edge(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_ck_i_edge(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn ck_out_edge(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_ck_out_edge(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 2u8, val as u64)
}
}
#[inline]
pub fn rd_byte_order(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_byte_order(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_byte_order(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_byte_order(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn fwrite_dual(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_fwrite_dual(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn fwrite_quad(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_fwrite_quad(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn fwrite_dio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_fwrite_dio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn fwrite_qio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_fwrite_qio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn sio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_sio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_hold_pol(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_hold_pol(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_dout_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_dout_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_din_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_din_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_dummy_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_dummy_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_addr_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_addr_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_cmd_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_cmd_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_prep_hold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_prep_hold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_miso_highpart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_miso_highpart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_mosi_highpart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_mosi_highpart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_dummy_idle(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_dummy_idle(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_mosi(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_mosi(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_miso(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_miso(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_dummy(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_dummy(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_command(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_command(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
doutdin: u32,
reserved1: u32,
cs_hold: u32,
cs_setup: u32,
ck_i_edge: u32,
ck_out_edge: u32,
reserved8: u32,
rd_byte_order: u32,
wr_byte_order: u32,
fwrite_dual: u32,
fwrite_quad: u32,
fwrite_dio: u32,
fwrite_qio: u32,
sio: u32,
usr_hold_pol: u32,
usr_dout_hold: u32,
usr_din_hold: u32,
usr_dummy_hold: u32,
usr_addr_hold: u32,
usr_cmd_hold: u32,
usr_prep_hold: u32,
usr_miso_highpart: u32,
usr_mosi_highpart: u32,
usr_dummy_idle: u32,
usr_mosi: u32,
usr_miso: u32,
usr_dummy: u32,
usr_addr: u32,
usr_command: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let doutdin: u32 = unsafe { ::core::mem::transmute(doutdin) };
doutdin as u64
});
__bindgen_bitfield_unit.set(1usize, 3u8, {
let reserved1: u32 = unsafe { ::core::mem::transmute(reserved1) };
reserved1 as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let cs_hold: u32 = unsafe { ::core::mem::transmute(cs_hold) };
cs_hold as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let cs_setup: u32 = unsafe { ::core::mem::transmute(cs_setup) };
cs_setup as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let ck_i_edge: u32 = unsafe { ::core::mem::transmute(ck_i_edge) };
ck_i_edge as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let ck_out_edge: u32 = unsafe { ::core::mem::transmute(ck_out_edge) };
ck_out_edge as u64
});
__bindgen_bitfield_unit.set(8usize, 2u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let rd_byte_order: u32 = unsafe { ::core::mem::transmute(rd_byte_order) };
rd_byte_order as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let wr_byte_order: u32 = unsafe { ::core::mem::transmute(wr_byte_order) };
wr_byte_order as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let fwrite_dual: u32 = unsafe { ::core::mem::transmute(fwrite_dual) };
fwrite_dual as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let fwrite_quad: u32 = unsafe { ::core::mem::transmute(fwrite_quad) };
fwrite_quad as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let fwrite_dio: u32 = unsafe { ::core::mem::transmute(fwrite_dio) };
fwrite_dio as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let fwrite_qio: u32 = unsafe { ::core::mem::transmute(fwrite_qio) };
fwrite_qio as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let sio: u32 = unsafe { ::core::mem::transmute(sio) };
sio as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let usr_hold_pol: u32 = unsafe { ::core::mem::transmute(usr_hold_pol) };
usr_hold_pol as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let usr_dout_hold: u32 = unsafe { ::core::mem::transmute(usr_dout_hold) };
usr_dout_hold as u64
});
__bindgen_bitfield_unit.set(19usize, 1u8, {
let usr_din_hold: u32 = unsafe { ::core::mem::transmute(usr_din_hold) };
usr_din_hold as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let usr_dummy_hold: u32 = unsafe { ::core::mem::transmute(usr_dummy_hold) };
usr_dummy_hold as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let usr_addr_hold: u32 = unsafe { ::core::mem::transmute(usr_addr_hold) };
usr_addr_hold as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let usr_cmd_hold: u32 = unsafe { ::core::mem::transmute(usr_cmd_hold) };
usr_cmd_hold as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let usr_prep_hold: u32 = unsafe { ::core::mem::transmute(usr_prep_hold) };
usr_prep_hold as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let usr_miso_highpart: u32 = unsafe { ::core::mem::transmute(usr_miso_highpart) };
usr_miso_highpart as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let usr_mosi_highpart: u32 = unsafe { ::core::mem::transmute(usr_mosi_highpart) };
usr_mosi_highpart as u64
});
__bindgen_bitfield_unit.set(26usize, 1u8, {
let usr_dummy_idle: u32 = unsafe { ::core::mem::transmute(usr_dummy_idle) };
usr_dummy_idle as u64
});
__bindgen_bitfield_unit.set(27usize, 1u8, {
let usr_mosi: u32 = unsafe { ::core::mem::transmute(usr_mosi) };
usr_mosi as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let usr_miso: u32 = unsafe { ::core::mem::transmute(usr_miso) };
usr_miso as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let usr_dummy: u32 = unsafe { ::core::mem::transmute(usr_dummy) };
usr_dummy as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let usr_addr: u32 = unsafe { ::core::mem::transmute(usr_addr) };
usr_addr as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let usr_command: u32 = unsafe { ::core::mem::transmute(usr_command) };
usr_command as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_8 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn usr_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_usr_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved8(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 18u8) as u32) }
}
#[inline]
pub fn set_reserved8(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 18u8, val as u64)
}
}
#[inline]
pub fn usr_addr_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 6u8) as u32) }
}
#[inline]
pub fn set_usr_addr_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 6u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_dummy_cyclelen: u32,
reserved8: u32,
usr_addr_bitlen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let usr_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(usr_dummy_cyclelen) };
usr_dummy_cyclelen as u64
});
__bindgen_bitfield_unit.set(8usize, 18u8, {
let reserved8: u32 = unsafe { ::core::mem::transmute(reserved8) };
reserved8 as u64
});
__bindgen_bitfield_unit.set(26usize, 6u8, {
let usr_addr_bitlen: u32 = unsafe { ::core::mem::transmute(usr_addr_bitlen) };
usr_addr_bitlen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_9 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn usr_command_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_usr_command_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 12u8, val as u64)
}
}
#[inline]
pub fn usr_command_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_usr_command_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_command_value: u32,
reserved16: u32,
usr_command_bitlen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let usr_command_value: u32 = unsafe { ::core::mem::transmute(usr_command_value) };
usr_command_value as u64
});
__bindgen_bitfield_unit.set(16usize, 12u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let usr_command_bitlen: u32 = unsafe { ::core::mem::transmute(usr_command_bitlen) };
usr_command_bitlen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_10 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn usr_mosi_dbitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_usr_mosi_dbitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_mosi_dbitlen: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let usr_mosi_dbitlen: u32 = unsafe { ::core::mem::transmute(usr_mosi_dbitlen) };
usr_mosi_dbitlen as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_11 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn usr_miso_dbitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_usr_miso_dbitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_miso_dbitlen: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let usr_miso_dbitlen: u32 = unsafe { ::core::mem::transmute(usr_miso_dbitlen) };
usr_miso_dbitlen as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_12 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn cs0_dis(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs0_dis(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn cs1_dis(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs1_dis(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn cs2_dis(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs2_dis(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 2u8, val as u64)
}
}
#[inline]
pub fn ck_dis(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_ck_dis(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn master_cs_pol(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 3u8) as u32) }
}
#[inline]
pub fn set_master_cs_pol(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 2u8, val as u64)
}
}
#[inline]
pub fn master_ck_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 3u8) as u32) }
}
#[inline]
pub fn set_master_ck_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved14(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved14(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 15u8, val as u64)
}
}
#[inline]
pub fn ck_idle_edge(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_ck_idle_edge(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn cs_keep_active(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_cs_keep_active(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved31(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved31(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
cs0_dis: u32,
cs1_dis: u32,
cs2_dis: u32,
reserved3: u32,
ck_dis: u32,
master_cs_pol: u32,
reserved9: u32,
master_ck_sel: u32,
reserved14: u32,
ck_idle_edge: u32,
cs_keep_active: u32,
reserved31: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let cs0_dis: u32 = unsafe { ::core::mem::transmute(cs0_dis) };
cs0_dis as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let cs1_dis: u32 = unsafe { ::core::mem::transmute(cs1_dis) };
cs1_dis as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let cs2_dis: u32 = unsafe { ::core::mem::transmute(cs2_dis) };
cs2_dis as u64
});
__bindgen_bitfield_unit.set(3usize, 2u8, {
let reserved3: u32 = unsafe { ::core::mem::transmute(reserved3) };
reserved3 as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let ck_dis: u32 = unsafe { ::core::mem::transmute(ck_dis) };
ck_dis as u64
});
__bindgen_bitfield_unit.set(6usize, 3u8, {
let master_cs_pol: u32 = unsafe { ::core::mem::transmute(master_cs_pol) };
master_cs_pol as u64
});
__bindgen_bitfield_unit.set(9usize, 2u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit.set(11usize, 3u8, {
let master_ck_sel: u32 = unsafe { ::core::mem::transmute(master_ck_sel) };
master_ck_sel as u64
});
__bindgen_bitfield_unit.set(14usize, 15u8, {
let reserved14: u32 = unsafe { ::core::mem::transmute(reserved14) };
reserved14 as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let ck_idle_edge: u32 = unsafe { ::core::mem::transmute(ck_idle_edge) };
ck_idle_edge as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let cs_keep_active: u32 = unsafe { ::core::mem::transmute(cs_keep_active) };
cs_keep_active as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let reserved31: u32 = unsafe { ::core::mem::transmute(reserved31) };
reserved31 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_13 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn rd_buf_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_buf_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_buf_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_buf_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rd_sta_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_sta_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_sta_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_sta_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn trans_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_trans_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn rd_buf_inten(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_buf_inten(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_buf_inten(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_buf_inten(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn rd_sta_inten(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_rd_sta_inten(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_sta_inten(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_sta_inten(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn trans_inten(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_trans_inten(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn cs_i_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 2u8) as u32) }
}
#[inline]
pub fn set_cs_i_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 5u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 5u8, val as u64)
}
}
#[inline]
pub fn last_command(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 3u8) as u32) }
}
#[inline]
pub fn set_last_command(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 3u8, val as u64)
}
}
#[inline]
pub fn last_state(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 3u8) as u32) }
}
#[inline]
pub fn set_last_state(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 3u8, val as u64)
}
}
#[inline]
pub fn trans_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 4u8) as u32) }
}
#[inline]
pub fn set_trans_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 4u8, val as u64)
}
}
#[inline]
pub fn cmd_define(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 1u8) as u32) }
}
#[inline]
pub fn set_cmd_define(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_rd_sta_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_rd_sta_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_rd_buf_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_wr_rd_buf_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn slave_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_slave_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn sync_reset(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_sync_reset(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rd_buf_done: u32,
wr_buf_done: u32,
rd_sta_done: u32,
wr_sta_done: u32,
trans_done: u32,
rd_buf_inten: u32,
wr_buf_inten: u32,
rd_sta_inten: u32,
wr_sta_inten: u32,
trans_inten: u32,
cs_i_mode: u32,
reserved12: u32,
last_command: u32,
last_state: u32,
trans_cnt: u32,
cmd_define: u32,
wr_rd_sta_en: u32,
wr_rd_buf_en: u32,
slave_mode: u32,
sync_reset: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rd_buf_done: u32 = unsafe { ::core::mem::transmute(rd_buf_done) };
rd_buf_done as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let wr_buf_done: u32 = unsafe { ::core::mem::transmute(wr_buf_done) };
wr_buf_done as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rd_sta_done: u32 = unsafe { ::core::mem::transmute(rd_sta_done) };
rd_sta_done as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let wr_sta_done: u32 = unsafe { ::core::mem::transmute(wr_sta_done) };
wr_sta_done as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let trans_done: u32 = unsafe { ::core::mem::transmute(trans_done) };
trans_done as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let rd_buf_inten: u32 = unsafe { ::core::mem::transmute(rd_buf_inten) };
rd_buf_inten as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let wr_buf_inten: u32 = unsafe { ::core::mem::transmute(wr_buf_inten) };
wr_buf_inten as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let rd_sta_inten: u32 = unsafe { ::core::mem::transmute(rd_sta_inten) };
rd_sta_inten as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let wr_sta_inten: u32 = unsafe { ::core::mem::transmute(wr_sta_inten) };
wr_sta_inten as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let trans_inten: u32 = unsafe { ::core::mem::transmute(trans_inten) };
trans_inten as u64
});
__bindgen_bitfield_unit.set(10usize, 2u8, {
let cs_i_mode: u32 = unsafe { ::core::mem::transmute(cs_i_mode) };
cs_i_mode as u64
});
__bindgen_bitfield_unit.set(12usize, 5u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit.set(17usize, 3u8, {
let last_command: u32 = unsafe { ::core::mem::transmute(last_command) };
last_command as u64
});
__bindgen_bitfield_unit.set(20usize, 3u8, {
let last_state: u32 = unsafe { ::core::mem::transmute(last_state) };
last_state as u64
});
__bindgen_bitfield_unit.set(23usize, 4u8, {
let trans_cnt: u32 = unsafe { ::core::mem::transmute(trans_cnt) };
trans_cnt as u64
});
__bindgen_bitfield_unit.set(27usize, 1u8, {
let cmd_define: u32 = unsafe { ::core::mem::transmute(cmd_define) };
cmd_define as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let wr_rd_sta_en: u32 = unsafe { ::core::mem::transmute(wr_rd_sta_en) };
wr_rd_sta_en as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let wr_rd_buf_en: u32 = unsafe { ::core::mem::transmute(wr_rd_buf_en) };
wr_rd_buf_en as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let slave_mode: u32 = unsafe { ::core::mem::transmute(slave_mode) };
slave_mode as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let sync_reset: u32 = unsafe { ::core::mem::transmute(sync_reset) };
sync_reset as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_14 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_14__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_14__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_14__bindgen_ty_1 {
#[inline]
pub fn rdbuf_dummy_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rdbuf_dummy_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn wrbuf_dummy_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_wrbuf_dummy_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn rdsta_dummy_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_rdsta_dummy_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn wrsta_dummy_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_wrsta_dummy_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn wr_addr_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 6u8) as u32) }
}
#[inline]
pub fn set_wr_addr_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 6u8, val as u64)
}
}
#[inline]
pub fn rd_addr_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 6u8) as u32) }
}
#[inline]
pub fn set_rd_addr_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 6u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 9u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 9u8, val as u64)
}
}
#[inline]
pub fn status_readback(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_status_readback(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn status_fast_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 1u8) as u32) }
}
#[inline]
pub fn set_status_fast_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 1u8, val as u64)
}
}
#[inline]
pub fn status_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 5u8) as u32) }
}
#[inline]
pub fn set_status_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 5u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rdbuf_dummy_en: u32,
wrbuf_dummy_en: u32,
rdsta_dummy_en: u32,
wrsta_dummy_en: u32,
wr_addr_bitlen: u32,
rd_addr_bitlen: u32,
reserved16: u32,
status_readback: u32,
status_fast_en: u32,
status_bitlen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rdbuf_dummy_en: u32 = unsafe { ::core::mem::transmute(rdbuf_dummy_en) };
rdbuf_dummy_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let wrbuf_dummy_en: u32 = unsafe { ::core::mem::transmute(wrbuf_dummy_en) };
wrbuf_dummy_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let rdsta_dummy_en: u32 = unsafe { ::core::mem::transmute(rdsta_dummy_en) };
rdsta_dummy_en as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let wrsta_dummy_en: u32 = unsafe { ::core::mem::transmute(wrsta_dummy_en) };
wrsta_dummy_en as u64
});
__bindgen_bitfield_unit.set(4usize, 6u8, {
let wr_addr_bitlen: u32 = unsafe { ::core::mem::transmute(wr_addr_bitlen) };
wr_addr_bitlen as u64
});
__bindgen_bitfield_unit.set(10usize, 6u8, {
let rd_addr_bitlen: u32 = unsafe { ::core::mem::transmute(rd_addr_bitlen) };
rd_addr_bitlen as u64
});
__bindgen_bitfield_unit.set(16usize, 9u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let status_readback: u32 = unsafe { ::core::mem::transmute(status_readback) };
status_readback as u64
});
__bindgen_bitfield_unit.set(26usize, 1u8, {
let status_fast_en: u32 = unsafe { ::core::mem::transmute(status_fast_en) };
status_fast_en as u64
});
__bindgen_bitfield_unit.set(27usize, 5u8, {
let status_bitlen: u32 = unsafe { ::core::mem::transmute(status_bitlen) };
status_bitlen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_15 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_15__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_15__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_15__bindgen_ty_1 {
#[inline]
pub fn rdsta_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_rdsta_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn wrsta_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_wrsta_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn rdbuf_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_rdbuf_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn wrbuf_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_wrbuf_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rdsta_dummy_cyclelen: u32,
wrsta_dummy_cyclelen: u32,
rdbuf_dummy_cyclelen: u32,
wrbuf_dummy_cyclelen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let rdsta_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(rdsta_dummy_cyclelen) };
rdsta_dummy_cyclelen as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let wrsta_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(wrsta_dummy_cyclelen) };
wrsta_dummy_cyclelen as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let rdbuf_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(rdbuf_dummy_cyclelen) };
rdbuf_dummy_cyclelen as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let wrbuf_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(wrbuf_dummy_cyclelen) };
wrbuf_dummy_cyclelen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_16 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_16__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_16__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_16__bindgen_ty_1 {
#[inline]
pub fn rdbuf_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_rdbuf_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn wrbuf_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_wrbuf_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn rdsta_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_rdsta_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn wrsta_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_wrsta_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rdbuf_cmd_value: u32,
wrbuf_cmd_value: u32,
rdsta_cmd_value: u32,
wrsta_cmd_value: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let rdbuf_cmd_value: u32 = unsafe { ::core::mem::transmute(rdbuf_cmd_value) };
rdbuf_cmd_value as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let wrbuf_cmd_value: u32 = unsafe { ::core::mem::transmute(wrbuf_cmd_value) };
wrbuf_cmd_value as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let rdsta_cmd_value: u32 = unsafe { ::core::mem::transmute(rdsta_cmd_value) };
rdsta_cmd_value as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let wrsta_cmd_value: u32 = unsafe { ::core::mem::transmute(wrsta_cmd_value) };
wrsta_cmd_value as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_17 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_17__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_17__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_17__bindgen_ty_1 {
#[inline]
pub fn bit_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_bit_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
bit_len: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let bit_len: u32 = unsafe { ::core::mem::transmute(bit_len) };
bit_len as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_18 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_18__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_18__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_18__bindgen_ty_1 {
#[inline]
pub fn bit_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_bit_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
bit_len: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let bit_len: u32 = unsafe { ::core::mem::transmute(bit_len) };
bit_len as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_19 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_19__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_19__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_19__bindgen_ty_1 {
#[inline]
pub fn req_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_req_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_cmd_4byte(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_cmd_4byte(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_usr_cmd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_usr_cmd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn flash_pes_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_flash_pes_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
req_en: u32,
usr_cmd_4byte: u32,
flash_usr_cmd: u32,
flash_pes_en: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let req_en: u32 = unsafe { ::core::mem::transmute(req_en) };
req_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let usr_cmd_4byte: u32 = unsafe { ::core::mem::transmute(usr_cmd_4byte) };
usr_cmd_4byte as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let flash_usr_cmd: u32 = unsafe { ::core::mem::transmute(flash_usr_cmd) };
flash_usr_cmd as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let flash_pes_en: u32 = unsafe { ::core::mem::transmute(flash_pes_en) };
flash_pes_en as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_20 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_20__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_20__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_3__bindgen_ty_20__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_sram_dio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_sram_dio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_sram_qio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_sram_qio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_wr_sram_dummy(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_wr_sram_dummy(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn usr_rd_sram_dummy(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_usr_rd_sram_dummy(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn cache_sram_usr_rcmd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_cache_sram_usr_rcmd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn sram_bytes_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 8u8) as u32) }
}
#[inline]
pub fn set_sram_bytes_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 8u8, val as u64)
}
}
#[inline]
pub fn sram_dummy_cyclelen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 8u8) as u32) }
}
#[inline]
pub fn set_sram_dummy_cyclelen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 8u8, val as u64)
}
}
#[inline]
pub fn sram_addr_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 6u8) as u32) }
}
#[inline]
pub fn set_sram_addr_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 6u8, val as u64)
}
}
#[inline]
pub fn cache_sram_usr_wcmd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_cache_sram_usr_wcmd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved29(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 3u8) as u32) }
}
#[inline]
pub fn set_reserved29(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 3u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
usr_sram_dio: u32,
usr_sram_qio: u32,
usr_wr_sram_dummy: u32,
usr_rd_sram_dummy: u32,
cache_sram_usr_rcmd: u32,
sram_bytes_len: u32,
sram_dummy_cyclelen: u32,
sram_addr_bitlen: u32,
cache_sram_usr_wcmd: u32,
reserved29: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let usr_sram_dio: u32 = unsafe { ::core::mem::transmute(usr_sram_dio) };
usr_sram_dio as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let usr_sram_qio: u32 = unsafe { ::core::mem::transmute(usr_sram_qio) };
usr_sram_qio as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let usr_wr_sram_dummy: u32 = unsafe { ::core::mem::transmute(usr_wr_sram_dummy) };
usr_wr_sram_dummy as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let usr_rd_sram_dummy: u32 = unsafe { ::core::mem::transmute(usr_rd_sram_dummy) };
usr_rd_sram_dummy as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let cache_sram_usr_rcmd: u32 = unsafe { ::core::mem::transmute(cache_sram_usr_rcmd) };
cache_sram_usr_rcmd as u64
});
__bindgen_bitfield_unit.set(6usize, 8u8, {
let sram_bytes_len: u32 = unsafe { ::core::mem::transmute(sram_bytes_len) };
sram_bytes_len as u64
});
__bindgen_bitfield_unit.set(14usize, 8u8, {
let sram_dummy_cyclelen: u32 = unsafe { ::core::mem::transmute(sram_dummy_cyclelen) };
sram_dummy_cyclelen as u64
});
__bindgen_bitfield_unit.set(22usize, 6u8, {
let sram_addr_bitlen: u32 = unsafe { ::core::mem::transmute(sram_addr_bitlen) };
sram_addr_bitlen as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let cache_sram_usr_wcmd: u32 = unsafe { ::core::mem::transmute(cache_sram_usr_wcmd) };
cache_sram_usr_wcmd as u64
});
__bindgen_bitfield_unit.set(29usize, 3u8, {
let reserved29: u32 = unsafe { ::core::mem::transmute(reserved29) };
reserved29 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_21 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_21__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_21__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_21__bindgen_ty_1 {
#[inline]
pub fn dio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_dio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn qio(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_qio(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 2u8, val as u64)
}
}
#[inline]
pub fn rst_io(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rst_io(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved5(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 27u8) as u32) }
}
#[inline]
pub fn set_reserved5(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 27u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
dio: u32,
qio: u32,
reserved2: u32,
rst_io: u32,
reserved5: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let dio: u32 = unsafe { ::core::mem::transmute(dio) };
dio as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let qio: u32 = unsafe { ::core::mem::transmute(qio) };
qio as u64
});
__bindgen_bitfield_unit.set(2usize, 2u8, {
let reserved2: u32 = unsafe { ::core::mem::transmute(reserved2) };
reserved2 as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rst_io: u32 = unsafe { ::core::mem::transmute(rst_io) };
rst_io as u64
});
__bindgen_bitfield_unit.set(5usize, 27u8, {
let reserved5: u32 = unsafe { ::core::mem::transmute(reserved5) };
reserved5 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_22 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_22__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_22__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_22__bindgen_ty_1 {
#[inline]
pub fn usr_rd_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_usr_rd_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 12u8, val as u64)
}
}
#[inline]
pub fn usr_rd_cmd_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_usr_rd_cmd_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_rd_cmd_value: u32,
reserved16: u32,
usr_rd_cmd_bitlen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let usr_rd_cmd_value: u32 = unsafe { ::core::mem::transmute(usr_rd_cmd_value) };
usr_rd_cmd_value as u64
});
__bindgen_bitfield_unit.set(16usize, 12u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let usr_rd_cmd_bitlen: u32 = unsafe { ::core::mem::transmute(usr_rd_cmd_bitlen) };
usr_rd_cmd_bitlen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_23 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_23__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_23__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_23__bindgen_ty_1 {
#[inline]
pub fn usr_wr_cmd_value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_usr_wr_cmd_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 12u8, val as u64)
}
}
#[inline]
pub fn usr_wr_cmd_bitlen(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_usr_wr_cmd_bitlen(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
usr_wr_cmd_value: u32,
reserved16: u32,
usr_wr_cmd_bitlen: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let usr_wr_cmd_value: u32 = unsafe { ::core::mem::transmute(usr_wr_cmd_value) };
usr_wr_cmd_value as u64
});
__bindgen_bitfield_unit.set(16usize, 12u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let usr_wr_cmd_bitlen: u32 = unsafe { ::core::mem::transmute(usr_wr_cmd_bitlen) };
usr_wr_cmd_bitlen as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_24 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_24__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_24__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_24__bindgen_ty_1 {
#[inline]
pub fn slv_rdata_bit(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_slv_rdata_bit(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
slv_rdata_bit: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let slv_rdata_bit: u32 = unsafe { ::core::mem::transmute(slv_rdata_bit) };
slv_rdata_bit as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_25 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_25__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_25__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_25__bindgen_ty_1 {
#[inline]
pub fn t_pp_time(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_t_pp_time(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn t_pp_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 4u8) as u32) }
}
#[inline]
pub fn set_t_pp_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 11u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 11u8, val as u64)
}
}
#[inline]
pub fn t_pp_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_t_pp_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t_pp_time: u32,
reserved12: u32,
t_pp_shift: u32,
reserved20: u32,
t_pp_ena: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let t_pp_time: u32 = unsafe { ::core::mem::transmute(t_pp_time) };
t_pp_time as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit.set(16usize, 4u8, {
let t_pp_shift: u32 = unsafe { ::core::mem::transmute(t_pp_shift) };
t_pp_shift as u64
});
__bindgen_bitfield_unit.set(20usize, 11u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let t_pp_ena: u32 = unsafe { ::core::mem::transmute(t_pp_ena) };
t_pp_ena as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_26 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_26__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_26__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_26__bindgen_ty_1 {
#[inline]
pub fn t_erase_time(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_t_erase_time(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 4u8, val as u64)
}
}
#[inline]
pub fn t_erase_shift(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 4u8) as u32) }
}
#[inline]
pub fn set_t_erase_shift(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 11u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 11u8, val as u64)
}
}
#[inline]
pub fn t_erase_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_t_erase_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t_erase_time: u32,
reserved12: u32,
t_erase_shift: u32,
reserved20: u32,
t_erase_ena: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let t_erase_time: u32 = unsafe { ::core::mem::transmute(t_erase_time) };
t_erase_time as u64
});
__bindgen_bitfield_unit.set(12usize, 4u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit.set(16usize, 4u8, {
let t_erase_shift: u32 = unsafe { ::core::mem::transmute(t_erase_shift) };
t_erase_shift as u64
});
__bindgen_bitfield_unit.set(20usize, 11u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let t_erase_ena: u32 = unsafe { ::core::mem::transmute(t_erase_ena) };
t_erase_ena as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_27 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_27__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_27__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_27__bindgen_ty_1 {
#[inline]
pub fn st(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_st(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 29u8) as u32) }
}
#[inline]
pub fn set_reserved3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 29u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(st: u32, reserved3: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let st: u32 = unsafe { ::core::mem::transmute(st) };
st as u64
});
__bindgen_bitfield_unit.set(3usize, 29u8, {
let reserved3: u32 = unsafe { ::core::mem::transmute(reserved3) };
reserved3 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_28 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_28__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_28__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_28__bindgen_ty_1 {
#[inline]
pub fn int_hold_ena(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_int_hold_ena(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn reserved2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 30u8) as u32) }
}
#[inline]
pub fn set_reserved2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 30u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
int_hold_ena: u32,
reserved2: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let int_hold_ena: u32 = unsafe { ::core::mem::transmute(int_hold_ena) };
int_hold_ena as u64
});
__bindgen_bitfield_unit.set(2usize, 30u8, {
let reserved2: u32 = unsafe { ::core::mem::transmute(reserved2) };
reserved2 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_29 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_29__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_29__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_3__bindgen_ty_29__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn in_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn ahbm_fifo_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_ahbm_fifo_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn ahbm_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_ahbm_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_loop_test(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_loop_test(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_loop_test(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_loop_test(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_auto_wrback(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_auto_wrback(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof_mode(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof_mode(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn outdscr_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_outdscr_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn indscr_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_indscr_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_data_burst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_data_burst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved13(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved13(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn dma_rx_stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_dma_rx_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn dma_tx_stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_dma_tx_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn dma_continue(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_dma_continue(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved17(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 15u8) as u32) }
}
#[inline]
pub fn set_reserved17(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 15u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
in_rst: u32,
out_rst: u32,
ahbm_fifo_rst: u32,
ahbm_rst: u32,
in_loop_test: u32,
out_loop_test: u32,
out_auto_wrback: u32,
out_eof_mode: u32,
outdscr_burst_en: u32,
indscr_burst_en: u32,
out_data_burst_en: u32,
reserved13: u32,
dma_rx_stop: u32,
dma_tx_stop: u32,
dma_continue: u32,
reserved17: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let in_rst: u32 = unsafe { ::core::mem::transmute(in_rst) };
in_rst as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let out_rst: u32 = unsafe { ::core::mem::transmute(out_rst) };
out_rst as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let ahbm_fifo_rst: u32 = unsafe { ::core::mem::transmute(ahbm_fifo_rst) };
ahbm_fifo_rst as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let ahbm_rst: u32 = unsafe { ::core::mem::transmute(ahbm_rst) };
ahbm_rst as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let in_loop_test: u32 = unsafe { ::core::mem::transmute(in_loop_test) };
in_loop_test as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_loop_test: u32 = unsafe { ::core::mem::transmute(out_loop_test) };
out_loop_test as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_auto_wrback: u32 = unsafe { ::core::mem::transmute(out_auto_wrback) };
out_auto_wrback as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let out_eof_mode: u32 = unsafe { ::core::mem::transmute(out_eof_mode) };
out_eof_mode as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let outdscr_burst_en: u32 = unsafe { ::core::mem::transmute(outdscr_burst_en) };
outdscr_burst_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let indscr_burst_en: u32 = unsafe { ::core::mem::transmute(indscr_burst_en) };
indscr_burst_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let out_data_burst_en: u32 = unsafe { ::core::mem::transmute(out_data_burst_en) };
out_data_burst_en as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let reserved13: u32 = unsafe { ::core::mem::transmute(reserved13) };
reserved13 as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let dma_rx_stop: u32 = unsafe { ::core::mem::transmute(dma_rx_stop) };
dma_rx_stop as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let dma_tx_stop: u32 = unsafe { ::core::mem::transmute(dma_tx_stop) };
dma_tx_stop as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let dma_continue: u32 = unsafe { ::core::mem::transmute(dma_continue) };
dma_continue as u64
});
__bindgen_bitfield_unit.set(17usize, 15u8, {
let reserved17: u32 = unsafe { ::core::mem::transmute(reserved17) };
reserved17 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_30 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_30__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_30__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_30__bindgen_ty_1 {
#[inline]
pub fn addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 8u8, val as u64)
}
}
#[inline]
pub fn stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn restart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_restart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved31(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved31(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
addr: u32,
reserved20: u32,
stop: u32,
start: u32,
restart: u32,
reserved31: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let addr: u32 = unsafe { ::core::mem::transmute(addr) };
addr as u64
});
__bindgen_bitfield_unit.set(20usize, 8u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let stop: u32 = unsafe { ::core::mem::transmute(stop) };
stop as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let restart: u32 = unsafe { ::core::mem::transmute(restart) };
restart as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let reserved31: u32 = unsafe { ::core::mem::transmute(reserved31) };
reserved31 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_31 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_31__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_31__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_31__bindgen_ty_1 {
#[inline]
pub fn addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn auto_ret(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_auto_ret(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved21(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved21(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 7u8, val as u64)
}
}
#[inline]
pub fn stop(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_stop(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn restart(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_restart(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved31(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved31(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
addr: u32,
auto_ret: u32,
reserved21: u32,
stop: u32,
start: u32,
restart: u32,
reserved31: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let addr: u32 = unsafe { ::core::mem::transmute(addr) };
addr as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let auto_ret: u32 = unsafe { ::core::mem::transmute(auto_ret) };
auto_ret as u64
});
__bindgen_bitfield_unit.set(21usize, 7u8, {
let reserved21: u32 = unsafe { ::core::mem::transmute(reserved21) };
reserved21 as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let stop: u32 = unsafe { ::core::mem::transmute(stop) };
stop as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let restart: u32 = unsafe { ::core::mem::transmute(restart) };
restart as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let reserved31: u32 = unsafe { ::core::mem::transmute(reserved31) };
reserved31 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_32 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_32__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_32__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_32__bindgen_ty_1 {
#[inline]
pub fn rx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 30u8) as u32) }
}
#[inline]
pub fn set_reserved2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 30u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_en: u32,
tx_en: u32,
reserved2: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rx_en: u32 = unsafe { ::core::mem::transmute(rx_en) };
rx_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let tx_en: u32 = unsafe { ::core::mem::transmute(tx_en) };
tx_en as u64
});
__bindgen_bitfield_unit.set(2usize, 30u8, {
let reserved2: u32 = unsafe { ::core::mem::transmute(reserved2) };
reserved2 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_33 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_33__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_33__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_33__bindgen_ty_1 {
#[inline]
pub fn inlink_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn outlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_outlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn inlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 23u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 23u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
inlink_dscr_empty: u32,
outlink_dscr_error: u32,
inlink_dscr_error: u32,
in_done: u32,
in_err_eof: u32,
in_suc_eof: u32,
out_done: u32,
out_eof: u32,
out_total_eof: u32,
reserved9: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let inlink_dscr_empty: u32 = unsafe { ::core::mem::transmute(inlink_dscr_empty) };
inlink_dscr_empty as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let outlink_dscr_error: u32 = unsafe { ::core::mem::transmute(outlink_dscr_error) };
outlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let inlink_dscr_error: u32 = unsafe { ::core::mem::transmute(inlink_dscr_error) };
inlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(9usize, 23u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_34 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_34__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_34__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_34__bindgen_ty_1 {
#[inline]
pub fn inlink_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn outlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_outlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn inlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 23u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 23u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
inlink_dscr_empty: u32,
outlink_dscr_error: u32,
inlink_dscr_error: u32,
in_done: u32,
in_err_eof: u32,
in_suc_eof: u32,
out_done: u32,
out_eof: u32,
out_total_eof: u32,
reserved9: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let inlink_dscr_empty: u32 = unsafe { ::core::mem::transmute(inlink_dscr_empty) };
inlink_dscr_empty as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let outlink_dscr_error: u32 = unsafe { ::core::mem::transmute(outlink_dscr_error) };
outlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let inlink_dscr_error: u32 = unsafe { ::core::mem::transmute(inlink_dscr_error) };
inlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(9usize, 23u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_35 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_35__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_35__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_35__bindgen_ty_1 {
#[inline]
pub fn inlink_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn outlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_outlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn inlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 23u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 23u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
inlink_dscr_empty: u32,
outlink_dscr_error: u32,
inlink_dscr_error: u32,
in_done: u32,
in_err_eof: u32,
in_suc_eof: u32,
out_done: u32,
out_eof: u32,
out_total_eof: u32,
reserved9: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let inlink_dscr_empty: u32 = unsafe { ::core::mem::transmute(inlink_dscr_empty) };
inlink_dscr_empty as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let outlink_dscr_error: u32 = unsafe { ::core::mem::transmute(outlink_dscr_error) };
outlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let inlink_dscr_error: u32 = unsafe { ::core::mem::transmute(inlink_dscr_error) };
inlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(9usize, 23u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_36 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_36__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_36__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_36__bindgen_ty_1 {
#[inline]
pub fn inlink_dscr_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn outlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_outlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn inlink_dscr_error(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_inlink_dscr_error(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_err_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_err_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn in_suc_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_in_suc_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn out_total_eof(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_out_total_eof(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved9(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 23u8) as u32) }
}
#[inline]
pub fn set_reserved9(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 23u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
inlink_dscr_empty: u32,
outlink_dscr_error: u32,
inlink_dscr_error: u32,
in_done: u32,
in_err_eof: u32,
in_suc_eof: u32,
out_done: u32,
out_eof: u32,
out_total_eof: u32,
reserved9: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let inlink_dscr_empty: u32 = unsafe { ::core::mem::transmute(inlink_dscr_empty) };
inlink_dscr_empty as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let outlink_dscr_error: u32 = unsafe { ::core::mem::transmute(outlink_dscr_error) };
outlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let inlink_dscr_error: u32 = unsafe { ::core::mem::transmute(inlink_dscr_error) };
inlink_dscr_error as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let in_done: u32 = unsafe { ::core::mem::transmute(in_done) };
in_done as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let in_err_eof: u32 = unsafe { ::core::mem::transmute(in_err_eof) };
in_err_eof as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let in_suc_eof: u32 = unsafe { ::core::mem::transmute(in_suc_eof) };
in_suc_eof as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let out_done: u32 = unsafe { ::core::mem::transmute(out_done) };
out_done as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let out_eof: u32 = unsafe { ::core::mem::transmute(out_eof) };
out_eof as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let out_total_eof: u32 = unsafe { ::core::mem::transmute(out_total_eof) };
out_total_eof as u64
});
__bindgen_bitfield_unit.set(9usize, 23u8, {
let reserved9: u32 = unsafe { ::core::mem::transmute(reserved9) };
reserved9 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_3__bindgen_ty_37 {
pub __bindgen_anon_1: _bindgen_ty_3__bindgen_ty_37__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_3__bindgen_ty_37__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_3__bindgen_ty_37__bindgen_ty_1 {
#[inline]
pub fn date(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 28u8) as u32) }
}
#[inline]
pub fn set_date(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 28u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(date: u32, reserved28: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 28u8, {
let date: u32 = unsafe { ::core::mem::transmute(date) };
date as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
pub type spi_dev_t = _bindgen_ty_3;
extern "C" {
pub static mut SPI0: spi_dev_t;
}
extern "C" {
pub static mut SPI1: spi_dev_t;
}
extern "C" {
pub static mut SPI2: spi_dev_t;
}
extern "C" {
pub static mut SPI3: spi_dev_t;
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_signal_conn_t {
pub spiclk_out: u8,
pub spiclk_in: u8,
pub spid_out: u8,
pub spiq_out: u8,
pub spiwp_out: u8,
pub spihd_out: u8,
pub spid_in: u8,
pub spiq_in: u8,
pub spiwp_in: u8,
pub spihd_in: u8,
pub spics_out: [u8; 3usize],
pub spics_in: u8,
pub spiclk_iomux_pin: u8,
pub spid_iomux_pin: u8,
pub spiq_iomux_pin: u8,
pub spiwp_iomux_pin: u8,
pub spihd_iomux_pin: u8,
pub spics0_iomux_pin: u8,
pub irq: u8,
pub irq_dma: u8,
pub module: periph_module_t,
pub hw: *mut spi_dev_t,
}
extern "C" {
pub static mut spi_periph_signal: [spi_signal_conn_t; 3usize];
}
#[doc = "< SPI1, SPI"]
pub const spi_host_device_t_SPI_HOST: spi_host_device_t = 0;
#[doc = "< SPI2, HSPI"]
pub const spi_host_device_t_HSPI_HOST: spi_host_device_t = 1;
#[doc = "< SPI3, VSPI"]
pub const spi_host_device_t_VSPI_HOST: spi_host_device_t = 2;
#[doc = " @brief Enum with the three SPI peripherals that are software-accessible in it"]
pub type spi_host_device_t = u32;
#[doc = " @brief This is a configuration structure for a SPI bus."]
#[doc = ""]
#[doc = " You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the"]
#[doc = " GPIO matrix to route the signals. An exception is made when all signals either can be routed through"]
#[doc = " the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds."]
#[doc = ""]
#[doc = " @note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_bus_config_t {
#[doc = "< GPIO pin for Master Out Slave In (=spi_d) signal, or -1 if not used."]
pub mosi_io_num: ::std::os::raw::c_int,
#[doc = "< GPIO pin for Master In Slave Out (=spi_q) signal, or -1 if not used."]
pub miso_io_num: ::std::os::raw::c_int,
#[doc = "< GPIO pin for Spi CLocK signal, or -1 if not used."]
pub sclk_io_num: ::std::os::raw::c_int,
#[doc = "< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used."]
pub quadwp_io_num: ::std::os::raw::c_int,
#[doc = "< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used."]
pub quadhd_io_num: ::std::os::raw::c_int,
#[doc = "< Maximum transfer size, in bytes. Defaults to 4094 if 0."]
pub max_transfer_sz: ::std::os::raw::c_int,
#[doc = "< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags."]
pub flags: u32,
#[doc = "< Interrupt flag for the bus to set the priority, and IRAM attribute, see"]
#[doc = " ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored"]
#[doc = " by the driver. Note that if ESP_INTR_FLAG_IRAM is set, ALL the callbacks of"]
#[doc = " the driver, and their callee functions, should be put in the IRAM."]
pub intr_flags: ::std::os::raw::c_int,
}
extern "C" {
#[doc = " @brief Try to claim a SPI peripheral"]
#[doc = ""]
#[doc = " Call this if your driver wants to manage a SPI peripheral."]
#[doc = ""]
#[doc = " @param host Peripheral to claim"]
#[doc = " @return True if peripheral is claimed successfully; false if peripheral already is claimed."]
pub fn spicommon_periph_claim(host: spi_host_device_t) -> bool;
}
extern "C" {
#[doc = " @brief Return the SPI peripheral so another driver can claim it."]
#[doc = ""]
#[doc = " @param host Peripheral to return"]
#[doc = " @return True if peripheral is returned successfully; false if peripheral was free to claim already."]
pub fn spicommon_periph_free(host: spi_host_device_t) -> bool;
}
extern "C" {
#[doc = " @brief Try to claim a SPI DMA channel"]
#[doc = ""]
#[doc = " Call this if your driver wants to use SPI with a DMA channnel."]
#[doc = ""]
#[doc = " @param dma_chan channel to claim"]
#[doc = ""]
#[doc = " @return True if success; false otherwise."]
pub fn spicommon_dma_chan_claim(dma_chan: ::std::os::raw::c_int) -> bool;
}
extern "C" {
#[doc = " @brief Return the SPI DMA channel so other driver can claim it, or just to power down DMA."]
#[doc = ""]
#[doc = " @param dma_chan channel to return"]
#[doc = ""]
#[doc = " @return True if success; false otherwise."]
pub fn spicommon_dma_chan_free(dma_chan: ::std::os::raw::c_int) -> bool;
}
extern "C" {
#[doc = " @brief Connect a SPI peripheral to GPIO pins"]
#[doc = ""]
#[doc = " This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in"]
#[doc = " the arguments. Depending on the IO-pads requested, the routing is done either using the"]
#[doc = " IO_mux or using the GPIO matrix."]
#[doc = ""]
#[doc = " @param host SPI peripheral to be routed"]
#[doc = " @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins"]
#[doc = " @param dma_chan DMA-channel (1 or 2) to use, or 0 for no DMA."]
#[doc = " @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions:"]
#[doc = " - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode"]
#[doc = " - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode"]
#[doc = " - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: Pins set should match the iomux pins of the controller."]
#[doc = " - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``:"]
#[doc = " Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capability according to the mode."]
#[doc = " - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so that DIO mode is capable."]
#[doc = " - ``SPICOMMON_BUSFLAG_WPHD`` Make sure WP and HD are set to valid output GPIOs."]
#[doc = " - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``."]
#[doc = " @param[out] flags_o A SPICOMMON_BUSFLAG_* flag combination of bus abilities will be written to this address."]
#[doc = " Leave to NULL if not needed."]
#[doc = " - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: The bus is connected to iomux pins."]
#[doc = " - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: The bus has"]
#[doc = " CLK/MISO/MOSI connected."]
#[doc = " - ``SPICOMMON_BUSFLAG_DUAL``: The bus is capable with DIO mode."]
#[doc = " - ``SPICOMMON_BUSFLAG_WPHD`` The bus has WP and HD connected."]
#[doc = " - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spicommon_bus_initialize_io(
host: spi_host_device_t,
bus_config: *const spi_bus_config_t,
dma_chan: ::std::os::raw::c_int,
flags: u32,
flags_o: *mut u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Free the IO used by a SPI peripheral"]
#[doc = " @deprecated Use spicommon_bus_free_io_cfg instead."]
#[doc = ""]
#[doc = " @param host SPI peripheral to be freed"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spicommon_bus_free_io(host: spi_host_device_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Free the IO used by a SPI peripheral"]
#[doc = ""]
#[doc = " @param bus_cfg Bus config struct which defines which pins to be used."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spicommon_bus_free_io_cfg(bus_cfg: *const spi_bus_config_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initialize a Chip Select pin for a specific SPI peripheral"]
#[doc = ""]
#[doc = ""]
#[doc = " @param host SPI peripheral"]
#[doc = " @param cs_io_num GPIO pin to route"]
#[doc = " @param cs_num CS id to route"]
#[doc = " @param force_gpio_matrix If true, CS will always be routed through the GPIO matrix. If false,"]
#[doc = " if the GPIO number allows it, the routing will happen through the IO_mux."]
pub fn spicommon_cs_initialize(
host: spi_host_device_t,
cs_io_num: ::std::os::raw::c_int,
cs_num: ::std::os::raw::c_int,
force_gpio_matrix: ::std::os::raw::c_int,
);
}
extern "C" {
#[doc = " @brief Free a chip select line"]
#[doc = " @deprecated Use spicommon_cs_io, which inputs the gpio num rather than the cs id instead."]
#[doc = ""]
#[doc = " @param host SPI peripheral"]
#[doc = " @param cs_num CS id to free"]
pub fn spicommon_cs_free(host: spi_host_device_t, cs_num: ::std::os::raw::c_int);
}
extern "C" {
#[doc = " @brief Free a chip select line"]
#[doc = ""]
#[doc = " @param cs_gpio_num CS gpio num to free"]
pub fn spicommon_cs_free_io(cs_gpio_num: ::std::os::raw::c_int);
}
extern "C" {
#[doc = " @brief Setup a DMA link chain"]
#[doc = ""]
#[doc = " This routine will set up a chain of linked DMA descriptors in the array pointed to by"]
#[doc = " ``dmadesc``. Enough DMA descriptors will be used to fit the buffer of ``len`` bytes in, and the"]
#[doc = " descriptors will point to the corresponding positions in ``buffer`` and linked together. The"]
#[doc = " end result is that feeding ``dmadesc[0]`` into DMA hardware results in the entirety ``len`` bytes"]
#[doc = " of ``data`` being read or written."]
#[doc = ""]
#[doc = " @param dmadesc Pointer to array of DMA descriptors big enough to be able to convey ``len`` bytes"]
#[doc = " @param len Length of buffer"]
#[doc = " @param data Data buffer to use for DMA transfer"]
#[doc = " @param isrx True if data is to be written into ``data``, false if it's to be read from ``data``."]
pub fn spicommon_setup_dma_desc_links(
dmadesc: *mut lldesc_t,
len: ::std::os::raw::c_int,
data: *const u8,
isrx: bool,
);
}
extern "C" {
#[doc = " @brief Get the position of the hardware registers for a specific SPI host"]
#[doc = ""]
#[doc = " @param host The SPI host"]
#[doc = ""]
#[doc = " @return A register descriptor stuct pointer, pointed at the hardware registers"]
pub fn spicommon_hw_for_host(host: spi_host_device_t) -> *mut spi_dev_t;
}
extern "C" {
#[doc = " @brief Get the IRQ source for a specific SPI host"]
#[doc = ""]
#[doc = " @param host The SPI host"]
#[doc = ""]
#[doc = " @return The hosts IRQ source"]
pub fn spicommon_irqsource_for_host(host: spi_host_device_t) -> ::std::os::raw::c_int;
}
#[doc = " Callback, to be called when a DMA engine reset is completed"]
pub type dmaworkaround_cb_t =
::core::option::Option<unsafe extern "C" fn(arg: *mut ::std::os::raw::c_void)>;
extern "C" {
#[doc = " @brief Request a reset for a certain DMA channel"]
#[doc = ""]
#[doc = " @note In some (well-defined) cases in the ESP32 (at least rev v.0 and v.1), a SPI DMA channel will get confused. This can be remedied"]
#[doc = " by resetting the SPI DMA hardware in case this happens. Unfortunately, the reset knob used for thsi will reset _both_ DMA channels, and"]
#[doc = " as such can only done safely when both DMA channels are idle. These functions coordinate this."]
#[doc = ""]
#[doc = " Essentially, when a reset is needed, a driver can request this using spicommon_dmaworkaround_req_reset. This is supposed to be called"]
#[doc = " with an user-supplied function as an argument. If both DMA channels are idle, this call will reset the DMA subsystem and return true."]
#[doc = " If the other DMA channel is still busy, it will return false; as soon as the other DMA channel is done, however, it will reset the"]
#[doc = " DMA subsystem and call the callback. The callback is then supposed to be used to continue the SPI drivers activity."]
#[doc = ""]
#[doc = " @param dmachan DMA channel associated with the SPI host that needs a reset"]
#[doc = " @param cb Callback to call in case DMA channel cannot be reset immediately"]
#[doc = " @param arg Argument to the callback"]
#[doc = ""]
#[doc = " @return True when a DMA reset could be executed immediately. False when it could not; in this"]
#[doc = " case the callback will be called with the specified argument when the logic can execute"]
#[doc = " a reset, after that reset."]
pub fn spicommon_dmaworkaround_req_reset(
dmachan: ::std::os::raw::c_int,
cb: dmaworkaround_cb_t,
arg: *mut ::std::os::raw::c_void,
) -> bool;
}
extern "C" {
#[doc = " @brief Check if a DMA reset is requested but has not completed yet"]
#[doc = ""]
#[doc = " @return True when a DMA reset is requested but hasn't completed yet. False otherwise."]
pub fn spicommon_dmaworkaround_reset_in_progress() -> bool;
}
extern "C" {
#[doc = " @brief Mark a DMA channel as idle."]
#[doc = ""]
#[doc = " A call to this function tells the workaround logic that this channel will"]
#[doc = " not be affected by a global SPI DMA reset."]
pub fn spicommon_dmaworkaround_idle(dmachan: ::std::os::raw::c_int);
}
extern "C" {
#[doc = " @brief Mark a DMA channel as active."]
#[doc = ""]
#[doc = " A call to this function tells the workaround logic that this channel will"]
#[doc = " be affected by a global SPI DMA reset, and a reset like that should not be attempted."]
pub fn spicommon_dmaworkaround_transfer_active(dmachan: ::std::os::raw::c_int);
}
pub type transaction_cb_t =
::core::option::Option<unsafe extern "C" fn(trans: *mut spi_transaction_t)>;
#[doc = " @brief This is a configuration for a SPI slave device that is connected to one of the SPI buses."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_device_interface_config_t {
#[doc = "< Default amount of bits in command phase (0-16), used when ``SPI_TRANS_VARIABLE_CMD`` is not used, otherwise ignored."]
pub command_bits: u8,
#[doc = "< Default amount of bits in address phase (0-64), used when ``SPI_TRANS_VARIABLE_ADDR`` is not used, otherwise ignored."]
pub address_bits: u8,
#[doc = "< Amount of dummy bits to insert between address and data phase"]
pub dummy_bits: u8,
#[doc = "< SPI mode (0-3)"]
pub mode: u8,
#[doc = "< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128."]
pub duty_cycle_pos: u8,
#[doc = "< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions."]
pub cs_ena_pretrans: u8,
#[doc = "< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)"]
pub cs_ena_posttrans: u8,
#[doc = "< Clock speed, divisors of 80MHz, in Hz. See ``SPI_MASTER_FREQ_*``."]
pub clock_speed_hz: ::std::os::raw::c_int,
#[doc = "< Maximum data valid time of slave. The time required between SCLK and MISO"]
#[doc = "valid, including the possible clock delay from slave to master. The driver uses this value to give an extra"]
#[doc = "delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing"]
#[doc = "performance at high frequency (over 8MHz), it's suggest to have the right value."]
pub input_delay_ns: ::std::os::raw::c_int,
#[doc = "< CS GPIO pin for this device, or -1 if not used"]
pub spics_io_num: ::std::os::raw::c_int,
#[doc = "< Bitwise OR of SPI_DEVICE_* flags"]
pub flags: u32,
#[doc = "< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_device_queue_trans but not yet finished using spi_device_get_trans_result) at the same time"]
pub queue_size: ::std::os::raw::c_int,
#[doc = "< Callback to be called before a transmission is started."]
#[doc = ""]
#[doc = " This callback is called within interrupt"]
#[doc = " context should be in IRAM for best"]
#[doc = " performance, see \"Transferring Speed\""]
#[doc = " section in the SPI Master documentation for"]
#[doc = " full details. If not, the callback may crash"]
#[doc = " during flash operation when the driver is"]
#[doc = " initialized with ESP_INTR_FLAG_IRAM."]
pub pre_cb: transaction_cb_t,
#[doc = "< Callback to be called after a transmission has completed."]
#[doc = ""]
#[doc = " This callback is called within interrupt"]
#[doc = " context should be in IRAM for best"]
#[doc = " performance, see \"Transferring Speed\""]
#[doc = " section in the SPI Master documentation for"]
#[doc = " full details. If not, the callback may crash"]
#[doc = " during flash operation when the driver is"]
#[doc = " initialized with ESP_INTR_FLAG_IRAM."]
pub post_cb: transaction_cb_t,
}
#[doc = " This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes."]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct spi_transaction_t {
#[doc = "< Bitwise OR of SPI_TRANS_* flags"]
pub flags: u32,
#[doc = "< Command data, of which the length is set in the ``command_bits`` of spi_device_interface_config_t."]
#[doc = ""]
#[doc = " <b>NOTE: this field, used to be \"command\" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF 3.0.</b>"]
#[doc = ""]
#[doc = " Example: write 0x0123 and command_bits=12 to send command 0x12, 0x3_ (in previous version, you may have to write 0x3_12)."]
pub cmd: u16,
#[doc = "< Address data, of which the length is set in the ``address_bits`` of spi_device_interface_config_t."]
#[doc = ""]
#[doc = " <b>NOTE: this field, used to be \"address\" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF3.0.</b>"]
#[doc = ""]
#[doc = " Example: write 0x123400 and address_bits=24 to send address of 0x12, 0x34, 0x00 (in previous version, you may have to write 0x12340000)."]
pub addr: u64,
#[doc = "< Total data length, in bits"]
pub length: usize,
#[doc = "< Total data length received, should be not greater than ``length`` in full-duplex mode (0 defaults this to the value of ``length``)."]
pub rxlength: usize,
#[doc = "< User-defined variable. Can be used to store eg transaction ID."]
pub user: *mut ::std::os::raw::c_void,
pub __bindgen_anon_1: spi_transaction_t__bindgen_ty_1,
pub __bindgen_anon_2: spi_transaction_t__bindgen_ty_2,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union spi_transaction_t__bindgen_ty_1 {
#[doc = "< Pointer to transmit buffer, or NULL for no MOSI phase"]
pub tx_buffer: *const ::std::os::raw::c_void,
#[doc = "< If SPI_USE_TXDATA is set, data set here is sent directly from this variable."]
pub tx_data: [u8; 4usize],
_bindgen_union_align: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union spi_transaction_t__bindgen_ty_2 {
#[doc = "< Pointer to receive buffer, or NULL for no MISO phase. Written by 4 bytes-unit if DMA is used."]
pub rx_buffer: *mut ::std::os::raw::c_void,
#[doc = "< If SPI_USE_RXDATA is set, data is received directly to this variable"]
pub rx_data: [u8; 4usize],
_bindgen_union_align: u32,
}
#[doc = " This struct is for SPI transactions which may change their address and command length."]
#[doc = " Please do set the flags in base to ``SPI_TRANS_VARIABLE_CMD_ADR`` to use the bit length here."]
#[repr(C)]
#[derive(Copy, Clone)]
pub struct spi_transaction_ext_t {
#[doc = "< Transaction data, so that pointer to spi_transaction_t can be converted into spi_transaction_ext_t"]
pub base: spi_transaction_t,
#[doc = "< The command length in this transaction, in bits."]
pub command_bits: u8,
#[doc = "< The address length in this transaction, in bits."]
pub address_bits: u8,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_device_t {
_unused: [u8; 0],
}
pub type spi_device_handle_t = *mut spi_device_t;
extern "C" {
#[doc = " @brief Initialize a SPI bus"]
#[doc = ""]
#[doc = " @warning For now, only supports HSPI and VSPI."]
#[doc = ""]
#[doc = " @param host SPI peripheral that controls this bus"]
#[doc = " @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized"]
#[doc = " @param dma_chan Either channel 1 or 2, or 0 in the case when no DMA is required. Selecting a DMA channel"]
#[doc = " for a SPI bus allows transfers on the bus to have sizes only limited by the amount of"]
#[doc = " internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of"]
#[doc = " bytes transfered to a maximum of 32."]
#[doc = ""]
#[doc = " @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in"]
#[doc = " DMA-capable memory."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if configuration is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if host already is in use"]
#[doc = " - ESP_ERR_NO_MEM if out of memory"]
#[doc = " - ESP_OK on success"]
pub fn spi_bus_initialize(
host: spi_host_device_t,
bus_config: *const spi_bus_config_t,
dma_chan: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Free a SPI bus"]
#[doc = ""]
#[doc = " @warning In order for this to succeed, all devices have to be removed first."]
#[doc = ""]
#[doc = " @param host SPI peripheral to free"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if not all devices on the bus are freed"]
#[doc = " - ESP_OK on success"]
pub fn spi_bus_free(host: spi_host_device_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Allocate a device on a SPI bus"]
#[doc = ""]
#[doc = " This initializes the internal structures for a device, plus allocates a CS pin on the indicated SPI master"]
#[doc = " peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control"]
#[doc = " up to three devices."]
#[doc = ""]
#[doc = " @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are"]
#[doc = " supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz."]
#[doc = ""]
#[doc = " @param host SPI peripheral to allocate device on"]
#[doc = " @param dev_config SPI interface protocol config for the device"]
#[doc = " @param handle Pointer to variable to hold the device handle"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_NOT_FOUND if host doesn't have any free CS slots"]
#[doc = " - ESP_ERR_NO_MEM if out of memory"]
#[doc = " - ESP_OK on success"]
pub fn spi_bus_add_device(
host: spi_host_device_t,
dev_config: *const spi_device_interface_config_t,
handle: *mut spi_device_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Remove a device from the SPI bus"]
#[doc = ""]
#[doc = " @param handle Device handle to free"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if device already is freed"]
#[doc = " - ESP_OK on success"]
pub fn spi_bus_remove_device(handle: spi_device_handle_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue a SPI transaction for interrupt transaction execution. Get the result by ``spi_device_get_trans_result``."]
#[doc = ""]
#[doc = " @note Normally a device cannot start (queue) polling and interrupt"]
#[doc = " transactions simultaneously."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param trans_desc Description of transaction to execute"]
#[doc = " @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to"]
#[doc = " never time out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_TIMEOUT if there was no room in the queue before ticks_to_wait expired"]
#[doc = " - ESP_ERR_NO_MEM if allocating DMA-capable temporary buffer failed"]
#[doc = " - ESP_ERR_INVALID_STATE if previous transactions are not finished"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_queue_trans(
handle: spi_device_handle_t,
trans_desc: *mut spi_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the result of a SPI transaction queued earlier by ``spi_device_queue_trans``."]
#[doc = ""]
#[doc = " This routine will wait until a transaction to the given device"]
#[doc = " succesfully completed. It will then return the description of the"]
#[doc = " completed transaction so software can inspect the result and e.g. free the memory or"]
#[doc = " re-use the buffers."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param trans_desc Pointer to variable able to contain a pointer to the description of the transaction"]
#[doc = "that is executed. The descriptor should not be modified until the descriptor is returned by"]
#[doc = "spi_device_get_trans_result."]
#[doc = " @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time"]
#[doc = "out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_TIMEOUT if there was no completed transaction before ticks_to_wait expired"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_get_trans_result(
handle: spi_device_handle_t,
trans_desc: *mut *mut spi_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Send a SPI transaction, wait for it to complete, and return the result"]
#[doc = ""]
#[doc = " This function is the equivalent of calling spi_device_queue_trans() followed by spi_device_get_trans_result()."]
#[doc = " Do not use this when there is still a transaction separately queued (started) from spi_device_queue_trans() or polling_start/transmit that hasn't been finalized."]
#[doc = ""]
#[doc = " @note This function is not thread safe when multiple tasks access the same SPI device."]
#[doc = " Normally a device cannot start (queue) polling and interrupt"]
#[doc = " transactions simutanuously."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param trans_desc Description of transaction to execute"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_transmit(
handle: spi_device_handle_t,
trans_desc: *mut spi_transaction_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Immediately start a polling transaction."]
#[doc = ""]
#[doc = " @note Normally a device cannot start (queue) polling and interrupt"]
#[doc = " transactions simutanuously. Moreover, a device cannot start a new polling"]
#[doc = " transaction if another polling transaction is not finished."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param trans_desc Description of transaction to execute"]
#[doc = " @param ticks_to_wait Ticks to wait until there's room in the queue;"]
#[doc = " currently only portMAX_DELAY is supported."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_TIMEOUT if the device cannot get control of the bus before ``ticks_to_wait`` expired"]
#[doc = " - ESP_ERR_NO_MEM if allocating DMA-capable temporary buffer failed"]
#[doc = " - ESP_ERR_INVALID_STATE if previous transactions are not finished"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_polling_start(
handle: spi_device_handle_t,
trans_desc: *mut spi_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Poll until the polling transaction ends."]
#[doc = ""]
#[doc = " This routine will not return until the transaction to the given device has"]
#[doc = " succesfully completed. The task is not blocked, but actively busy-spins for"]
#[doc = " the transaction to be completed."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time"]
#[doc = "out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_TIMEOUT if the transaction cannot finish before ticks_to_wait expired"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_polling_end(
handle: spi_device_handle_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Send a polling transaction, wait for it to complete, and return the result"]
#[doc = ""]
#[doc = " This function is the equivalent of calling spi_device_polling_start() followed by spi_device_polling_end()."]
#[doc = " Do not use this when there is still a transaction that hasn't been finalized."]
#[doc = ""]
#[doc = " @note This function is not thread safe when multiple tasks access the same SPI device."]
#[doc = " Normally a device cannot start (queue) polling and interrupt"]
#[doc = " transactions simutanuously."]
#[doc = ""]
#[doc = " @param handle Device handle obtained using spi_host_add_dev"]
#[doc = " @param trans_desc Description of transaction to execute"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spi_device_polling_transmit(
handle: spi_device_handle_t,
trans_desc: *mut spi_transaction_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Occupy the SPI bus for a device to do continuous transactions."]
#[doc = ""]
#[doc = " Transactions to all other devices will be put off until ``spi_device_release_bus`` is called."]
#[doc = ""]
#[doc = " @note The function will wait until all the existing transactions have been sent."]
#[doc = ""]
#[doc = " @param device The device to occupy the bus."]
#[doc = " @param wait Time to wait before the the bus is occupied by the device. Currently MUST set to portMAX_DELAY."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG : ``wait`` is not set to portMAX_DELAY."]
#[doc = " - ESP_OK : Success."]
pub fn spi_device_acquire_bus(device: spi_device_handle_t, wait: TickType_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Release the SPI bus occupied by the device. All other devices can start sending transactions."]
#[doc = ""]
#[doc = " @param dev The device to release the bus."]
pub fn spi_device_release_bus(dev: spi_device_handle_t);
}
extern "C" {
#[doc = " @brief Calculate the working frequency that is most close to desired frequency, and also the register value."]
#[doc = ""]
#[doc = " @param fapb The frequency of apb clock, should be ``APB_CLK_FREQ``."]
#[doc = " @param hz Desired working frequency"]
#[doc = " @param duty_cycle Duty cycle of the spi clock"]
#[doc = " @param reg_o Output of value to be set in clock register, or NULL if not needed."]
#[doc = " @return Actual working frequency that most fit."]
pub fn spi_cal_clock(
fapb: ::std::os::raw::c_int,
hz: ::std::os::raw::c_int,
duty_cycle: ::std::os::raw::c_int,
reg_o: *mut u32,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Calculate the timing settings of specified frequency and settings."]
#[doc = ""]
#[doc = " @param gpio_is_used True if using GPIO matrix, or False if iomux pins are used."]
#[doc = " @param input_delay_ns Input delay from SCLK launch edge to MISO data valid."]
#[doc = " @param eff_clk Effective clock frequency (in Hz) from spi_cal_clock."]
#[doc = " @param dummy_o Address of dummy bits used output. Set to NULL if not needed."]
#[doc = " @param cycles_remain_o Address of cycles remaining (after dummy bits are used) output."]
#[doc = " - -1 If too many cycles remaining, suggest to compensate half a clock."]
#[doc = " - 0 If no remaining cycles or dummy bits are not used."]
#[doc = " - positive value: cycles suggest to compensate."]
#[doc = ""]
#[doc = " @note If **dummy_o* is not zero, it means dummy bits should be applied in half duplex mode, and full duplex mode may not work."]
pub fn spi_get_timing(
gpio_is_used: bool,
input_delay_ns: ::std::os::raw::c_int,
eff_clk: ::std::os::raw::c_int,
dummy_o: *mut ::std::os::raw::c_int,
cycles_remain_o: *mut ::std::os::raw::c_int,
);
}
extern "C" {
#[doc = " @brief Get the frequency limit of current configurations."]
#[doc = " SPI master working at this limit is OK, while above the limit, full duplex mode and DMA will not work,"]
#[doc = " and dummy bits will be aplied in the half duplex mode."]
#[doc = ""]
#[doc = " @param gpio_is_used True if using GPIO matrix, or False if native pins are used."]
#[doc = " @param input_delay_ns Input delay from SCLK launch edge to MISO data valid."]
#[doc = " @return Frequency limit of current configurations."]
pub fn spi_get_freq_limit(
gpio_is_used: bool,
input_delay_ns: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
pub type slave_transaction_cb_t =
::core::option::Option<unsafe extern "C" fn(trans: *mut spi_slave_transaction_t)>;
#[doc = " @brief This is a configuration for a SPI host acting as a slave device."]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_slave_interface_config_t {
#[doc = "< CS GPIO pin for this device"]
pub spics_io_num: ::std::os::raw::c_int,
#[doc = "< Bitwise OR of SPI_SLAVE_* flags"]
pub flags: u32,
#[doc = "< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_queue_trans but not yet finished using spi_slave_get_trans_result) at the same time"]
pub queue_size: ::std::os::raw::c_int,
#[doc = "< SPI mode (0-3)"]
pub mode: u8,
#[doc = "< Callback called after the SPI registers are loaded with new data."]
#[doc = ""]
#[doc = " This callback is called within interrupt"]
#[doc = " context should be in IRAM for best"]
#[doc = " performance, see \"Transferring Speed\""]
#[doc = " section in the SPI Master documentation for"]
#[doc = " full details. If not, the callback may crash"]
#[doc = " during flash operation when the driver is"]
#[doc = " initialized with ESP_INTR_FLAG_IRAM."]
pub post_setup_cb: slave_transaction_cb_t,
#[doc = "< Callback called after a transaction is done."]
#[doc = ""]
#[doc = " This callback is called within interrupt"]
#[doc = " context should be in IRAM for best"]
#[doc = " performance, see \"Transferring Speed\""]
#[doc = " section in the SPI Master documentation for"]
#[doc = " full details. If not, the callback may crash"]
#[doc = " during flash operation when the driver is"]
#[doc = " initialized with ESP_INTR_FLAG_IRAM."]
pub post_trans_cb: slave_transaction_cb_t,
}
#[doc = " This structure describes one SPI transaction"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct spi_slave_transaction_t {
#[doc = "< Total data length, in bits"]
pub length: usize,
#[doc = "< Transaction data length, in bits"]
pub trans_len: usize,
#[doc = "< Pointer to transmit buffer, or NULL for no MOSI phase"]
pub tx_buffer: *const ::std::os::raw::c_void,
#[doc = "< Pointer to receive buffer, or NULL for no MISO phase"]
pub rx_buffer: *mut ::std::os::raw::c_void,
#[doc = "< User-defined variable. Can be used to store eg transaction ID."]
pub user: *mut ::std::os::raw::c_void,
}
extern "C" {
#[doc = " @brief Initialize a SPI bus as a slave interface"]
#[doc = ""]
#[doc = " @warning For now, only supports HSPI and VSPI."]
#[doc = ""]
#[doc = " @param host SPI peripheral to use as a SPI slave interface"]
#[doc = " @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized"]
#[doc = " @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface"]
#[doc = " @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with"]
#[doc = " it. The SPI hardware has two DMA channels to share. This parameter indicates which"]
#[doc = " one to use."]
#[doc = ""]
#[doc = " @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in"]
#[doc = " DMA-capable memory."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if configuration is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if host already is in use"]
#[doc = " - ESP_ERR_NO_MEM if out of memory"]
#[doc = " - ESP_OK on success"]
pub fn spi_slave_initialize(
host: spi_host_device_t,
bus_config: *const spi_bus_config_t,
slave_config: *const spi_slave_interface_config_t,
dma_chan: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Free a SPI bus claimed as a SPI slave interface"]
#[doc = ""]
#[doc = " @param host SPI peripheral to free"]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_ERR_INVALID_STATE if not all devices on the bus are freed"]
#[doc = " - ESP_OK on success"]
pub fn spi_slave_free(host: spi_host_device_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Queue a SPI transaction for execution"]
#[doc = ""]
#[doc = " Queues a SPI transaction to be executed by this slave device. (The transaction queue size was specified when the slave"]
#[doc = " device was initialised via spi_slave_initialize.) This function may block if the queue is full (depending on the"]
#[doc = " ticks_to_wait parameter). No SPI operation is directly initiated by this function, the next queued transaction"]
#[doc = " will happen when the master initiates a SPI transaction by pulling down CS and sending out clock signals."]
#[doc = ""]
#[doc = " This function hands over ownership of the buffers in ``trans_desc`` to the SPI slave driver; the application is"]
#[doc = " not to access this memory until ``spi_slave_queue_trans`` is called to hand ownership back to the application."]
#[doc = ""]
#[doc = " @param host SPI peripheral that is acting as a slave"]
#[doc = " @param trans_desc Description of transaction to execute. Not const because we may want to write status back"]
#[doc = " into the transaction description."]
#[doc = " @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to"]
#[doc = " never time out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spi_slave_queue_trans(
host: spi_host_device_t,
trans_desc: *const spi_slave_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the result of a SPI transaction queued earlier"]
#[doc = ""]
#[doc = " This routine will wait until a transaction to the given device (queued earlier with"]
#[doc = " spi_slave_queue_trans) has succesfully completed. It will then return the description of the"]
#[doc = " completed transaction so software can inspect the result and e.g. free the memory or"]
#[doc = " re-use the buffers."]
#[doc = ""]
#[doc = " It is mandatory to eventually use this function for any transaction queued by ``spi_slave_queue_trans``."]
#[doc = ""]
#[doc = " @param host SPI peripheral to that is acting as a slave"]
#[doc = " @param[out] trans_desc Pointer to variable able to contain a pointer to the description of the"]
#[doc = " transaction that is executed"]
#[doc = " @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time"]
#[doc = " out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spi_slave_get_trans_result(
host: spi_host_device_t,
trans_desc: *mut *mut spi_slave_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Do a SPI transaction"]
#[doc = ""]
#[doc = " Essentially does the same as spi_slave_queue_trans followed by spi_slave_get_trans_result. Do"]
#[doc = " not use this when there is still a transaction queued that hasn't been finalized"]
#[doc = " using spi_slave_get_trans_result."]
#[doc = ""]
#[doc = " @param host SPI peripheral to that is acting as a slave"]
#[doc = " @param trans_desc Pointer to variable able to contain a pointer to the description of the"]
#[doc = " transaction that is executed. Not const because we may want to write status back"]
#[doc = " into the transaction description."]
#[doc = " @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time"]
#[doc = " out."]
#[doc = " @return"]
#[doc = " - ESP_ERR_INVALID_ARG if parameter is invalid"]
#[doc = " - ESP_OK on success"]
pub fn spi_slave_transmit(
host: spi_host_device_t,
trans_desc: *mut spi_slave_transaction_t,
ticks_to_wait: TickType_t,
) -> esp_err_t;
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_4 {
pub hw_timer: [_bindgen_ty_4__bindgen_ty_1; 2usize],
pub wdt_config0: _bindgen_ty_4__bindgen_ty_2,
pub wdt_config1: _bindgen_ty_4__bindgen_ty_3,
pub wdt_config2: u32,
pub wdt_config3: u32,
pub wdt_config4: u32,
pub wdt_config5: u32,
pub wdt_feed: u32,
pub wdt_wprotect: u32,
pub rtc_cali_cfg: _bindgen_ty_4__bindgen_ty_4,
pub rtc_cali_cfg1: _bindgen_ty_4__bindgen_ty_5,
pub lactconfig: _bindgen_ty_4__bindgen_ty_6,
pub lactrtc: _bindgen_ty_4__bindgen_ty_7,
pub lactlo: u32,
pub lacthi: u32,
pub lactupdate: u32,
pub lactalarmlo: u32,
pub lactalarmhi: u32,
pub lactloadlo: u32,
pub lactloadhi: u32,
pub lactload: u32,
pub int_ena: _bindgen_ty_4__bindgen_ty_8,
pub int_raw: _bindgen_ty_4__bindgen_ty_9,
pub int_st_timers: _bindgen_ty_4__bindgen_ty_10,
pub int_clr_timers: _bindgen_ty_4__bindgen_ty_11,
pub reserved_a8: u32,
pub reserved_ac: u32,
pub reserved_b0: u32,
pub reserved_b4: u32,
pub reserved_b8: u32,
pub reserved_bc: u32,
pub reserved_c0: u32,
pub reserved_c4: u32,
pub reserved_c8: u32,
pub reserved_cc: u32,
pub reserved_d0: u32,
pub reserved_d4: u32,
pub reserved_d8: u32,
pub reserved_dc: u32,
pub reserved_e0: u32,
pub reserved_e4: u32,
pub reserved_e8: u32,
pub reserved_ec: u32,
pub reserved_f0: u32,
pub reserved_f4: u32,
pub timg_date: _bindgen_ty_4__bindgen_ty_12,
pub clk: _bindgen_ty_4__bindgen_ty_13,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_1 {
pub config: _bindgen_ty_4__bindgen_ty_1__bindgen_ty_1,
pub cnt_low: u32,
pub cnt_high: u32,
pub update: u32,
pub alarm_low: u32,
pub alarm_high: u32,
pub load_low: u32,
pub load_high: u32,
pub reload: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_1__bindgen_ty_1 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_1__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_1__bindgen_ty_1__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_4__bindgen_ty_1__bindgen_ty_1__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn alarm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_alarm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn level_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_level_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn edge_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_edge_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn divider(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 16u8) as u32) }
}
#[inline]
pub fn set_divider(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 16u8, val as u64)
}
}
#[inline]
pub fn autoreload(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_autoreload(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn increase(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_increase(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn enable(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_enable(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
alarm_en: u32,
level_int_en: u32,
edge_int_en: u32,
divider: u32,
autoreload: u32,
increase: u32,
enable: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let alarm_en: u32 = unsafe { ::core::mem::transmute(alarm_en) };
alarm_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let level_int_en: u32 = unsafe { ::core::mem::transmute(level_int_en) };
level_int_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let edge_int_en: u32 = unsafe { ::core::mem::transmute(edge_int_en) };
edge_int_en as u64
});
__bindgen_bitfield_unit.set(13usize, 16u8, {
let divider: u32 = unsafe { ::core::mem::transmute(divider) };
divider as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let autoreload: u32 = unsafe { ::core::mem::transmute(autoreload) };
autoreload as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let increase: u32 = unsafe { ::core::mem::transmute(increase) };
increase as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let enable: u32 = unsafe { ::core::mem::transmute(enable) };
enable as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_2 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_4__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 14u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 14u8, val as u64)
}
}
#[inline]
pub fn flashboot_mod_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_flashboot_mod_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn sys_reset_length(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 3u8) as u32) }
}
#[inline]
pub fn set_sys_reset_length(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 3u8, val as u64)
}
}
#[inline]
pub fn cpu_reset_length(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 3u8) as u32) }
}
#[inline]
pub fn set_cpu_reset_length(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 3u8, val as u64)
}
}
#[inline]
pub fn level_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_level_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn edge_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_edge_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn stg3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 2u8) as u32) }
}
#[inline]
pub fn set_stg3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 2u8, val as u64)
}
}
#[inline]
pub fn stg2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 2u8) as u32) }
}
#[inline]
pub fn set_stg2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 2u8, val as u64)
}
}
#[inline]
pub fn stg1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 2u8) as u32) }
}
#[inline]
pub fn set_stg1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 2u8, val as u64)
}
}
#[inline]
pub fn stg0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 2u8) as u32) }
}
#[inline]
pub fn set_stg0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 2u8, val as u64)
}
}
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
flashboot_mod_en: u32,
sys_reset_length: u32,
cpu_reset_length: u32,
level_int_en: u32,
edge_int_en: u32,
stg3: u32,
stg2: u32,
stg1: u32,
stg0: u32,
en: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 14u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let flashboot_mod_en: u32 = unsafe { ::core::mem::transmute(flashboot_mod_en) };
flashboot_mod_en as u64
});
__bindgen_bitfield_unit.set(15usize, 3u8, {
let sys_reset_length: u32 = unsafe { ::core::mem::transmute(sys_reset_length) };
sys_reset_length as u64
});
__bindgen_bitfield_unit.set(18usize, 3u8, {
let cpu_reset_length: u32 = unsafe { ::core::mem::transmute(cpu_reset_length) };
cpu_reset_length as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let level_int_en: u32 = unsafe { ::core::mem::transmute(level_int_en) };
level_int_en as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let edge_int_en: u32 = unsafe { ::core::mem::transmute(edge_int_en) };
edge_int_en as u64
});
__bindgen_bitfield_unit.set(23usize, 2u8, {
let stg3: u32 = unsafe { ::core::mem::transmute(stg3) };
stg3 as u64
});
__bindgen_bitfield_unit.set(25usize, 2u8, {
let stg2: u32 = unsafe { ::core::mem::transmute(stg2) };
stg2 as u64
});
__bindgen_bitfield_unit.set(27usize, 2u8, {
let stg1: u32 = unsafe { ::core::mem::transmute(stg1) };
stg1 as u64
});
__bindgen_bitfield_unit.set(29usize, 2u8, {
let stg0: u32 = unsafe { ::core::mem::transmute(stg0) };
stg0 as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_3 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_4__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 16u8, val as u64)
}
}
#[inline]
pub fn clk_prescale(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_clk_prescale(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
clk_prescale: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 16u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let clk_prescale: u32 = unsafe { ::core::mem::transmute(clk_prescale) };
clk_prescale as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_4 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_4__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 12u8, val as u64)
}
}
#[inline]
pub fn start_cycling(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_start_cycling(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn clk_sel(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 2u8) as u32) }
}
#[inline]
pub fn set_clk_sel(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 2u8, val as u64)
}
}
#[inline]
pub fn rdy(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rdy(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn max(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 15u8) as u32) }
}
#[inline]
pub fn set_max(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 15u8, val as u64)
}
}
#[inline]
pub fn start(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_start(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
start_cycling: u32,
clk_sel: u32,
rdy: u32,
max: u32,
start: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 12u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let start_cycling: u32 = unsafe { ::core::mem::transmute(start_cycling) };
start_cycling as u64
});
__bindgen_bitfield_unit.set(13usize, 2u8, {
let clk_sel: u32 = unsafe { ::core::mem::transmute(clk_sel) };
clk_sel as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rdy: u32 = unsafe { ::core::mem::transmute(rdy) };
rdy as u64
});
__bindgen_bitfield_unit.set(16usize, 15u8, {
let max: u32 = unsafe { ::core::mem::transmute(max) };
max as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let start: u32 = unsafe { ::core::mem::transmute(start) };
start as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_5 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 7u8, val as u64)
}
}
#[inline]
pub fn value(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 25u8) as u32) }
}
#[inline]
pub fn set_value(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 25u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(reserved0: u32, value: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 7u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(7usize, 25u8, {
let value: u32 = unsafe { ::core::mem::transmute(value) };
value as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_6 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_4__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 7u8, val as u64)
}
}
#[inline]
pub fn rtc_only(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_rtc_only(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn cpst_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_cpst_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn lac_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_lac_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn alarm_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_alarm_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn level_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_level_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn edge_int_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_edge_int_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn divider(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 16u8) as u32) }
}
#[inline]
pub fn set_divider(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 16u8, val as u64)
}
}
#[inline]
pub fn autoreload(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_autoreload(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn increase(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_increase(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
rtc_only: u32,
cpst_en: u32,
lac_en: u32,
alarm_en: u32,
level_int_en: u32,
edge_int_en: u32,
divider: u32,
autoreload: u32,
increase: u32,
en: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 7u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let rtc_only: u32 = unsafe { ::core::mem::transmute(rtc_only) };
rtc_only as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let cpst_en: u32 = unsafe { ::core::mem::transmute(cpst_en) };
cpst_en as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let lac_en: u32 = unsafe { ::core::mem::transmute(lac_en) };
lac_en as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let alarm_en: u32 = unsafe { ::core::mem::transmute(alarm_en) };
alarm_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let level_int_en: u32 = unsafe { ::core::mem::transmute(level_int_en) };
level_int_en as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let edge_int_en: u32 = unsafe { ::core::mem::transmute(edge_int_en) };
edge_int_en as u64
});
__bindgen_bitfield_unit.set(13usize, 16u8, {
let divider: u32 = unsafe { ::core::mem::transmute(divider) };
divider as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let autoreload: u32 = unsafe { ::core::mem::transmute(autoreload) };
autoreload as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let increase: u32 = unsafe { ::core::mem::transmute(increase) };
increase as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_7 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 6u8, val as u64)
}
}
#[inline]
pub fn step_len(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 26u8) as u32) }
}
#[inline]
pub fn set_step_len(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 26u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
step_len: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 6u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(6usize, 26u8, {
let step_len: u32 = unsafe { ::core::mem::transmute(step_len) };
step_len as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_8 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn t0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_t0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn t1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_t1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn wdt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_wdt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn lact(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_lact(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t0: u32,
t1: u32,
wdt: u32,
lact: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let t0: u32 = unsafe { ::core::mem::transmute(t0) };
t0 as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let t1: u32 = unsafe { ::core::mem::transmute(t1) };
t1 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let wdt: u32 = unsafe { ::core::mem::transmute(wdt) };
wdt as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let lact: u32 = unsafe { ::core::mem::transmute(lact) };
lact as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_9 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn t0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_t0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn t1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_t1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn wdt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_wdt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn lact(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_lact(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t0: u32,
t1: u32,
wdt: u32,
lact: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let t0: u32 = unsafe { ::core::mem::transmute(t0) };
t0 as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let t1: u32 = unsafe { ::core::mem::transmute(t1) };
t1 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let wdt: u32 = unsafe { ::core::mem::transmute(wdt) };
wdt as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let lact: u32 = unsafe { ::core::mem::transmute(lact) };
lact as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_10 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn t0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_t0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn t1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_t1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn wdt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_wdt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn lact(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_lact(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t0: u32,
t1: u32,
wdt: u32,
lact: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let t0: u32 = unsafe { ::core::mem::transmute(t0) };
t0 as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let t1: u32 = unsafe { ::core::mem::transmute(t1) };
t1 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let wdt: u32 = unsafe { ::core::mem::transmute(wdt) };
wdt as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let lact: u32 = unsafe { ::core::mem::transmute(lact) };
lact as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_11 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn t0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_t0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn t1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_t1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn wdt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_wdt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn lact(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_lact(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved4(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 28u8) as u32) }
}
#[inline]
pub fn set_reserved4(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 28u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
t0: u32,
t1: u32,
wdt: u32,
lact: u32,
reserved4: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let t0: u32 = unsafe { ::core::mem::transmute(t0) };
t0 as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let t1: u32 = unsafe { ::core::mem::transmute(t1) };
t1 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let wdt: u32 = unsafe { ::core::mem::transmute(wdt) };
wdt as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let lact: u32 = unsafe { ::core::mem::transmute(lact) };
lact as u64
});
__bindgen_bitfield_unit.set(4usize, 28u8, {
let reserved4: u32 = unsafe { ::core::mem::transmute(reserved4) };
reserved4 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_12 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn date(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 28u8) as u32) }
}
#[inline]
pub fn set_date(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 28u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(date: u32, reserved28: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 28u8, {
let date: u32 = unsafe { ::core::mem::transmute(date) };
date as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_4__bindgen_ty_13 {
pub __bindgen_anon_1: _bindgen_ty_4__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_4__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_4__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 31u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 31u8, val as u64)
}
}
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(reserved0: u32, en: u32) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 31u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit
}
}
pub type timg_dev_t = _bindgen_ty_4;
extern "C" {
pub static mut TIMERG0: timg_dev_t;
}
extern "C" {
pub static mut TIMERG1: timg_dev_t;
}
#[doc = "<Hw timer group 0"]
pub const timer_group_t_TIMER_GROUP_0: timer_group_t = 0;
#[doc = "<Hw timer group 1"]
pub const timer_group_t_TIMER_GROUP_1: timer_group_t = 1;
pub const timer_group_t_TIMER_GROUP_MAX: timer_group_t = 2;
#[doc = " @brief Selects a Timer-Group out of 2 available groups"]
pub type timer_group_t = u32;
#[doc = "<Select timer0 of GROUPx"]
pub const timer_idx_t_TIMER_0: timer_idx_t = 0;
#[doc = "<Select timer1 of GROUPx"]
pub const timer_idx_t_TIMER_1: timer_idx_t = 1;
pub const timer_idx_t_TIMER_MAX: timer_idx_t = 2;
#[doc = " @brief Select a hardware timer from timer groups"]
pub type timer_idx_t = u32;
#[doc = "< Descending Count from cnt.high|cnt.low"]
pub const timer_count_dir_t_TIMER_COUNT_DOWN: timer_count_dir_t = 0;
#[doc = "< Ascending Count from Zero"]
pub const timer_count_dir_t_TIMER_COUNT_UP: timer_count_dir_t = 1;
pub const timer_count_dir_t_TIMER_COUNT_MAX: timer_count_dir_t = 2;
#[doc = " @brief Decides the direction of counter"]
pub type timer_count_dir_t = u32;
#[doc = "<Pause timer counter"]
pub const timer_start_t_TIMER_PAUSE: timer_start_t = 0;
#[doc = "<Start timer counter"]
pub const timer_start_t_TIMER_START: timer_start_t = 1;
#[doc = " @brief Decides whether timer is on or paused"]
pub type timer_start_t = u32;
#[doc = "< Disable timer alarm"]
pub const timer_alarm_t_TIMER_ALARM_DIS: timer_alarm_t = 0;
#[doc = "< Enable timer alarm"]
pub const timer_alarm_t_TIMER_ALARM_EN: timer_alarm_t = 1;
pub const timer_alarm_t_TIMER_ALARM_MAX: timer_alarm_t = 2;
#[doc = " @brief Decides whether to enable alarm mode"]
pub type timer_alarm_t = u32;
#[doc = "< Interrupt mode: level mode"]
pub const timer_intr_mode_t_TIMER_INTR_LEVEL: timer_intr_mode_t = 0;
pub const timer_intr_mode_t_TIMER_INTR_MAX: timer_intr_mode_t = 1;
#[doc = " @brief Select interrupt type if running in alarm mode."]
pub type timer_intr_mode_t = u32;
#[doc = "< Disable auto-reload: hardware will not load counter value after an alarm event"]
pub const timer_autoreload_t_TIMER_AUTORELOAD_DIS: timer_autoreload_t = 0;
#[doc = "< Enable auto-reload: hardware will load counter value after an alarm event"]
pub const timer_autoreload_t_TIMER_AUTORELOAD_EN: timer_autoreload_t = 1;
pub const timer_autoreload_t_TIMER_AUTORELOAD_MAX: timer_autoreload_t = 2;
#[doc = " @brief Select if Alarm needs to be loaded by software or automatically reload by hardware."]
pub type timer_autoreload_t = u32;
#[doc = " @brief Data structure with timer's configuration settings"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct timer_config_t {
#[doc = "< Timer alarm enable"]
pub alarm_en: bool,
#[doc = "< Counter enable"]
pub counter_en: bool,
#[doc = "< Interrupt mode"]
pub intr_type: timer_intr_mode_t,
#[doc = "< Counter direction"]
pub counter_dir: timer_count_dir_t,
#[doc = "< Timer auto-reload"]
pub auto_reload: bool,
#[doc = "< Counter clock divider. The divider's range is from from 2 to 65536."]
pub divider: u32,
}
#[doc = " @brief Interrupt handle, used in order to free the isr after use."]
#[doc = " Aliases to an int handle for now."]
pub type timer_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief Read the counter value of hardware timer."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param timer_val Pointer to accept timer counter value."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_get_counter_value(
group_num: timer_group_t,
timer_num: timer_idx_t,
timer_val: *mut u64,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Read the counter value of hardware timer, in unit of a given scale."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param time Pointer, type of double*, to accept timer counter value, in seconds."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_get_counter_time_sec(
group_num: timer_group_t,
timer_num: timer_idx_t,
time: *mut f64,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set counter value to hardware timer."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param load_val Counter value to write to the hardware timer."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_counter_value(
group_num: timer_group_t,
timer_num: timer_idx_t,
load_val: u64,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Start the counter of hardware timer."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_start(group_num: timer_group_t, timer_num: timer_idx_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Pause the counter of hardware timer."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_pause(group_num: timer_group_t, timer_num: timer_idx_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set counting mode for hardware timer."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param counter_dir Counting direction of timer, count-up or count-down"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_counter_mode(
group_num: timer_group_t,
timer_num: timer_idx_t,
counter_dir: timer_count_dir_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable or disable counter reload function when alarm event occurs."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param reload Counter reload mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_auto_reload(
group_num: timer_group_t,
timer_num: timer_idx_t,
reload: timer_autoreload_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set hardware timer source clock divider. Timer groups clock are divider from APB clock."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param divider Timer clock divider value. The divider's range is from from 2 to 65536."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_divider(
group_num: timer_group_t,
timer_num: timer_idx_t,
divider: u32,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set timer alarm value."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param alarm_value A 64-bit value to set the alarm value."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_alarm_value(
group_num: timer_group_t,
timer_num: timer_idx_t,
alarm_value: u64,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get timer alarm value."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param alarm_value Pointer of A 64-bit value to accept the alarm value."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_get_alarm_value(
group_num: timer_group_t,
timer_num: timer_idx_t,
alarm_value: *mut u64,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable or disable generation of timer alarm events."]
#[doc = ""]
#[doc = " @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param alarm_en To enable or disable timer alarm function."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_set_alarm(
group_num: timer_group_t,
timer_num: timer_idx_t,
alarm_en: timer_alarm_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register Timer interrupt handler, the handler is an ISR."]
#[doc = " The handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " @param group_num Timer group number"]
#[doc = " @param timer_num Timer index of timer group"]
#[doc = " @param fn Interrupt handler function."]
#[doc = " @param arg Parameter for handler function"]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will"]
#[doc = " be returned here."]
#[doc = ""]
#[doc = " @note If the intr_alloc_flags value ESP_INTR_FLAG_IRAM is set,"]
#[doc = " the handler function must be declared with IRAM_ATTR attribute"]
#[doc = " and can only call functions in IRAM or ROM. It cannot call other timer APIs."]
#[doc = " Use direct register access to configure timers from inside the ISR in this case."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_isr_register(
group_num: timer_group_t,
timer_num: timer_idx_t,
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut timer_isr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Initializes and configure the timer."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param config Pointer to timer initialization parameters."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_init(
group_num: timer_group_t,
timer_num: timer_idx_t,
config: *const timer_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get timer configure value."]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]"]
#[doc = " @param config Pointer of struct to accept timer parameters."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_get_config(
group_num: timer_group_t,
timer_num: timer_idx_t,
config: *mut timer_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable timer group interrupt, by enable mask"]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param en_mask Timer interrupt enable mask."]
#[doc = " Use TIMG_T0_INT_ENA_M to enable t0 interrupt"]
#[doc = " Use TIMG_T1_INT_ENA_M to enable t1 interrupt"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_group_intr_enable(group_num: timer_group_t, en_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable timer group interrupt, by disable mask"]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param disable_mask Timer interrupt disable mask."]
#[doc = " Use TIMG_T0_INT_ENA_M to disable t0 interrupt"]
#[doc = " Use TIMG_T1_INT_ENA_M to disable t1 interrupt"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_group_intr_disable(group_num: timer_group_t, disable_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable timer interrupt"]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_enable_intr(group_num: timer_group_t, timer_num: timer_idx_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable timer interrupt"]
#[doc = ""]
#[doc = " @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1"]
#[doc = " @param timer_num Timer index."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn timer_disable_intr(group_num: timer_group_t, timer_num: timer_idx_t) -> esp_err_t;
}
#[repr(C)]
#[derive(Copy, Clone)]
pub struct _bindgen_ty_5 {
pub fifo: _bindgen_ty_5__bindgen_ty_1,
pub int_raw: _bindgen_ty_5__bindgen_ty_2,
pub int_st: _bindgen_ty_5__bindgen_ty_3,
pub int_ena: _bindgen_ty_5__bindgen_ty_4,
pub int_clr: _bindgen_ty_5__bindgen_ty_5,
pub clk_div: _bindgen_ty_5__bindgen_ty_6,
pub auto_baud: _bindgen_ty_5__bindgen_ty_7,
pub status: _bindgen_ty_5__bindgen_ty_8,
pub conf0: _bindgen_ty_5__bindgen_ty_9,
pub conf1: _bindgen_ty_5__bindgen_ty_10,
pub lowpulse: _bindgen_ty_5__bindgen_ty_11,
pub highpulse: _bindgen_ty_5__bindgen_ty_12,
pub rxd_cnt: _bindgen_ty_5__bindgen_ty_13,
pub flow_conf: _bindgen_ty_5__bindgen_ty_14,
pub sleep_conf: _bindgen_ty_5__bindgen_ty_15,
pub swfc_conf: _bindgen_ty_5__bindgen_ty_16,
pub idle_conf: _bindgen_ty_5__bindgen_ty_17,
pub rs485_conf: _bindgen_ty_5__bindgen_ty_18,
pub at_cmd_precnt: _bindgen_ty_5__bindgen_ty_19,
pub at_cmd_postcnt: _bindgen_ty_5__bindgen_ty_20,
pub at_cmd_gaptout: _bindgen_ty_5__bindgen_ty_21,
pub at_cmd_char: _bindgen_ty_5__bindgen_ty_22,
pub mem_conf: _bindgen_ty_5__bindgen_ty_23,
pub mem_tx_status: _bindgen_ty_5__bindgen_ty_24,
pub mem_rx_status: _bindgen_ty_5__bindgen_ty_25,
pub mem_cnt_status: _bindgen_ty_5__bindgen_ty_26,
pub pospulse: _bindgen_ty_5__bindgen_ty_27,
pub negpulse: _bindgen_ty_5__bindgen_ty_28,
pub reserved_70: u32,
pub reserved_74: u32,
pub date: u32,
pub id: u32,
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_1 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_1__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_1__bindgen_ty_1 {
pub rw_byte: u8,
pub reserved: [u8; 3usize],
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_2 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_2__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_2__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_2__bindgen_ty_1 {
#[inline]
pub fn rxfifo_full(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_full(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_txfifo_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_ovf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_ovf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsr_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsr_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cts_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cts_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn brk_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_brk_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_tout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_tout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn glitch_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_glitch_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_idle_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_idle_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_clash(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_clash(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn at_cmd_char_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_at_cmd_char_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_full: u32,
txfifo_empty: u32,
parity_err: u32,
frm_err: u32,
rxfifo_ovf: u32,
dsr_chg: u32,
cts_chg: u32,
brk_det: u32,
rxfifo_tout: u32,
sw_xon: u32,
sw_xoff: u32,
glitch_det: u32,
tx_brk_done: u32,
tx_brk_idle_done: u32,
tx_done: u32,
rs485_parity_err: u32,
rs485_frm_err: u32,
rs485_clash: u32,
at_cmd_char_det: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rxfifo_full: u32 = unsafe { ::core::mem::transmute(rxfifo_full) };
rxfifo_full as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let txfifo_empty: u32 = unsafe { ::core::mem::transmute(txfifo_empty) };
txfifo_empty as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let parity_err: u32 = unsafe { ::core::mem::transmute(parity_err) };
parity_err as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let frm_err: u32 = unsafe { ::core::mem::transmute(frm_err) };
frm_err as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rxfifo_ovf: u32 = unsafe { ::core::mem::transmute(rxfifo_ovf) };
rxfifo_ovf as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let dsr_chg: u32 = unsafe { ::core::mem::transmute(dsr_chg) };
dsr_chg as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cts_chg: u32 = unsafe { ::core::mem::transmute(cts_chg) };
cts_chg as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let brk_det: u32 = unsafe { ::core::mem::transmute(brk_det) };
brk_det as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let rxfifo_tout: u32 = unsafe { ::core::mem::transmute(rxfifo_tout) };
rxfifo_tout as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let sw_xon: u32 = unsafe { ::core::mem::transmute(sw_xon) };
sw_xon as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let sw_xoff: u32 = unsafe { ::core::mem::transmute(sw_xoff) };
sw_xoff as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let glitch_det: u32 = unsafe { ::core::mem::transmute(glitch_det) };
glitch_det as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let tx_brk_done: u32 = unsafe { ::core::mem::transmute(tx_brk_done) };
tx_brk_done as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let tx_brk_idle_done: u32 = unsafe { ::core::mem::transmute(tx_brk_idle_done) };
tx_brk_idle_done as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let tx_done: u32 = unsafe { ::core::mem::transmute(tx_done) };
tx_done as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rs485_parity_err: u32 = unsafe { ::core::mem::transmute(rs485_parity_err) };
rs485_parity_err as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let rs485_frm_err: u32 = unsafe { ::core::mem::transmute(rs485_frm_err) };
rs485_frm_err as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rs485_clash: u32 = unsafe { ::core::mem::transmute(rs485_clash) };
rs485_clash as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let at_cmd_char_det: u32 = unsafe { ::core::mem::transmute(at_cmd_char_det) };
at_cmd_char_det as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_3 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_3__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_3__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_3__bindgen_ty_1 {
#[inline]
pub fn rxfifo_full(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_full(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_txfifo_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_ovf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_ovf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsr_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsr_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cts_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cts_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn brk_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_brk_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_tout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_tout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn glitch_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_glitch_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_idle_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_idle_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_clash(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_clash(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn at_cmd_char_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_at_cmd_char_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_full: u32,
txfifo_empty: u32,
parity_err: u32,
frm_err: u32,
rxfifo_ovf: u32,
dsr_chg: u32,
cts_chg: u32,
brk_det: u32,
rxfifo_tout: u32,
sw_xon: u32,
sw_xoff: u32,
glitch_det: u32,
tx_brk_done: u32,
tx_brk_idle_done: u32,
tx_done: u32,
rs485_parity_err: u32,
rs485_frm_err: u32,
rs485_clash: u32,
at_cmd_char_det: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rxfifo_full: u32 = unsafe { ::core::mem::transmute(rxfifo_full) };
rxfifo_full as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let txfifo_empty: u32 = unsafe { ::core::mem::transmute(txfifo_empty) };
txfifo_empty as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let parity_err: u32 = unsafe { ::core::mem::transmute(parity_err) };
parity_err as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let frm_err: u32 = unsafe { ::core::mem::transmute(frm_err) };
frm_err as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rxfifo_ovf: u32 = unsafe { ::core::mem::transmute(rxfifo_ovf) };
rxfifo_ovf as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let dsr_chg: u32 = unsafe { ::core::mem::transmute(dsr_chg) };
dsr_chg as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cts_chg: u32 = unsafe { ::core::mem::transmute(cts_chg) };
cts_chg as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let brk_det: u32 = unsafe { ::core::mem::transmute(brk_det) };
brk_det as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let rxfifo_tout: u32 = unsafe { ::core::mem::transmute(rxfifo_tout) };
rxfifo_tout as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let sw_xon: u32 = unsafe { ::core::mem::transmute(sw_xon) };
sw_xon as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let sw_xoff: u32 = unsafe { ::core::mem::transmute(sw_xoff) };
sw_xoff as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let glitch_det: u32 = unsafe { ::core::mem::transmute(glitch_det) };
glitch_det as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let tx_brk_done: u32 = unsafe { ::core::mem::transmute(tx_brk_done) };
tx_brk_done as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let tx_brk_idle_done: u32 = unsafe { ::core::mem::transmute(tx_brk_idle_done) };
tx_brk_idle_done as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let tx_done: u32 = unsafe { ::core::mem::transmute(tx_done) };
tx_done as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rs485_parity_err: u32 = unsafe { ::core::mem::transmute(rs485_parity_err) };
rs485_parity_err as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let rs485_frm_err: u32 = unsafe { ::core::mem::transmute(rs485_frm_err) };
rs485_frm_err as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rs485_clash: u32 = unsafe { ::core::mem::transmute(rs485_clash) };
rs485_clash as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let at_cmd_char_det: u32 = unsafe { ::core::mem::transmute(at_cmd_char_det) };
at_cmd_char_det as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_4 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_4__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_4__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_4__bindgen_ty_1 {
#[inline]
pub fn rxfifo_full(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_full(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_txfifo_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_ovf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_ovf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsr_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsr_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cts_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cts_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn brk_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_brk_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_tout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_tout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn glitch_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_glitch_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_idle_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_idle_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_clash(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_clash(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn at_cmd_char_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_at_cmd_char_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_full: u32,
txfifo_empty: u32,
parity_err: u32,
frm_err: u32,
rxfifo_ovf: u32,
dsr_chg: u32,
cts_chg: u32,
brk_det: u32,
rxfifo_tout: u32,
sw_xon: u32,
sw_xoff: u32,
glitch_det: u32,
tx_brk_done: u32,
tx_brk_idle_done: u32,
tx_done: u32,
rs485_parity_err: u32,
rs485_frm_err: u32,
rs485_clash: u32,
at_cmd_char_det: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rxfifo_full: u32 = unsafe { ::core::mem::transmute(rxfifo_full) };
rxfifo_full as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let txfifo_empty: u32 = unsafe { ::core::mem::transmute(txfifo_empty) };
txfifo_empty as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let parity_err: u32 = unsafe { ::core::mem::transmute(parity_err) };
parity_err as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let frm_err: u32 = unsafe { ::core::mem::transmute(frm_err) };
frm_err as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rxfifo_ovf: u32 = unsafe { ::core::mem::transmute(rxfifo_ovf) };
rxfifo_ovf as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let dsr_chg: u32 = unsafe { ::core::mem::transmute(dsr_chg) };
dsr_chg as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cts_chg: u32 = unsafe { ::core::mem::transmute(cts_chg) };
cts_chg as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let brk_det: u32 = unsafe { ::core::mem::transmute(brk_det) };
brk_det as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let rxfifo_tout: u32 = unsafe { ::core::mem::transmute(rxfifo_tout) };
rxfifo_tout as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let sw_xon: u32 = unsafe { ::core::mem::transmute(sw_xon) };
sw_xon as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let sw_xoff: u32 = unsafe { ::core::mem::transmute(sw_xoff) };
sw_xoff as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let glitch_det: u32 = unsafe { ::core::mem::transmute(glitch_det) };
glitch_det as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let tx_brk_done: u32 = unsafe { ::core::mem::transmute(tx_brk_done) };
tx_brk_done as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let tx_brk_idle_done: u32 = unsafe { ::core::mem::transmute(tx_brk_idle_done) };
tx_brk_idle_done as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let tx_done: u32 = unsafe { ::core::mem::transmute(tx_done) };
tx_done as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rs485_parity_err: u32 = unsafe { ::core::mem::transmute(rs485_parity_err) };
rs485_parity_err as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let rs485_frm_err: u32 = unsafe { ::core::mem::transmute(rs485_frm_err) };
rs485_frm_err as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rs485_clash: u32 = unsafe { ::core::mem::transmute(rs485_clash) };
rs485_clash as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let at_cmd_char_det: u32 = unsafe { ::core::mem::transmute(at_cmd_char_det) };
at_cmd_char_det as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_5 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_5__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_5__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_5__bindgen_ty_1 {
#[inline]
pub fn rxfifo_full(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_full(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_empty(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_txfifo_empty(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_ovf(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_ovf(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsr_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsr_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn cts_chg(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_cts_chg(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn brk_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_brk_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_tout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_tout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn glitch_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_glitch_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_brk_idle_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_brk_idle_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_done(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_done(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_parity_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_parity_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_frm_err(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_frm_err(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rs485_clash(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rs485_clash(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn at_cmd_char_det(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_at_cmd_char_det(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved19(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 13u8) as u32) }
}
#[inline]
pub fn set_reserved19(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 13u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_full: u32,
txfifo_empty: u32,
parity_err: u32,
frm_err: u32,
rxfifo_ovf: u32,
dsr_chg: u32,
cts_chg: u32,
brk_det: u32,
rxfifo_tout: u32,
sw_xon: u32,
sw_xoff: u32,
glitch_det: u32,
tx_brk_done: u32,
tx_brk_idle_done: u32,
tx_done: u32,
rs485_parity_err: u32,
rs485_frm_err: u32,
rs485_clash: u32,
at_cmd_char_det: u32,
reserved19: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let rxfifo_full: u32 = unsafe { ::core::mem::transmute(rxfifo_full) };
rxfifo_full as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let txfifo_empty: u32 = unsafe { ::core::mem::transmute(txfifo_empty) };
txfifo_empty as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let parity_err: u32 = unsafe { ::core::mem::transmute(parity_err) };
parity_err as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let frm_err: u32 = unsafe { ::core::mem::transmute(frm_err) };
frm_err as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rxfifo_ovf: u32 = unsafe { ::core::mem::transmute(rxfifo_ovf) };
rxfifo_ovf as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let dsr_chg: u32 = unsafe { ::core::mem::transmute(dsr_chg) };
dsr_chg as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let cts_chg: u32 = unsafe { ::core::mem::transmute(cts_chg) };
cts_chg as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let brk_det: u32 = unsafe { ::core::mem::transmute(brk_det) };
brk_det as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let rxfifo_tout: u32 = unsafe { ::core::mem::transmute(rxfifo_tout) };
rxfifo_tout as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let sw_xon: u32 = unsafe { ::core::mem::transmute(sw_xon) };
sw_xon as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let sw_xoff: u32 = unsafe { ::core::mem::transmute(sw_xoff) };
sw_xoff as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let glitch_det: u32 = unsafe { ::core::mem::transmute(glitch_det) };
glitch_det as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let tx_brk_done: u32 = unsafe { ::core::mem::transmute(tx_brk_done) };
tx_brk_done as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let tx_brk_idle_done: u32 = unsafe { ::core::mem::transmute(tx_brk_idle_done) };
tx_brk_idle_done as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let tx_done: u32 = unsafe { ::core::mem::transmute(tx_done) };
tx_done as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rs485_parity_err: u32 = unsafe { ::core::mem::transmute(rs485_parity_err) };
rs485_parity_err as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let rs485_frm_err: u32 = unsafe { ::core::mem::transmute(rs485_frm_err) };
rs485_frm_err as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rs485_clash: u32 = unsafe { ::core::mem::transmute(rs485_clash) };
rs485_clash as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let at_cmd_char_det: u32 = unsafe { ::core::mem::transmute(at_cmd_char_det) };
at_cmd_char_det as u64
});
__bindgen_bitfield_unit.set(19usize, 13u8, {
let reserved19: u32 = unsafe { ::core::mem::transmute(reserved19) };
reserved19 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_6 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_6__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_6__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_6__bindgen_ty_1 {
#[inline]
pub fn div_int(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_div_int(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn div_frag(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 4u8) as u32) }
}
#[inline]
pub fn set_div_frag(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
div_int: u32,
div_frag: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let div_int: u32 = unsafe { ::core::mem::transmute(div_int) };
div_int as u64
});
__bindgen_bitfield_unit.set(20usize, 4u8, {
let div_frag: u32 = unsafe { ::core::mem::transmute(div_frag) };
div_frag as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_7 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_7__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_7__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_7__bindgen_ty_1 {
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 7u8) as u32) }
}
#[inline]
pub fn set_reserved1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 7u8, val as u64)
}
}
#[inline]
pub fn glitch_filt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_glitch_filt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
en: u32,
reserved1: u32,
glitch_filt: u32,
reserved16: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit.set(1usize, 7u8, {
let reserved1: u32 = unsafe { ::core::mem::transmute(reserved1) };
reserved1 as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let glitch_filt: u32 = unsafe { ::core::mem::transmute(glitch_filt) };
glitch_filt as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_8 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_8__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_8__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_5__bindgen_ty_8__bindgen_ty_1 {
#[inline]
pub fn rxfifo_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_rxfifo_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn st_urx_out(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 4u8) as u32) }
}
#[inline]
pub fn set_st_urx_out(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved12(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved12(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsrn(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsrn(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn ctsn(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_ctsn(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_txfifo_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn st_utx_out(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 4u8) as u32) }
}
#[inline]
pub fn set_st_utx_out(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 1u8, val as u64)
}
}
#[inline]
pub fn dtrn(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 1u8) as u32) }
}
#[inline]
pub fn set_dtrn(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(29usize, 1u8, val as u64)
}
}
#[inline]
pub fn rtsn(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(30usize, 1u8) as u32) }
}
#[inline]
pub fn set_rtsn(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(30usize, 1u8, val as u64)
}
}
#[inline]
pub fn txd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_txd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_cnt: u32,
st_urx_out: u32,
reserved12: u32,
dsrn: u32,
ctsn: u32,
rxd: u32,
txfifo_cnt: u32,
st_utx_out: u32,
reserved28: u32,
dtrn: u32,
rtsn: u32,
txd: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let rxfifo_cnt: u32 = unsafe { ::core::mem::transmute(rxfifo_cnt) };
rxfifo_cnt as u64
});
__bindgen_bitfield_unit.set(8usize, 4u8, {
let st_urx_out: u32 = unsafe { ::core::mem::transmute(st_urx_out) };
st_urx_out as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let reserved12: u32 = unsafe { ::core::mem::transmute(reserved12) };
reserved12 as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let dsrn: u32 = unsafe { ::core::mem::transmute(dsrn) };
dsrn as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let ctsn: u32 = unsafe { ::core::mem::transmute(ctsn) };
ctsn as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let rxd: u32 = unsafe { ::core::mem::transmute(rxd) };
rxd as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let txfifo_cnt: u32 = unsafe { ::core::mem::transmute(txfifo_cnt) };
txfifo_cnt as u64
});
__bindgen_bitfield_unit.set(24usize, 4u8, {
let st_utx_out: u32 = unsafe { ::core::mem::transmute(st_utx_out) };
st_utx_out as u64
});
__bindgen_bitfield_unit.set(28usize, 1u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit.set(29usize, 1u8, {
let dtrn: u32 = unsafe { ::core::mem::transmute(dtrn) };
dtrn as u64
});
__bindgen_bitfield_unit.set(30usize, 1u8, {
let rtsn: u32 = unsafe { ::core::mem::transmute(rtsn) };
rtsn as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let txd: u32 = unsafe { ::core::mem::transmute(txd) };
txd as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_9 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_9__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_9__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_5__bindgen_ty_9__bindgen_ty_1 {
#[inline]
pub fn parity(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn parity_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_parity_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn bit_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 2u8) as u32) }
}
#[inline]
pub fn set_bit_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 2u8, val as u64)
}
}
#[inline]
pub fn stop_bit_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 2u8) as u32) }
}
#[inline]
pub fn set_stop_bit_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 2u8, val as u64)
}
}
#[inline]
pub fn sw_rts(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_rts(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 1u8, val as u64)
}
}
#[inline]
pub fn sw_dtr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_dtr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn txd_brk(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 1u8) as u32) }
}
#[inline]
pub fn set_txd_brk(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_dplx(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(9usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_dplx(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(9usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_tx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_tx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_wctl(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_wctl(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_tx_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_tx_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(12usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_rx_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_rx_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 1u8, val as u64)
}
}
#[inline]
pub fn loopback(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 1u8) as u32) }
}
#[inline]
pub fn set_loopback(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(14usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_flow_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_flow_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn irda_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 1u8) as u32) }
}
#[inline]
pub fn set_irda_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxfifo_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(17usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxfifo_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(17usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_rst(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 1u8) as u32) }
}
#[inline]
pub fn set_txfifo_rst(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 1u8, val as u64)
}
}
#[inline]
pub fn rxd_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(19usize, 1u8) as u32) }
}
#[inline]
pub fn set_rxd_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(19usize, 1u8, val as u64)
}
}
#[inline]
pub fn cts_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 1u8) as u32) }
}
#[inline]
pub fn set_cts_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 1u8, val as u64)
}
}
#[inline]
pub fn dsr_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 1u8) as u32) }
}
#[inline]
pub fn set_dsr_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 1u8, val as u64)
}
}
#[inline]
pub fn txd_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(22usize, 1u8) as u32) }
}
#[inline]
pub fn set_txd_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(22usize, 1u8, val as u64)
}
}
#[inline]
pub fn rts_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_rts_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn dtr_inv(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 1u8) as u32) }
}
#[inline]
pub fn set_dtr_inv(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 1u8, val as u64)
}
}
#[inline]
pub fn clk_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 1u8) as u32) }
}
#[inline]
pub fn set_clk_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 1u8, val as u64)
}
}
#[inline]
pub fn err_wr_mask(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(26usize, 1u8) as u32) }
}
#[inline]
pub fn set_err_wr_mask(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(26usize, 1u8, val as u64)
}
}
#[inline]
pub fn tick_ref_always_on(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(27usize, 1u8) as u32) }
}
#[inline]
pub fn set_tick_ref_always_on(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(27usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
parity: u32,
parity_en: u32,
bit_num: u32,
stop_bit_num: u32,
sw_rts: u32,
sw_dtr: u32,
txd_brk: u32,
irda_dplx: u32,
irda_tx_en: u32,
irda_wctl: u32,
irda_tx_inv: u32,
irda_rx_inv: u32,
loopback: u32,
tx_flow_en: u32,
irda_en: u32,
rxfifo_rst: u32,
txfifo_rst: u32,
rxd_inv: u32,
cts_inv: u32,
dsr_inv: u32,
txd_inv: u32,
rts_inv: u32,
dtr_inv: u32,
clk_en: u32,
err_wr_mask: u32,
tick_ref_always_on: u32,
reserved28: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let parity: u32 = unsafe { ::core::mem::transmute(parity) };
parity as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let parity_en: u32 = unsafe { ::core::mem::transmute(parity_en) };
parity_en as u64
});
__bindgen_bitfield_unit.set(2usize, 2u8, {
let bit_num: u32 = unsafe { ::core::mem::transmute(bit_num) };
bit_num as u64
});
__bindgen_bitfield_unit.set(4usize, 2u8, {
let stop_bit_num: u32 = unsafe { ::core::mem::transmute(stop_bit_num) };
stop_bit_num as u64
});
__bindgen_bitfield_unit.set(6usize, 1u8, {
let sw_rts: u32 = unsafe { ::core::mem::transmute(sw_rts) };
sw_rts as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let sw_dtr: u32 = unsafe { ::core::mem::transmute(sw_dtr) };
sw_dtr as u64
});
__bindgen_bitfield_unit.set(8usize, 1u8, {
let txd_brk: u32 = unsafe { ::core::mem::transmute(txd_brk) };
txd_brk as u64
});
__bindgen_bitfield_unit.set(9usize, 1u8, {
let irda_dplx: u32 = unsafe { ::core::mem::transmute(irda_dplx) };
irda_dplx as u64
});
__bindgen_bitfield_unit.set(10usize, 1u8, {
let irda_tx_en: u32 = unsafe { ::core::mem::transmute(irda_tx_en) };
irda_tx_en as u64
});
__bindgen_bitfield_unit.set(11usize, 1u8, {
let irda_wctl: u32 = unsafe { ::core::mem::transmute(irda_wctl) };
irda_wctl as u64
});
__bindgen_bitfield_unit.set(12usize, 1u8, {
let irda_tx_inv: u32 = unsafe { ::core::mem::transmute(irda_tx_inv) };
irda_tx_inv as u64
});
__bindgen_bitfield_unit.set(13usize, 1u8, {
let irda_rx_inv: u32 = unsafe { ::core::mem::transmute(irda_rx_inv) };
irda_rx_inv as u64
});
__bindgen_bitfield_unit.set(14usize, 1u8, {
let loopback: u32 = unsafe { ::core::mem::transmute(loopback) };
loopback as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let tx_flow_en: u32 = unsafe { ::core::mem::transmute(tx_flow_en) };
tx_flow_en as u64
});
__bindgen_bitfield_unit.set(16usize, 1u8, {
let irda_en: u32 = unsafe { ::core::mem::transmute(irda_en) };
irda_en as u64
});
__bindgen_bitfield_unit.set(17usize, 1u8, {
let rxfifo_rst: u32 = unsafe { ::core::mem::transmute(rxfifo_rst) };
rxfifo_rst as u64
});
__bindgen_bitfield_unit.set(18usize, 1u8, {
let txfifo_rst: u32 = unsafe { ::core::mem::transmute(txfifo_rst) };
txfifo_rst as u64
});
__bindgen_bitfield_unit.set(19usize, 1u8, {
let rxd_inv: u32 = unsafe { ::core::mem::transmute(rxd_inv) };
rxd_inv as u64
});
__bindgen_bitfield_unit.set(20usize, 1u8, {
let cts_inv: u32 = unsafe { ::core::mem::transmute(cts_inv) };
cts_inv as u64
});
__bindgen_bitfield_unit.set(21usize, 1u8, {
let dsr_inv: u32 = unsafe { ::core::mem::transmute(dsr_inv) };
dsr_inv as u64
});
__bindgen_bitfield_unit.set(22usize, 1u8, {
let txd_inv: u32 = unsafe { ::core::mem::transmute(txd_inv) };
txd_inv as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let rts_inv: u32 = unsafe { ::core::mem::transmute(rts_inv) };
rts_inv as u64
});
__bindgen_bitfield_unit.set(24usize, 1u8, {
let dtr_inv: u32 = unsafe { ::core::mem::transmute(dtr_inv) };
dtr_inv as u64
});
__bindgen_bitfield_unit.set(25usize, 1u8, {
let clk_en: u32 = unsafe { ::core::mem::transmute(clk_en) };
clk_en as u64
});
__bindgen_bitfield_unit.set(26usize, 1u8, {
let err_wr_mask: u32 = unsafe { ::core::mem::transmute(err_wr_mask) };
err_wr_mask as u64
});
__bindgen_bitfield_unit.set(27usize, 1u8, {
let tick_ref_always_on: u32 = unsafe { ::core::mem::transmute(tick_ref_always_on) };
tick_ref_always_on as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_10 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_10__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_10__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_5__bindgen_ty_10__bindgen_ty_1 {
#[inline]
pub fn rxfifo_full_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 7u8) as u32) }
}
#[inline]
pub fn set_rxfifo_full_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 7u8, val as u64)
}
}
#[inline]
pub fn reserved7(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved7(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 1u8, val as u64)
}
}
#[inline]
pub fn txfifo_empty_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 7u8) as u32) }
}
#[inline]
pub fn set_txfifo_empty_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 7u8, val as u64)
}
}
#[inline]
pub fn reserved15(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved15(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_flow_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 7u8) as u32) }
}
#[inline]
pub fn set_rx_flow_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 7u8, val as u64)
}
}
#[inline]
pub fn rx_flow_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_flow_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_tout_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 7u8) as u32) }
}
#[inline]
pub fn set_rx_tout_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 7u8, val as u64)
}
}
#[inline]
pub fn rx_tout_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_tout_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rxfifo_full_thrhd: u32,
reserved7: u32,
txfifo_empty_thrhd: u32,
reserved15: u32,
rx_flow_thrhd: u32,
rx_flow_en: u32,
rx_tout_thrhd: u32,
rx_tout_en: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 7u8, {
let rxfifo_full_thrhd: u32 = unsafe { ::core::mem::transmute(rxfifo_full_thrhd) };
rxfifo_full_thrhd as u64
});
__bindgen_bitfield_unit.set(7usize, 1u8, {
let reserved7: u32 = unsafe { ::core::mem::transmute(reserved7) };
reserved7 as u64
});
__bindgen_bitfield_unit.set(8usize, 7u8, {
let txfifo_empty_thrhd: u32 = unsafe { ::core::mem::transmute(txfifo_empty_thrhd) };
txfifo_empty_thrhd as u64
});
__bindgen_bitfield_unit.set(15usize, 1u8, {
let reserved15: u32 = unsafe { ::core::mem::transmute(reserved15) };
reserved15 as u64
});
__bindgen_bitfield_unit.set(16usize, 7u8, {
let rx_flow_thrhd: u32 = unsafe { ::core::mem::transmute(rx_flow_thrhd) };
rx_flow_thrhd as u64
});
__bindgen_bitfield_unit.set(23usize, 1u8, {
let rx_flow_en: u32 = unsafe { ::core::mem::transmute(rx_flow_en) };
rx_flow_en as u64
});
__bindgen_bitfield_unit.set(24usize, 7u8, {
let rx_tout_thrhd: u32 = unsafe { ::core::mem::transmute(rx_tout_thrhd) };
rx_tout_thrhd as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let rx_tout_en: u32 = unsafe { ::core::mem::transmute(rx_tout_en) };
rx_tout_en as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_11 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_11__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_11__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_11__bindgen_ty_1 {
#[inline]
pub fn min_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_min_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 12u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
min_cnt: u32,
reserved20: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let min_cnt: u32 = unsafe { ::core::mem::transmute(min_cnt) };
min_cnt as u64
});
__bindgen_bitfield_unit.set(20usize, 12u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_12 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_12__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_12__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_12__bindgen_ty_1 {
#[inline]
pub fn min_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_min_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 12u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
min_cnt: u32,
reserved20: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let min_cnt: u32 = unsafe { ::core::mem::transmute(min_cnt) };
min_cnt as u64
});
__bindgen_bitfield_unit.set(20usize, 12u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_13 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_13__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_13__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_13__bindgen_ty_1 {
#[inline]
pub fn edge_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_edge_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn reserved10(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 22u8) as u32) }
}
#[inline]
pub fn set_reserved10(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 22u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
edge_cnt: u32,
reserved10: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let edge_cnt: u32 = unsafe { ::core::mem::transmute(edge_cnt) };
edge_cnt as u64
});
__bindgen_bitfield_unit.set(10usize, 22u8, {
let reserved10: u32 = unsafe { ::core::mem::transmute(reserved10) };
reserved10 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_14 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_14__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_14__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_14__bindgen_ty_1 {
#[inline]
pub fn sw_flow_con_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_sw_flow_con_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn xonoff_del(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_xonoff_del(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn force_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_force_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn force_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_force_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn send_xon(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_send_xon(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn send_xoff(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_send_xoff(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved6(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 26u8) as u32) }
}
#[inline]
pub fn set_reserved6(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 26u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
sw_flow_con_en: u32,
xonoff_del: u32,
force_xon: u32,
force_xoff: u32,
send_xon: u32,
send_xoff: u32,
reserved6: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let sw_flow_con_en: u32 = unsafe { ::core::mem::transmute(sw_flow_con_en) };
sw_flow_con_en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let xonoff_del: u32 = unsafe { ::core::mem::transmute(xonoff_del) };
xonoff_del as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let force_xon: u32 = unsafe { ::core::mem::transmute(force_xon) };
force_xon as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let force_xoff: u32 = unsafe { ::core::mem::transmute(force_xoff) };
force_xoff as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let send_xon: u32 = unsafe { ::core::mem::transmute(send_xon) };
send_xon as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let send_xoff: u32 = unsafe { ::core::mem::transmute(send_xoff) };
send_xoff as u64
});
__bindgen_bitfield_unit.set(6usize, 26u8, {
let reserved6: u32 = unsafe { ::core::mem::transmute(reserved6) };
reserved6 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_15 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_15__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_15__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_15__bindgen_ty_1 {
#[inline]
pub fn active_threshold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_active_threshold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn reserved10(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 22u8) as u32) }
}
#[inline]
pub fn set_reserved10(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 22u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
active_threshold: u32,
reserved10: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let active_threshold: u32 = unsafe { ::core::mem::transmute(active_threshold) };
active_threshold as u64
});
__bindgen_bitfield_unit.set(10usize, 22u8, {
let reserved10: u32 = unsafe { ::core::mem::transmute(reserved10) };
reserved10 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_16 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_16__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_16__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_5__bindgen_ty_16__bindgen_ty_1 {
#[inline]
pub fn xon_threshold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_xon_threshold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn xoff_threshold(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_xoff_threshold(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn xon_char(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
}
#[inline]
pub fn set_xon_char(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 8u8, val as u64)
}
}
#[inline]
pub fn xoff_char(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_xoff_char(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
xon_threshold: u32,
xoff_threshold: u32,
xon_char: u32,
xoff_char: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let xon_threshold: u32 = unsafe { ::core::mem::transmute(xon_threshold) };
xon_threshold as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let xoff_threshold: u32 = unsafe { ::core::mem::transmute(xoff_threshold) };
xoff_threshold as u64
});
__bindgen_bitfield_unit.set(16usize, 8u8, {
let xon_char: u32 = unsafe { ::core::mem::transmute(xon_char) };
xon_char as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let xoff_char: u32 = unsafe { ::core::mem::transmute(xoff_char) };
xoff_char as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_17 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_17__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_17__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_17__bindgen_ty_1 {
#[inline]
pub fn rx_idle_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 10u8) as u32) }
}
#[inline]
pub fn set_rx_idle_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 10u8, val as u64)
}
}
#[inline]
pub fn tx_idle_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 10u8) as u32) }
}
#[inline]
pub fn set_tx_idle_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 10u8, val as u64)
}
}
#[inline]
pub fn tx_brk_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 8u8) as u32) }
}
#[inline]
pub fn set_tx_brk_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved28(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved28(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 4u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_idle_thrhd: u32,
tx_idle_num: u32,
tx_brk_num: u32,
reserved28: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 10u8, {
let rx_idle_thrhd: u32 = unsafe { ::core::mem::transmute(rx_idle_thrhd) };
rx_idle_thrhd as u64
});
__bindgen_bitfield_unit.set(10usize, 10u8, {
let tx_idle_num: u32 = unsafe { ::core::mem::transmute(tx_idle_num) };
tx_idle_num as u64
});
__bindgen_bitfield_unit.set(20usize, 8u8, {
let tx_brk_num: u32 = unsafe { ::core::mem::transmute(tx_brk_num) };
tx_brk_num as u64
});
__bindgen_bitfield_unit.set(28usize, 4u8, {
let reserved28: u32 = unsafe { ::core::mem::transmute(reserved28) };
reserved28 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_18 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_18__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_18__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_18__bindgen_ty_1 {
#[inline]
pub fn en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn dl0_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_dl0_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn dl1_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_dl1_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_rx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
}
#[inline]
pub fn set_tx_rx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_busy_tx_en(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_busy_tx_en(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(4usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_dly_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
}
#[inline]
pub fn set_rx_dly_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(5usize, 1u8, val as u64)
}
}
#[inline]
pub fn tx_dly_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 4u8) as u32) }
}
#[inline]
pub fn set_tx_dly_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved10(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(10usize, 22u8) as u32) }
}
#[inline]
pub fn set_reserved10(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(10usize, 22u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
en: u32,
dl0_en: u32,
dl1_en: u32,
tx_rx_en: u32,
rx_busy_tx_en: u32,
rx_dly_num: u32,
tx_dly_num: u32,
reserved10: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let en: u32 = unsafe { ::core::mem::transmute(en) };
en as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let dl0_en: u32 = unsafe { ::core::mem::transmute(dl0_en) };
dl0_en as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let dl1_en: u32 = unsafe { ::core::mem::transmute(dl1_en) };
dl1_en as u64
});
__bindgen_bitfield_unit.set(3usize, 1u8, {
let tx_rx_en: u32 = unsafe { ::core::mem::transmute(tx_rx_en) };
tx_rx_en as u64
});
__bindgen_bitfield_unit.set(4usize, 1u8, {
let rx_busy_tx_en: u32 = unsafe { ::core::mem::transmute(rx_busy_tx_en) };
rx_busy_tx_en as u64
});
__bindgen_bitfield_unit.set(5usize, 1u8, {
let rx_dly_num: u32 = unsafe { ::core::mem::transmute(rx_dly_num) };
rx_dly_num as u64
});
__bindgen_bitfield_unit.set(6usize, 4u8, {
let tx_dly_num: u32 = unsafe { ::core::mem::transmute(tx_dly_num) };
tx_dly_num as u64
});
__bindgen_bitfield_unit.set(10usize, 22u8, {
let reserved10: u32 = unsafe { ::core::mem::transmute(reserved10) };
reserved10 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_19 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_19__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_19__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_19__bindgen_ty_1 {
#[inline]
pub fn pre_idle_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_pre_idle_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
pre_idle_num: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let pre_idle_num: u32 = unsafe { ::core::mem::transmute(pre_idle_num) };
pre_idle_num as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_20 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_20__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_20__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_20__bindgen_ty_1 {
#[inline]
pub fn post_idle_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_post_idle_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
post_idle_num: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let post_idle_num: u32 = unsafe { ::core::mem::transmute(post_idle_num) };
post_idle_num as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_21 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_21__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_21__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_21__bindgen_ty_1 {
#[inline]
pub fn rx_gap_tout(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_rx_gap_tout(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_gap_tout: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let rx_gap_tout: u32 = unsafe { ::core::mem::transmute(rx_gap_tout) };
rx_gap_tout as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_22 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_22__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_22__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_22__bindgen_ty_1 {
#[inline]
pub fn data(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
}
#[inline]
pub fn set_data(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 8u8, val as u64)
}
}
#[inline]
pub fn char_num(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 8u8) as u32) }
}
#[inline]
pub fn set_char_num(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(8usize, 8u8, val as u64)
}
}
#[inline]
pub fn reserved16(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
}
#[inline]
pub fn set_reserved16(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(16usize, 16u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
data: u32,
char_num: u32,
reserved16: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 8u8, {
let data: u32 = unsafe { ::core::mem::transmute(data) };
data as u64
});
__bindgen_bitfield_unit.set(8usize, 8u8, {
let char_num: u32 = unsafe { ::core::mem::transmute(char_num) };
char_num as u64
});
__bindgen_bitfield_unit.set(16usize, 16u8, {
let reserved16: u32 = unsafe { ::core::mem::transmute(reserved16) };
reserved16 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_23 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_23__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_23__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u8>,
}
impl _bindgen_ty_5__bindgen_ty_23__bindgen_ty_1 {
#[inline]
pub fn mem_pd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
}
#[inline]
pub fn set_mem_pd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved1(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved1(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(1usize, 1u8, val as u64)
}
}
#[inline]
pub fn reserved2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 1u8, val as u64)
}
}
#[inline]
pub fn rx_size(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 4u8) as u32) }
}
#[inline]
pub fn set_rx_size(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 4u8, val as u64)
}
}
#[inline]
pub fn tx_size(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 4u8) as u32) }
}
#[inline]
pub fn set_tx_size(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(7usize, 4u8, val as u64)
}
}
#[inline]
pub fn reserved11(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 4u8) as u32) }
}
#[inline]
pub fn set_reserved11(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(11usize, 4u8, val as u64)
}
}
#[inline]
pub fn rx_flow_thrhd_h3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(15usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_flow_thrhd_h3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(15usize, 3u8, val as u64)
}
}
#[inline]
pub fn rx_tout_thrhd_h3(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(18usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_tout_thrhd_h3(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(18usize, 3u8, val as u64)
}
}
#[inline]
pub fn xon_threshold_h2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 2u8) as u32) }
}
#[inline]
pub fn set_xon_threshold_h2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(21usize, 2u8, val as u64)
}
}
#[inline]
pub fn xoff_threshold_h2(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(23usize, 2u8) as u32) }
}
#[inline]
pub fn set_xoff_threshold_h2(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(23usize, 2u8, val as u64)
}
}
#[inline]
pub fn rx_mem_full_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(25usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_mem_full_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(25usize, 3u8, val as u64)
}
}
#[inline]
pub fn tx_mem_empty_thrhd(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(28usize, 3u8) as u32) }
}
#[inline]
pub fn set_tx_mem_empty_thrhd(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(28usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved31(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(31usize, 1u8) as u32) }
}
#[inline]
pub fn set_reserved31(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(31usize, 1u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
mem_pd: u32,
reserved1: u32,
reserved2: u32,
rx_size: u32,
tx_size: u32,
reserved11: u32,
rx_flow_thrhd_h3: u32,
rx_tout_thrhd_h3: u32,
xon_threshold_h2: u32,
xoff_threshold_h2: u32,
rx_mem_full_thrhd: u32,
tx_mem_empty_thrhd: u32,
reserved31: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u8> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u8> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 1u8, {
let mem_pd: u32 = unsafe { ::core::mem::transmute(mem_pd) };
mem_pd as u64
});
__bindgen_bitfield_unit.set(1usize, 1u8, {
let reserved1: u32 = unsafe { ::core::mem::transmute(reserved1) };
reserved1 as u64
});
__bindgen_bitfield_unit.set(2usize, 1u8, {
let reserved2: u32 = unsafe { ::core::mem::transmute(reserved2) };
reserved2 as u64
});
__bindgen_bitfield_unit.set(3usize, 4u8, {
let rx_size: u32 = unsafe { ::core::mem::transmute(rx_size) };
rx_size as u64
});
__bindgen_bitfield_unit.set(7usize, 4u8, {
let tx_size: u32 = unsafe { ::core::mem::transmute(tx_size) };
tx_size as u64
});
__bindgen_bitfield_unit.set(11usize, 4u8, {
let reserved11: u32 = unsafe { ::core::mem::transmute(reserved11) };
reserved11 as u64
});
__bindgen_bitfield_unit.set(15usize, 3u8, {
let rx_flow_thrhd_h3: u32 = unsafe { ::core::mem::transmute(rx_flow_thrhd_h3) };
rx_flow_thrhd_h3 as u64
});
__bindgen_bitfield_unit.set(18usize, 3u8, {
let rx_tout_thrhd_h3: u32 = unsafe { ::core::mem::transmute(rx_tout_thrhd_h3) };
rx_tout_thrhd_h3 as u64
});
__bindgen_bitfield_unit.set(21usize, 2u8, {
let xon_threshold_h2: u32 = unsafe { ::core::mem::transmute(xon_threshold_h2) };
xon_threshold_h2 as u64
});
__bindgen_bitfield_unit.set(23usize, 2u8, {
let xoff_threshold_h2: u32 = unsafe { ::core::mem::transmute(xoff_threshold_h2) };
xoff_threshold_h2 as u64
});
__bindgen_bitfield_unit.set(25usize, 3u8, {
let rx_mem_full_thrhd: u32 = unsafe { ::core::mem::transmute(rx_mem_full_thrhd) };
rx_mem_full_thrhd as u64
});
__bindgen_bitfield_unit.set(28usize, 3u8, {
let tx_mem_empty_thrhd: u32 = unsafe { ::core::mem::transmute(tx_mem_empty_thrhd) };
tx_mem_empty_thrhd as u64
});
__bindgen_bitfield_unit.set(31usize, 1u8, {
let reserved31: u32 = unsafe { ::core::mem::transmute(reserved31) };
reserved31 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_24 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_24__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_24__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_24__bindgen_ty_1 {
#[inline]
pub fn status(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_status(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
status: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let status: u32 = unsafe { ::core::mem::transmute(status) };
status as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_25 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_25__bindgen_ty_1,
pub __bindgen_anon_2: _bindgen_ty_5__bindgen_ty_25__bindgen_ty_2,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_25__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_25__bindgen_ty_1 {
#[inline]
pub fn status(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 24u8) as u32) }
}
#[inline]
pub fn set_status(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 24u8, val as u64)
}
}
#[inline]
pub fn reserved24(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved24(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
status: u32,
reserved24: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 24u8, {
let status: u32 = unsafe { ::core::mem::transmute(status) };
status as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved24: u32 = unsafe { ::core::mem::transmute(reserved24) };
reserved24 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_25__bindgen_ty_2 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u16>,
}
impl _bindgen_ty_5__bindgen_ty_25__bindgen_ty_2 {
#[inline]
pub fn reserved0(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 2u8) as u32) }
}
#[inline]
pub fn set_reserved0(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 2u8, val as u64)
}
}
#[inline]
pub fn rd_addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 11u8) as u32) }
}
#[inline]
pub fn set_rd_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(2usize, 11u8, val as u64)
}
}
#[inline]
pub fn wr_addr(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(13usize, 11u8) as u32) }
}
#[inline]
pub fn set_wr_addr(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(13usize, 11u8, val as u64)
}
}
#[inline]
pub fn reserved(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
}
#[inline]
pub fn set_reserved(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(24usize, 8u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
reserved0: u32,
rd_addr: u32,
wr_addr: u32,
reserved: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u16> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u16> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 2u8, {
let reserved0: u32 = unsafe { ::core::mem::transmute(reserved0) };
reserved0 as u64
});
__bindgen_bitfield_unit.set(2usize, 11u8, {
let rd_addr: u32 = unsafe { ::core::mem::transmute(rd_addr) };
rd_addr as u64
});
__bindgen_bitfield_unit.set(13usize, 11u8, {
let wr_addr: u32 = unsafe { ::core::mem::transmute(wr_addr) };
wr_addr as u64
});
__bindgen_bitfield_unit.set(24usize, 8u8, {
let reserved: u32 = unsafe { ::core::mem::transmute(reserved) };
reserved as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_26 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_26__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_26__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_26__bindgen_ty_1 {
#[inline]
pub fn rx_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 3u8) as u32) }
}
#[inline]
pub fn set_rx_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 3u8, val as u64)
}
}
#[inline]
pub fn tx_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 3u8) as u32) }
}
#[inline]
pub fn set_tx_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(3usize, 3u8, val as u64)
}
}
#[inline]
pub fn reserved6(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 26u8) as u32) }
}
#[inline]
pub fn set_reserved6(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(6usize, 26u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
rx_cnt: u32,
tx_cnt: u32,
reserved6: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 3u8, {
let rx_cnt: u32 = unsafe { ::core::mem::transmute(rx_cnt) };
rx_cnt as u64
});
__bindgen_bitfield_unit.set(3usize, 3u8, {
let tx_cnt: u32 = unsafe { ::core::mem::transmute(tx_cnt) };
tx_cnt as u64
});
__bindgen_bitfield_unit.set(6usize, 26u8, {
let reserved6: u32 = unsafe { ::core::mem::transmute(reserved6) };
reserved6 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_27 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_27__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_27__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_27__bindgen_ty_1 {
#[inline]
pub fn min_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_min_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 12u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
min_cnt: u32,
reserved20: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let min_cnt: u32 = unsafe { ::core::mem::transmute(min_cnt) };
min_cnt as u64
});
__bindgen_bitfield_unit.set(20usize, 12u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit
}
}
#[repr(C)]
#[derive(Copy, Clone)]
pub union _bindgen_ty_5__bindgen_ty_28 {
pub __bindgen_anon_1: _bindgen_ty_5__bindgen_ty_28__bindgen_ty_1,
pub val: u32,
_bindgen_union_align: u32,
}
#[repr(C)]
#[repr(align(4))]
#[derive(Debug, Copy, Clone)]
pub struct _bindgen_ty_5__bindgen_ty_28__bindgen_ty_1 {
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize], u32>,
}
impl _bindgen_ty_5__bindgen_ty_28__bindgen_ty_1 {
#[inline]
pub fn min_cnt(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 20u8) as u32) }
}
#[inline]
pub fn set_min_cnt(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(0usize, 20u8, val as u64)
}
}
#[inline]
pub fn reserved20(&self) -> u32 {
unsafe { ::core::mem::transmute(self._bitfield_1.get(20usize, 12u8) as u32) }
}
#[inline]
pub fn set_reserved20(&mut self, val: u32) {
unsafe {
let val: u32 = ::core::mem::transmute(val);
self._bitfield_1.set(20usize, 12u8, val as u64)
}
}
#[inline]
pub fn new_bitfield_1(
min_cnt: u32,
reserved20: u32,
) -> __BindgenBitfieldUnit<[u8; 4usize], u32> {
let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize], u32> =
Default::default();
__bindgen_bitfield_unit.set(0usize, 20u8, {
let min_cnt: u32 = unsafe { ::core::mem::transmute(min_cnt) };
min_cnt as u64
});
__bindgen_bitfield_unit.set(20usize, 12u8, {
let reserved20: u32 = unsafe { ::core::mem::transmute(reserved20) };
reserved20 as u64
});
__bindgen_bitfield_unit
}
}
pub type uart_dev_t = _bindgen_ty_5;
extern "C" {
pub static mut UART0: uart_dev_t;
}
extern "C" {
pub static mut UART1: uart_dev_t;
}
extern "C" {
pub static mut UART2: uart_dev_t;
}
#[doc = "< mode: regular UART mode"]
pub const uart_mode_t_UART_MODE_UART: uart_mode_t = 0;
#[doc = "< mode: half duplex RS485 UART mode control by RTS pin"]
pub const uart_mode_t_UART_MODE_RS485_HALF_DUPLEX: uart_mode_t = 1;
#[doc = "< mode: IRDA UART mode"]
pub const uart_mode_t_UART_MODE_IRDA: uart_mode_t = 2;
#[doc = "< mode: RS485 collision detection UART mode (used for test purposes)"]
pub const uart_mode_t_UART_MODE_RS485_COLLISION_DETECT: uart_mode_t = 3;
#[doc = "< mode: application control RS485 UART mode (used for test purposes)"]
pub const uart_mode_t_UART_MODE_RS485_APP_CTRL: uart_mode_t = 4;
#[doc = " @brief UART mode selection"]
pub type uart_mode_t = u32;
#[doc = "< word length: 5bits"]
pub const uart_word_length_t_UART_DATA_5_BITS: uart_word_length_t = 0;
#[doc = "< word length: 6bits"]
pub const uart_word_length_t_UART_DATA_6_BITS: uart_word_length_t = 1;
#[doc = "< word length: 7bits"]
pub const uart_word_length_t_UART_DATA_7_BITS: uart_word_length_t = 2;
#[doc = "< word length: 8bits"]
pub const uart_word_length_t_UART_DATA_8_BITS: uart_word_length_t = 3;
pub const uart_word_length_t_UART_DATA_BITS_MAX: uart_word_length_t = 4;
#[doc = " @brief UART word length constants"]
pub type uart_word_length_t = u32;
#[doc = "< stop bit: 1bit"]
pub const uart_stop_bits_t_UART_STOP_BITS_1: uart_stop_bits_t = 1;
#[doc = "< stop bit: 1.5bits"]
pub const uart_stop_bits_t_UART_STOP_BITS_1_5: uart_stop_bits_t = 2;
#[doc = "< stop bit: 2bits"]
pub const uart_stop_bits_t_UART_STOP_BITS_2: uart_stop_bits_t = 3;
pub const uart_stop_bits_t_UART_STOP_BITS_MAX: uart_stop_bits_t = 4;
#[doc = " @brief UART stop bits number"]
pub type uart_stop_bits_t = u32;
#[doc = "< UART base address 0x3ff40000"]
pub const uart_port_t_UART_NUM_0: uart_port_t = 0;
#[doc = "< UART base address 0x3ff50000"]
pub const uart_port_t_UART_NUM_1: uart_port_t = 1;
#[doc = "< UART base address 0x3ff6e000"]
pub const uart_port_t_UART_NUM_2: uart_port_t = 2;
pub const uart_port_t_UART_NUM_MAX: uart_port_t = 3;
#[doc = " @brief UART peripheral number"]
pub type uart_port_t = u32;
#[doc = "< Disable UART parity"]
pub const uart_parity_t_UART_PARITY_DISABLE: uart_parity_t = 0;
#[doc = "< Enable UART even parity"]
pub const uart_parity_t_UART_PARITY_EVEN: uart_parity_t = 2;
#[doc = "< Enable UART odd parity"]
pub const uart_parity_t_UART_PARITY_ODD: uart_parity_t = 3;
#[doc = " @brief UART parity constants"]
pub type uart_parity_t = u32;
#[doc = "< disable hardware flow control"]
pub const uart_hw_flowcontrol_t_UART_HW_FLOWCTRL_DISABLE: uart_hw_flowcontrol_t = 0;
#[doc = "< enable RX hardware flow control (rts)"]
pub const uart_hw_flowcontrol_t_UART_HW_FLOWCTRL_RTS: uart_hw_flowcontrol_t = 1;
#[doc = "< enable TX hardware flow control (cts)"]
pub const uart_hw_flowcontrol_t_UART_HW_FLOWCTRL_CTS: uart_hw_flowcontrol_t = 2;
#[doc = "< enable hardware flow control"]
pub const uart_hw_flowcontrol_t_UART_HW_FLOWCTRL_CTS_RTS: uart_hw_flowcontrol_t = 3;
pub const uart_hw_flowcontrol_t_UART_HW_FLOWCTRL_MAX: uart_hw_flowcontrol_t = 4;
#[doc = " @brief UART hardware flow control modes"]
pub type uart_hw_flowcontrol_t = u32;
#[doc = " @brief UART configuration parameters for uart_param_config function"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct uart_config_t {
#[doc = "< UART baud rate"]
pub baud_rate: ::std::os::raw::c_int,
#[doc = "< UART byte size"]
pub data_bits: uart_word_length_t,
#[doc = "< UART parity mode"]
pub parity: uart_parity_t,
#[doc = "< UART stop bits"]
pub stop_bits: uart_stop_bits_t,
#[doc = "< UART HW flow control mode (cts/rts)"]
pub flow_ctrl: uart_hw_flowcontrol_t,
#[doc = "< UART HW RTS threshold"]
pub rx_flow_ctrl_thresh: u8,
#[doc = "< Set to true if UART should be clocked from REF_TICK"]
pub use_ref_tick: bool,
}
#[doc = " @brief UART interrupt configuration parameters for uart_intr_config function"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct uart_intr_config_t {
#[doc = "< UART interrupt enable mask, choose from UART_XXXX_INT_ENA_M under UART_INT_ENA_REG(i), connect with bit-or operator"]
pub intr_enable_mask: u32,
#[doc = "< UART timeout interrupt threshold (unit: time of sending one byte)"]
pub rx_timeout_thresh: u8,
#[doc = "< UART TX empty interrupt threshold."]
pub txfifo_empty_intr_thresh: u8,
#[doc = "< UART RX full interrupt threshold."]
pub rxfifo_full_thresh: u8,
}
#[doc = "< UART data event"]
pub const uart_event_type_t_UART_DATA: uart_event_type_t = 0;
#[doc = "< UART break event"]
pub const uart_event_type_t_UART_BREAK: uart_event_type_t = 1;
#[doc = "< UART RX buffer full event"]
pub const uart_event_type_t_UART_BUFFER_FULL: uart_event_type_t = 2;
#[doc = "< UART FIFO overflow event"]
pub const uart_event_type_t_UART_FIFO_OVF: uart_event_type_t = 3;
#[doc = "< UART RX frame error event"]
pub const uart_event_type_t_UART_FRAME_ERR: uart_event_type_t = 4;
#[doc = "< UART RX parity event"]
pub const uart_event_type_t_UART_PARITY_ERR: uart_event_type_t = 5;
#[doc = "< UART TX data and break event"]
pub const uart_event_type_t_UART_DATA_BREAK: uart_event_type_t = 6;
#[doc = "< UART pattern detected"]
pub const uart_event_type_t_UART_PATTERN_DET: uart_event_type_t = 7;
#[doc = "< UART event max index"]
pub const uart_event_type_t_UART_EVENT_MAX: uart_event_type_t = 8;
#[doc = " @brief UART event types used in the ring buffer"]
pub type uart_event_type_t = u32;
#[doc = " @brief Event structure used in UART event queue"]
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct uart_event_t {
#[doc = "< UART event type"]
pub type_: uart_event_type_t,
#[doc = "< UART data size for UART_DATA event"]
pub size: usize,
}
pub type uart_isr_handle_t = intr_handle_t;
extern "C" {
#[doc = " @brief Set UART data bits."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param data_bit UART data bits"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_word_length(uart_num: uart_port_t, data_bit: uart_word_length_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get UART data bits."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param data_bit Pointer to accept value of UART data bits."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success, result will be put in (*data_bit)"]
pub fn uart_get_word_length(
uart_num: uart_port_t,
data_bit: *mut uart_word_length_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART stop bits."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param stop_bits UART stop bits"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Fail"]
pub fn uart_set_stop_bits(uart_num: uart_port_t, stop_bits: uart_stop_bits_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get UART stop bits."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param stop_bits Pointer to accept value of UART stop bits."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success, result will be put in (*stop_bit)"]
pub fn uart_get_stop_bits(uart_num: uart_port_t, stop_bits: *mut uart_stop_bits_t)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART parity mode."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param parity_mode the enum of uart parity configuration"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn uart_set_parity(uart_num: uart_port_t, parity_mode: uart_parity_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get UART parity mode."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param parity_mode Pointer to accept value of UART parity mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success, result will be put in (*parity_mode)"]
#[doc = ""]
pub fn uart_get_parity(uart_num: uart_port_t, parity_mode: *mut uart_parity_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART baud rate."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param baudrate UART baud rate."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn uart_set_baudrate(uart_num: uart_port_t, baudrate: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get UART baud rate."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param baudrate Pointer to accept value of UART baud rate"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success, result will be put in (*baudrate)"]
#[doc = ""]
pub fn uart_get_baudrate(uart_num: uart_port_t, baudrate: *mut u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART line inverse mode"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param inverse_mask Choose the wires that need to be inverted."]
#[doc = " Inverse_mask should be chosen from"]
#[doc = " UART_INVERSE_RXD / UART_INVERSE_TXD / UART_INVERSE_RTS / UART_INVERSE_CTS,"]
#[doc = " combined with OR operation."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_line_inverse(uart_num: uart_port_t, inverse_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set hardware flow control."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param flow_ctrl Hardware flow control mode"]
#[doc = " @param rx_thresh Threshold of Hardware RX flow control (0 ~ UART_FIFO_LEN)."]
#[doc = " Only when UART_HW_FLOWCTRL_RTS is set, will the rx_thresh value be set."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_hw_flow_ctrl(
uart_num: uart_port_t,
flow_ctrl: uart_hw_flowcontrol_t,
rx_thresh: u8,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set software flow control."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param enable switch on or off"]
#[doc = " @param rx_thresh_xon low water mark"]
#[doc = " @param rx_thresh_xoff high water mark"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_sw_flow_ctrl(
uart_num: uart_port_t,
enable: bool,
rx_thresh_xon: u8,
rx_thresh_xoff: u8,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get hardware flow control mode"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param flow_ctrl Option for different flow control mode."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success, result will be put in (*flow_ctrl)"]
pub fn uart_get_hw_flow_ctrl(
uart_num: uart_port_t,
flow_ctrl: *mut uart_hw_flowcontrol_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Clear UART interrupt status"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param clr_mask Bit mask of the interrupt status to be cleared."]
#[doc = " The bit mask should be composed from the fields of register UART_INT_CLR_REG."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_clear_intr_status(uart_num: uart_port_t, clr_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART interrupt enable"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param enable_mask Bit mask of the enable bits."]
#[doc = " The bit mask should be composed from the fields of register UART_INT_ENA_REG."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_enable_intr_mask(uart_num: uart_port_t, enable_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Clear UART interrupt enable bits"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param disable_mask Bit mask of the disable bits."]
#[doc = " The bit mask should be composed from the fields of register UART_INT_ENA_REG."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_disable_intr_mask(uart_num: uart_port_t, disable_mask: u32) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable UART RX interrupt (RX_FULL & RX_TIMEOUT INTERRUPT)"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_enable_rx_intr(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable UART RX interrupt (RX_FULL & RX_TIMEOUT INTERRUPT)"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_disable_rx_intr(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Disable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_disable_tx_intr(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Enable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param enable 1: enable; 0: disable"]
#[doc = " @param thresh Threshold of TX interrupt, 0 ~ UART_FIFO_LEN"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_enable_tx_intr(
uart_num: uart_port_t,
enable: ::std::os::raw::c_int,
thresh: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Register UART interrupt handler (ISR)."]
#[doc = ""]
#[doc = " @note UART ISR handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param fn Interrupt handler function."]
#[doc = " @param arg parameter for handler function"]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info."]
#[doc = " @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will"]
#[doc = " be returned here."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_isr_register(
uart_num: uart_port_t,
fn_: ::core::option::Option<unsafe extern "C" fn(arg1: *mut ::std::os::raw::c_void)>,
arg: *mut ::std::os::raw::c_void,
intr_alloc_flags: ::std::os::raw::c_int,
handle: *mut uart_isr_handle_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Free UART interrupt handler registered by uart_isr_register. Must be called on the same core as"]
#[doc = " uart_isr_register was called."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_isr_free(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART pin number"]
#[doc = ""]
#[doc = " @note Internal signal can be output to multiple GPIO pads."]
#[doc = " Only one GPIO pad can connect with input signal."]
#[doc = ""]
#[doc = " @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided"]
#[doc = "to keep the currently allocated pin."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param tx_io_num UART TX pin GPIO number."]
#[doc = " @param rx_io_num UART RX pin GPIO number."]
#[doc = " @param rts_io_num UART RTS pin GPIO number."]
#[doc = " @param cts_io_num UART CTS pin GPIO number."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_pin(
uart_num: uart_port_t,
tx_io_num: ::std::os::raw::c_int,
rx_io_num: ::std::os::raw::c_int,
rts_io_num: ::std::os::raw::c_int,
cts_io_num: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Manually set the UART RTS pin level."]
#[doc = " @note UART must be configured with hardware flow control disabled."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param level 1: RTS output low (active); 0: RTS output high (block)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_rts(uart_num: uart_port_t, level: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Manually set the UART DTR pin level."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param level 1: DTR output low; 0: DTR output high"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_dtr(uart_num: uart_port_t, level: ::std::os::raw::c_int) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART idle interval after tx FIFO is empty"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param idle_num idle interval after tx FIFO is empty(unit: the time it takes to send one bit"]
#[doc = " under current baudrate)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_set_tx_idle_num(uart_num: uart_port_t, idle_num: u16) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set UART configuration parameters."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param uart_config UART parameter settings"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_param_config(uart_num: uart_port_t, uart_config: *const uart_config_t)
-> esp_err_t;
}
extern "C" {
#[doc = " @brief Configure UART interrupts."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param intr_conf UART interrupt settings"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_intr_config(
uart_num: uart_port_t,
intr_conf: *const uart_intr_config_t,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Install UART driver."]
#[doc = ""]
#[doc = " UART ISR handler will be attached to the same CPU core that this function is running on."]
#[doc = ""]
#[doc = " @note Rx_buffer_size should be greater than UART_FIFO_LEN. Tx_buffer_size should be either zero or greater than UART_FIFO_LEN."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param rx_buffer_size UART RX ring buffer size."]
#[doc = " @param tx_buffer_size UART TX ring buffer size."]
#[doc = " If set to zero, driver will not use TX buffer, TX function will block task until all data have been sent out."]
#[doc = " @param queue_size UART event queue size/depth."]
#[doc = " @param uart_queue UART event queue handle (out param). On success, a new queue handle is written here to provide"]
#[doc = " access to UART events. If set to NULL, driver will not use an event queue."]
#[doc = " @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)"]
#[doc = " ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. Do not set ESP_INTR_FLAG_IRAM here"]
#[doc = " (the driver's ISR handler is not located in IRAM)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_driver_install(
uart_num: uart_port_t,
rx_buffer_size: ::std::os::raw::c_int,
tx_buffer_size: ::std::os::raw::c_int,
queue_size: ::std::os::raw::c_int,
uart_queue: *mut QueueHandle_t,
intr_alloc_flags: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Uninstall UART driver."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_driver_delete(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Wait until UART TX FIFO is empty."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param ticks_to_wait Timeout, count in RTOS ticks"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_ERR_TIMEOUT Timeout"]
pub fn uart_wait_tx_done(uart_num: uart_port_t, ticks_to_wait: TickType_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Send data to the UART port from a given buffer and length."]
#[doc = ""]
#[doc = " This function will not wait for enough space in TX FIFO. It will just fill the available TX FIFO and return when the FIFO is full."]
#[doc = " @note This function should only be used when UART TX buffer is not enabled."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param buffer data buffer address"]
#[doc = " @param len data length to send"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - (-1) Parameter error"]
#[doc = " - OTHERS (>=0) The number of bytes pushed to the TX FIFO"]
pub fn uart_tx_chars(
uart_num: uart_port_t,
buffer: *const ::std::os::raw::c_char,
len: u32,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Send data to the UART port from a given buffer and length,"]
#[doc = ""]
#[doc = " If the UART driver's parameter 'tx_buffer_size' is set to zero:"]
#[doc = " This function will not return until all the data have been sent out, or at least pushed into TX FIFO."]
#[doc = ""]
#[doc = " Otherwise, if the 'tx_buffer_size' > 0, this function will return after copying all the data to tx ring buffer,"]
#[doc = " UART ISR will then move data from the ring buffer to TX FIFO gradually."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param src data buffer address"]
#[doc = " @param size data length to send"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - (-1) Parameter error"]
#[doc = " - OTHERS (>=0) The number of bytes pushed to the TX FIFO"]
pub fn uart_write_bytes(
uart_num: uart_port_t,
src: *const ::std::os::raw::c_char,
size: usize,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Send data to the UART port from a given buffer and length,"]
#[doc = ""]
#[doc = " If the UART driver's parameter 'tx_buffer_size' is set to zero:"]
#[doc = " This function will not return until all the data and the break signal have been sent out."]
#[doc = " After all data is sent out, send a break signal."]
#[doc = ""]
#[doc = " Otherwise, if the 'tx_buffer_size' > 0, this function will return after copying all the data to tx ring buffer,"]
#[doc = " UART ISR will then move data from the ring buffer to TX FIFO gradually."]
#[doc = " After all data sent out, send a break signal."]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param src data buffer address"]
#[doc = " @param size data length to send"]
#[doc = " @param brk_len break signal duration(unit: the time it takes to send one bit at current baudrate)"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - (-1) Parameter error"]
#[doc = " - OTHERS (>=0) The number of bytes pushed to the TX FIFO"]
pub fn uart_write_bytes_with_break(
uart_num: uart_port_t,
src: *const ::std::os::raw::c_char,
size: usize,
brk_len: ::std::os::raw::c_int,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief UART read bytes from UART buffer"]
#[doc = ""]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = " @param buf pointer to the buffer."]
#[doc = " @param length data length"]
#[doc = " @param ticks_to_wait sTimeout, count in RTOS ticks"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - (-1) Error"]
#[doc = " - OTHERS (>=0) The number of bytes read from UART FIFO"]
pub fn uart_read_bytes(
uart_num: uart_port_t,
buf: *mut u8,
length: u32,
ticks_to_wait: TickType_t,
) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Alias of uart_flush_input."]
#[doc = " UART ring buffer flush. This will discard all data in the UART RX buffer."]
#[doc = " @note Instead of waiting the data sent out, this function will clear UART rx buffer."]
#[doc = " In order to send all the data in tx FIFO, we can use uart_wait_tx_done function."]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_flush(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Clear input buffer, discard all the data is in the ring-buffer."]
#[doc = " @note In order to send all the data in tx FIFO, we can use uart_wait_tx_done function."]
#[doc = " @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_flush_input(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief UART get RX ring buffer cached data length"]
#[doc = ""]
#[doc = " @param uart_num UART port number."]
#[doc = " @param size Pointer of size_t to accept cached data length"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_get_buffered_data_len(uart_num: uart_port_t, size: *mut usize) -> esp_err_t;
}
extern "C" {
#[doc = " @brief UART disable pattern detect function."]
#[doc = " Designed for applications like 'AT commands'."]
#[doc = " When the hardware detects a series of one same character, the interrupt will be triggered."]
#[doc = ""]
#[doc = " @param uart_num UART port number."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_disable_pattern_det_intr(uart_num: uart_port_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief UART enable pattern detect function."]
#[doc = " Designed for applications like 'AT commands'."]
#[doc = " When the hardware detect a series of one same character, the interrupt will be triggered."]
#[doc = ""]
#[doc = " @param uart_num UART port number."]
#[doc = " @param pattern_chr character of the pattern"]
#[doc = " @param chr_num number of the character, 8bit value."]
#[doc = " @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle."]
#[doc = " When the duration is less than this value, it will not take this data as at_cmd char"]
#[doc = " @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle."]
#[doc = " When the duration is less than this value, it will not take the previous data as the last at_cmd char"]
#[doc = " @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle."]
#[doc = " When the duration is less than this value, it will not take this data as the first at_cmd char"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_FAIL Parameter error"]
pub fn uart_enable_pattern_det_intr(
uart_num: uart_port_t,
pattern_chr: ::std::os::raw::c_char,
chr_num: u8,
chr_tout: ::std::os::raw::c_int,
post_idle: ::std::os::raw::c_int,
pre_idle: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Return the nearest detected pattern position in buffer."]
#[doc = " The positions of the detected pattern are saved in a queue,"]
#[doc = " this function will dequeue the first pattern position and move the pointer to next pattern position."]
#[doc = " @note If the RX buffer is full and flow control is not enabled,"]
#[doc = " the detected pattern may not be found in the rx buffer due to overflow."]
#[doc = ""]
#[doc = " The following APIs will modify the pattern position info:"]
#[doc = " uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos"]
#[doc = " It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer"]
#[doc = " when using pattern detect feature."]
#[doc = ""]
#[doc = " @param uart_num UART port number"]
#[doc = " @return"]
#[doc = " - (-1) No pattern found for current index or parameter error"]
#[doc = " - others the pattern position in rx buffer."]
pub fn uart_pattern_pop_pos(uart_num: uart_port_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Return the nearest detected pattern position in buffer."]
#[doc = " The positions of the detected pattern are saved in a queue,"]
#[doc = " This function do nothing to the queue."]
#[doc = " @note If the RX buffer is full and flow control is not enabled,"]
#[doc = " the detected pattern may not be found in the rx buffer due to overflow."]
#[doc = ""]
#[doc = " The following APIs will modify the pattern position info:"]
#[doc = " uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos"]
#[doc = " It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer"]
#[doc = " when using pattern detect feature."]
#[doc = ""]
#[doc = " @param uart_num UART port number"]
#[doc = " @return"]
#[doc = " - (-1) No pattern found for current index or parameter error"]
#[doc = " - others the pattern position in rx buffer."]
pub fn uart_pattern_get_pos(uart_num: uart_port_t) -> ::std::os::raw::c_int;
}
extern "C" {
#[doc = " @brief Allocate a new memory with the given length to save record the detected pattern position in rx buffer."]
#[doc = " @param uart_num UART port number"]
#[doc = " @param queue_length Max queue length for the detected pattern."]
#[doc = " If the queue length is not large enough, some pattern positions might be lost."]
#[doc = " Set this value to the maximum number of patterns that could be saved in data buffer at the same time."]
#[doc = " @return"]
#[doc = " - ESP_ERR_NO_MEM No enough memory"]
#[doc = " - ESP_ERR_INVALID_STATE Driver not installed"]
#[doc = " - ESP_FAIL Parameter error"]
#[doc = " - ESP_OK Success"]
pub fn uart_pattern_queue_reset(
uart_num: uart_port_t,
queue_length: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief UART set communication mode"]
#[doc = " @note This function must be executed after uart_driver_install(), when the driver object is initialized."]
#[doc = " @param uart_num Uart number to configure"]
#[doc = " @param mode UART UART mode to set"]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn uart_set_mode(uart_num: uart_port_t, mode: uart_mode_t) -> esp_err_t;
}
extern "C" {
#[doc = " @brief UART set threshold timeout for TOUT feature"]
#[doc = ""]
#[doc = " @param uart_num Uart number to configure"]
#[doc = " @param tout_thresh This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126."]
#[doc = " tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate."]
#[doc = " If the time is expired the UART_RXFIFO_TOUT_INT interrupt is triggered. If tout_thresh == 0,"]
#[doc = " the TOUT feature is disabled."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
#[doc = " - ESP_ERR_INVALID_STATE Driver is not installed"]
pub fn uart_set_rx_timeout(uart_num: uart_port_t, tout_thresh: u8) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Returns collision detection flag for RS485 mode"]
#[doc = " Function returns the collision detection flag into variable pointed by collision_flag."]
#[doc = " *collision_flag = true, if collision detected else it is equal to false."]
#[doc = " This function should be executed when actual transmission is completed (after uart_write_bytes())."]
#[doc = ""]
#[doc = " @param uart_num Uart number to configure"]
#[doc = " @param collision_flag Pointer to variable of type bool to return collision flag."]
#[doc = ""]
#[doc = " @return"]
#[doc = " - ESP_OK Success"]
#[doc = " - ESP_ERR_INVALID_ARG Parameter error"]
pub fn uart_get_collision_flag(uart_num: uart_port_t, collision_flag: *mut bool) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Set the number of RX pin signal edges for light sleep wakeup"]
#[doc = ""]
#[doc = " UART can be used to wake up the system from light sleep. This feature works"]
#[doc = " by counting the number of positive edges on RX pin and comparing the count to"]
#[doc = " the threshold. When the count exceeds the threshold, system is woken up from"]
#[doc = " light sleep. This function allows setting the threshold value."]
#[doc = ""]
#[doc = " Stop bit and parity bits (if enabled) also contribute to the number of edges."]
#[doc = " For example, letter 'a' with ASCII code 97 is encoded as 010001101 on the wire"]
#[doc = " (with 8n1 configuration), start and stop bits included. This sequence has 3"]
#[doc = " positive edges (transitions from 0 to 1). Therefore, to wake up the system"]
#[doc = " when 'a' is sent, set wakeup_threshold=3."]
#[doc = ""]
#[doc = " The character that triggers wakeup is not received by UART (i.e. it can not"]
#[doc = " be obtained from UART FIFO). Depending on the baud rate, a few characters"]
#[doc = " after that will also not be received. Note that when the chip enters and exits"]
#[doc = " light sleep mode, APB frequency will be changing. To make sure that UART has"]
#[doc = " correct baud rate all the time, select REF_TICK as UART clock source,"]
#[doc = " by setting use_ref_tick field in uart_config_t to true."]
#[doc = ""]
#[doc = " @note in ESP32, UART2 does not support light sleep wakeup feature."]
#[doc = ""]
#[doc = " @param uart_num UART number"]
#[doc = " @param wakeup_threshold number of RX edges for light sleep wakeup, value is 3 .. 0x3ff."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if uart_num is incorrect or wakeup_threshold is"]
#[doc = " outside of [3, 0x3ff] range."]
pub fn uart_set_wakeup_threshold(
uart_num: uart_port_t,
wakeup_threshold: ::std::os::raw::c_int,
) -> esp_err_t;
}
extern "C" {
#[doc = " @brief Get the number of RX pin signal edges for light sleep wakeup."]
#[doc = ""]
#[doc = " See description of uart_set_wakeup_threshold for the explanation of UART"]
#[doc = " wakeup feature."]
#[doc = ""]
#[doc = " @param uart_num UART number"]
#[doc = " @param[out] out_wakeup_threshold output, set to the current value of wakeup"]
#[doc = " threshold for the given UART."]
#[doc = " @return"]
#[doc = " - ESP_OK on success"]
#[doc = " - ESP_ERR_INVALID_ARG if out_wakeup_threshold is NULL"]
pub fn uart_get_wakeup_threshold(
uart_num: uart_port_t,
out_wakeup_threshold: *mut ::std::os::raw::c_int,
) -> esp_err_t;
}
pub type __builtin_va_list = __va_list_tag;
#[repr(C)]
#[derive(Debug, Copy, Clone)]
pub struct __va_list_tag {
pub __va_stk: *mut ::std::os::raw::c_int,
pub __va_reg: *mut ::std::os::raw::c_int,
pub __va_ndx: ::std::os::raw::c_int,
}