List of all items

Structs

• A1_REGS
• ADC
• AIP
• AUD
• CBP
• CFG_CTL
• CPUID
• CRU
• CorePeripherals
• DCB
• DMA
• DWT
• EXTM4REGS
• EXTREGSFFE
• FPB
• FPU
• I2S_SLAVE
• INTR_CTRL
• IOMUX
• ITM
• MISC
• MPU
• NVIC
• PKFB
• PMU
• Peripherals
• SCB
• SDMA
• SDMA_BRIDGE
• SDMA_SRAM
• SPI
• SPI_TLC
• SPT
• SYST
• TIMER
• TPIU
• UART
• WDT
• a1_regs::RegisterBlock
• a1_regs::cfg_ctrl::CFG_CTRL_SPEC
• a1_regs::cfg_ctrl::CFG_IN_SEL_R
• a1_regs::cfg_ctrl::CFG_IN_SEL_W
• a1_regs::cfg_ctrl::R
• a1_regs::cfg_ctrl::W
• adc::RegisterBlock
• adc::adc_control::ADC_CONTROL_SPEC
• adc::adc_control::BAT_R
• adc::adc_control::BAT_W
• adc::adc_control::R
• adc::adc_control::SEL_R
• adc::adc_control::SEL_W
• adc::adc_control::SOC_R
• adc::adc_control::SOC_W
• adc::adc_control::W
• adc::adc_out::ADC_OUT_SPEC
• adc::adc_out::OUT_R
• adc::adc_out::R
• adc::adc_status::ADC_STATUS_SPEC
• adc::adc_status::EOC_R
• adc::adc_status::R
• aip::RegisterBlock
• aip::apc_ctrl_0::APC_CTRL_0_SPEC
• aip::apc_ctrl_0::DIS_R
• aip::apc_ctrl_0::R
• aip::apc_ctrl_1::APC_CTRL_1_SPEC
• aip::apc_ctrl_1::R
• aip::apc_ctrl_1::TT_R
• aip::apc_ctrl_1::TT_W
• aip::apc_ctrl_1::VT_R
• aip::apc_ctrl_1::VT_W
• aip::apc_ctrl_1::W
• aip::apc_ctrl_2::APC_CTRL_2_SPEC
• aip::apc_ctrl_2::IT_R
• aip::apc_ctrl_2::IT_W
• aip::apc_ctrl_2::R
• aip::apc_ctrl_2::TEST_R
• aip::apc_ctrl_2::TEST_W
• aip::apc_ctrl_2::W
• aip::apc_ctrl_3::APC_CTRL_3_SPEC
• aip::apc_ctrl_3::R
• aip::apc_ctrl_4::APC_CTRL_4_SPEC
• aip::apc_ctrl_4::R
• aip::apc_ctrl_5::APC_CTRL_5_SPEC
• aip::apc_ctrl_5::R
• aip::apc_ctrl_6::APC_CTRL_6_SPEC
• aip::apc_ctrl_6::R
• aip::apc_ctrl_7::APC_CTRL_7_SPEC
• aip::apc_ctrl_7::R
• aip::apc_sta_0::APC_STA_0_SPEC
• aip::apc_sta_0::DIGTESTBUS_R
• aip::apc_sta_0::PORZ_R
• aip::apc_sta_0::R
• aip::apc_sta_0::TESTREQ_R
• aip::apc_sta_1::APC_STA_1_SPEC
• aip::apc_sta_1::R
• aip::ldo_30_ctrl_0::DISPG_R
• aip::ldo_30_ctrl_0::DISPG_W
• aip::ldo_30_ctrl_0::DIS_R
• aip::ldo_30_ctrl_0::DIS_W
• aip::ldo_30_ctrl_0::DI_R
• aip::ldo_30_ctrl_0::DI_W
• aip::ldo_30_ctrl_0::IMAX_R
• aip::ldo_30_ctrl_0::IMAX_W
• aip::ldo_30_ctrl_0::LDO_30_CTRL_0_SPEC
• aip::ldo_30_ctrl_0::R
• aip::ldo_30_ctrl_0::W
• aip::ldo_30_ctrl_1::LDO_30_CTRL_1_SPEC
• aip::ldo_30_ctrl_1::R
• aip::ldo_30_ctrl_1::TESTREQ_R
• aip::ldo_30_ctrl_1::TEST_R
• aip::ldo_30_ctrl_1::TEST_W
• aip::ldo_30_ctrl_1::W
• aip::ldo_50_ctrl_0::DISPG_R
• aip::ldo_50_ctrl_0::DISPG_W
• aip::ldo_50_ctrl_0::DIS_R
• aip::ldo_50_ctrl_0::DIS_W
• aip::ldo_50_ctrl_0::DI_R
• aip::ldo_50_ctrl_0::DI_W
• aip::ldo_50_ctrl_0::IMAX_R
• aip::ldo_50_ctrl_0::IMAX_W
• aip::ldo_50_ctrl_0::LDO_50_CTRL_0_SPEC
• aip::ldo_50_ctrl_0::R
• aip::ldo_50_ctrl_0::W
• aip::ldo_50_ctrl_1::LDO_50_CTRL_1_SPEC
• aip::ldo_50_ctrl_1::R
• aip::ldo_50_ctrl_1::TESTREQ_R
• aip::ldo_50_ctrl_1::TEST_R
• aip::ldo_50_ctrl_1::TEST_W
• aip::ldo_50_ctrl_1::W
• aip::osc_ctrl_0::EN_R
• aip::osc_ctrl_0::EN_W
• aip::osc_ctrl_0::FREF16K_SEL_R
• aip::osc_ctrl_0::FREF16K_SEL_W
• aip::osc_ctrl_0::OSC_CTRL_0_SPEC
• aip::osc_ctrl_0::R
• aip::osc_ctrl_0::W
• aip::osc_ctrl_1::GENERAL_PURPOS_SFR_R
• aip::osc_ctrl_1::GENERAL_PURPOS_SFR_W
• aip::osc_ctrl_1::OSC_CTRL_1_SPEC
• aip::osc_ctrl_1::PROG_R
• aip::osc_ctrl_1::PROG_W
• aip::osc_ctrl_1::R
• aip::osc_ctrl_1::W
• aip::osc_ctrl_2::DELTA_R
• aip::osc_ctrl_2::DELTA_W
• aip::osc_ctrl_2::OSC_CTRL_2_SPEC
• aip::osc_ctrl_2::R
• aip::osc_ctrl_2::W
• aip::osc_ctrl_3::ENMON_R
• aip::osc_ctrl_3::ENMON_W
• aip::osc_ctrl_3::GENERAL_PURPOS_SFR_R
• aip::osc_ctrl_3::GENERAL_PURPOS_SFR_W
• aip::osc_ctrl_3::OSC_CTRL_3_SPEC
• aip::osc_ctrl_3::R
• aip::osc_ctrl_3::REFOK_R
• aip::osc_ctrl_3::REFOK_W
• aip::osc_ctrl_3::W
• aip::osc_ctrl_4::CE_R
• aip::osc_ctrl_4::CE_W
• aip::osc_ctrl_4::OSC_CTRL_4_SPEC
• aip::osc_ctrl_4::R
• aip::osc_ctrl_4::TEST_R
• aip::osc_ctrl_4::TEST_W
• aip::osc_ctrl_4::W
• aip::osc_ctrl_4::WR_R
• aip::osc_ctrl_4::WR_W
• aip::osc_ctrl_5::OSC_CTRL_5_SPEC
• aip::osc_ctrl_5::R
• aip::osc_ctrl_5::SDI_R
• aip::osc_ctrl_5::SDI_W
• aip::osc_ctrl_5::W
• aip::osc_ctrl_6::OSC_CTRL_6_SPEC
• aip::osc_ctrl_6::R
• aip::osc_ctrl_6::SCK_R
• aip::osc_ctrl_6::SCK_W
• aip::osc_ctrl_6::W
• aip::osc_ctrl_7::OSC_CTRL_7_SPEC
• aip::osc_ctrl_7::R
• aip::osc_ctrl_7::W
• aip::osc_sta_0::ANATESTREQ__R
• aip::osc_sta_0::LOCK_R
• aip::osc_sta_0::OSC_STA_0_SPEC
• aip::osc_sta_0::R
• aip::osc_sta_1::OSC_STA_1_SPEC
• aip::osc_sta_1::R
• aip::osc_sta_1::SDO_R
• aip::ring_osc::GENERAL_PURPOS_SFR_R
• aip::ring_osc::GENERAL_PURPOS_SFR_W
• aip::ring_osc::R
• aip::ring_osc::RING_OSC_EN_R
• aip::ring_osc::RING_OSC_EN_W
• aip::ring_osc::RING_OSC_SPEC
• aip::ring_osc::W
• aip::rtc_ctrl_1::CLKDIV_R
• aip::rtc_ctrl_1::CLKDIV_W
• aip::rtc_ctrl_1::R
• aip::rtc_ctrl_1::RTC_CTRL_1_SPEC
• aip::rtc_ctrl_1::W
• aip::rtc_ctrl_2::BYP16K_R
• aip::rtc_ctrl_2::BYP16K_W
• aip::rtc_ctrl_2::CLKE_R
• aip::rtc_ctrl_2::CLKE_W
• aip::rtc_ctrl_2::R
• aip::rtc_ctrl_2::RTC_CTRL_2_SPEC
• aip::rtc_ctrl_2::TEST_CTRL_R
• aip::rtc_ctrl_2::TEST_CTRL_W
• aip::rtc_ctrl_2::W
• aip::rtc_ctrl_3::CE_R
• aip::rtc_ctrl_3::CE_W
• aip::rtc_ctrl_3::R
• aip::rtc_ctrl_3::RTC_CTRL_3_SPEC
• aip::rtc_ctrl_3::W
• aip::rtc_ctrl_4::R
• aip::rtc_ctrl_4::RTC_CTRL_4_SPEC
• aip::rtc_ctrl_4::W
• aip::rtc_ctrl_4::WR_R
• aip::rtc_ctrl_4::WR_W
• aip::rtc_ctrl_5::C_R
• aip::rtc_ctrl_5::C_W
• aip::rtc_ctrl_5::R
• aip::rtc_ctrl_5::RTC_CTRL_5_SPEC
• aip::rtc_ctrl_5::W
• aip::rtc_ctrl_6::PI_R
• aip::rtc_ctrl_6::PI_W
• aip::rtc_ctrl_6::R
• aip::rtc_ctrl_6::RTC_CTRL_6_SPEC
• aip::rtc_ctrl_6::W
• aip::rtc_ctrl_7::R
• aip::rtc_ctrl_7::RTC_CTRL_7_SPEC
• aip::rtc_ctrl_7::TEST_R
• aip::rtc_ctrl_7::TEST_W
• aip::rtc_ctrl_7::W
• aip::rtc_sta_0::ALARM_R
• aip::rtc_sta_0::DIGTESTBUS_R
• aip::rtc_sta_0::OSCOK_R
• aip::rtc_sta_0::R
• aip::rtc_sta_0::RTC_STA_0_SPEC
• aip::rtc_sta_0::TESTREQ_R
• aip::rtc_sta_1::PO_R
• aip::rtc_sta_1::R
• aip::rtc_sta_1::RTC_STA_1_SPEC
• aud::RegisterBlock
• aud::dbg_mux_cfg::DBG_MUX_CFG_SPEC
• aud::dbg_mux_cfg::DBG_MUX_R
• aud::dbg_mux_cfg::DBG_MUX_W
• aud::dbg_mux_cfg::R
• aud::dbg_mux_cfg::W
• aud::fifo_sram_cfg::FIFO_SRAM_CFG_SPEC
• aud::fifo_sram_cfg::R
• aud::fifo_sram_cfg::SRAM_0A_RME_R
• aud::fifo_sram_cfg::SRAM_0A_RME_W
• aud::fifo_sram_cfg::SRAM_0A_RM_R
• aud::fifo_sram_cfg::SRAM_0A_RM_W
• aud::fifo_sram_cfg::SRAM_0A_TEST1_R
• aud::fifo_sram_cfg::SRAM_0A_TEST1_W
• aud::fifo_sram_cfg::SRAM_0B_RME_R
• aud::fifo_sram_cfg::SRAM_0B_RME_W
• aud::fifo_sram_cfg::SRAM_0B_RM_R
• aud::fifo_sram_cfg::SRAM_0B_RM_W
• aud::fifo_sram_cfg::SRAM_0B_TEST1_R
• aud::fifo_sram_cfg::SRAM_0B_TEST1_W
• aud::fifo_sram_cfg::SRAM_1A_RME_R
• aud::fifo_sram_cfg::SRAM_1A_RME_W
• aud::fifo_sram_cfg::SRAM_1A_RM_R
• aud::fifo_sram_cfg::SRAM_1A_RM_W
• aud::fifo_sram_cfg::SRAM_1A_TEST1_R
• aud::fifo_sram_cfg::SRAM_1A_TEST1_W
• aud::fifo_sram_cfg::SRAM_1B_RME_R
• aud::fifo_sram_cfg::SRAM_1B_RME_W
• aud::fifo_sram_cfg::SRAM_1B_RM_R
• aud::fifo_sram_cfg::SRAM_1B_RM_W
• aud::fifo_sram_cfg::SRAM_1B_TEST1_R
• aud::fifo_sram_cfg::SRAM_1B_TEST1_W
• aud::fifo_sram_cfg::W
• aud::i2s_config::I2S_BLKDIV_R
• aud::i2s_config::I2S_BLKDIV_W
• aud::i2s_config::I2S_CLK_INV_R
• aud::i2s_config::I2S_CLK_INV_W
• aud::i2s_config::I2S_CONFIG_SPEC
• aud::i2s_config::I2S_IWL_R
• aud::i2s_config::I2S_IWL_W
• aud::i2s_config::I2S_LRCDIV_R
• aud::i2s_config::I2S_LRCDIV_W
• aud::i2s_config::R
• aud::i2s_config::W
• aud::lpsd_config::LPSD_CONFIG_SPEC
• aud::lpsd_config::LPSD_RATIO_RUN_R
• aud::lpsd_config::LPSD_RATIO_RUN_W
• aud::lpsd_config::LPSD_RATIO_STOP_R
• aud::lpsd_config::LPSD_RATIO_STOP_W
• aud::lpsd_config::LPSD_THD_R
• aud::lpsd_config::LPSD_THD_W
• aud::lpsd_config::R
• aud::lpsd_config::W
• aud::pdm_core_config::ADCHPD_R
• aud::pdm_core_config::ADCHPD_W
• aud::pdm_core_config::DIV_MODE_R
• aud::pdm_core_config::DIV_MODE_W
• aud::pdm_core_config::DIV_WD_MODE_R
• aud::pdm_core_config::DIV_WD_MODE_W
• aud::pdm_core_config::DMICK_DLY_R
• aud::pdm_core_config::DMICK_DLY_W
• aud::pdm_core_config::HP_GAIN_R
• aud::pdm_core_config::HP_GAIN_W
• aud::pdm_core_config::M_CLK_DIV_R
• aud::pdm_core_config::M_CLK_DIV_W
• aud::pdm_core_config::PDM_CORE_CONFIG_R
• aud::pdm_core_config::PDM_CORE_CONFIG_SPEC
• aud::pdm_core_config::PDM_CORE_CONFIG_W
• aud::pdm_core_config::PGA_L_R
• aud::pdm_core_config::PGA_L_W
• aud::pdm_core_config::PGA_R_R
• aud::pdm_core_config::PGA_R_W
• aud::pdm_core_config::R
• aud::pdm_core_config::SINC_RATE_R
• aud::pdm_core_config::SINC_RATE_W
• aud::pdm_core_config::SOFT_MUTE_R
• aud::pdm_core_config::SOFT_MUTE_W
• aud::pdm_core_config::S_CYCLES_R
• aud::pdm_core_config::S_CYCLES_W
• aud::pdm_core_config::W
• aud::pdma_sram_cfg::PDMA_SRAM_CFG_SPEC
• aud::pdma_sram_cfg::PDM_SRAM_L_RME_R
• aud::pdma_sram_cfg::PDM_SRAM_L_RME_W
• aud::pdma_sram_cfg::PDM_SRAM_L_RM_R
• aud::pdma_sram_cfg::PDM_SRAM_L_RM_W
• aud::pdma_sram_cfg::PDM_SRAM_L_TEST1_R
• aud::pdma_sram_cfg::PDM_SRAM_L_TEST1_W
• aud::pdma_sram_cfg::R
• aud::pdma_sram_cfg::W
• aud::voice_config::AP_PDM_CLK_IB_MASK_W
• aud::voice_config::AP_PDM_CLK_OFF_MASK_W
• aud::voice_config::DIV_AP_R
• aud::voice_config::DIV_AP_W
• aud::voice_config::DIV_WD_R
• aud::voice_config::DIV_WD_W
• aud::voice_config::DMAC_BLK_DONE_MASK_W
• aud::voice_config::DMAC_BUF_DONE_MASK_W
• aud::voice_config::DMIC_SEL_R
• aud::voice_config::DMIC_SEL_W
• aud::voice_config::DMIC_VOICE_DETECTED_MASK_W
• aud::voice_config::FIFO_0_CLEAR_R
• aud::voice_config::FIFO_0_CLEAR_W
• aud::voice_config::FIFO_1_CLEAR_R
• aud::voice_config::FIFO_1_CLEAR_W
• aud::voice_config::I2S_DS_EN_R
• aud::voice_config::I2S_DS_EN_W
• aud::voice_config::I2S_FPGA_EN_R
• aud::voice_config::I2S_FPGA_EN_W
• aud::voice_config::LPSD_MUX_R
• aud::voice_config::LPSD_MUX_W
• aud::voice_config::LPSD_NO_R
• aud::voice_config::LPSD_NO_W
• aud::voice_config::LPSD_SEL_R
• aud::voice_config::LPSD_SEL_W
• aud::voice_config::LPSD_USE_DC_BLOCK_R
• aud::voice_config::LPSD_USE_DC_BLOCK_W
• aud::voice_config::LPSD_VOICE_DETECTED_MASK_R
• aud::voice_config::LPSD_VOICE_DETECTED_MASK_W
• aud::voice_config::MODE_SEL_R
• aud::voice_config::MODE_SEL_W
• aud::voice_config::MONO_CHN_SEL_R
• aud::voice_config::MONO_CHN_SEL_W
• aud::voice_config::PDM_MIC_SWITCH_TO_AP_R
• aud::voice_config::PDM_MIC_SWITCH_TO_AP_W
• aud::voice_config::PDM_VOICE_SCENARIO_R
• aud::voice_config::PDM_VOICE_SCENARIO_W
• aud::voice_config::R
• aud::voice_config::VOICE_CONFIG_SPEC
• aud::voice_config::W
• aud::voice_dma_config::AHB_BURST_LENGHT_R
• aud::voice_dma_config::AHB_BURST_LENGHT_W
• aud::voice_dma_config::AHB_RDY_R
• aud::voice_dma_config::AHB_RDY_W
• aud::voice_dma_config::DMAC_EN_R
• aud::voice_dma_config::DMAC_EN_W
• aud::voice_dma_config::DMAC_START_W
• aud::voice_dma_config::DMAC_STOP_R
• aud::voice_dma_config::DMAC_STOP_W
• aud::voice_dma_config::PINGPONG_MODE_R
• aud::voice_dma_config::PINGPONG_MODE_W
• aud::voice_dma_config::R
• aud::voice_dma_config::STEREO_DUAL_BUF_MODE_R
• aud::voice_dma_config::STEREO_DUAL_BUF_MODE_W
• aud::voice_dma_config::VOICE_DMAC_BURST_SPD_R
• aud::voice_dma_config::VOICE_DMAC_BURST_SPD_W
• aud::voice_dma_config::VOICE_DMA_CONFIG_SPEC
• aud::voice_dma_config::W
• aud::voice_dmac_dst_addr0::R
• aud::voice_dmac_dst_addr0::VOICE_DMAC_DST_ADDR0_R
• aud::voice_dmac_dst_addr0::VOICE_DMAC_DST_ADDR0_SPEC
• aud::voice_dmac_dst_addr0::VOICE_DMAC_DST_ADDR0_W
• aud::voice_dmac_dst_addr0::W
• aud::voice_dmac_dst_addr1::R
• aud::voice_dmac_dst_addr1::VOICE_DMAC_DST_ADDR1_R
• aud::voice_dmac_dst_addr1::VOICE_DMAC_DST_ADDR1_SPEC
• aud::voice_dmac_dst_addr1::VOICE_DMAC_DST_ADDR1_W
• aud::voice_dmac_dst_addr1::W
• aud::voice_dmac_fifo::DMAC_BUF_OFFSER_R
• aud::voice_dmac_fifo::DMAC_BUF_OFFSER_W
• aud::voice_dmac_fifo::R
• aud::voice_dmac_fifo::VOICE_DMAC_FIFO_SPEC
• aud::voice_dmac_fifo::W
• aud::voice_dmac_len::DMAC_BLK_LEN_R
• aud::voice_dmac_len::DMAC_BLK_LEN_W
• aud::voice_dmac_len::DMAC_BUF_LEN_R
• aud::voice_dmac_len::DMAC_BUF_LEN_W
• aud::voice_dmac_len::R
• aud::voice_dmac_len::VOICE_DMAC_LEN_SPEC
• aud::voice_dmac_len::W
• aud::voice_status::AP_PDM_CLK_OFF_REG_R
• aud::voice_status::AP_PDM_CLK_ON_REG_R
• aud::voice_status::DMAC0_BLK_DONE_REG_R
• aud::voice_status::DMAC0_BLK_DONE_REG_W
• aud::voice_status::DMAC0_BUF_DONE_REG_R
• aud::voice_status::DMAC0_BUF_DONE_REG_W
• aud::voice_status::DMAC1_BLK_DONE_REG_R
• aud::voice_status::DMAC1_BLK_DONE_REG_W
• aud::voice_status::DMAC1_BUF_DONE_REG_R
• aud::voice_status::DMAC1_BUF_DONE_REG_W
• aud::voice_status::DMIC_VOICE_DETECTED_REG_R
• aud::voice_status::FIFO_0A_EMPTY_R
• aud::voice_status::FIFO_0A_FULL_R
• aud::voice_status::FIFO_0A_FULL_W
• aud::voice_status::FIFO_0A_OVERFLOW_R
• aud::voice_status::FIFO_0A_OVERFLOW_W
• aud::voice_status::FIFO_0B_EMPTY_R
• aud::voice_status::FIFO_0B_FULL_R
• aud::voice_status::FIFO_0B_FULL_W
• aud::voice_status::FIFO_0B_OVERFLOW_R
• aud::voice_status::FIFO_0B_OVERFLOW_W
• aud::voice_status::FIFO_1A_EMPTY_R
• aud::voice_status::FIFO_1A_FULL_R
• aud::voice_status::FIFO_1A_FULL_W
• aud::voice_status::FIFO_1A_OVERFLOW_R
• aud::voice_status::FIFO_1A_OVERFLOW_W
• aud::voice_status::FIFO_1B_EMPTY_R
• aud::voice_status::FIFO_1B_FULL_R
• aud::voice_status::FIFO_1B_FULL_W
• aud::voice_status::FIFO_1B_OVERFLOW_R
• aud::voice_status::FIFO_1B_OVERFLOW_W
• aud::voice_status::LPSD_VOICE_DETECTED_REG_R
• aud::voice_status::R
• aud::voice_status::VOICE_STATUS_SPEC
• aud::voice_status::W
• cfg_ctl::RegisterBlock
• cfg_ctl::cfg_ctl::APB_BLM_SEL_R
• cfg_ctl::cfg_ctl::APB_BLM_SEL_W
• cfg_ctl::cfg_ctl::APB_BL_SEL_R
• cfg_ctl::cfg_ctl::APB_BL_SEL_W
• cfg_ctl::cfg_ctl::APB_BRM_SEL_R
• cfg_ctl::cfg_ctl::APB_BRM_SEL_W
• cfg_ctl::cfg_ctl::APB_BR_SEL_R
• cfg_ctl::cfg_ctl::APB_BR_SEL_W
• cfg_ctl::cfg_ctl::APB_CFG_RD_R
• cfg_ctl::cfg_ctl::APB_CFG_RD_W
• cfg_ctl::cfg_ctl::APB_CFG_WR_R
• cfg_ctl::cfg_ctl::APB_CFG_WR_W
• cfg_ctl::cfg_ctl::APB_PARTIAL_LOAD_R
• cfg_ctl::cfg_ctl::APB_PARTIAL_LOAD_W
• cfg_ctl::cfg_ctl::APB_SEL_CFG_R
• cfg_ctl::cfg_ctl::APB_SEL_CFG_W
• cfg_ctl::cfg_ctl::APB_TLM_SEL_R
• cfg_ctl::cfg_ctl::APB_TLM_SEL_W
• cfg_ctl::cfg_ctl::APB_TL_SEL_R
• cfg_ctl::cfg_ctl::APB_TL_SEL_W
• cfg_ctl::cfg_ctl::APB_TRM_SEL_R
• cfg_ctl::cfg_ctl::APB_TRM_SEL_W
• cfg_ctl::cfg_ctl::APB_TR_SEL_R
• cfg_ctl::cfg_ctl::APB_TR_SEL_W
• cfg_ctl::cfg_ctl::APB_WL_DIN_R
• cfg_ctl::cfg_ctl::APB_WL_DIN_W
• cfg_ctl::cfg_ctl::CFG_CTL_SPEC
• cfg_ctl::cfg_ctl::R
• cfg_ctl::cfg_ctl::SW_PWR_GATE_R
• cfg_ctl::cfg_ctl::SW_PWR_GATE_W
• cfg_ctl::cfg_ctl::W
• cfg_ctl::cfg_data::CFG_DATA_R
• cfg_ctl::cfg_data::CFG_DATA_SPEC
• cfg_ctl::cfg_data::CFG_DATA_W
• cfg_ctl::cfg_data::R
• cfg_ctl::cfg_data::W
• cfg_ctl::max_bl_cnt::MAX_BL_CNT_R
• cfg_ctl::max_bl_cnt::MAX_BL_CNT_SPEC
• cfg_ctl::max_bl_cnt::MAX_BL_CNT_W
• cfg_ctl::max_bl_cnt::R
• cfg_ctl::max_bl_cnt::W
• cfg_ctl::max_wl_cnt::MAX_WL_CNT_R
• cfg_ctl::max_wl_cnt::MAX_WL_CNT_SPEC
• cfg_ctl::max_wl_cnt::MAX_WL_CNT_W
• cfg_ctl::max_wl_cnt::R
• cfg_ctl::max_wl_cnt::W
• cfg_ctl::ramfifo0::R
• cfg_ctl::ramfifo0::RAMFIFO0_R
• cfg_ctl::ramfifo0::RAMFIFO0_SPEC
• cfg_ctl::ramfifo0::RAMFIFO0_W
• cfg_ctl::ramfifo0::W
• cfg_ctl::ramfifo1::R
• cfg_ctl::ramfifo1::RAMFIFO1_R
• cfg_ctl::ramfifo1::RAMFIFO1_SPEC
• cfg_ctl::ramfifo1::RAMFIFO1_W
• cfg_ctl::ramfifo1::W
• cfg_ctl::ramfifo2::R
• cfg_ctl::ramfifo2::RAMFIFO2_R
• cfg_ctl::ramfifo2::RAMFIFO2_SPEC
• cfg_ctl::ramfifo2::RAMFIFO2_W
• cfg_ctl::ramfifo2::W
• cfg_ctl::ramfifo3::R
• cfg_ctl::ramfifo3::RAMFIFO3_R
• cfg_ctl::ramfifo3::RAMFIFO3_SPEC
• cfg_ctl::ramfifo3::RAMFIFO3_W
• cfg_ctl::ramfifo3::W
• cru::RegisterBlock
• cru::a1_sw_reset::A1_SW_RESET_SPEC
• cru::a1_sw_reset::CFGSM_SW_RESET_R
• cru::a1_sw_reset::CFGSM_SW_RESET_W
• cru::a1_sw_reset::R
• cru::a1_sw_reset::SPT_SW_RESET_R
• cru::a1_sw_reset::SPT_SW_RESET_W
• cru::a1_sw_reset::W
• cru::audio_misc_sw_reset::AD0_SW_RESET_R
• cru::audio_misc_sw_reset::AD0_SW_RESET_W
• cru::audio_misc_sw_reset::AD1_SW_RESET_W
• cru::audio_misc_sw_reset::AD2_SW_RESET_W
• cru::audio_misc_sw_reset::AD3_SW_RESET_W
• cru::audio_misc_sw_reset::AD4_SW_RESET_W
• cru::audio_misc_sw_reset::AD5_SW_RESET_W
• cru::audio_misc_sw_reset::AUDIO_MISC_SW_RESET_SPEC
• cru::audio_misc_sw_reset::DMA_SW_RESET_W
• cru::audio_misc_sw_reset::I2S_SW_RESET_W
• cru::audio_misc_sw_reset::R
• cru::audio_misc_sw_reset::W
• cru::c01_clk_div::C01_CLK_DIV_CG_R
• cru::c01_clk_div::C01_CLK_DIV_CG_W
• cru::c01_clk_div::C01_CLK_DIV_R
• cru::c01_clk_div::C01_CLK_DIV_SPEC
• cru::c01_clk_div::C01_CLK_DIV_W
• cru::c01_clk_div::R
• cru::c01_clk_div::W
• cru::c01_clk_gate::C01_CLK_GATE_SPEC
• cru::c01_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_1_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_2_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_3_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_4_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_5_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_6_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_7_GATING_CONTROL_W
• cru::c01_clk_gate::PATH_9_GATING_CONTROL_W
• cru::c01_clk_gate::R
• cru::c01_clk_gate::W
• cru::c02_clk_gate::C02_CLK_GATE_SPEC
• cru::c02_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c02_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c02_clk_gate::PATH_1_GATING_CONTROL_W
• cru::c02_clk_gate::PATH_2_GATING_CONTROL_W
• cru::c02_clk_gate::R
• cru::c02_clk_gate::W
• cru::c08_x1_clk_gate::C08_X1_CLK_GATE_SPEC
• cru::c08_x1_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c08_x1_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c08_x1_clk_gate::PATH_2_GATING_CONTROL_W
• cru::c08_x1_clk_gate::PATH_3_GATING_CONTROL_W
• cru::c08_x1_clk_gate::R
• cru::c08_x1_clk_gate::W
• cru::c08_x4_clk_gate::C08_X4_CLK_GATE_SPEC
• cru::c08_x4_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c08_x4_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c08_x4_clk_gate::R
• cru::c08_x4_clk_gate::W
• cru::c09_clk_div::C01_CLK_DIV_CG_R
• cru::c09_clk_div::C01_CLK_DIV_CG_W
• cru::c09_clk_div::C01_CLK_DIV_R
• cru::c09_clk_div::C01_CLK_DIV_W
• cru::c09_clk_div::C09_CLK_DIV_SPEC
• cru::c09_clk_div::R
• cru::c09_clk_div::W
• cru::c09_clk_gate::C09_CLK_GATE_SPEC
• cru::c09_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c09_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c09_clk_gate::PATH_1_GATING_CONTROL_W
• cru::c09_clk_gate::PATH_2_GATING_CONTROL_W
• cru::c09_clk_gate::R
• cru::c09_clk_gate::W
• cru::c10_fclk_gate::C10_FCLK_GATE_SPEC
• cru::c10_fclk_gate::PATH_0_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_1_GATING_CONTROL_W
• cru::c10_fclk_gate::PATH_2_GATING_CONTROL_W
• cru::c10_fclk_gate::PATH_3_GATING_CONTROL_W
• cru::c10_fclk_gate::PATH_4_GATING_CONTROL_W
• cru::c10_fclk_gate::PATH_5_GATING_CONTROL_W
• cru::c10_fclk_gate::PATH_6_GATING_CONTROL_W
• cru::c10_fclk_gate::R
• cru::c10_fclk_gate::W
• cru::c11_clk_gate::C11_CLK_GATE_SPEC
• cru::c11_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c11_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c11_clk_gate::R
• cru::c11_clk_gate::W
• cru::c12_clk_gate_reserved::C12_CLK_GATE_RESERVED_SPEC
• cru::c12_clk_gate_reserved::R
• cru::c16_clk_gate::C16_CLK_GATE_SPEC
• cru::c16_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c16_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c16_clk_gate::R
• cru::c16_clk_gate::W
• cru::c19_clk_gate::C19_CLK_GATE_SPEC
• cru::c19_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c19_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c19_clk_gate::R
• cru::c19_clk_gate::W
• cru::c21_clk_gate::C21_CLK_GATE_SPEC
• cru::c21_clk_gate::PATH_0_GATING_CONTROL_R
• cru::c21_clk_gate::PATH_0_GATING_CONTROL_W
• cru::c21_clk_gate::R
• cru::c21_clk_gate::W
• cru::c30_c31_clk_gate::C30_C31_CLK_GATE_SPEC
• cru::c30_c31_clk_gate::C30_PATH_0_GATING_CONTROL_R
• cru::c30_c31_clk_gate::C30_PATH_0_GATING_CONTROL_W
• cru::c30_c31_clk_gate::C30_PATH_1_GATING_CONTROL_W
• cru::c30_c31_clk_gate::C30_PATH_2_GATING_CONTROL_W
• cru::c30_c31_clk_gate::C31_PATH_0_GATING_CONTROL_W
• cru::c30_c31_clk_gate::R
• cru::c30_c31_clk_gate::W
• cru::c31_clk_div::C01_CLK_DIV_CG_R
• cru::c31_clk_div::C01_CLK_DIV_CG_W
• cru::c31_clk_div::C01_CLK_DIV_R
• cru::c31_clk_div::C01_CLK_DIV_W
• cru::c31_clk_div::C31_CLK_DIV_SPEC
• cru::c31_clk_div::R
• cru::c31_clk_div::W
• cru::clk_ctrl_a_0::CLK_CTRL_A_0_SPEC
• cru::clk_ctrl_a_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_a_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_a_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_a_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_a_0::R
• cru::clk_ctrl_a_0::W
• cru::clk_ctrl_a_1::CLK_CTRL_A_1_SPEC
• cru::clk_ctrl_a_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_a_1::CLOCK_SOURCE_SELECTION_W
• cru::clk_ctrl_a_1::R
• cru::clk_ctrl_a_1::W
• cru::clk_ctrl_b_0::CLK_CTRL_B_0_SPEC
• cru::clk_ctrl_b_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_b_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_b_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_b_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_b_0::R
• cru::clk_ctrl_b_0::W
• cru::clk_ctrl_b_1::CLK_CTRL_B_1_SPEC
• cru::clk_ctrl_b_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_b_1::CLOCK_SOURCE_SELECTION_W
• cru::clk_ctrl_b_1::R
• cru::clk_ctrl_b_1::W
• cru::clk_ctrl_c_0::CLK_CTRL_C_0_SPEC
• cru::clk_ctrl_c_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_c_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_c_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_c_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_c_0::R
• cru::clk_ctrl_c_0::W
• cru::clk_ctrl_d_0::CLK_CTRL_D_0_SPEC
• cru::clk_ctrl_d_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_d_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_d_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_d_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_d_0::R
• cru::clk_ctrl_d_0::W
• cru::clk_ctrl_e_0::CLK_CTRL_E_0_SPEC
• cru::clk_ctrl_e_0::R
• cru::clk_ctrl_e_0::W
• cru::clk_ctrl_e_1::CLK_CTRL_E_1_SPEC
• cru::clk_ctrl_e_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_e_1::R
• cru::clk_ctrl_f_0::CLK_CTRL_F_0_SPEC
• cru::clk_ctrl_f_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_f_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_f_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_f_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_f_0::R
• cru::clk_ctrl_f_0::W
• cru::clk_ctrl_f_1::CLK_CTRL_F_1_SPEC
• cru::clk_ctrl_f_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_f_1::CLOCK_SOURCE_SELECTION_W
• cru::clk_ctrl_f_1::R
• cru::clk_ctrl_f_1::W
• cru::clk_ctrl_g_0::CLK_CTRL_G_0_SPEC
• cru::clk_ctrl_g_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_g_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_g_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_g_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_g_0::R
• cru::clk_ctrl_g_0::W
• cru::clk_ctrl_h_0::CLK_CTRL_H_0_SPEC
• cru::clk_ctrl_h_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_h_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_h_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_h_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_h_0::R
• cru::clk_ctrl_h_0::W
• cru::clk_ctrl_h_1::CLK_CTRL_H_1_SPEC
• cru::clk_ctrl_h_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_h_1::R
• cru::clk_ctrl_i_0::CLK_CTRL_I_0_SPEC
• cru::clk_ctrl_i_0::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_i_0::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_i_0::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_i_0::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_i_0::R
• cru::clk_ctrl_i_0::W
• cru::clk_ctrl_i_1::CLK_CTRL_I_1_SPEC
• cru::clk_ctrl_i_1::CLOCK_SOURCE_SELECTION_R
• cru::clk_ctrl_i_1::CLOCK_SOURCE_SELECTION_W
• cru::clk_ctrl_i_1::R
• cru::clk_ctrl_i_1::W
• cru::clk_ctrl_pmu::CLK_CTRL_PMU_SPEC
• cru::clk_ctrl_pmu::CLOCK_DIVIDER_RATIO_R
• cru::clk_ctrl_pmu::CLOCK_DIVIDER_RATIO_W
• cru::clk_ctrl_pmu::ENABLE_CLOCK_DIVIDER_R
• cru::clk_ctrl_pmu::ENABLE_CLOCK_DIVIDER_W
• cru::clk_ctrl_pmu::R
• cru::clk_ctrl_pmu::W
• cru::clk_divider_clk_gating::CLK_DIVIDER_A_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_A_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_B_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_CLK_GATING_SPEC
• cru::clk_divider_clk_gating::CLK_DIVIDER_C_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_D_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_F_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_G_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_H_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_I_CG_W
• cru::clk_divider_clk_gating::CLK_DIVIDER_J_CG_W
• cru::clk_divider_clk_gating::R
• cru::clk_divider_clk_gating::W
• cru::clk_reserved_0::CLK_RESERVED_0_SPEC
• cru::clk_reserved_0::R
• cru::clk_switch_for_b::CLK_SWITCH_FOR_B_SPEC
• cru::clk_switch_for_b::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_b::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_b::R
• cru::clk_switch_for_b::W
• cru::clk_switch_for_c::CLK_SWITCH_FOR_C_SPEC
• cru::clk_switch_for_c::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_c::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_c::R
• cru::clk_switch_for_c::W
• cru::clk_switch_for_d::CLK_SWITCH_FOR_D_SPEC
• cru::clk_switch_for_d::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_d::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_d::R
• cru::clk_switch_for_d::W
• cru::clk_switch_for_g::CLK_SWITCH_FOR_G_SPEC
• cru::clk_switch_for_g::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_g::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_g::R
• cru::clk_switch_for_g::W
• cru::clk_switch_for_h::CLK_SWITCH_FOR_H_SPEC
• cru::clk_switch_for_h::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_h::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_h::R
• cru::clk_switch_for_h::W
• cru::clk_switch_for_j::CLK_SWITCH_FOR_J_SPEC
• cru::clk_switch_for_j::CLOCK_SOURCE_SELECTION_R
• cru::clk_switch_for_j::CLOCK_SOURCE_SELECTION_W
• cru::clk_switch_for_j::R
• cru::clk_switch_for_j::W
• cru::cru_debug::CRU_DEBUG_SELECT_R
• cru::cru_debug::CRU_DEBUG_SELECT_W
• cru::cru_debug::CRU_DEBUG_SPEC
• cru::cru_debug::R
• cru::cru_debug::W
• cru::cru_general::CRU_GENERAL_SPEC
• cru::cru_general::GENERAL_R
• cru::cru_general::GENERAL_W
• cru::cru_general::R
• cru::cru_general::SPICLK_ALWAYS_ON_R
• cru::cru_general::SPICLK_ALWAYS_ON_W
• cru::cru_general::W
• cru::cs_clk_gate::CS_CLK_GATE_SPEC
• cru::cs_clk_gate::PATH_0_GATING_CONTROL_R
• cru::cs_clk_gate::PATH_0_GATING_CONTROL_W
• cru::cs_clk_gate::R
• cru::cs_clk_gate::W
• cru::cu_clk_gate_reserved::CU_CLK_GATE_RESERVED_SPEC
• cru::cu_clk_gate_reserved::R
• cru::fb_misc_sw_rst_ctl::AHBWB_SW_RESET_R
• cru::fb_misc_sw_rst_ctl::AHBWB_SW_RESET_W
• cru::fb_misc_sw_rst_ctl::FB_MISC_SW_RST_CTL_SPEC
• cru::fb_misc_sw_rst_ctl::PFAFIFO1_SW_RESET_W
• cru::fb_misc_sw_rst_ctl::R
• cru::fb_misc_sw_rst_ctl::W
• cru::fb_sw_reset::FB_C02_DOMAIN_SW_RESET_R
• cru::fb_sw_reset::FB_C02_DOMAIN_SW_RESET_W
• cru::fb_sw_reset::FB_C09_DOMAIN_SW_RESET_W
• cru::fb_sw_reset::FB_C16_DOMAIN_SW_RESET_W
• cru::fb_sw_reset::FB_C21_DOMAIN_SW_RESET_W
• cru::fb_sw_reset::FB_SW_RESET_SPEC
• cru::fb_sw_reset::R
• cru::fb_sw_reset::W
• cru::ffe_sw_reset::FFE_0_X1_SW_RESET_R
• cru::ffe_sw_reset::FFE_0_X1_SW_RESET_W
• cru::ffe_sw_reset::FFE_0_X4_SW_RESET_R
• cru::ffe_sw_reset::FFE_0_X4_SW_RESET_W
• cru::ffe_sw_reset::FFE_SW_RESET_SPEC
• cru::ffe_sw_reset::R
• cru::ffe_sw_reset::W
• cru::pf_sw_reset::PF_ASYNC_FIFO_0_SW_RESET_W
• cru::pf_sw_reset::PF_FIFO_0_SW_RESET_R
• cru::pf_sw_reset::PF_FIFO_0_SW_RESET_W
• cru::pf_sw_reset::PF_FIFO_1_SW_RESET_W
• cru::pf_sw_reset::PF_FIFO_2_SW_RESET_W
• cru::pf_sw_reset::PF_FIFO_8K_SW_RESET_W
• cru::pf_sw_reset::PF_PERIPHERAL_SW_RESET_W
• cru::pf_sw_reset::PF_SW_RESET_SPEC
• cru::pf_sw_reset::R
• cru::pf_sw_reset::W
• dma::RegisterBlock
• dma::cfg_flash_header::CFG_FLASH_HEADER_SPEC
• dma::cfg_flash_header::DMA_BOOT_XFR_SIZE_R
• dma::cfg_flash_header::DMA_DEVICE_ID_R
• dma::cfg_flash_header::DMA_SPI_CLIK_DIVIDE_R
• dma::cfg_flash_header::R
• dma::cfg_machine_st_delay::CFG_MACHINE_ST_DELAY_SPEC
• dma::cfg_machine_st_delay::DELAY_REG_R
• dma::cfg_machine_st_delay::DELAY_REG_W
• dma::cfg_machine_st_delay::R
• dma::cfg_machine_st_delay::W
• dma::dma_ctrl::BRIDGE_XFR_PENDING_R
• dma::dma_ctrl::DMA_AHB_SEL_R
• dma::dma_ctrl::DMA_AHB_SEL_W
• dma::dma_ctrl::DMA_CTRL_SPEC
• dma::dma_ctrl::DMA_HREADY_R
• dma::dma_ctrl::DMA_HSEL_R
• dma::dma_ctrl::DMA_HTRANS_0_R
• dma::dma_ctrl::DMA_HTRANS_1_R
• dma::dma_ctrl::DMA_START_R
• dma::dma_ctrl::DMA_START_W
• dma::dma_ctrl::DMA_STOP_R
• dma::dma_ctrl::DMA_STOP_W
• dma::dma_ctrl::DMA_XFR_PENDING_R
• dma::dma_ctrl::R
• dma::dma_ctrl::W
• dma::dma_dest_addr::DMA_DEST_ADDR_R
• dma::dma_dest_addr::DMA_DEST_ADDR_SPEC
• dma::dma_dest_addr::DMA_DEST_ADDR_W
• dma::dma_dest_addr::R
• dma::dma_dest_addr::W
• dma::dma_intr::AHB_BRIDGE_FIFO_OVERFLOW_R
• dma::dma_intr::DMA_HERROR_R
• dma::dma_intr::DMA_INTR_SPEC
• dma::dma_intr::R
• dma::dma_intr::RX_DATA_AVAILABLE_R
• dma::dma_intr::SPIM_SSI_MST_INTR_R
• dma::dma_intr::SPIM_SSI_RXF_INTR_R
• dma::dma_intr::SPIM_SSI_RXO_INTR_R
• dma::dma_intr::SPIM_SSI_RXU_INTR_R
• dma::dma_intr::SPIM_SSI_TXE_INTR_R
• dma::dma_intr::SPIM_SSI_TXO_INTR_R
• dma::dma_intr_mask::AHB_BRIDGE_FIFO_OVERFLOW_MASK_W
• dma::dma_intr_mask::DMA_HERROR_MASK_R
• dma::dma_intr_mask::DMA_HERROR_MASK_W
• dma::dma_intr_mask::DMA_INTR_MASK_SPEC
• dma::dma_intr_mask::R
• dma::dma_intr_mask::RX_DATA_AVAILABLE_MASK_W
• dma::dma_intr_mask::W
• dma::dma_xfer_cnt::DMA_XFER_CNT_SPEC
• dma::dma_xfer_cnt::DMA_XFR_CNT_R
• dma::dma_xfer_cnt::DMA_XFR_CNT_W
• dma::dma_xfer_cnt::R
• dma::dma_xfer_cnt::W
• ext_regs_ffe::RegisterBlock
• ext_regs_ffe::addr::ADDR_R
• ext_regs_ffe::addr::ADDR_SPEC
• ext_regs_ffe::addr::ADDR_W
• ext_regs_ffe::addr::R
• ext_regs_ffe::addr::SLAVE_SEL_R
• ext_regs_ffe::addr::SLAVE_SEL_W
• ext_regs_ffe::addr::W
• ext_regs_ffe::cmd::CMD_SPEC
• ext_regs_ffe::cmd::RUN_FFE0_ONCE_W
• ext_regs_ffe::cmd::RUN_FFE1_W
• ext_regs_ffe::cmd::RUN_SM0_ONCE_W
• ext_regs_ffe::cmd::RUN_SM1_ONCE_W
• ext_regs_ffe::cmd::W
• ext_regs_ffe::csr::BUSY_R
• ext_regs_ffe::csr::CSR_SPEC
• ext_regs_ffe::csr::I2C0_MUX_SEL_R
• ext_regs_ffe::csr::I2C0_MUX_SEL_W
• ext_regs_ffe::csr::I2C1_MUX_SEL_W
• ext_regs_ffe::csr::MUX_WB_SM_W
• ext_regs_ffe::csr::OVFL_R
• ext_regs_ffe::csr::R
• ext_regs_ffe::csr::SPI0_MUX_SEL_W
• ext_regs_ffe::csr::W
• ext_regs_ffe::csr::WB_MS_START_R
• ext_regs_ffe::csr::WB_MS_START_W
• ext_regs_ffe::csr::WB_MS_WEN_R
• ext_regs_ffe::csr::WB_MS_WEN_W
• ext_regs_ffe::ffe0_bp_xpc_0::FFE0_BP_XPC_0_R
• ext_regs_ffe::ffe0_bp_xpc_0::FFE0_BP_XPC_0_SPEC
• ext_regs_ffe::ffe0_bp_xpc_0::FFE0_BP_XPC_0_W
• ext_regs_ffe::ffe0_bp_xpc_0::R
• ext_regs_ffe::ffe0_bp_xpc_0::W
• ext_regs_ffe::ffe0_bp_xpc_1::FFE0_BP_XPC_1_R
• ext_regs_ffe::ffe0_bp_xpc_1::FFE0_BP_XPC_1_SPEC
• ext_regs_ffe::ffe0_bp_xpc_1::FFE0_BP_XPC_1_W
• ext_regs_ffe::ffe0_bp_xpc_1::R
• ext_regs_ffe::ffe0_bp_xpc_1::W
• ext_regs_ffe::ffe0_bp_xpc_2::FFE0_BP_XPC_2_R
• ext_regs_ffe::ffe0_bp_xpc_2::FFE0_BP_XPC_2_SPEC
• ext_regs_ffe::ffe0_bp_xpc_2::FFE0_BP_XPC_2_W
• ext_regs_ffe::ffe0_bp_xpc_2::R
• ext_regs_ffe::ffe0_bp_xpc_2::W
• ext_regs_ffe::ffe0_bp_xpc_3::FFE0_BP_XPC_3_R
• ext_regs_ffe::ffe0_bp_xpc_3::FFE0_BP_XPC_3_SPEC
• ext_regs_ffe::ffe0_bp_xpc_3::FFE0_BP_XPC_3_W
• ext_regs_ffe::ffe0_bp_xpc_3::R
• ext_regs_ffe::ffe0_bp_xpc_3::W
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_BP_EN_R
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_BP_EN_W
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_BREAKPT_SWBRK_R
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_BREAKPT_SWBRK_W
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_BREAK_POINT_CFG_SPEC
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_FORCE_STOP_R
• ext_regs_ffe::ffe0_break_point_cfg::FFE0_FORCE_STOP_W
• ext_regs_ffe::ffe0_break_point_cfg::R
• ext_regs_ffe::ffe0_break_point_cfg::W
• ext_regs_ffe::ffe0_break_point_cont::FFE0_BP_CONT_R
• ext_regs_ffe::ffe0_break_point_cont::FFE0_BP_CONT_W
• ext_regs_ffe::ffe0_break_point_cont::FFE0_BREAK_POINT_CONT_SPEC
• ext_regs_ffe::ffe0_break_point_cont::R
• ext_regs_ffe::ffe0_break_point_cont::SM0_BP_CONT_R
• ext_regs_ffe::ffe0_break_point_cont::SM0_BP_CONT_W
• ext_regs_ffe::ffe0_break_point_cont::SM1_BP_CONT_R
• ext_regs_ffe::ffe0_break_point_cont::SM1_BP_CONT_W
• ext_regs_ffe::ffe0_break_point_cont::W
• ext_regs_ffe::ffe0_break_point_stat::FFE0_BP_MATCH_R
• ext_regs_ffe::ffe0_break_point_stat::FFE0_BREAK_POINT_STAT_SPEC
• ext_regs_ffe::ffe0_break_point_stat::R
• ext_regs_ffe::ffe0_break_point_stat::SM0_BP_MATCH_R
• ext_regs_ffe::ffe0_break_point_stat::SM1_BP_MATCH_R
• ext_regs_ffe::ffe_csr::FFE_CSR_SPEC
• ext_regs_ffe::ffe_csr::I2C0_DYN_PULLUP_EN_R
• ext_regs_ffe::ffe_csr::I2C0_DYN_PULLUP_EN_W
• ext_regs_ffe::ffe_csr::I2C1_DYN_PULLUP_EN_R
• ext_regs_ffe::ffe_csr::I2C1_DYN_PULLUP_EN_W
• ext_regs_ffe::ffe_csr::I2C2_DYN_PULLUP_EN_R
• ext_regs_ffe::ffe_csr::I2C2_DYN_PULLUP_EN_W
• ext_regs_ffe::ffe_csr::I2C2_SEL_R
• ext_regs_ffe::ffe_csr::I2C2_SEL_W
• ext_regs_ffe::ffe_csr::R
• ext_regs_ffe::ffe_csr::W
• ext_regs_ffe::ffe_dbg_combined::FFE0_DEBUG_R
• ext_regs_ffe::ffe_dbg_combined::FFE_DBG_COMBINED_SPEC
• ext_regs_ffe::ffe_dbg_combined::R
• ext_regs_ffe::ffe_dbg_combined::SM0_SM_DEBUG_R
• ext_regs_ffe::ffe_dbg_combined::SM1_SM_DEBUG_R
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_FFE0_R
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_FFE0_W
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_SM0_R
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_SM0_W
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_SM1_R
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_SM1_W
• ext_regs_ffe::ffe_debug_sel::FFE_DEBUG_SEL_SPEC
• ext_regs_ffe::ffe_debug_sel::FFE_TOP_DEBUG_SEL_R
• ext_regs_ffe::ffe_debug_sel::FFE_TOP_DEBUG_SEL_W
• ext_regs_ffe::ffe_debug_sel::R
• ext_regs_ffe::ffe_debug_sel::W
• ext_regs_ffe::interrupt::AHBM_BUS_ERROR_INTR_R
• ext_regs_ffe::interrupt::AHBM_BUS_ERROR_INTR_W
• ext_regs_ffe::interrupt::CM_2K_LP_INTR_R
• ext_regs_ffe::interrupt::CM_2K_LP_INTR_W
• ext_regs_ffe::interrupt::CM_8K_LP_INTR_R
• ext_regs_ffe::interrupt::CM_8K_LP_INTR_W
• ext_regs_ffe::interrupt::DM0_LP_INTR_R
• ext_regs_ffe::interrupt::DM0_LP_INTR_W
• ext_regs_ffe::interrupt::DM1_LP_INTR_R
• ext_regs_ffe::interrupt::DM1_LP_INTR_W
• ext_regs_ffe::interrupt::DM2_LP_INTR_R
• ext_regs_ffe::interrupt::DM2_LP_INTR_W
• ext_regs_ffe::interrupt::DM3_LP_INTR_R
• ext_regs_ffe::interrupt::DM3_LP_INTR_W
• ext_regs_ffe::interrupt::FFE0_BP_MATCH_INTR_R
• ext_regs_ffe::interrupt::FFE0_BP_MATCH_INTR_W
• ext_regs_ffe::interrupt::FFE0_SM0_OBERRUN_R
• ext_regs_ffe::interrupt::FFE0_SM0_OBERRUN_W
• ext_regs_ffe::interrupt::FFE0_SM1_OBERRUN_R
• ext_regs_ffe::interrupt::FFE0_SM1_OBERRUN_W
• ext_regs_ffe::interrupt::FFE1_OVERRUN_R
• ext_regs_ffe::interrupt::FFE1_OVERRUN_W
• ext_regs_ffe::interrupt::I2C_MS_0_ERROR_R
• ext_regs_ffe::interrupt::I2C_MS_0_ERROR_W
• ext_regs_ffe::interrupt::I2C_MS_1_ERROR_R
• ext_regs_ffe::interrupt::I2C_MS_1_ERROR_W
• ext_regs_ffe::interrupt::INTERRUPT_SPEC
• ext_regs_ffe::interrupt::PFE0_OVERRUN_R
• ext_regs_ffe::interrupt::PFE0_OVERRUN_W
• ext_regs_ffe::interrupt::PKFB_OVF_INTR_R
• ext_regs_ffe::interrupt::PKFB_OVF_INTR_W
• ext_regs_ffe::interrupt::R
• ext_regs_ffe::interrupt::SM0_BP_MATCH_INTR_R
• ext_regs_ffe::interrupt::SM0_BP_MATCH_INTR_W
• ext_regs_ffe::interrupt::SM0_LP_INTR_R
• ext_regs_ffe::interrupt::SM0_LP_INTR_W
• ext_regs_ffe::interrupt::SM1_BP_MATCH_INTR_R
• ext_regs_ffe::interrupt::SM1_BP_MATCH_INTR_W
• ext_regs_ffe::interrupt::SM1_LP_INTR_R
• ext_regs_ffe::interrupt::SM1_LP_INTR_W
• ext_regs_ffe::interrupt::SM_MULT_WR_INTR_R
• ext_regs_ffe::interrupt::SM_MULT_WR_INTR_W
• ext_regs_ffe::interrupt::SPI_MS_INTR_R
• ext_regs_ffe::interrupt::SPI_MS_INTR_W
• ext_regs_ffe::interrupt::W
• ext_regs_ffe::interrupt_en::AHBM_BUS_ERROR_INTR_EN_W
• ext_regs_ffe::interrupt_en::CM_2K_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::CM_8K_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::DM0_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::DM1_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::DM2_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::DM3_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::FFE0_BP_MATCH_INTR_EN_W
• ext_regs_ffe::interrupt_en::FFE0_OVERRUN_EN_W
• ext_regs_ffe::interrupt_en::FFE0_SM0_OVERRUN_EN_W
• ext_regs_ffe::interrupt_en::FFE0_SM1_OVERRUN_EN_W
• ext_regs_ffe::interrupt_en::FFE1_OVERRUN_EN_W
• ext_regs_ffe::interrupt_en::I2C_MS_0_ERROR_EN_W
• ext_regs_ffe::interrupt_en::I2C_MS_1_ERROR_EN_W
• ext_regs_ffe::interrupt_en::INTERRUPT_EN_SPEC
• ext_regs_ffe::interrupt_en::PKFB_OVF_EN_W
• ext_regs_ffe::interrupt_en::R
• ext_regs_ffe::interrupt_en::SM0_BP_MATCH_INTR_EN_W
• ext_regs_ffe::interrupt_en::SM0_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::SM1_BP_MATCH_INTR_EN_W
• ext_regs_ffe::interrupt_en::SM1_LP_INTR_EN_W
• ext_regs_ffe::interrupt_en::SM_MULT_WR_INTR_EN_R
• ext_regs_ffe::interrupt_en::SM_MULT_WR_INTR_EN_W
• ext_regs_ffe::interrupt_en::SPI_MS_INTR_EN_W
• ext_regs_ffe::interrupt_en::W
• ext_regs_ffe::mailbox_to_ffe0::MAILBOX_TO_FFE0_R
• ext_regs_ffe::mailbox_to_ffe0::MAILBOX_TO_FFE0_SPEC
• ext_regs_ffe::mailbox_to_ffe0::MAILBOX_TO_FFE0_W
• ext_regs_ffe::mailbox_to_ffe0::R
• ext_regs_ffe::mailbox_to_ffe0::W
• ext_regs_ffe::rdata::R
• ext_regs_ffe::rdata::RDATA_R
• ext_regs_ffe::rdata::RDATA_SPEC
• ext_regs_ffe::rdata::RDATA_W
• ext_regs_ffe::rdata::W
• ext_regs_ffe::sm0_debug_sel::R
• ext_regs_ffe::sm0_debug_sel::SM0_DEBUG_SEL_R
• ext_regs_ffe::sm0_debug_sel::SM0_DEBUG_SEL_SPEC
• ext_regs_ffe::sm0_debug_sel::SM0_DEBUG_SEL_W
• ext_regs_ffe::sm0_debug_sel::W
• ext_regs_ffe::sm0_runtime_addr_ctrl::R
• ext_regs_ffe::sm0_runtime_addr_ctrl::SM0_RUNTIME_ADDR_CTRL_R
• ext_regs_ffe::sm0_runtime_addr_ctrl::SM0_RUNTIME_ADDR_CTRL_SPEC
• ext_regs_ffe::sm0_runtime_addr_ctrl::SM0_RUNTIME_ADDR_CTRL_W
• ext_regs_ffe::sm0_runtime_addr_ctrl::W
• ext_regs_ffe::sm0_runtime_addr_cur::R
• ext_regs_ffe::sm0_runtime_addr_cur::SM0_RUNTIME_ADDR_CUR_R
• ext_regs_ffe::sm0_runtime_addr_cur::SM0_RUNTIME_ADDR_CUR_SPEC
• ext_regs_ffe::sm0_runtime_addr_cur::SM0_RUNTIME_ADDR_CUR_W
• ext_regs_ffe::sm0_runtime_addr_cur::W
• ext_regs_ffe::sm1_debug_sel::R
• ext_regs_ffe::sm1_debug_sel::SM1_DEBUG_SEL_R
• ext_regs_ffe::sm1_debug_sel::SM1_DEBUG_SEL_SPEC
• ext_regs_ffe::sm1_debug_sel::SM1_DEBUG_SEL_W
• ext_regs_ffe::sm1_debug_sel::W
• ext_regs_ffe::sm1_runtime_addr_ctrl::R
• ext_regs_ffe::sm1_runtime_addr_ctrl::SM1_RUNTIME_ADDR_CTRL_R
• ext_regs_ffe::sm1_runtime_addr_ctrl::SM1_RUNTIME_ADDR_CTRL_SPEC
• ext_regs_ffe::sm1_runtime_addr_ctrl::SM1_RUNTIME_ADDR_CTRL_W
• ext_regs_ffe::sm1_runtime_addr_ctrl::W
• ext_regs_ffe::sm1_runtime_addr_cur::R
• ext_regs_ffe::sm1_runtime_addr_cur::SM1_RUNTIME_ADDR_CUR_R
• ext_regs_ffe::sm1_runtime_addr_cur::SM1_RUNTIME_ADDR_CUR_SPEC
• ext_regs_ffe::sm1_runtime_addr_cur::SM1_RUNTIME_ADDR_CUR_W
• ext_regs_ffe::sm1_runtime_addr_cur::W
• ext_regs_ffe::sm_runtime_addr::R
• ext_regs_ffe::sm_runtime_addr::SM_RUNTIME_ADDR_R
• ext_regs_ffe::sm_runtime_addr::SM_RUNTIME_ADDR_SPEC
• ext_regs_ffe::sm_runtime_addr::SM_RUNTIME_ADDR_W
• ext_regs_ffe::sm_runtime_addr::W
• ext_regs_ffe::sram_test_reg1::CM2K_RME_R
• ext_regs_ffe::sram_test_reg1::CM2K_RME_W
• ext_regs_ffe::sram_test_reg1::CM2K_RM_R
• ext_regs_ffe::sram_test_reg1::CM2K_RM_W
• ext_regs_ffe::sram_test_reg1::CM2K_TEST1_R
• ext_regs_ffe::sram_test_reg1::CM2K_TEST1_W
• ext_regs_ffe::sram_test_reg1::CM8K_RME_R
• ext_regs_ffe::sram_test_reg1::CM8K_RME_W
• ext_regs_ffe::sram_test_reg1::CM8K_RM_R
• ext_regs_ffe::sram_test_reg1::CM8K_RM_W
• ext_regs_ffe::sram_test_reg1::CM8K_TEST1_R
• ext_regs_ffe::sram_test_reg1::CM8K_TEST1_W
• ext_regs_ffe::sram_test_reg1::DM0_RME_R
• ext_regs_ffe::sram_test_reg1::DM0_RME_W
• ext_regs_ffe::sram_test_reg1::DM0_RM_R
• ext_regs_ffe::sram_test_reg1::DM0_RM_W
• ext_regs_ffe::sram_test_reg1::DM0_TEST1_R
• ext_regs_ffe::sram_test_reg1::DM0_TEST1_W
• ext_regs_ffe::sram_test_reg1::DM1_RME_R
• ext_regs_ffe::sram_test_reg1::DM1_RME_W
• ext_regs_ffe::sram_test_reg1::DM1_TEST1_R
• ext_regs_ffe::sram_test_reg1::DM1_TEST1_W
• ext_regs_ffe::sram_test_reg1::R
• ext_regs_ffe::sram_test_reg1::SM0_RME_R
• ext_regs_ffe::sram_test_reg1::SM0_RME_W
• ext_regs_ffe::sram_test_reg1::SM0_RM_R
• ext_regs_ffe::sram_test_reg1::SM0_RM_W
• ext_regs_ffe::sram_test_reg1::SM0_TEST1_R
• ext_regs_ffe::sram_test_reg1::SM0_TEST1_W
• ext_regs_ffe::sram_test_reg1::SM1_RME_R
• ext_regs_ffe::sram_test_reg1::SM1_RME_W
• ext_regs_ffe::sram_test_reg1::SM1_RM_R
• ext_regs_ffe::sram_test_reg1::SM1_RM_W
• ext_regs_ffe::sram_test_reg1::SM1_TEST1_R
• ext_regs_ffe::sram_test_reg1::SM1_TEST1_W
• ext_regs_ffe::sram_test_reg1::SRAM_TEST_REG1_SPEC
• ext_regs_ffe::sram_test_reg1::W
• ext_regs_ffe::sram_test_reg2::DM1_RM_R
• ext_regs_ffe::sram_test_reg2::DM1_RM_W
• ext_regs_ffe::sram_test_reg2::DM2_RME_R
• ext_regs_ffe::sram_test_reg2::DM2_RME_W
• ext_regs_ffe::sram_test_reg2::DM2_RM_R
• ext_regs_ffe::sram_test_reg2::DM2_RM_W
• ext_regs_ffe::sram_test_reg2::DM2_TEST1_R
• ext_regs_ffe::sram_test_reg2::DM2_TEST1_W
• ext_regs_ffe::sram_test_reg2::DM3_RME_R
• ext_regs_ffe::sram_test_reg2::DM3_RME_W
• ext_regs_ffe::sram_test_reg2::DM3_RM_R
• ext_regs_ffe::sram_test_reg2::DM3_RM_W
• ext_regs_ffe::sram_test_reg2::DM3_TEST1_R
• ext_regs_ffe::sram_test_reg2::DM3_TEST1_W
• ext_regs_ffe::sram_test_reg2::R
• ext_regs_ffe::sram_test_reg2::SRAM_TEST_REG2_SPEC
• ext_regs_ffe::sram_test_reg2::W
• ext_regs_ffe::status::FFE0_BG_FLAG_R
• ext_regs_ffe::status::FFE0_BG_FLAG_W
• ext_regs_ffe::status::FFE0_BUSY_R
• ext_regs_ffe::status::FFE0_BUSY_W
• ext_regs_ffe::status::FFE0_FG_FLAG_R
• ext_regs_ffe::status::FFE0_FG_FLAG_W
• ext_regs_ffe::status::FFE1_BUSY_R
• ext_regs_ffe::status::FFE1_BUSY_W
• ext_regs_ffe::status::R
• ext_regs_ffe::status::SM0_BUSY_R
• ext_regs_ffe::status::SM1_BUSY_R
• ext_regs_ffe::status::STATUS_SPEC
• ext_regs_ffe::status::W
• ext_regs_ffe::wdata::R
• ext_regs_ffe::wdata::W
• ext_regs_ffe::wdata::WDATA_R
• ext_regs_ffe::wdata::WDATA_SPEC
• ext_regs_ffe::wdata::WDATA_W
• extm4regs::RegisterBlock
• extm4regs::a1_power_stat::A1_POWER_STAT_R
• extm4regs::a1_power_stat::A1_POWER_STAT_SPEC
• extm4regs::a1_power_stat::R
• extm4regs::config1::BRCHSTAT_R
• extm4regs::config1::CONFIG1_SPEC
• extm4regs::config1::CURRPRI_R
• extm4regs::config1::EXREQD_R
• extm4regs::config1::EXREQS_R
• extm4regs::config1::HALTED_R
• extm4regs::config1::MEMATTRD_R
• extm4regs::config1::MEMATTRI_R
• extm4regs::config1::MEMATTRS_R
• extm4regs::config1::R
• extm4regs::config2::BIGEND_R
• extm4regs::config2::BIGEND_W
• extm4regs::config2::CONFIG2_SPEC
• extm4regs::config2::DBGRESTART_R
• extm4regs::config2::DBGRESTART_W
• extm4regs::config2::DBG_DIS_R
• extm4regs::config2::DBG_DIS_W
• extm4regs::config2::EDBGEQ_R
• extm4regs::config2::EDBGEQ_W
• extm4regs::config2::EXRESPD_R
• extm4regs::config2::EXRESPD_W
• extm4regs::config2::EXRESPS_R
• extm4regs::config2::EXRESPS_W
• extm4regs::config2::FPU_DISABLE_R
• extm4regs::config2::FPU_DISABLE_W
• extm4regs::config2::MPU_DISABLE_R
• extm4regs::config2::MPU_DISABLE_W
• extm4regs::config2::R
• extm4regs::config2::W
• extm4regs::config_fp1::CONFIG_FP1_SPEC
• extm4regs::config_fp1::FPIDC_R
• extm4regs::config_fp1::FPIFC_R
• extm4regs::config_fp1::FPIOC_R
• extm4regs::config_fp1::FPIXC_R
• extm4regs::config_fp1::FPIZC_R
• extm4regs::config_fp1::FPOFC_R
• extm4regs::config_fp1::R
• extm4regs::config_fp2::CONFIG_FP2_SPEC
• extm4regs::config_fp2::FPIDC_EN_R
• extm4regs::config_fp2::FPIDC_EN_W
• extm4regs::config_fp2::FPIDZC_EN_R
• extm4regs::config_fp2::FPIDZC_EN_W
• extm4regs::config_fp2::FPIFC_EN_R
• extm4regs::config_fp2::FPIFC_EN_W
• extm4regs::config_fp2::FPIOC_EN_R
• extm4regs::config_fp2::FPIOC_EN_W
• extm4regs::config_fp2::FPIXC_EN_R
• extm4regs::config_fp2::FPIXC_EN_W
• extm4regs::config_fp2::R
• extm4regs::config_fp2::W
• extm4regs::config_mem1::CONFIG_MEM1_SPEC
• extm4regs::config_mem1::MEM0_32K_DST_R
• extm4regs::config_mem1::MEM0_32K_DST_W
• extm4regs::config_mem1::MEM0_32K_RM_R
• extm4regs::config_mem1::MEM0_32K_RM_W
• extm4regs::config_mem1::MEM1_32K_DST_R
• extm4regs::config_mem1::MEM1_32K_DST_W
• extm4regs::config_mem1::MEM1_32K_RM_R
• extm4regs::config_mem1::MEM1_32K_RM_W
• extm4regs::config_mem1::MEM2_32K_DST_R
• extm4regs::config_mem1::MEM2_32K_DST_W
• extm4regs::config_mem1::MEM2_32K_RM_R
• extm4regs::config_mem1::MEM2_32K_RM_W
• extm4regs::config_mem1::MEM3_32K_RM_R
• extm4regs::config_mem1::MEM3_32K_RM_W
• extm4regs::config_mem1::MEM4_32K_DST_R
• extm4regs::config_mem1::MEM4_32K_DST_W
• extm4regs::config_mem1::R
• extm4regs::config_mem1::W
• extm4regs::config_mem2::CONFIG_MEM2_SPEC
• extm4regs::config_mem2::MEM0_32K_DST_R
• extm4regs::config_mem2::MEM0_32K_DST_W
• extm4regs::config_mem2::MEM0_32K_RM_R
• extm4regs::config_mem2::MEM0_32K_RM_W
• extm4regs::config_mem2::MEM1_32K_DST_R
• extm4regs::config_mem2::MEM1_32K_DST_W
• extm4regs::config_mem2::MEM1_32K_RM_R
• extm4regs::config_mem2::MEM1_32K_RM_W
• extm4regs::config_mem2::MEM2_32K_DST_R
• extm4regs::config_mem2::MEM2_32K_DST_W
• extm4regs::config_mem2::MEM2_32K_RM_R
• extm4regs::config_mem2::MEM2_32K_RM_W
• extm4regs::config_mem2::MEM3_32K_RM_R
• extm4regs::config_mem2::MEM3_32K_RM_W
• extm4regs::config_mem2::MEM4_32K_DST_R
• extm4regs::config_mem2::MEM4_32K_DST_W
• extm4regs::config_mem2::R
• extm4regs::config_mem2::W
• extm4regs::config_mem3::CONFIG_MEM3_SPEC
• extm4regs::config_mem3::MEM0_32K_DST_R
• extm4regs::config_mem3::MEM0_32K_DST_W
• extm4regs::config_mem3::MEM0_32K_RM_R
• extm4regs::config_mem3::MEM0_32K_RM_W
• extm4regs::config_mem3::MEM1_32K_DST_R
• extm4regs::config_mem3::MEM1_32K_DST_W
• extm4regs::config_mem3::MEM1_32K_RM_R
• extm4regs::config_mem3::MEM1_32K_RM_W
• extm4regs::config_mem3::MEM2_32K_DST_R
• extm4regs::config_mem3::MEM2_32K_DST_W
• extm4regs::config_mem3::MEM2_32K_RM_R
• extm4regs::config_mem3::MEM2_32K_RM_W
• extm4regs::config_mem3::MEM3_32K_RM_R
• extm4regs::config_mem3::MEM3_32K_RM_W
• extm4regs::config_mem3::MEM4_32K_DST_R
• extm4regs::config_mem3::MEM4_32K_DST_W
• extm4regs::config_mem3::R
• extm4regs::config_mem3::W
• extm4regs::fb_ramfifo::FB_RAMFIFO_MODE_R
• extm4regs::fb_ramfifo::FB_RAMFIFO_MODE_W
• extm4regs::fb_ramfifo::FB_RAMFIFO_SPEC
• extm4regs::fb_ramfifo::R
• extm4regs::fb_ramfifo::W
• extm4regs::m4_mem_int::M4_MEM_INT_SPEC
• extm4regs::m4_mem_int::MEM1_INTR0_R
• extm4regs::m4_mem_int::MEM1_INTR0_W
• extm4regs::m4_mem_int::MEM1_INTR1_R
• extm4regs::m4_mem_int::MEM1_INTR1_W
• extm4regs::m4_mem_int::MEM1_INTR2_R
• extm4regs::m4_mem_int::MEM1_INTR2_W
• extm4regs::m4_mem_int::MEM1_INTR3_R
• extm4regs::m4_mem_int::MEM1_INTR3_W
• extm4regs::m4_mem_int::MEM2_INTR0_R
• extm4regs::m4_mem_int::MEM2_INTR0_W
• extm4regs::m4_mem_int::MEM2_INTR1_R
• extm4regs::m4_mem_int::MEM2_INTR1_W
• extm4regs::m4_mem_int::MEM2_INTR2_R
• extm4regs::m4_mem_int::MEM2_INTR2_W
• extm4regs::m4_mem_int::MEM2_INTR3_R
• extm4regs::m4_mem_int::MEM2_INTR3_W
• extm4regs::m4_mem_int::MEMO_INTR0_R
• extm4regs::m4_mem_int::MEMO_INTR0_W
• extm4regs::m4_mem_int::MEMO_INTR1_R
• extm4regs::m4_mem_int::MEMO_INTR1_W
• extm4regs::m4_mem_int::MEMO_INTR2_R
• extm4regs::m4_mem_int::MEMO_INTR2_W
• extm4regs::m4_mem_int::MEMO_INTR3_R
• extm4regs::m4_mem_int::MEMO_INTR3_W
• extm4regs::m4_mem_int::R
• extm4regs::m4_mem_int::W
• extm4regs::m4_mem_intr_en::M4_MEM_INTR_EN_SPEC
• extm4regs::m4_mem_intr_en::MEM0_INTR0_EN_R
• extm4regs::m4_mem_intr_en::MEM0_INTR0_EN_W
• extm4regs::m4_mem_intr_en::MEM0_INTR1_EN_R
• extm4regs::m4_mem_intr_en::MEM0_INTR1_EN_W
• extm4regs::m4_mem_intr_en::MEM0_INTR2_EN_R
• extm4regs::m4_mem_intr_en::MEM0_INTR2_EN_W
• extm4regs::m4_mem_intr_en::MEM0_INTR3_EN_R
• extm4regs::m4_mem_intr_en::MEM0_INTR3_EN_W
• extm4regs::m4_mem_intr_en::MEM1_INTR0_EN_R
• extm4regs::m4_mem_intr_en::MEM1_INTR0_EN_W
• extm4regs::m4_mem_intr_en::MEM1_INTR1_EN_R
• extm4regs::m4_mem_intr_en::MEM1_INTR1_EN_W
• extm4regs::m4_mem_intr_en::MEM1_INTR2_EN_R
• extm4regs::m4_mem_intr_en::MEM1_INTR2_EN_W
• extm4regs::m4_mem_intr_en::MEM1_INTR3_EN_R
• extm4regs::m4_mem_intr_en::MEM1_INTR3_EN_W
• extm4regs::m4_mem_intr_en::MEM2_INTR0_EN_R
• extm4regs::m4_mem_intr_en::MEM2_INTR0_EN_W
• extm4regs::m4_mem_intr_en::MEM2_INTR1_EN_R
• extm4regs::m4_mem_intr_en::MEM2_INTR1_EN_W
• extm4regs::m4_mem_intr_en::MEM2_INTR2_EN_R
• extm4regs::m4_mem_intr_en::MEM2_INTR2_EN_W
• extm4regs::m4_mem_intr_en::MEM2_INTR3_EN_R
• extm4regs::m4_mem_intr_en::MEM2_INTR3_EN_W
• extm4regs::m4_mem_intr_en::R
• extm4regs::m4_mem_intr_en::W
• extm4regs::systick_reg::R
• extm4regs::systick_reg::SYSTICK_NOREF_R
• extm4regs::systick_reg::SYSTICK_NOREF_W
• extm4regs::systick_reg::SYSTICK_REG_SPEC
• extm4regs::systick_reg::SYSTICK_SKEW_R
• extm4regs::systick_reg::SYSTICK_SKEW_W
• extm4regs::systick_reg::SYSTICK_TENMS_R
• extm4regs::systick_reg::SYSTICK_TENMS_W
• extm4regs::systick_reg::W
• extm4regs::to_intr::R
• extm4regs::to_intr::TO_INTR_AON_R
• extm4regs::to_intr::TO_INTR_AON_W
• extm4regs::to_intr::TO_INTR_SPEC
• extm4regs::to_intr::TO_INTR_TMR_MON_R
• extm4regs::to_intr::TO_INTR_TMR_MON_W
• extm4regs::to_intr::TO_INTR_UART_MON_R
• extm4regs::to_intr::TO_INTR_UART_MON_W
• extm4regs::to_intr::W
• extm4regs::to_intr_en::R
• extm4regs::to_intr_en::TO_INTR_AON_EN_R
• extm4regs::to_intr_en::TO_INTR_AON_EN_W
• extm4regs::to_intr_en::TO_INTR_EN_SPEC
• extm4regs::to_intr_en::TO_INTR_TMR_MON_EN_R
• extm4regs::to_intr_en::TO_INTR_TMR_MON_EN_W
• extm4regs::to_intr_en::TO_INTR_UART_MON_EN_R
• extm4regs::to_intr_en::TO_INTR_UART_MON_EN_W
• extm4regs::to_intr_en::W
• generic::FieldReader
• generic::R
• generic::Reg
• generic::W
• i2s_slave::RegisterBlock
• i2s_slave::i2s_comp_param_1::APB_DATA_WIDTH_R
• i2s_slave::i2s_comp_param_1::I2S_COMP_PARAM_1_SPEC
• i2s_slave::i2s_comp_param_1::I2S_FIFO_DEPTH_GLOBAL_R
• i2s_slave::i2s_comp_param_1::I2S_MODE_EN_R
• i2s_slave::i2s_comp_param_1::I2S_TRANSMITTER_BLOCK_R
• i2s_slave::i2s_comp_param_1::I2S_TX_CHANNELS_R
• i2s_slave::i2s_comp_param_1::I2S_TX_WORDSIZE_0_R
• i2s_slave::i2s_comp_param_1::R
• i2s_slave::i2s_comp_type::I2S_COMP_TYPE_R
• i2s_slave::i2s_comp_type::I2S_COMP_TYPE_SPEC
• i2s_slave::i2s_comp_type::R
• i2s_slave::i2s_comp_version::I2S_COMP_VERSION_R
• i2s_slave::i2s_comp_version::I2S_COMP_VERSION_SPEC
• i2s_slave::i2s_comp_version::R
• i2s_slave::i2s_stereo_en::I2S_STEREO_EN_R
• i2s_slave::i2s_stereo_en::I2S_STEREO_EN_SPEC
• i2s_slave::i2s_stereo_en::I2S_STEREO_EN_W
• i2s_slave::i2s_stereo_en::R
• i2s_slave::i2s_stereo_en::W
• i2s_slave::ier::IEN_R
• i2s_slave::ier::IEN_W
• i2s_slave::ier::IER_SPEC
• i2s_slave::ier::R
• i2s_slave::ier::W
• i2s_slave::imr0::IMR0_SPEC
• i2s_slave::imr0::R
• i2s_slave::imr0::RXFOM_R
• i2s_slave::imr0::RXFOM_W
• i2s_slave::imr0::TXFOM_W
• i2s_slave::imr0::W
• i2s_slave::isr0::ISR0_SPEC
• i2s_slave::isr0::R
• i2s_slave::isr0::TXFE_R
• i2s_slave::isr0::TXFO_R
• i2s_slave::iter::ITER_SPEC
• i2s_slave::iter::R
• i2s_slave::iter::TXEN_R
• i2s_slave::iter::TXEN_W
• i2s_slave::iter::W
• i2s_slave::lthr0::LTHR0_SPEC
• i2s_slave::lthr0::LTHR0_W
• i2s_slave::lthr0::W
• i2s_slave::rthr0::RTHR0_SPEC
• i2s_slave::rthr0::RTHR0_W
• i2s_slave::rthr0::W
• i2s_slave::rtxdma::RTXDMA_SPEC
• i2s_slave::rtxdma::RTXDMA_W
• i2s_slave::rtxdma::W
• i2s_slave::tcr0::R
• i2s_slave::tcr0::TCR0_SPEC
• i2s_slave::tcr0::W
• i2s_slave::tcr0::WLEN_R
• i2s_slave::tcr0::WLEN_W
• i2s_slave::ter0::R
• i2s_slave::ter0::TER0_SPEC
• i2s_slave::ter0::TXCHEN0_R
• i2s_slave::ter0::TXCHEN0_W
• i2s_slave::ter0::W
• i2s_slave::tfcr0::R
• i2s_slave::tfcr0::TFCR0_SPEC
• i2s_slave::tfcr0::TXCHET_R
• i2s_slave::tfcr0::TXCHET_W
• i2s_slave::tfcr0::W
• i2s_slave::tff0::TFF0_SPEC
• i2s_slave::tff0::TXCHFR_W
• i2s_slave::tff0::W
• i2s_slave::tor0::R
• i2s_slave::tor0::TOR0_SPEC
• i2s_slave::tor0::TXCHO_R
• i2s_slave::txdma::TXDMA_SPEC
• i2s_slave::txdma::TXDMA_W
• i2s_slave::txdma::W
• i2s_slave::txffr::TXFFR_SPEC
• i2s_slave::txffr::TXFFR_W
• i2s_slave::txffr::W
• intr_ctrl::RegisterBlock
• intr_ctrl::fb_intr::FB_0_INTR_R
• intr_ctrl::fb_intr::FB_0_INTR_W
• intr_ctrl::fb_intr::FB_1_INTR_R
• intr_ctrl::fb_intr::FB_1_INTR_W
• intr_ctrl::fb_intr::FB_2_INTR_R
• intr_ctrl::fb_intr::FB_2_INTR_W
• intr_ctrl::fb_intr::FB_3_INTR_R
• intr_ctrl::fb_intr::FB_3_INTR_W
• intr_ctrl::fb_intr::FB_INTR_SPEC
• intr_ctrl::fb_intr::R
• intr_ctrl::fb_intr::W
• intr_ctrl::fb_intr_en_ap::FB_0_INTR_EN_AP_R
• intr_ctrl::fb_intr_en_ap::FB_0_INTR_EN_AP_W
• intr_ctrl::fb_intr_en_ap::FB_1_INTR_EN_AP_W
• intr_ctrl::fb_intr_en_ap::FB_2_INTR_EN_AP_W
• intr_ctrl::fb_intr_en_ap::FB_3_INTR_EN_AP_W
• intr_ctrl::fb_intr_en_ap::FB_INTR_EN_AP_SPEC
• intr_ctrl::fb_intr_en_ap::R
• intr_ctrl::fb_intr_en_ap::W
• intr_ctrl::fb_intr_en_m4::FB_0_INTR_EN_M4_R
• intr_ctrl::fb_intr_en_m4::FB_0_INTR_EN_M4_W
• intr_ctrl::fb_intr_en_m4::FB_1_INTR_EN_M4_W
• intr_ctrl::fb_intr_en_m4::FB_2_INTR_EN_M4_W
• intr_ctrl::fb_intr_en_m4::FB_3_INTR_EN_M4_W
• intr_ctrl::fb_intr_en_m4::FB_INTR_EN_M4_SPEC
• intr_ctrl::fb_intr_en_m4::R
• intr_ctrl::fb_intr_en_m4::W
• intr_ctrl::fb_intr_pol::FB_0_INTR_POL_R
• intr_ctrl::fb_intr_pol::FB_0_INTR_POL_W
• intr_ctrl::fb_intr_pol::FB_1_INTR_POL_W
• intr_ctrl::fb_intr_pol::FB_2_INTR_POL_W
• intr_ctrl::fb_intr_pol::FB_3_INTR_POL_W
• intr_ctrl::fb_intr_pol::FB_INTR_POL_SPEC
• intr_ctrl::fb_intr_pol::R
• intr_ctrl::fb_intr_pol::W
• intr_ctrl::fb_intr_raw::FB_0_INTR_RAW_R
• intr_ctrl::fb_intr_raw::FB_1_INTR_RAW_R
• intr_ctrl::fb_intr_raw::FB_2_INTR_RAW_R
• intr_ctrl::fb_intr_raw::FB_3_INTR_RAW_R
• intr_ctrl::fb_intr_raw::FB_INTR_RAW_SPEC
• intr_ctrl::fb_intr_raw::R
• intr_ctrl::fb_intr_type::FB_0_INTR_TYPE_R
• intr_ctrl::fb_intr_type::FB_0_INTR_TYPE_W
• intr_ctrl::fb_intr_type::FB_1_INTR_TYPE_W
• intr_ctrl::fb_intr_type::FB_2_INTR_TYPE_W
• intr_ctrl::fb_intr_type::FB_3_INTR_TYPE_W
• intr_ctrl::fb_intr_type::FB_INTR_TYPE_SPEC
• intr_ctrl::fb_intr_type::R
• intr_ctrl::fb_intr_type::W
• intr_ctrl::ffe_intr::FFE0_0_INTR_R
• intr_ctrl::ffe_intr::FFE0_0_INTR_W
• intr_ctrl::ffe_intr::FFE0_1_INTR_R
• intr_ctrl::ffe_intr::FFE0_1_INTR_W
• intr_ctrl::ffe_intr::FFE0_2_INTR_R
• intr_ctrl::ffe_intr::FFE0_2_INTR_W
• intr_ctrl::ffe_intr::FFE0_3_INTR_R
• intr_ctrl::ffe_intr::FFE0_3_INTR_W
• intr_ctrl::ffe_intr::FFE0_4_INTR_R
• intr_ctrl::ffe_intr::FFE0_4_INTR_W
• intr_ctrl::ffe_intr::FFE0_5_INTR_R
• intr_ctrl::ffe_intr::FFE0_5_INTR_W
• intr_ctrl::ffe_intr::FFE0_6_INTR_R
• intr_ctrl::ffe_intr::FFE0_6_INTR_W
• intr_ctrl::ffe_intr::FFE0_7_INTR_R
• intr_ctrl::ffe_intr::FFE0_7_INTR_W
• intr_ctrl::ffe_intr::FFE_INTR_SPEC
• intr_ctrl::ffe_intr::R
• intr_ctrl::ffe_intr::W
• intr_ctrl::ffe_intr_en_ap::FFE0_0_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_0_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_1_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_2_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_3_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_4_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_5_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_6_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE0_7_INTR_EN_AP_W
• intr_ctrl::ffe_intr_en_ap::FFE_INTR_EN_AP_SPEC
• intr_ctrl::ffe_intr_en_ap::R
• intr_ctrl::ffe_intr_en_ap::W
• intr_ctrl::ffe_intr_en_m4::FFE0_0_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_0_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_1_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_2_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_3_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_4_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_5_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_6_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE0_7_INTR_EN_M4_W
• intr_ctrl::ffe_intr_en_m4::FFE_INTR_EN_M4_SPEC
• intr_ctrl::ffe_intr_en_m4::R
• intr_ctrl::ffe_intr_en_m4::W
• intr_ctrl::gpio_intr::GPIO_0_INTR_R
• intr_ctrl::gpio_intr::GPIO_0_INTR_W
• intr_ctrl::gpio_intr::GPIO_1_INTR_R
• intr_ctrl::gpio_intr::GPIO_1_INTR_W
• intr_ctrl::gpio_intr::GPIO_2_INTR_R
• intr_ctrl::gpio_intr::GPIO_2_INTR_W
• intr_ctrl::gpio_intr::GPIO_3_INTR_R
• intr_ctrl::gpio_intr::GPIO_3_INTR_W
• intr_ctrl::gpio_intr::GPIO_4_INTR_R
• intr_ctrl::gpio_intr::GPIO_4_INTR_W
• intr_ctrl::gpio_intr::GPIO_5_INTR_R
• intr_ctrl::gpio_intr::GPIO_5_INTR_W
• intr_ctrl::gpio_intr::GPIO_6_INTR_R
• intr_ctrl::gpio_intr::GPIO_6_INTR_W
• intr_ctrl::gpio_intr::GPIO_7_INTR_R
• intr_ctrl::gpio_intr::GPIO_7_INTR_W
• intr_ctrl::gpio_intr::GPIO_INTR_SPEC
• intr_ctrl::gpio_intr::R
• intr_ctrl::gpio_intr::W
• intr_ctrl::gpio_intr_en_ap::GPIO_0_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_0_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_1_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_2_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_3_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_4_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_5_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_6_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_7_INTR_EN_AP_W
• intr_ctrl::gpio_intr_en_ap::GPIO_INTR_EN_AP_SPEC
• intr_ctrl::gpio_intr_en_ap::R
• intr_ctrl::gpio_intr_en_ap::W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_0_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_0_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_1_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_2_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_3_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_4_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_5_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_6_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_7_INTR_EN_FFE0_W
• intr_ctrl::gpio_intr_en_ffe0::GPIO_INTR_EN_FFE0_SPEC
• intr_ctrl::gpio_intr_en_ffe0::R
• intr_ctrl::gpio_intr_en_ffe0::W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_0_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_0_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_1_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_2_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_3_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_4_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_5_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_6_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_7_INTR_EN_FFE1_W
• intr_ctrl::gpio_intr_en_ffe1::GPIO_INTR_EN_FFE1_SPEC
• intr_ctrl::gpio_intr_en_ffe1::R
• intr_ctrl::gpio_intr_en_ffe1::W
• intr_ctrl::gpio_intr_en_m4::GPIO_1_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_1_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_2_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_3_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_4_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_5_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_6_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_7_INTR_EN_M4_W
• intr_ctrl::gpio_intr_en_m4::GPIO_INTR_EN_M4_SPEC
• intr_ctrl::gpio_intr_en_m4::R
• intr_ctrl::gpio_intr_en_m4::W
• intr_ctrl::gpio_intr_pol::GPIO_0_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_0_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_1_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_2_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_3_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_4_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_5_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_6_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_7_INTR_POL_W
• intr_ctrl::gpio_intr_pol::GPIO_INTR_POL_SPEC
• intr_ctrl::gpio_intr_pol::R
• intr_ctrl::gpio_intr_pol::W
• intr_ctrl::gpio_intr_raw::GPIO_0_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_1_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_2_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_3_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_4_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_5_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_6_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_7_INTR_RAW_R
• intr_ctrl::gpio_intr_raw::GPIO_INTR_RAW_SPEC
• intr_ctrl::gpio_intr_raw::R
• intr_ctrl::gpio_intr_type::GPIO_1_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_2_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_3_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_4_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_5_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_6_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_7_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::GPIO_INTR_TYPE_SPEC
• intr_ctrl::gpio_intr_type::GPIO_O_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_O_INTR_TYPE_W
• intr_ctrl::gpio_intr_type::R
• intr_ctrl::gpio_intr_type::W
• intr_ctrl::m4_mem_aon_intr::M4_MEM_AON_INTR_SPEC
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR0_R
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR0_W
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR1_R
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR1_W
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR2_R
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR2_W
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR3_R
• intr_ctrl::m4_mem_aon_intr::MEM3_AON_INTR3_W
• intr_ctrl::m4_mem_aon_intr::R
• intr_ctrl::m4_mem_aon_intr::W
• intr_ctrl::m4_mem_aon_intr_en::M4_MEM_AON_INTR_EN_SPEC
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR0_EN_R
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR0_EN_W
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR1_EN_R
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR1_EN_W
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR2_EN_R
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR2_EN_W
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR3_EN_R
• intr_ctrl::m4_mem_aon_intr_en::MEM3_AON_INTR3_EN_W
• intr_ctrl::m4_mem_aon_intr_en::R
• intr_ctrl::m4_mem_aon_intr_en::W
• intr_ctrl::other_intr::ADC_INTR_R
• intr_ctrl::other_intr::ADC_INTR_W
• intr_ctrl::other_intr::APBOOT_EN_INTR_R
• intr_ctrl::other_intr::APBOOT_EN_INTR_W
• intr_ctrl::other_intr::CFG_DMA_INTR_R
• intr_ctrl::other_intr::CFG_DMA_INTR_W
• intr_ctrl::other_intr::DMIC_VOICE_DET_R
• intr_ctrl::other_intr::DMIC_VOICE_DET_W
• intr_ctrl::other_intr::FFE0_INTR_OTHERS_R
• intr_ctrl::other_intr::FFE0_INTR_OTHERS_W
• intr_ctrl::other_intr::FPU_INTR_R
• intr_ctrl::other_intr::FPU_INTR_W
• intr_ctrl::other_intr::LDO30_PG_INTR_R
• intr_ctrl::other_intr::LDO30_PG_INTR_W
• intr_ctrl::other_intr::LDO50_PG_INTR_R
• intr_ctrl::other_intr::LDO50_PG_INTR_W
• intr_ctrl::other_intr::LPSD_VOICE_DET_R
• intr_ctrl::other_intr::LPSD_VOICE_DET_W
• intr_ctrl::other_intr::M4_SRAM_INTR_R
• intr_ctrl::other_intr::M4_SRAM_INTR_W
• intr_ctrl::other_intr::OTHER_INTR_SPEC
• intr_ctrl::other_intr::PKFB_INTR_R
• intr_ctrl::other_intr::PKFB_INTR_W
• intr_ctrl::other_intr::PMU_TMR_INTR_R
• intr_ctrl::other_intr::PMU_TMR_INTR_W
• intr_ctrl::other_intr::R
• intr_ctrl::other_intr::RST_INTR_R
• intr_ctrl::other_intr::RST_INTR_W
• intr_ctrl::other_intr::RTC_INTR_R
• intr_ctrl::other_intr::RTC_INTR_W
• intr_ctrl::other_intr::SPI_MS_INTR_R
• intr_ctrl::other_intr::SPI_MS_INTR_W
• intr_ctrl::other_intr::TIMEOUT_INTR_R
• intr_ctrl::other_intr::TIMEOUT_INTR_W
• intr_ctrl::other_intr::TIMER_INTR_R
• intr_ctrl::other_intr::TIMER_INTR_W
• intr_ctrl::other_intr::UART_INTR_R
• intr_ctrl::other_intr::UART_INTR_W
• intr_ctrl::other_intr::W
• intr_ctrl::other_intr::WDOG_INTR_R
• intr_ctrl::other_intr::WDOG_INTR_W
• intr_ctrl::other_intr::WDOG_RST_R
• intr_ctrl::other_intr::WDOG_RST_W
• intr_ctrl::other_intr_en_ap::ADC_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::APBOOT_EN_AP_W
• intr_ctrl::other_intr_en_ap::CFG_DMA_DONE_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::DMIC_VOICE_DET_EN_AP_W
• intr_ctrl::other_intr_en_ap::FFE0_INTR_OTHERS_EN_AP_W
• intr_ctrl::other_intr_en_ap::FPU_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::LDO30_PG_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::LDO50_PG_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::LPSD_VOICE_DET_EN_AP_W
• intr_ctrl::other_intr_en_ap::M4_SRAM_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::M4_SRAM_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::OTHER_INTR_EN_AP_SPEC
• intr_ctrl::other_intr_en_ap::PKFB_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::PMU_TMR_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::R
• intr_ctrl::other_intr_en_ap::RST_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::RTC_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::SPI_MS_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::SRAM_128KB_TIMEOUT_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::TIMEOUT_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::TIMER_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::UART_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::W
• intr_ctrl::other_intr_en_ap::WDOG_INTR_EN_AP_W
• intr_ctrl::other_intr_en_ap::WDOG_RST_EN_AP_W
• intr_ctrl::other_intr_en_m4::ADC_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::APBOOT_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::CFG_DMA_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::DMIC_VOICE_DET_EN_M4_W
• intr_ctrl::other_intr_en_m4::FFE0_INTR_OTHERS_EN_M4_W
• intr_ctrl::other_intr_en_m4::FPU_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::LDO30_PG_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::LDO50_PG_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::LPSD_VOICE_DET_EN_M4_W
• intr_ctrl::other_intr_en_m4::M4_SRAM_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::M4_SRAM_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::OTHER_INTR_EN_M4_SPEC
• intr_ctrl::other_intr_en_m4::PKFB_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::PMU_TMR_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::R
• intr_ctrl::other_intr_en_m4::RST_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::RTC_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::SPI_MS_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::TIMEOUT_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::TIMER_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::UART_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::W
• intr_ctrl::other_intr_en_m4::WDOG_INTR_EN_M4_W
• intr_ctrl::other_intr_en_m4::WDOG_RST_EN_M4_W
• intr_ctrl::software_intr_1::R
• intr_ctrl::software_intr_1::SOFTWARE_INTR_1_SPEC
• intr_ctrl::software_intr_1::SW_INTR_1_R
• intr_ctrl::software_intr_1::SW_INTR_1_W
• intr_ctrl::software_intr_1::W
• intr_ctrl::software_intr_1_en_ap::R
• intr_ctrl::software_intr_1_en_ap::SOFTWARE_INTR_1_EN_AP_SPEC
• intr_ctrl::software_intr_1_en_ap::SW_INTR_1_EN_AP_R
• intr_ctrl::software_intr_1_en_ap::SW_INTR_1_EN_AP_W
• intr_ctrl::software_intr_1_en_ap::W
• intr_ctrl::software_intr_2::R
• intr_ctrl::software_intr_2::SOFTWARE_INTR_2_SPEC
• intr_ctrl::software_intr_2::SW_INTR_2_R
• intr_ctrl::software_intr_2::SW_INTR_2_W
• intr_ctrl::software_intr_2::W
• intr_ctrl::software_intr_2_en_ap::R
• intr_ctrl::software_intr_2_en_ap::SOFTWARE_INTR_2_EN_AP_SPEC
• intr_ctrl::software_intr_2_en_ap::SW_INTR_2_EN_AP_R
• intr_ctrl::software_intr_2_en_ap::SW_INTR_2_EN_AP_W
• intr_ctrl::software_intr_2_en_ap::W
• intr_ctrl::software_intr_en_m4::R
• intr_ctrl::software_intr_en_m4::SOFTWARE_INTR_EN_M4_SPEC
• intr_ctrl::software_intr_en_m4::SW_INTR_2_EN_M4_R
• intr_ctrl::software_intr_en_m4::SW_INTR_2_EN_M4_W
• intr_ctrl::software_intr_en_m4::W
• iomux::RegisterBlock
• iomux::fbio_sel_1::FBIO_SEL_1_SPEC
• iomux::fbio_sel_1::R
• iomux::fbio_sel_1::SEL_R
• iomux::fbio_sel_1::SEL_W
• iomux::fbio_sel_1::W
• iomux::fbio_sel_2::FBIO_SEL_2_SPEC
• iomux::fbio_sel_2::R
• iomux::fbio_sel_2::SEL_R
• iomux::fbio_sel_2::SEL_W
• iomux::fbio_sel_2::W
• iomux::i2s_clkin_sel::I2S_CLKIN_SEL_SPEC
• iomux::i2s_clkin_sel::R
• iomux::i2s_clkin_sel::SEL_R
• iomux::i2s_clkin_sel::SEL_W
• iomux::i2s_clkin_sel::W
• iomux::i2s_data_select::I2S_DATA_SELECT_SPEC
• iomux::i2s_data_select::R
• iomux::i2s_data_select::SEL_R
• iomux::i2s_data_select::SEL_W
• iomux::i2s_data_select::W
• iomux::i2s_wd_clkin_sel::I2S_WD_CLKIN_SEL_SPEC
• iomux::i2s_wd_clkin_sel::R
• iomux::i2s_wd_clkin_sel::SEL_R
• iomux::i2s_wd_clkin_sel::SEL_W
• iomux::i2s_wd_clkin_sel::W
• iomux::io_reg_sel::IO_REG_SEL_SPEC
• iomux::io_reg_sel::IO_SEL_0_R
• iomux::io_reg_sel::IO_SEL_0_W
• iomux::io_reg_sel::IO_SEL_1_R
• iomux::io_reg_sel::IO_SEL_1_W
• iomux::io_reg_sel::IO_SEL_2_R
• iomux::io_reg_sel::IO_SEL_2_W
• iomux::io_reg_sel::IO_SEL_3_R
• iomux::io_reg_sel::IO_SEL_3_W
• iomux::io_reg_sel::IO_SEL_4_R
• iomux::io_reg_sel::IO_SEL_4_W
• iomux::io_reg_sel::IO_SEL_5_R
• iomux::io_reg_sel::IO_SEL_5_W
• iomux::io_reg_sel::IO_SEL_6_R
• iomux::io_reg_sel::IO_SEL_6_W
• iomux::io_reg_sel::IO_SEL_7_R
• iomux::io_reg_sel::IO_SEL_7_W
• iomux::io_reg_sel::R
• iomux::io_reg_sel::W
• iomux::ir_da_sirin_sel::IRDA_SIRIN_SEL_SPEC
• iomux::ir_da_sirin_sel::R
• iomux::ir_da_sirin_sel::SEL_R
• iomux::ir_da_sirin_sel::SEL_W
• iomux::ir_da_sirin_sel::W
• iomux::nuartcts_sel::NUARTCTS_SEL_SPEC
• iomux::nuartcts_sel::R
• iomux::nuartcts_sel::SEL_R
• iomux::nuartcts_sel::SEL_W
• iomux::nuartcts_sel::W
• iomux::pad__ctrl::CTRL_SEL_R
• iomux::pad__ctrl::CTRL_SEL_W
• iomux::pad__ctrl::E_R
• iomux::pad__ctrl::E_W
• iomux::pad__ctrl::FUNC_SEL_R
• iomux::pad__ctrl::FUNC_SEL_W
• iomux::pad__ctrl::OEN_R
• iomux::pad__ctrl::OEN_W
• iomux::pad__ctrl::PAD__CTRL_SPEC
• iomux::pad__ctrl::P_R
• iomux::pad__ctrl::P_W
• iomux::pad__ctrl::R
• iomux::pad__ctrl::REN_R
• iomux::pad__ctrl::REN_W
• iomux::pad__ctrl::SMT_R
• iomux::pad__ctrl::SMT_W
• iomux::pad__ctrl::SR_R
• iomux::pad__ctrl::SR_W
• iomux::pad__ctrl::W
• iomux::pad__ctrl_ffe::CTRL_SEL_R
• iomux::pad__ctrl_ffe::CTRL_SEL_W
• iomux::pad__ctrl_ffe::E_R
• iomux::pad__ctrl_ffe::E_W
• iomux::pad__ctrl_ffe::FUNC_SEL_R
• iomux::pad__ctrl_ffe::FUNC_SEL_W
• iomux::pad__ctrl_ffe::OEN_R
• iomux::pad__ctrl_ffe::OEN_W
• iomux::pad__ctrl_ffe::PAD__CTRL_FFE_SPEC
• iomux::pad__ctrl_ffe::P_R
• iomux::pad__ctrl_ffe::P_W
• iomux::pad__ctrl_ffe::R
• iomux::pad__ctrl_ffe::REN_R
• iomux::pad__ctrl_ffe::REN_W
• iomux::pad__ctrl_ffe::SMT_R
• iomux::pad__ctrl_ffe::SMT_W
• iomux::pad__ctrl_ffe::SR_R
• iomux::pad__ctrl_ffe::SR_W
• iomux::pad__ctrl_ffe::W
• iomux::pdm_clkin_sel::PDM_CLKIN_SEL_SPEC
• iomux::pdm_clkin_sel::R
• iomux::pdm_clkin_sel::SEL_R
• iomux::pdm_clkin_sel::SEL_W
• iomux::pdm_clkin_sel::W
• iomux::pdm_data_sele::PDM_DATA_SELE_SPEC
• iomux::pdm_data_sele::R
• iomux::pdm_data_sele::SEL_R
• iomux::pdm_data_sele::SEL_W
• iomux::pdm_data_sele::W
• iomux::pdm_stat_in_sel::PDM_STAT_IN_SEL_SPEC
• iomux::pdm_stat_in_sel::R
• iomux::pdm_stat_in_sel::SEL_R
• iomux::pdm_stat_in_sel::SEL_W
• iomux::pdm_stat_in_sel::W
• iomux::s_intr_0_sel_reg::R
• iomux::s_intr_0_sel_reg::SEL_R
• iomux::s_intr_0_sel_reg::SEL_W
• iomux::s_intr_0_sel_reg::S_INTR_0_SEL_REG_SPEC
• iomux::s_intr_0_sel_reg::W
• iomux::s_intr_1_sel_reg::R
• iomux::s_intr_1_sel_reg::SEL_R
• iomux::s_intr_1_sel_reg::SEL_W
• iomux::s_intr_1_sel_reg::S_INTR_1_SEL_REG_SPEC
• iomux::s_intr_1_sel_reg::W
• iomux::s_intr_2_sel::R
• iomux::s_intr_2_sel::SEL_R
• iomux::s_intr_2_sel::SEL_W
• iomux::s_intr_2_sel::S_INTR_2_SEL_SPEC
• iomux::s_intr_2_sel::W
• iomux::s_intr_3_sel::R
• iomux::s_intr_3_sel::SEL_R
• iomux::s_intr_3_sel::SEL_W
• iomux::s_intr_3_sel::S_INTR_3_SEL_SPEC
• iomux::s_intr_3_sel::W
• iomux::s_intr_4_sel::R
• iomux::s_intr_4_sel::SEL_R
• iomux::s_intr_4_sel::SEL_W
• iomux::s_intr_4_sel::S_INTR_4_SEL_SPEC
• iomux::s_intr_4_sel::W
• iomux::s_intr_5_sel::R
• iomux::s_intr_5_sel::SEL_R
• iomux::s_intr_5_sel::SEL_W
• iomux::s_intr_5_sel::S_INTR_5_SEL_SPEC
• iomux::s_intr_5_sel::W
• iomux::s_intr_6_sel::R
• iomux::s_intr_6_sel::SEL_R
• iomux::s_intr_6_sel::SEL_W
• iomux::s_intr_6_sel::S_INTR_6_SEL_SPEC
• iomux::s_intr_6_sel::W
• iomux::s_intr_7_sel::R
• iomux::s_intr_7_sel::SEL_R
• iomux::s_intr_7_sel::SEL_W
• iomux::s_intr_7_sel::S_INTR_7_SEL_SPEC
• iomux::s_intr_7_sel::W
• iomux::scl0_sel_reg::R
• iomux::scl0_sel_reg::SCL0_SEL_REG_SPEC
• iomux::scl0_sel_reg::SEL_R
• iomux::scl0_sel_reg::SEL_W
• iomux::scl0_sel_reg::W
• iomux::scl1_sel_reg::R
• iomux::scl1_sel_reg::SCL1_SEL_REG_SPEC
• iomux::scl1_sel_reg::SEL_R
• iomux::scl1_sel_reg::SEL_W
• iomux::scl1_sel_reg::W
• iomux::scl2_sel_reg::R
• iomux::scl2_sel_reg::SCL2_SEL_REG_SPEC
• iomux::scl2_sel_reg::SEL_R
• iomux::scl2_sel_reg::SEL_W
• iomux::scl2_sel_reg::W
• iomux::sda0_sel_reg::R
• iomux::sda0_sel_reg::SDA0_SEL_REG_SPEC
• iomux::sda0_sel_reg::SEL_R
• iomux::sda0_sel_reg::SEL_W
• iomux::sda0_sel_reg::W
• iomux::sda1_sel_reg::R
• iomux::sda1_sel_reg::SDA1_SEL_REG_SPEC
• iomux::sda1_sel_reg::SEL_R
• iomux::sda1_sel_reg::SEL_W
• iomux::sda1_sel_reg::W
• iomux::sda2_sel_reg::R
• iomux::sda2_sel_reg::SDA2_SEL_REG_SPEC
• iomux::sda2_sel_reg::SEL_R
• iomux::sda2_sel_reg::SEL_W
• iomux::sda2_sel_reg::W
• iomux::spi_sensor_miso_sel::R
• iomux::spi_sensor_miso_sel::SEL_R
• iomux::spi_sensor_miso_sel::SEL_W
• iomux::spi_sensor_miso_sel::SPI_SENSOR_MISO_SEL_SPEC
• iomux::spi_sensor_miso_sel::W
• iomux::spi_sensor_mosi_sel::R
• iomux::spi_sensor_mosi_sel::SEL_R
• iomux::spi_sensor_mosi_sel::SEL_W
• iomux::spi_sensor_mosi_sel::SPI_SENSOR_MOSI_SEL_SPEC
• iomux::spi_sensor_mosi_sel::W
• iomux::spis_clk_sel::R
• iomux::spis_clk_sel::SEL_R
• iomux::spis_clk_sel::SEL_W
• iomux::spis_clk_sel::SPIS_CLK_SEL_SPEC
• iomux::spis_clk_sel::W
• iomux::spis_miso_sel::R
• iomux::spis_miso_sel::SEL_R
• iomux::spis_miso_sel::SEL_W
• iomux::spis_miso_sel::SPIS_MISO_SEL_SPEC
• iomux::spis_miso_sel::W
• iomux::spis_mosi_sel::R
• iomux::spis_mosi_sel::SEL_R
• iomux::spis_mosi_sel::SEL_W
• iomux::spis_mosi_sel::SPIS_MOSI_SEL_SPEC
• iomux::spis_mosi_sel::W
• iomux::spis_ssn_sel::R
• iomux::spis_ssn_sel::SEL_R
• iomux::spis_ssn_sel::SEL_W
• iomux::spis_ssn_sel::SPIS_SSN_SEL_SPEC
• iomux::spis_ssn_sel::W
• iomux::sw_clk_sel::R
• iomux::sw_clk_sel::SEL_R
• iomux::sw_clk_sel::SEL_W
• iomux::sw_clk_sel::SW_CLK_SEL_SPEC
• iomux::sw_clk_sel::W
• iomux::sw_io_sel::R
• iomux::sw_io_sel::SEL_R
• iomux::sw_io_sel::SEL_W
• iomux::sw_io_sel::SW_IO_SEL_SPEC
• iomux::sw_io_sel::W
• iomux::uart_rxd_sel::R
• iomux::uart_rxd_sel::SEL_R
• iomux::uart_rxd_sel::SEL_W
• iomux::uart_rxd_sel::UART_RXD_SEL_SPEC
• iomux::uart_rxd_sel::W
• misc::RegisterBlock
• misc::a0_dbg_mon_sel::A0_DBG_MON_SEL_SPEC
• misc::a0_dbg_mon_sel::A0_DEBUG_MON_SEL_R
• misc::a0_dbg_mon_sel::A0_DEBUG_MON_SEL_W
• misc::a0_dbg_mon_sel::R
• misc::a0_dbg_mon_sel::W
• misc::a0_pmu_dbg_mon_sel::A0_PMU_DBG_MON_SEL_SPEC
• misc::a0_pmu_dbg_mon_sel::A0_PMU_DEBUG_MON_SEL_R
• misc::a0_pmu_dbg_mon_sel::A0_PMU_DEBUG_MON_SEL_W
• misc::a0_pmu_dbg_mon_sel::R
• misc::a0_pmu_dbg_mon_sel::W
• misc::config_mem128_aon::CONFIG_MEM128_AON_SPEC
• misc::config_mem128_aon::MEM0_32K_DST_R
• misc::config_mem128_aon::MEM0_32K_DST_W
• misc::config_mem128_aon::MEM0_32K_RM_R
• misc::config_mem128_aon::MEM0_32K_RM_W
• misc::config_mem128_aon::MEM1_32K_DST_R
• misc::config_mem128_aon::MEM1_32K_DST_W
• misc::config_mem128_aon::MEM1_32K_RM_R
• misc::config_mem128_aon::MEM1_32K_RM_W
• misc::config_mem128_aon::MEM2_32K_DST_R
• misc::config_mem128_aon::MEM2_32K_DST_W
• misc::config_mem128_aon::MEM2_32K_RM_R
• misc::config_mem128_aon::MEM2_32K_RM_W
• misc::config_mem128_aon::MEM3_32K_DST_R
• misc::config_mem128_aon::MEM3_32K_RM_R
• misc::config_mem128_aon::MEM3_32K_RM_W
• misc::config_mem128_aon::R
• misc::config_mem128_aon::W
• misc::dbg_mon::DBG_MON_SPEC
• misc::dbg_mon::DEBUG_MON_R
• misc::dbg_mon::R
• misc::fb_device_id::FB_DEVICE_ID_SPEC
• misc::fb_device_id::ID_R
• misc::fb_device_id::R
• misc::io_input::IO_0_R
• misc::io_input::IO_1_R
• misc::io_input::IO_2_R
• misc::io_input::IO_3_R
• misc::io_input::IO_4_R
• misc::io_input::IO_5_R
• misc::io_input::IO_6_R
• misc::io_input::IO_7_R
• misc::io_input::IO_INPUT_SPEC
• misc::io_input::R
• misc::io_output::IO_0_R
• misc::io_output::IO_0_W
• misc::io_output::IO_1_R
• misc::io_output::IO_1_W
• misc::io_output::IO_2_R
• misc::io_output::IO_2_W
• misc::io_output::IO_3_R
• misc::io_output::IO_3_W
• misc::io_output::IO_4_R
• misc::io_output::IO_4_W
• misc::io_output::IO_5_R
• misc::io_output::IO_5_W
• misc::io_output::IO_6_R
• misc::io_output::IO_6_W
• misc::io_output::IO_7_R
• misc::io_output::IO_7_W
• misc::io_output::IO_OUTPUT_SPEC
• misc::io_output::R
• misc::io_output::W
• misc::lock_key_ctrl::LOCK_KEY_CTRL_SPEC
• misc::lock_key_ctrl::LOCK_KEY_EN_R
• misc::lock_key_ctrl::LOCK_KEY_EN_W
• misc::lock_key_ctrl::LOCK_KEY_W
• misc::lock_key_ctrl::R
• misc::lock_key_ctrl::W
• misc::pad_sel18::BOTTOM_BANK_2_R
• misc::pad_sel18::BOTTOM_BANK_2_W
• misc::pad_sel18::BOTTOM_BANK_3_R
• misc::pad_sel18::BOTTOM_BANK_3_W
• misc::pad_sel18::PAD_SEL18_SPEC
• misc::pad_sel18::R
• misc::pad_sel18::TOP_BANK_0_R
• misc::pad_sel18::TOP_BANK_0_W
• misc::pad_sel18::TOP_BANK_1_R
• misc::pad_sel18::TOP_BANK_1_W
• misc::pad_sel18::W
• misc::subsys_dbg_mon_sel::R
• misc::subsys_dbg_mon_sel::SUBSYS_DBG_MON_SEL_SPEC
• misc::subsys_dbg_mon_sel::SUBSYS_DEBUG_MON_SEL_R
• misc::subsys_dbg_mon_sel::SUBSYS_DEBUG_MON_SEL_W
• misc::subsys_dbg_mon_sel::W
• misc::sw_mb_1::R
• misc::sw_mb_1::SW_MB_1_SPEC
• misc::sw_mb_1::W
• misc::sw_mb_2::R
• misc::sw_mb_2::SW_MB_2_SPEC
• misc::sw_mb_2::W
• pkfb::RegisterBlock
• pkfb::pkfb_fifo_coll_intr::PF0_COLL_INTR_R
• pkfb::pkfb_fifo_coll_intr::PF0_COLL_INTR_W
• pkfb::pkfb_fifo_coll_intr::PF1_COLL_INTR_R
• pkfb::pkfb_fifo_coll_intr::PF1_COLL_INTR_W
• pkfb::pkfb_fifo_coll_intr::PF2_COLL_INTR_R
• pkfb::pkfb_fifo_coll_intr::PF2_COLL_INTR_W
• pkfb::pkfb_fifo_coll_intr::PF8K_COLL_INTR_R
• pkfb::pkfb_fifo_coll_intr::PF8K_COLL_INTR_W
• pkfb::pkfb_fifo_coll_intr::PKFB_FIFO_COLL_INTR_SPEC
• pkfb::pkfb_fifo_coll_intr::R
• pkfb::pkfb_fifo_coll_intr::W
• pkfb::pkfb_fifo_coll_intr_en::PF0_COLL_INTR_EN_R
• pkfb::pkfb_fifo_coll_intr_en::PF0_COLL_INTR_EN_W
• pkfb::pkfb_fifo_coll_intr_en::PF1_COLL_INTR_EN_W
• pkfb::pkfb_fifo_coll_intr_en::PF2_COLL_INTR_EN_W
• pkfb::pkfb_fifo_coll_intr_en::PF8K_COLL_INTR_EN_W
• pkfb::pkfb_fifo_coll_intr_en::PKFB_FIFO_COLL_INTR_EN_SPEC
• pkfb::pkfb_fifo_coll_intr_en::R
• pkfb::pkfb_fifo_coll_intr_en::W
• pkfb::pkfb_fifoctrl::PF0_EN_R
• pkfb::pkfb_fifoctrl::PF0_EN_W
• pkfb::pkfb_fifoctrl::PF0_FFE_SEL_R
• pkfb::pkfb_fifoctrl::PF0_FFE_SEL_W
• pkfb::pkfb_fifoctrl::PF0_POP_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF0_POP_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF0_POP_MUX_R
• pkfb::pkfb_fifoctrl::PF0_POP_MUX_W
• pkfb::pkfb_fifoctrl::PF0_PUSH_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF0_PUSH_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF0_PUSH_MUX_R
• pkfb::pkfb_fifoctrl::PF0_PUSH_MUX_W
• pkfb::pkfb_fifoctrl::PF1_EN_W
• pkfb::pkfb_fifoctrl::PF1_FFE_SEL_W
• pkfb::pkfb_fifoctrl::PF1_POP_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF1_POP_MUX_W
• pkfb::pkfb_fifoctrl::PF1_PUSH_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF1_PUSH_MUX_W
• pkfb::pkfb_fifoctrl::PF2_EN_W
• pkfb::pkfb_fifoctrl::PF2_FFE_SEL_W
• pkfb::pkfb_fifoctrl::PF2_POP_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF2_POP_MUX_W
• pkfb::pkfb_fifoctrl::PF2_PUSH_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF2_PUSH_MUX_W
• pkfb::pkfb_fifoctrl::PF8K_EN_W
• pkfb::pkfb_fifoctrl::PF8K_FFE_SEL_W
• pkfb::pkfb_fifoctrl::PF8K_POP_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF8K_POP_MUX_W
• pkfb::pkfb_fifoctrl::PF8K_PUSH_INT_MUX_W
• pkfb::pkfb_fifoctrl::PF8K_PUSH_MUX_W
• pkfb::pkfb_fifoctrl::PKFB_FIFOCTRL_SPEC
• pkfb::pkfb_fifoctrl::R
• pkfb::pkfb_fifoctrl::W
• pkfb::pkfb_fifosramctrl0::PF0_RMA_R
• pkfb::pkfb_fifosramctrl0::PF0_RMA_W
• pkfb::pkfb_fifosramctrl0::PF0_RMB_R
• pkfb::pkfb_fifosramctrl0::PF0_RMB_W
• pkfb::pkfb_fifosramctrl0::PF0_RMEA_R
• pkfb::pkfb_fifosramctrl0::PF0_RMEA_W
• pkfb::pkfb_fifosramctrl0::PF0_RMEB_R
• pkfb::pkfb_fifosramctrl0::PF0_RMEB_W
• pkfb::pkfb_fifosramctrl0::PF0_TEST1A_R
• pkfb::pkfb_fifosramctrl0::PF0_TEST1A_W
• pkfb::pkfb_fifosramctrl0::PF0_TEST1B_R
• pkfb::pkfb_fifosramctrl0::PF0_TEST1B_W
• pkfb::pkfb_fifosramctrl0::PF1_RMA_R
• pkfb::pkfb_fifosramctrl0::PF1_RMA_W
• pkfb::pkfb_fifosramctrl0::PF1_RMB_R
• pkfb::pkfb_fifosramctrl0::PF1_RMB_W
• pkfb::pkfb_fifosramctrl0::PF1_RMEA_R
• pkfb::pkfb_fifosramctrl0::PF1_RMEA_W
• pkfb::pkfb_fifosramctrl0::PF1_RMEB_R
• pkfb::pkfb_fifosramctrl0::PF1_RMEB_W
• pkfb::pkfb_fifosramctrl0::PF1_TEST1A_R
• pkfb::pkfb_fifosramctrl0::PF1_TEST1A_W
• pkfb::pkfb_fifosramctrl0::PF1_TEST1B_R
• pkfb::pkfb_fifosramctrl0::PF1_TEST1B_W
• pkfb::pkfb_fifosramctrl0::PKFB_FIFOSRAMCTRL0_SPEC
• pkfb::pkfb_fifosramctrl0::R
• pkfb::pkfb_fifosramctrl0::W
• pkfb::pkfb_fifosramctrl1::PF2_RMA_R
• pkfb::pkfb_fifosramctrl1::PF2_RMA_W
• pkfb::pkfb_fifosramctrl1::PF2_RMB_R
• pkfb::pkfb_fifosramctrl1::PF2_RMB_W
• pkfb::pkfb_fifosramctrl1::PF2_RMEA_R
• pkfb::pkfb_fifosramctrl1::PF2_RMEA_W
• pkfb::pkfb_fifosramctrl1::PF2_RMEB_R
• pkfb::pkfb_fifosramctrl1::PF2_RMEB_W
• pkfb::pkfb_fifosramctrl1::PF2_TEST1A_R
• pkfb::pkfb_fifosramctrl1::PF2_TEST1A_W
• pkfb::pkfb_fifosramctrl1::PF2_TEST1B_R
• pkfb::pkfb_fifosramctrl1::PF2_TEST1B_W
• pkfb::pkfb_fifosramctrl1::PF8K_RMA_R
• pkfb::pkfb_fifosramctrl1::PF8K_RMA_W
• pkfb::pkfb_fifosramctrl1::PF8K_RMB_R
• pkfb::pkfb_fifosramctrl1::PF8K_RMB_W
• pkfb::pkfb_fifosramctrl1::PF8K_RMEA_R
• pkfb::pkfb_fifosramctrl1::PF8K_RMEA_W
• pkfb::pkfb_fifosramctrl1::PF8K_RMEB_R
• pkfb::pkfb_fifosramctrl1::PF8K_RMEB_W
• pkfb::pkfb_fifosramctrl1::PF8K_TEST1A_R
• pkfb::pkfb_fifosramctrl1::PF8K_TEST1A_W
• pkfb::pkfb_fifosramctrl1::PF8K_TEST1B_R
• pkfb::pkfb_fifosramctrl1::PF8K_TEST1B_W
• pkfb::pkfb_fifosramctrl1::PKFB_FIFOSRAMCTRL1_SPEC
• pkfb::pkfb_fifosramctrl1::R
• pkfb::pkfb_fifosramctrl1::W
• pkfb::pkfb_fifostatus::PF0_POP_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF0_POP_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF0_POP_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF0_POP_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF0_POP_INT_UNDER_R
• pkfb::pkfb_fifostatus::PF0_POP_INT_UNDER_W
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_OVER_R
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_OVER_W
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF0_PUSH_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF0_SRAM_SLEEP_R
• pkfb::pkfb_fifostatus::PF0_SRAM_SLEEP_W
• pkfb::pkfb_fifostatus::PF1_POP_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF1_POP_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF1_POP_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF1_POP_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF1_POP_INT_UNDER_R
• pkfb::pkfb_fifostatus::PF1_POP_INT_UNDER_W
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_OVER_R
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_OVER_W
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF1_PUSH_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF1_SRAM_SLEEP_W
• pkfb::pkfb_fifostatus::PF2_POP_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF2_POP_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF2_POP_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF2_POP_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF2_POP_INT_UNDER_R
• pkfb::pkfb_fifostatus::PF2_POP_INT_UNDER_W
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_OVER_R
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_OVER_W
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF2_PUSH_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF2_SRAM_SLEEP_W
• pkfb::pkfb_fifostatus::PF8K_POP_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF8K_POP_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF8K_POP_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF8K_POP_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF8K_POP_INT_UNDER_R
• pkfb::pkfb_fifostatus::PF8K_POP_INT_UNDER_W
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_OVER_R
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_OVER_W
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_SLEEP_R
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_SLEEP_W
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_THRESH_R
• pkfb::pkfb_fifostatus::PF8K_PUSH_INT_THRESH_W
• pkfb::pkfb_fifostatus::PF8K_SRAM_SLEEP_W
• pkfb::pkfb_fifostatus::PKFB_FIFOSTATUS_SPEC
• pkfb::pkfb_fifostatus::R
• pkfb::pkfb_fifostatus::W
• pkfb::pkfb_pf0cnt::PF0_EMPTY_R
• pkfb::pkfb_pf0cnt::PF0_FULL_R
• pkfb::pkfb_pf0cnt::PF0_POP_CNT_R
• pkfb::pkfb_pf0cnt::PF0_PUSH_CNT_R
• pkfb::pkfb_pf0cnt::PKFB_PF0CNT_SPEC
• pkfb::pkfb_pf0cnt::R
• pkfb::pkfb_pf0data::PF0_DATA_REG_R
• pkfb::pkfb_pf0data::PF0_DATA_REG_W
• pkfb::pkfb_pf0data::PKFB_PF0DATA_SPEC
• pkfb::pkfb_pf0data::R
• pkfb::pkfb_pf0data::W
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_OV_R
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_OV_W
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_THRESH_W
• pkfb::pkfb_pf0popctl::PF0_POP_SLEEP_EN_R
• pkfb::pkfb_pf0popctl::PF0_POP_SLEEP_EN_W
• pkfb::pkfb_pf0popctl::PF0_POP_SLEEP_TYPE_R
• pkfb::pkfb_pf0popctl::PF0_POP_SLEEP_TYPE_W
• pkfb::pkfb_pf0popctl::PF0_POP_THRESH_R
• pkfb::pkfb_pf0popctl::PF0_POP_THRESH_W
• pkfb::pkfb_pf0popctl::PKFB_PF0POPCTL_SPEC
• pkfb::pkfb_pf0popctl::R
• pkfb::pkfb_pf0popctl::W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_OV_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_OV_W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_THRESH_W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_SLEEP_EN_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_SLEEP_EN_W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_SLEEP_TYPE_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_SLEEP_TYPE_W
• pkfb::pkfb_pf0pushctl::PF0_PUSH_THRESH_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_THRESH_W
• pkfb::pkfb_pf0pushctl::PKFB_PF0PUSHCTL_SPEC
• pkfb::pkfb_pf0pushctl::R
• pkfb::pkfb_pf0pushctl::W
• pkfb::pkfb_pf1cnt::PF1_EMPTY_R
• pkfb::pkfb_pf1cnt::PF1_FULL_R
• pkfb::pkfb_pf1cnt::PF1_POP_CNT_R
• pkfb::pkfb_pf1cnt::PF1_PUSH_CNT_R
• pkfb::pkfb_pf1cnt::PKFB_PF1CNT_SPEC
• pkfb::pkfb_pf1cnt::R
• pkfb::pkfb_pf1data::PF1_DATA_REG_R
• pkfb::pkfb_pf1data::PF1_DATA_REG_W
• pkfb::pkfb_pf1data::PKFB_PF1DATA_SPEC
• pkfb::pkfb_pf1data::R
• pkfb::pkfb_pf1data::W
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_OV_R
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_OV_W
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_THRESH_W
• pkfb::pkfb_pf1popctl::PF1_POP_SLEEP_EN_R
• pkfb::pkfb_pf1popctl::PF1_POP_SLEEP_EN_W
• pkfb::pkfb_pf1popctl::PF1_POP_SLEEP_TYPE_R
• pkfb::pkfb_pf1popctl::PF1_POP_SLEEP_TYPE_W
• pkfb::pkfb_pf1popctl::PF1_POP_THRESH_R
• pkfb::pkfb_pf1popctl::PF1_POP_THRESH_W
• pkfb::pkfb_pf1popctl::PKFB_PF1POPCTL_SPEC
• pkfb::pkfb_pf1popctl::R
• pkfb::pkfb_pf1popctl::W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_OV_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_OV_W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_THRESH_W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_SLEEP_EN_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_SLEEP_EN_W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_SLEEP_TYPE_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_SLEEP_TYPE_W
• pkfb::pkfb_pf1pushctl::PF1_PUSH_THRESH_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_THRESH_W
• pkfb::pkfb_pf1pushctl::PKFB_PF1PUSHCTL_SPEC
• pkfb::pkfb_pf1pushctl::R
• pkfb::pkfb_pf1pushctl::W
• pkfb::pkfb_pf2cnt::PF2_EMPTY_R
• pkfb::pkfb_pf2cnt::PF2_FULL_R
• pkfb::pkfb_pf2cnt::PF2_POP_CNT_R
• pkfb::pkfb_pf2cnt::PF2_PUSH_CNT_R
• pkfb::pkfb_pf2cnt::PKFB_PF2CNT_SPEC
• pkfb::pkfb_pf2cnt::R
• pkfb::pkfb_pf2data::PF2_DATA_REG_R
• pkfb::pkfb_pf2data::PF2_DATA_REG_W
• pkfb::pkfb_pf2data::PKFB_PF2DATA_SPEC
• pkfb::pkfb_pf2data::R
• pkfb::pkfb_pf2data::W
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_OV_R
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_OV_W
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_THRESH_W
• pkfb::pkfb_pf2popctl::PF2_POP_SLEEP_EN_R
• pkfb::pkfb_pf2popctl::PF2_POP_SLEEP_EN_W
• pkfb::pkfb_pf2popctl::PF2_POP_SLEEP_TYPE_R
• pkfb::pkfb_pf2popctl::PF2_POP_SLEEP_TYPE_W
• pkfb::pkfb_pf2popctl::PF2_POP_THRESH_R
• pkfb::pkfb_pf2popctl::PF2_POP_THRESH_W
• pkfb::pkfb_pf2popctl::PKFB_PF2POPCTL_SPEC
• pkfb::pkfb_pf2popctl::R
• pkfb::pkfb_pf2popctl::W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_OV_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_OV_W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_THRESH_W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_SLEEP_EN_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_SLEEP_EN_W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_SLEEP_TYPE_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_SLEEP_TYPE_W
• pkfb::pkfb_pf2pushctl::PF2_PUSH_THRESH_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_THRESH_W
• pkfb::pkfb_pf2pushctl::PKFB_PF2PUSHCTL_SPEC
• pkfb::pkfb_pf2pushctl::R
• pkfb::pkfb_pf2pushctl::W
• pkfb::pkfb_pf8k_data::PF8K_DATA_REG_R
• pkfb::pkfb_pf8k_data::PF8K_DATA_REG_W
• pkfb::pkfb_pf8k_data::PF8K_PUSH_EOP_W
• pkfb::pkfb_pf8k_data::PKFB_PF8KDATA_SPEC
• pkfb::pkfb_pf8k_data::R
• pkfb::pkfb_pf8k_data::W
• pkfb::pkfb_pf8kcnt::PF8K_EMPTY_R
• pkfb::pkfb_pf8kcnt::PF8K_FULL_R
• pkfb::pkfb_pf8kcnt::PF8K_POP_CNT_R
• pkfb::pkfb_pf8kcnt::PF8K_PUSH_CNT_R
• pkfb::pkfb_pf8kcnt::PKFB_PF8KCNT_SPEC
• pkfb::pkfb_pf8kcnt::R
• pkfb::pkfb_pf8kpopctl::PF8K_FIFO_PKT_MODE_R
• pkfb::pkfb_pf8kpopctl::PF8K_FIFO_PKT_MODE_W
• pkfb::pkfb_pf8kpopctl::PF8K_FIFO_RING_BUFF_MODE_R
• pkfb::pkfb_pf8kpopctl::PF8K_FIFO_RING_BUFF_MODE_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_OV_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_OV_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_THRESH_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_SLEEP_EN_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_SLEEP_EN_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_SLEEP_TYPE_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_SLEEP_TYPE_W
• pkfb::pkfb_pf8kpopctl::PF8K_POP_THRESH_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_THRESH_W
• pkfb::pkfb_pf8kpopctl::PKFB_PF8KPOPCTL_SPEC
• pkfb::pkfb_pf8kpopctl::R
• pkfb::pkfb_pf8kpopctl::W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_OV_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_OV_W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_SRAM_SLEEP_W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_THRESH_W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_SLEEP_EN_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_SLEEP_EN_W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_SLEEP_TYPE_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_SLEEP_TYPE_W
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_THRESH_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_THRESH_W
• pkfb::pkfb_pf8kpushctl::PKFB_PF8KPUSHCTL_SPEC
• pkfb::pkfb_pf8kpushctl::R
• pkfb::pkfb_pf8kpushctl::W
• pmu::RegisterBlock
• pmu::a1_pd_src_mask_n::A1_PD_SRC_MASK_N_SPEC
• pmu::a1_pd_src_mask_n::R
• pmu::a1_pwr_mode_cfg::A1_POWER_MODE_CFG_R
• pmu::a1_pwr_mode_cfg::A1_POWER_MODE_CFG_W
• pmu::a1_pwr_mode_cfg::A1_PWR_MODE_CFG_SPEC
• pmu::a1_pwr_mode_cfg::R
• pmu::a1_pwr_mode_cfg::W
• pmu::a1_status::A1_STATUS_SPEC
• pmu::a1_status::M4S0_ACTIVE_R
• pmu::a1_status::M4S0_CLOCK_GATING_R
• pmu::a1_status::M4S0_DEEP_SLEEP_R
• pmu::a1_status::M4S0_SHUT_DOWN_R
• pmu::a1_status::R
• pmu::a1_wu_src_mask_n::A1_WU_EVENT_MASK_M_R
• pmu::a1_wu_src_mask_n::A1_WU_EVENT_MASK_M_W
• pmu::a1_wu_src_mask_n::A1_WU_SRC_MASK_N_SPEC
• pmu::a1_wu_src_mask_n::R
• pmu::a1_wu_src_mask_n::W
• pmu::apreboot_status::APREBOOTSTATUS_R
• pmu::apreboot_status::APREBOOTSTATUS_SPEC
• pmu::apreboot_status::APREBOOTSTATUS_W
• pmu::apreboot_status::R
• pmu::apreboot_status::W
• pmu::audio_mem_cfg::AUDIO_MEM_CFG_SPEC
• pmu::audio_mem_cfg::R
• pmu::audio_mem_ctrl_0::AUDIO_MEM_CTRL_0_SPEC
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_0_R
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_0_W
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_1_W
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_2_W
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_0_W
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_1_W
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_2_W
• pmu::audio_mem_ctrl_0::R
• pmu::audio_mem_ctrl_0::W
• pmu::audio_mem_ctrl_1::AUDIO_MEM_CTRL_1_SPEC
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_0_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_0_W
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_1_W
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_2_W
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_0_W
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_1_W
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_2_W
• pmu::audio_mem_ctrl_1::R
• pmu::audio_mem_ctrl_1::W
• pmu::audio_sram_sw_wu::AUDIO_AD0_WU_R
• pmu::audio_sram_sw_wu::AUDIO_AD0_WU_W
• pmu::audio_sram_sw_wu::AUDIO_AD1_WU_W
• pmu::audio_sram_sw_wu::AUDIO_AD2_WU_W
• pmu::audio_sram_sw_wu::AUDIO_AD3_WU_W
• pmu::audio_sram_sw_wu::AUDIO_AD4_WU_W
• pmu::audio_sram_sw_wu::AUDIO_AD5_WU_W
• pmu::audio_sram_sw_wu::AUDIO_SRAM_SW_WU_SPEC
• pmu::audio_sram_sw_wu::R
• pmu::audio_sram_sw_wu::W
• pmu::audio_status::AD0_R
• pmu::audio_status::AD1_R
• pmu::audio_status::AD2_R
• pmu::audio_status::AD3_R
• pmu::audio_status::AD4_R
• pmu::audio_status::AD5_R
• pmu::audio_status::AUDIO_STATUS_SPEC
• pmu::audio_status::R
• pmu::audio_sw_pd::AUDIO_AD0_PD_R
• pmu::audio_sw_pd::AUDIO_AD0_PD_W
• pmu::audio_sw_pd::AUDIO_AD1_PD_W
• pmu::audio_sw_pd::AUDIO_AD2_PD_W
• pmu::audio_sw_pd::AUDIO_AD3_PD_W
• pmu::audio_sw_pd::AUDIO_AD4_PD_W
• pmu::audio_sw_pd::AUDIO_AD5_PD_W
• pmu::audio_sw_pd::AUDIO_SW_PD_SPEC
• pmu::audio_sw_pd::R
• pmu::audio_sw_pd::W
• pmu::audio_wu_src_mask_n::AD0_WU_EVENT_MASK_N_R
• pmu::audio_wu_src_mask_n::AD0_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AD1_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AD2_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AD3_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AD4_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AD5_WU_EVENT_MASK_N_W
• pmu::audio_wu_src_mask_n::AUDIO_WU_SRC_MASK_N_SPEC
• pmu::audio_wu_src_mask_n::R
• pmu::audio_wu_src_mask_n::W
• pmu::chip_sta_0::CHIP_STA_0_SPEC
• pmu::chip_sta_0::R
• pmu::chip_sta_1::CHIP_STA_1_SPEC
• pmu::chip_sta_1::CLOCK_BYPASS_CFG_R
• pmu::chip_sta_1::CODE_SOURCE_CFG_R
• pmu::chip_sta_1::DEBUG_PORT_CFG_R
• pmu::chip_sta_1::FB_0_R
• pmu::chip_sta_1::FB_1_R
• pmu::chip_sta_1::FB_2_R
• pmu::chip_sta_1::FB_3_R
• pmu::chip_sta_1::FFE0_BUSY_R
• pmu::chip_sta_1::R
• pmu::chip_sta_1::SWD_MODE_CFG_R
• pmu::ext_waking_up_src::EXT_WAKING_UP_SRC_SPEC
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_GPIO_INT_R
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_GPIO_INT_W
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_PMU_TIMER_R
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_PMU_TIMER_W
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_RESET_INTERRUPT_R
• pmu::ext_waking_up_src::EXT_WU_SOURCE_MASK_N_0_RESET_INTERRUPT_W
• pmu::ext_waking_up_src::R
• pmu::ext_waking_up_src::W
• pmu::fb_isolation::ENABLE_THE_FB_ISOLATION_R
• pmu::fb_isolation::ENABLE_THE_FB_ISOLATION_W
• pmu::fb_isolation::FB_ISOLATION_SPEC
• pmu::fb_isolation::R
• pmu::fb_isolation::W
• pmu::fb_pd_src_mask_n::FB_PD_SRC_MASK_N_SPEC
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_0_R
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_0_W
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_1_W
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_2_W
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_3_W
• pmu::fb_pd_src_mask_n::R
• pmu::fb_pd_src_mask_n::W
• pmu::fb_pwr_mode_cfg::FB_POWER_MODE_CFG_R
• pmu::fb_pwr_mode_cfg::FB_POWER_MODE_CFG_W
• pmu::fb_pwr_mode_cfg::FB_PWR_MODE_CFG_SPEC
• pmu::fb_pwr_mode_cfg::R
• pmu::fb_pwr_mode_cfg::W
• pmu::fb_status::FB_ACTIVE_R
• pmu::fb_status::FB_DEEP_SLEEP_R
• pmu::fb_status::FB_SHUT_DOWN_R
• pmu::fb_status::FB_STATUS_SPEC
• pmu::fb_status::R
• pmu::fb_wu_src_mask_n::FB_WU_SRC_MASK_N_SPEC
• pmu::fb_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_W
• pmu::fb_wu_src_mask_n::R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_0_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_0_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_1_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_2_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_3_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_4_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_5_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_6_INT_W
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_7_INT_W
• pmu::fb_wu_src_mask_n::W
• pmu::fbvlpmin_width::FBVLPMINWIDTH_R
• pmu::fbvlpmin_width::FBVLPMINWIDTH_SPEC
• pmu::fbvlpmin_width::FBVLPMINWIDTH_W
• pmu::fbvlpmin_width::R
• pmu::fbvlpmin_width::W
• pmu::ffe_fb_pf_sw_pd::FB_SOFTWARE_PD_W
• pmu::ffe_fb_pf_sw_pd::FFE_FB_PF_SW_PD_SPEC
• pmu::ffe_fb_pf_sw_pd::FFE_SOFTWARE_PD_R
• pmu::ffe_fb_pf_sw_pd::FFE_SOFTWARE_PD_W
• pmu::ffe_fb_pf_sw_pd::PF_SOFTWARE_PD_W
• pmu::ffe_fb_pf_sw_pd::R
• pmu::ffe_fb_pf_sw_pd::W
• pmu::ffe_fb_pf_sw_wu::FB_SOFTWARE_WU_W
• pmu::ffe_fb_pf_sw_wu::FFE_FB_PF_SW_WU_SPEC
• pmu::ffe_fb_pf_sw_wu::FFE_SOFTWARE_WU_R
• pmu::ffe_fb_pf_sw_wu::FFE_SOFTWARE_WU_W
• pmu::ffe_fb_pf_sw_wu::PF_SOFTWARE_WU_W
• pmu::ffe_fb_pf_sw_wu::R
• pmu::ffe_fb_pf_sw_wu::W
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_0_R
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_0_W
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_1_W
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_2_W
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_3_W
• pmu::ffe_mem_cfg::FFE_MEM_CFG_SPEC
• pmu::ffe_mem_cfg::GENERAL_PURPOSE_SFR_R
• pmu::ffe_mem_cfg::GENERAL_PURPOSE_SFR_W
• pmu::ffe_mem_cfg::R
• pmu::ffe_mem_cfg::W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM0_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM0_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM1_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM0_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM1_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM2_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM3_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM0_W
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM1_W
• pmu::ffe_mem_ctrl_0::FFE_MEM_CTRL_0_SPEC
• pmu::ffe_mem_ctrl_0::R
• pmu::ffe_mem_ctrl_0::W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM0_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM0_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM1_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM0_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM1_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM2_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM3_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM0_W
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM1_W
• pmu::ffe_mem_ctrl_1::FFE_MEM_CTRL_1_SPEC
• pmu::ffe_mem_ctrl_1::R
• pmu::ffe_mem_ctrl_1::W
• pmu::ffe_pd_src_mask_n::FFE_PD_EVENT_MASK_R
• pmu::ffe_pd_src_mask_n::FFE_PD_EVENT_MASK_W
• pmu::ffe_pd_src_mask_n::FFE_PD_SRC_MASK_N_SPEC
• pmu::ffe_pd_src_mask_n::R
• pmu::ffe_pd_src_mask_n::W
• pmu::ffe_pwr_mode_cfg::FFE_POWER_MODE_CFG_R
• pmu::ffe_pwr_mode_cfg::FFE_POWER_MODE_CFG_W
• pmu::ffe_pwr_mode_cfg::FFE_PWR_MODE_CFG_SPEC
• pmu::ffe_pwr_mode_cfg::R
• pmu::ffe_pwr_mode_cfg::W
• pmu::ffe_status::FFE_ACTIVE_R
• pmu::ffe_status::FFE_CLOCK_GATING_R
• pmu::ffe_status::FFE_DEEP_SLEEP_R
• pmu::ffe_status::FFE_SHUT_DOWN_R
• pmu::ffe_status::FFE_STATUS_SPEC
• pmu::ffe_status::R
• pmu::ffe_wu_src_mask_n::FFE_WU_SRC_MASK_N_SPEC
• pmu::ffe_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_R
• pmu::ffe_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_W
• pmu::ffe_wu_src_mask_n::R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_0_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_1_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_2_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_3_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_4_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_5_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_6_INT_W
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_7_INT_W
• pmu::ffe_wu_src_mask_n::W
• pmu::gen_purpose_0::AUDIO_SRAM_HW_DS_CFG_R
• pmu::gen_purpose_0::AUDIO_SRAM_HW_DS_CFG_W
• pmu::gen_purpose_0::FB_CFG_ENABLE_R
• pmu::gen_purpose_0::FB_CFG_ENABLE_W
• pmu::gen_purpose_0::GENERAL_PURPOSE_R
• pmu::gen_purpose_0::GENERAL_PURPOSE_W
• pmu::gen_purpose_0::GEN_PURPOSE_0_SPEC
• pmu::gen_purpose_0::R
• pmu::gen_purpose_0::W
• pmu::gen_purpose_1::GENERAL_PURPOSE_R
• pmu::gen_purpose_1::GENERAL_PURPOSE_W
• pmu::gen_purpose_1::GEN_PURPOSE_1_SPEC
• pmu::gen_purpose_1::KICKOFF_FFE_USE_INT_R
• pmu::gen_purpose_1::KICKOFF_FFE_USE_INT_W
• pmu::gen_purpose_1::LOW_POWER_MODE_FFE_R
• pmu::gen_purpose_1::LOW_POWER_MODE_FFE_W
• pmu::gen_purpose_1::LOW_POWER_MODE_M4_R
• pmu::gen_purpose_1::LOW_POWER_MODE_M4_W
• pmu::gen_purpose_1::LOW_POWER_MODE_R
• pmu::gen_purpose_1::LOW_POWER_MODE_W
• pmu::gen_purpose_1::R
• pmu::gen_purpose_1::W
• pmu::m4_mem_cfg::M4_MEM_CFG_SPEC
• pmu::m4_mem_cfg::R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_0_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_0_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_10_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_11_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_12_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_13_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_14_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_15_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_1_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_2_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_3_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_4_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_5_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_6_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_7_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_8_W
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_9_W
• pmu::m4_mem_ctrl_0::M4_MEM_CTRL_0_SPEC
• pmu::m4_mem_ctrl_0::R
• pmu::m4_mem_ctrl_0::W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_0_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_0_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_10_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_11_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_12_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_13_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_14_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_15_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_1_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_2_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_3_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_4_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_5_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_6_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_7_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_8_W
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_9_W
• pmu::m4_mem_ctrl_1::M4_MEM_CTRL_1_SPEC
• pmu::m4_mem_ctrl_1::R
• pmu::m4_mem_ctrl_1::W
• pmu::m4_mem_ctrl_pwr_0::M4_MEM_CTRL_PWR_0_SPEC
• pmu::m4_mem_ctrl_pwr_0::R
• pmu::m4_mem_ctrl_pwr_1::M4_MEM_CTRL_PWR_1_SPEC
• pmu::m4_mem_ctrl_pwr_1::R
• pmu::m4_mem_ctrl_pwr_2::M4_MEM_CTRL_PWR_2_SPEC
• pmu::m4_mem_ctrl_pwr_2::R
• pmu::m4_pd_src_maskk_n::M4_PD_SRC_MASKK_N_SPEC
• pmu::m4_pd_src_maskk_n::R
• pmu::m4_pwr_mode_cfg::M4_POWER_MODE_CFG_R
• pmu::m4_pwr_mode_cfg::M4_POWER_MODE_CFG_W
• pmu::m4_pwr_mode_cfg::M4_PWR_MODE_CFG_SPEC
• pmu::m4_pwr_mode_cfg::R
• pmu::m4_pwr_mode_cfg::W
• pmu::m4_sram_status::M4S0_R
• pmu::m4_sram_status::M4S10_R
• pmu::m4_sram_status::M4S11_R
• pmu::m4_sram_status::M4S12_R
• pmu::m4_sram_status::M4S13_R
• pmu::m4_sram_status::M4S14_R
• pmu::m4_sram_status::M4S15_R
• pmu::m4_sram_status::M4S1_R
• pmu::m4_sram_status::M4S2_R
• pmu::m4_sram_status::M4S3_R
• pmu::m4_sram_status::M4S4_R
• pmu::m4_sram_status::M4S5_R
• pmu::m4_sram_status::M4S6_R
• pmu::m4_sram_status::M4S7_R
• pmu::m4_sram_status::M4S8_R
• pmu::m4_sram_status::M4S9_R
• pmu::m4_sram_status::M4_SRAM_STATUS_SPEC
• pmu::m4_sram_status::R
• pmu::m4_sram_sw_pd::M4S0_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S0_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S10_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S11_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S12_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S13_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S14_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S15_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S1_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S2_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S3_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S4_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S5_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S6_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S7_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S8_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4S9_SOFTWARE_PD_W
• pmu::m4_sram_sw_pd::M4_SRAM_SW_PD_SPEC
• pmu::m4_sram_sw_pd::R
• pmu::m4_sram_sw_pd::W
• pmu::m4_sram_sw_wu::M4S0_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S0_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S10_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S11_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S12_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S13_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S14_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S15_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S1_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S2_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S3_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S4_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S5_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S6_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S7_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S8_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4S9_SOFTWARE_WU_W
• pmu::m4_sram_sw_wu::M4_SRAM_SW_WU_SPEC
• pmu::m4_sram_sw_wu::R
• pmu::m4_sram_sw_wu::W
• pmu::m4_status::M4_ACTIVE_R
• pmu::m4_status::M4_CLOCK_GATING_R
• pmu::m4_status::M4_DEEP_SLEEP_R
• pmu::m4_status::M4_SHUT_DOWN_R
• pmu::m4_status::M4_STATUS_SPEC
• pmu::m4_status::R
• pmu::m4_wu::M4_WU_SPEC
• pmu::m4_wu::R
• pmu::m4s0_pd_src_mask_n::M4S0_PD_EVENT_MASK_R
• pmu::m4s0_pd_src_mask_n::M4S0_PD_EVENT_MASK_W
• pmu::m4s0_pd_src_mask_n::M4S0_PD_SRC_MASK_N_SPEC
• pmu::m4s0_pd_src_mask_n::R
• pmu::m4s0_pd_src_mask_n::W
• pmu::m4s0_pwr_mode_cfg::M4S0_POWER_MODE_CFG_R
• pmu::m4s0_pwr_mode_cfg::M4S0_POWER_MODE_CFG_W
• pmu::m4s0_pwr_mode_cfg::M4S0_PWR_MODE_CFG_SPEC
• pmu::m4s0_pwr_mode_cfg::R
• pmu::m4s0_pwr_mode_cfg::W
• pmu::m4s0_sram_status::M4S0_ACTIVE_R
• pmu::m4s0_sram_status::M4S0_CLOCK_GATING_R
• pmu::m4s0_sram_status::M4S0_DEEP_SLEEP_R
• pmu::m4s0_sram_status::M4S0_SHUT_DOWN_R
• pmu::m4s0_sram_status::M4S0_SRAM_STATUS_SPEC
• pmu::m4s0_sram_status::R
• pmu::m4s0_wu_src_mask_n::M4S0_PD_EVENT_MASK_R
• pmu::m4s0_wu_src_mask_n::M4S0_PD_EVENT_MASK_W
• pmu::m4s0_wu_src_mask_n::M4S0_WU_SRC_MASK_N_SPEC
• pmu::m4s0_wu_src_mask_n::R
• pmu::m4s0_wu_src_mask_n::W
• pmu::m4sram_ssw_lpmf::M4SRAM_LPMF_R
• pmu::m4sram_ssw_lpmf::M4SRAM_LPMF_W
• pmu::m4sram_ssw_lpmf::M4SRAM_SSW_LPMF_SPEC
• pmu::m4sram_ssw_lpmf::R
• pmu::m4sram_ssw_lpmf::W
• pmu::m4sram_ssw_lpmh_mask_n::M4SRAM_LPMH_MASK_N_R
• pmu::m4sram_ssw_lpmh_mask_n::M4SRAM_LPMH_MASK_N_W
• pmu::m4sram_ssw_lpmh_mask_n::M4SRAM_SSW_LPMH_MASK_N_SPEC
• pmu::m4sram_ssw_lpmh_mask_n::R
• pmu::m4sram_ssw_lpmh_mask_n::W
• pmu::mem_pwr_dwn_ctrl::FFE_SRAM_PD_CFG_R
• pmu::mem_pwr_dwn_ctrl::FFE_SRAM_PD_CFG_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S0_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S0_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S10_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S10_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S11_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S11_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S1_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S1_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S2_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S2_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S3_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S3_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S4_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S4_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S5_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S5_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S6_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S6_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S7_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S7_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S8_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S8_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S9_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_0_M4S9_W
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_1_M4S12_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_1_M4S13_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_1_M4S14_R
• pmu::mem_pwr_dwn_ctrl::M4_SRAM_PD_CFG_1_M4S15_R
• pmu::mem_pwr_dwn_ctrl::MEM_PWR_DWN_CTRL_SPEC
• pmu::mem_pwr_dwn_ctrl::PF_SRAM_PD_CFG_R
• pmu::mem_pwr_dwn_ctrl::PF_SRAM_PD_CFG_W
• pmu::mem_pwr_dwn_ctrl::R
• pmu::mem_pwr_dwn_ctrl::SDMA_SRAM_PD_CFG_R
• pmu::mem_pwr_dwn_ctrl::SDMA_SRAM_PD_CFG_W
• pmu::mem_pwr_dwn_ctrl::W
• pmu::misc_por_0::M4_RST_RELEASE_R
• pmu::misc_por_0::M4_RST_RELEASE_W
• pmu::misc_por_0::MISC_POR_0_SPEC
• pmu::misc_por_0::R
• pmu::misc_por_0::W
• pmu::misc_por_1::CFG_FPD_ON_R
• pmu::misc_por_1::CFG_FPD_ON_W
• pmu::misc_por_1::MISC_POR_1_SPEC
• pmu::misc_por_1::R
• pmu::misc_por_1::SYS_RST_AS_INT_PW_R
• pmu::misc_por_1::SYS_RST_AS_INT_PW_W
• pmu::misc_por_1::SYS_RST_AS_INT_R
• pmu::misc_por_1::SYS_RST_AS_INT_W
• pmu::misc_por_1::SYS_RST_PULSE_EXT_R
• pmu::misc_por_1::SYS_RST_PULSE_EXT_W
• pmu::misc_por_1::W
• pmu::misc_por_2::AP_REBOOT_ENABLE_N_R
• pmu::misc_por_2::AP_REBOOT_ENABLE_N_W
• pmu::misc_por_2::MISC_POR_2_SPEC
• pmu::misc_por_2::R
• pmu::misc_por_2::SPI_REBOOT_ENABLE_N_R
• pmu::misc_por_2::SPI_REBOOT_ENABLE_N_W
• pmu::misc_por_2::W
• pmu::misc_por_3::MISC_POR_3_SPEC
• pmu::misc_por_3::R
• pmu::misc_por_3::SCRATCH_BYTE_0_R
• pmu::misc_por_3::SCRATCH_BYTE_0_W
• pmu::misc_por_3::SCRATCH_BYTE_1_R
• pmu::misc_por_3::SCRATCH_BYTE_1_W
• pmu::misc_por_3::W
• pmu::misc_status::I2S_R
• pmu::misc_status::MISC_STATUS_SPEC
• pmu::misc_status::R
• pmu::misc_sw_pd::A1_SOFTWARE_PD_W
• pmu::misc_sw_pd::GENERAL_PURPOSE_1_R
• pmu::misc_sw_pd::GENERAL_PURPOSE_1_W
• pmu::misc_sw_pd::GENERAL_PURPOSE_2_R
• pmu::misc_sw_pd::GENERAL_PURPOSE_2_W
• pmu::misc_sw_pd::GENERAL_PURPOSE_3_R
• pmu::misc_sw_pd::GENERAL_PURPOSE_3_W
• pmu::misc_sw_pd::I2S_SOFTWARE_PD_W
• pmu::misc_sw_pd::MISC_SW_PD_SPEC
• pmu::misc_sw_pd::R
• pmu::misc_sw_pd::SDMA_SOFTWARE_PD_R
• pmu::misc_sw_pd::SDMA_SOFTWARE_PD_W
• pmu::misc_sw_pd::W
• pmu::misc_sw_wu::A1_SOFTWARE_WU_W
• pmu::misc_sw_wu::GENERAL_PURPOSE_1_R
• pmu::misc_sw_wu::GENERAL_PURPOSE_1_W
• pmu::misc_sw_wu::GENERAL_PURPOSE_2_R
• pmu::misc_sw_wu::GENERAL_PURPOSE_2_W
• pmu::misc_sw_wu::GENERAL_PURPOSE_3_R
• pmu::misc_sw_wu::GENERAL_PURPOSE_3_W
• pmu::misc_sw_wu::I2S_SOFTWARE_WU_W
• pmu::misc_sw_wu::MISC_SW_WU_SPEC
• pmu::misc_sw_wu::R
• pmu::misc_sw_wu::SDMA_SOFTWARE_WU_R
• pmu::misc_sw_wu::SDMA_SOFTWARE_WU_W
• pmu::misc_sw_wu::W
• pmu::pdwu_timer_cfg::PDWU_TIMER_CFG_SPEC
• pmu::pdwu_timer_cfg::PDWU_TIMER_PERIOD_R
• pmu::pdwu_timer_cfg::PDWU_TIMER_PERIOD_W
• pmu::pdwu_timer_cfg::R
• pmu::pdwu_timer_cfg::W
• pmu::pf_mem_cfg::PF_MEM_CFG_SPEC
• pmu::pf_mem_cfg::R
• pmu::pf_mem_ctrl_0::PF_MEM_CTRL_0_SPEC
• pmu::pf_mem_ctrl_0::R
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_0_R
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_0_W
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_8K_W
• pmu::pf_mem_ctrl_1::PF_MEM_CTRL_1_SPEC
• pmu::pf_mem_ctrl_1::R
• pmu::pf_mem_ctrl_1::W
• pmu::pf_pd_src_mask_n::PF_PD_SRC_MASK_N_SPEC
• pmu::pf_pd_src_mask_n::R
• pmu::pf_pwr_mode_cfg::PF_POWER_MODE_CFG_R
• pmu::pf_pwr_mode_cfg::PF_POWER_MODE_CFG_W
• pmu::pf_pwr_mode_cfg::PF_PWR_MODE_CFG_SPEC
• pmu::pf_pwr_mode_cfg::R
• pmu::pf_pwr_mode_cfg::W
• pmu::pf_status::FB_ACTIVE_R
• pmu::pf_status::FB_CLOCK_GATING_R
• pmu::pf_status::FB_DEEP_SLEEP_R
• pmu::pf_status::FB_SHUT_DOWN_R
• pmu::pf_status::PF_STATUS_SPEC
• pmu::pf_status::R
• pmu::pf_wu_src_mask_n::PF_WU_SRC_MASK_N_SPEC
• pmu::pf_wu_src_mask_n::R
• pmu::pmu_stm_priority::PMU_STM_PRIORITY_R
• pmu::pmu_stm_priority::PMU_STM_PRIORITY_SPEC
• pmu::pmu_stm_priority::PMU_STM_PRIORITY_W
• pmu::pmu_stm_priority::R
• pmu::pmu_stm_priority::W
• pmu::pmu_timer_cfg_0::PMU_TIMER_CFG_0_SPEC
• pmu::pmu_timer_cfg_0::PMU_TIME_OUT_PERIOD_R
• pmu::pmu_timer_cfg_0::PMU_TIME_OUT_PERIOD_W
• pmu::pmu_timer_cfg_0::R
• pmu::pmu_timer_cfg_0::W
• pmu::pmu_timer_cfg_1::PMU_TIMER_CFG_1_SPEC
• pmu::pmu_timer_cfg_1::PMU_TIMER_ENABLE_R
• pmu::pmu_timer_cfg_1::PMU_TIMER_ENABLE_W
• pmu::pmu_timer_cfg_1::R
• pmu::pmu_timer_cfg_1::W
• pmu::pwr_dwn_sch::AUDIO_PD_R
• pmu::pwr_dwn_sch::AUDIO_PD_W
• pmu::pwr_dwn_sch::AUDIO_WU_R
• pmu::pwr_dwn_sch::AUDIO_WU_W
• pmu::pwr_dwn_sch::FFEFB_PD_R
• pmu::pwr_dwn_sch::FFEFB_PD_W
• pmu::pwr_dwn_sch::FFEFB_WU_R
• pmu::pwr_dwn_sch::FFEFB_WU_W
• pmu::pwr_dwn_sch::M4M4S0_PD_R
• pmu::pwr_dwn_sch::M4M4S0_PD_W
• pmu::pwr_dwn_sch::M4M4S0_WU_R
• pmu::pwr_dwn_sch::M4M4S0_WU_W
• pmu::pwr_dwn_sch::PWR_DWN_SCH_SPEC
• pmu::pwr_dwn_sch::R
• pmu::pwr_dwn_sch::SRAM_PD_R
• pmu::pwr_dwn_sch::SRAM_PD_W
• pmu::pwr_dwn_sch::SRAM_WU_R
• pmu::pwr_dwn_sch::SRAM_WU_W
• pmu::pwr_dwn_sch::W
• pmu::pwr_off_osc::POWER_OFF_OSC_R
• pmu::pwr_off_osc::POWER_OFF_OSC_W
• pmu::pwr_off_osc::PWR_OFF_OSC_SPEC
• pmu::pwr_off_osc::R
• pmu::pwr_off_osc::W
• pmu::rst_ctrl_0::R
• pmu::rst_ctrl_0::RST_CTRL_0_SPEC
• pmu::rst_ctrl_1::R
• pmu::rst_ctrl_1::RST_CTRL_1_SPEC
• pmu::sdma_mem_ctrl_0::R
• pmu::sdma_mem_ctrl_0::SDMA_MEM_CTRL_0_SPEC
• pmu::sdma_mem_ctrl_0::SDMA_SRAM_DS_R
• pmu::sdma_mem_ctrl_0::SDMA_SRAM_DS_W
• pmu::sdma_mem_ctrl_0::W
• pmu::sdma_mem_ctrl_1::R
• pmu::sdma_mem_ctrl_1::SDMA_MEM_CTRL_1_SPEC
• pmu::sdma_mem_ctrl_1::SDMA_SRAM_SD_R
• pmu::sdma_mem_ctrl_1::SDMA_SRAM_SD_W
• pmu::sdma_mem_ctrl_1::W
• pmu::sdma_pd_src_mask_n::R
• pmu::sdma_pd_src_mask_n::SDMA_PD_EVENT_R
• pmu::sdma_pd_src_mask_n::SDMA_PD_EVENT_W
• pmu::sdma_pd_src_mask_n::SDMA_PD_SRC_MASK_N_SPEC
• pmu::sdma_pd_src_mask_n::W
• pmu::sdma_power_mode_cfg::R
• pmu::sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_R
• pmu::sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_SPEC
• pmu::sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_W
• pmu::sdma_power_mode_cfg::W
• pmu::sdma_status::R
• pmu::sdma_status::SDMA_ACTIVE_R
• pmu::sdma_status::SDMA_CLOCK_GATING_R
• pmu::sdma_status::SDMA_DEEP_SLEEP_R
• pmu::sdma_status::SDMA_SHUT_DOWN_R
• pmu::sdma_status::SDMA_STATUS_SPEC
• pmu::sdma_wu_src_mask_n::R
• pmu::sdma_wu_src_mask_n::SDMA_WU_SRC_MASK_N_SPEC
• pmu::wic_ctrl::R
• pmu::wic_ctrl::W
• pmu::wic_ctrl::WIC_CTRL_SPEC
• pmu::wic_ctrl::WIC_ENABLE_R
• pmu::wic_ctrl::WIC_ENABLE_W
• pmu::wic_status::R
• pmu::wic_status::WIC_READY_R
• pmu::wic_status::WIC_STATUS_SPEC
• sdma::RegisterBlock
• sdma::alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_R
• sdma::alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_SPEC
• sdma::alt_ctrl_base_ptr::R
• sdma::chnl_enable_clr::CHNL_ENABLE_CLR_SPEC
• sdma::chnl_enable_clr::CHNL_ENABLE_CLR_W
• sdma::chnl_enable_clr::W
• sdma::chnl_enable_set::CHNL_ENABLE_SET_R
• sdma::chnl_enable_set::CHNL_ENABLE_SET_SPEC
• sdma::chnl_enable_set::CHNL_ENABLE_SET_W
• sdma::chnl_enable_set::R
• sdma::chnl_enable_set::W
• sdma::chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_SPEC
• sdma::chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_W
• sdma::chnl_pri_alt_clr::W
• sdma::chnl_pri_alt_set::CHNL_PRI_ALT_SET_R
• sdma::chnl_pri_alt_set::CHNL_PRI_ALT_SET_SPEC
• sdma::chnl_pri_alt_set::CHNL_PRI_ALT_SET_W
• sdma::chnl_pri_alt_set::R
• sdma::chnl_pri_alt_set::W
• sdma::chnl_priority_clear::CHNL_PRIORITY_CLEAR_R
• sdma::chnl_priority_clear::CHNL_PRIORITY_CLEAR_SPEC
• sdma::chnl_priority_clear::CHNL_PRIORITY_CLEAR_W
• sdma::chnl_priority_clear::R
• sdma::chnl_priority_clear::W
• sdma::chnl_priority_set::CHNL_PRIORITY_SET_SPEC
• sdma::chnl_priority_set::CHNL_PRIORITY_SET_W
• sdma::chnl_priority_set::W
• sdma::chnl_req_mask_clr::CHNL_REQ_MASK_CLER_W
• sdma::chnl_req_mask_clr::CHNL_REQ_MASK_CLR_SPEC
• sdma::chnl_req_mask_clr::W
• sdma::chnl_req_mask_set::CHNL_REQ_MASK_SET_R
• sdma::chnl_req_mask_set::CHNL_REQ_MASK_SET_SPEC
• sdma::chnl_req_mask_set::CHNL_REQ_MASK_SET_W
• sdma::chnl_req_mask_set::R
• sdma::chnl_req_mask_set::W
• sdma::chnl_sw_req::CHNL_SW_REQUEST_W
• sdma::chnl_sw_req::CHNL_SW_REQ_SPEC
• sdma::chnl_sw_req::W
• sdma::chnl_use_burst_set::CHNL_USE_BURST_SET_R
• sdma::chnl_use_burst_set::CHNL_USE_BURST_SET_SPEC
• sdma::chnl_use_burst_set::CHNL_USE_BURST_SET_W
• sdma::chnl_use_burst_set::R
• sdma::chnl_use_burst_set::W
• sdma::chnl_useburst_set::CHNL_USEBURST_CLR_W
• sdma::chnl_useburst_set::CHNL_USEBURST_SET_SPEC
• sdma::chnl_useburst_set::W
• sdma::ctrl_base_ptr::CTRL_BASE_PTR_R
• sdma::ctrl_base_ptr::CTRL_BASE_PTR_SPEC
• sdma::ctrl_base_ptr::CTRL_BASE_PTR_W
• sdma::ctrl_base_ptr::R
• sdma::ctrl_base_ptr::W
• sdma::dma_cfg::CHNL_PROT_CTRL_W
• sdma::dma_cfg::DMA_CFG_SPEC
• sdma::dma_cfg::MASTER_ENABLE_W
• sdma::dma_cfg::W
• sdma::dma_status::CHNLS_MINUS1_R
• sdma::dma_status::DMA_STATUS_SPEC
• sdma::dma_status::MASTER_ENABLE_R
• sdma::dma_status::R
• sdma::dma_status::STATE_R
• sdma::dma_status::TEST_STATUS_R
• sdma::dma_waitonreq_status::DMA_WAITONREQ_STATUS_R
• sdma::dma_waitonreq_status::DMA_WAITONREQ_STATUS_SPEC
• sdma::dma_waitonreq_status::R
• sdma::err_clr::ERR_CLR_R
• sdma::err_clr::ERR_CLR_SPEC
• sdma::err_clr::ERR_CLR_W
• sdma::err_clr::R
• sdma::err_clr::W
• sdma::pcell_id_0::PCELL_ID_0_R
• sdma::pcell_id_0::PCELL_ID_0_SPEC
• sdma::pcell_id_0::R
• sdma::pcell_id_1::PCELL_ID_1_R
• sdma::pcell_id_1::PCELL_ID_1_SPEC
• sdma::pcell_id_1::R
• sdma::pcell_id_2::PCELL_ID_2_R
• sdma::pcell_id_2::PCELL_ID_2_SPEC
• sdma::pcell_id_2::R
• sdma::pcell_id_3::PCELL_ID_3_R
• sdma::pcell_id_3::PCELL_ID_3_SPEC
• sdma::pcell_id_3::R
• sdma::periph_id_0::PERIPH_ID_0_R
• sdma::periph_id_0::PERIPH_ID_0_SPEC
• sdma::periph_id_0::R
• sdma::periph_id_1::PERIPH_ID_1_R
• sdma::periph_id_1::PERIPH_ID_1_SPEC
• sdma::periph_id_1::R
• sdma::periph_id_2::PERIPH_ID_2_R
• sdma::periph_id_2::PERIPH_ID_2_SPEC
• sdma::periph_id_2::R
• sdma::periph_id_3::PERIPH_ID_3_R
• sdma::periph_id_3::PERIPH_ID_3_SPEC
• sdma::periph_id_3::R
• sdma::periph_id_4::PERIPH_ID_4_R
• sdma::periph_id_4::PERIPH_ID_4_SPEC
• sdma::periph_id_4::R
• sdma_bridge::RegisterBlock
• sdma_bridge::dma_active_reg::DMA_ACTIVE_R
• sdma_bridge::dma_active_reg::DMA_ACTIVE_REG_SPEC
• sdma_bridge::dma_active_reg::R
• sdma_bridge::dma_req::DMA_REQ_SPEC
• sdma_bridge::dma_req::DMA_REQ_W
• sdma_bridge::dma_req::DMA_SREQ_W
• sdma_bridge::dma_req::W
• sdma_bridge::dma_waitonreq_reg::DMA_WAITONREQ_R
• sdma_bridge::dma_waitonreq_reg::DMA_WAITONREQ_REG_SPEC
• sdma_bridge::dma_waitonreq_reg::DMA_WAITONREQ_W
• sdma_bridge::dma_waitonreq_reg::R
• sdma_bridge::dma_waitonreq_reg::W
• sdma_bridge::sdma_pwrd_cnt::R
• sdma_bridge::sdma_pwrd_cnt::SDMA_PWRDN_CNT_R
• sdma_bridge::sdma_pwrd_cnt::SDMA_PWRDN_CNT_W
• sdma_bridge::sdma_pwrd_cnt::SDMA_PWRD_CNT_SPEC
• sdma_bridge::sdma_pwrd_cnt::W
• sdma_bridge::sdma_sram_ctl::R
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_CTL_SPEC
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_RME_R
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_RME_W
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_RM_R
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_RM_W
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_TEST1_R
• sdma_bridge::sdma_sram_ctl::SDMA_SRAM_TEST1_W
• sdma_bridge::sdma_sram_ctl::W
• sdma_sram::RegisterBlock
• sdma_sram::alt_chn_cfg_ch0::ALT_CHN_CFG_CH0_SPEC
• sdma_sram::alt_chn_cfg_ch0::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch0::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch0::DST_INC_R
• sdma_sram::alt_chn_cfg_ch0::DST_INC_W
• sdma_sram::alt_chn_cfg_ch0::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch0::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch0::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch0::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch0::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch0::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch0::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch0::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch0::R
• sdma_sram::alt_chn_cfg_ch0::R_POWER_R
• sdma_sram::alt_chn_cfg_ch0::R_POWER_W
• sdma_sram::alt_chn_cfg_ch0::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch0::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch0::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch0::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch0::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch0::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch0::W
• sdma_sram::alt_chn_cfg_ch10::ALT_CHN_CFG_CH10_SPEC
• sdma_sram::alt_chn_cfg_ch10::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch10::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch10::DST_INC_R
• sdma_sram::alt_chn_cfg_ch10::DST_INC_W
• sdma_sram::alt_chn_cfg_ch10::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch10::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch10::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch10::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch10::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch10::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch10::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch10::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch10::R
• sdma_sram::alt_chn_cfg_ch10::R_POWER_R
• sdma_sram::alt_chn_cfg_ch10::R_POWER_W
• sdma_sram::alt_chn_cfg_ch10::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch10::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch10::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch10::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch10::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch10::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch10::W
• sdma_sram::alt_chn_cfg_ch11::ALT_CHN_CFG_CH11_SPEC
• sdma_sram::alt_chn_cfg_ch11::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch11::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch11::DST_INC_R
• sdma_sram::alt_chn_cfg_ch11::DST_INC_W
• sdma_sram::alt_chn_cfg_ch11::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch11::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch11::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch11::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch11::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch11::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch11::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch11::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch11::R
• sdma_sram::alt_chn_cfg_ch11::R_POWER_R
• sdma_sram::alt_chn_cfg_ch11::R_POWER_W
• sdma_sram::alt_chn_cfg_ch11::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch11::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch11::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch11::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch11::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch11::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch11::W
• sdma_sram::alt_chn_cfg_ch12::ALT_CHN_CFG_CH12_SPEC
• sdma_sram::alt_chn_cfg_ch12::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch12::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch12::DST_INC_R
• sdma_sram::alt_chn_cfg_ch12::DST_INC_W
• sdma_sram::alt_chn_cfg_ch12::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch12::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch12::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch12::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch12::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch12::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch12::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch12::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch12::R
• sdma_sram::alt_chn_cfg_ch12::R_POWER_R
• sdma_sram::alt_chn_cfg_ch12::R_POWER_W
• sdma_sram::alt_chn_cfg_ch12::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch12::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch12::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch12::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch12::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch12::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch12::W
• sdma_sram::alt_chn_cfg_ch13::ALT_CHN_CFG_CH13_SPEC
• sdma_sram::alt_chn_cfg_ch13::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch13::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch13::DST_INC_R
• sdma_sram::alt_chn_cfg_ch13::DST_INC_W
• sdma_sram::alt_chn_cfg_ch13::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch13::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch13::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch13::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch13::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch13::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch13::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch13::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch13::R
• sdma_sram::alt_chn_cfg_ch13::R_POWER_R
• sdma_sram::alt_chn_cfg_ch13::R_POWER_W
• sdma_sram::alt_chn_cfg_ch13::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch13::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch13::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch13::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch13::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch13::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch13::W
• sdma_sram::alt_chn_cfg_ch14::ALT_CHN_CFG_CH14_SPEC
• sdma_sram::alt_chn_cfg_ch14::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch14::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch14::DST_INC_R
• sdma_sram::alt_chn_cfg_ch14::DST_INC_W
• sdma_sram::alt_chn_cfg_ch14::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch14::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch14::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch14::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch14::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch14::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch14::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch14::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch14::R
• sdma_sram::alt_chn_cfg_ch14::R_POWER_R
• sdma_sram::alt_chn_cfg_ch14::R_POWER_W
• sdma_sram::alt_chn_cfg_ch14::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch14::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch14::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch14::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch14::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch14::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch14::W
• sdma_sram::alt_chn_cfg_ch15::ALT_CHN_CFG_CH15_SPEC
• sdma_sram::alt_chn_cfg_ch15::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch15::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch15::DST_INC_R
• sdma_sram::alt_chn_cfg_ch15::DST_INC_W
• sdma_sram::alt_chn_cfg_ch15::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch15::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch15::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch15::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch15::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch15::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch15::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch15::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch15::R
• sdma_sram::alt_chn_cfg_ch15::R_POWER_R
• sdma_sram::alt_chn_cfg_ch15::R_POWER_W
• sdma_sram::alt_chn_cfg_ch15::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch15::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch15::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch15::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch15::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch15::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch15::W
• sdma_sram::alt_chn_cfg_ch1::ALT_CHN_CFG_CH1_SPEC
• sdma_sram::alt_chn_cfg_ch1::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch1::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch1::DST_INC_R
• sdma_sram::alt_chn_cfg_ch1::DST_INC_W
• sdma_sram::alt_chn_cfg_ch1::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch1::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch1::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch1::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch1::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch1::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch1::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch1::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch1::R
• sdma_sram::alt_chn_cfg_ch1::R_POWER_R
• sdma_sram::alt_chn_cfg_ch1::R_POWER_W
• sdma_sram::alt_chn_cfg_ch1::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch1::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch1::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch1::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch1::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch1::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch1::W
• sdma_sram::alt_chn_cfg_ch2::ALT_CHN_CFG_CH2_SPEC
• sdma_sram::alt_chn_cfg_ch2::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch2::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch2::DST_INC_R
• sdma_sram::alt_chn_cfg_ch2::DST_INC_W
• sdma_sram::alt_chn_cfg_ch2::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch2::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch2::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch2::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch2::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch2::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch2::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch2::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch2::R
• sdma_sram::alt_chn_cfg_ch2::R_POWER_R
• sdma_sram::alt_chn_cfg_ch2::R_POWER_W
• sdma_sram::alt_chn_cfg_ch2::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch2::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch2::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch2::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch2::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch2::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch2::W
• sdma_sram::alt_chn_cfg_ch3::ALT_CHN_CFG_CH3_SPEC
• sdma_sram::alt_chn_cfg_ch3::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch3::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch3::DST_INC_R
• sdma_sram::alt_chn_cfg_ch3::DST_INC_W
• sdma_sram::alt_chn_cfg_ch3::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch3::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch3::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch3::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch3::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch3::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch3::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch3::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch3::R
• sdma_sram::alt_chn_cfg_ch3::R_POWER_R
• sdma_sram::alt_chn_cfg_ch3::R_POWER_W
• sdma_sram::alt_chn_cfg_ch3::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch3::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch3::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch3::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch3::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch3::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch3::W
• sdma_sram::alt_chn_cfg_ch4::ALT_CHN_CFG_CH4_SPEC
• sdma_sram::alt_chn_cfg_ch4::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch4::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch4::DST_INC_R
• sdma_sram::alt_chn_cfg_ch4::DST_INC_W
• sdma_sram::alt_chn_cfg_ch4::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch4::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch4::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch4::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch4::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch4::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch4::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch4::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch4::R
• sdma_sram::alt_chn_cfg_ch4::R_POWER_R
• sdma_sram::alt_chn_cfg_ch4::R_POWER_W
• sdma_sram::alt_chn_cfg_ch4::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch4::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch4::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch4::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch4::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch4::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch4::W
• sdma_sram::alt_chn_cfg_ch5::ALT_CHN_CFG_CH5_SPEC
• sdma_sram::alt_chn_cfg_ch5::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch5::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch5::DST_INC_R
• sdma_sram::alt_chn_cfg_ch5::DST_INC_W
• sdma_sram::alt_chn_cfg_ch5::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch5::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch5::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch5::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch5::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch5::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch5::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch5::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch5::R
• sdma_sram::alt_chn_cfg_ch5::R_POWER_R
• sdma_sram::alt_chn_cfg_ch5::R_POWER_W
• sdma_sram::alt_chn_cfg_ch5::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch5::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch5::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch5::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch5::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch5::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch5::W
• sdma_sram::alt_chn_cfg_ch6::ALT_CHN_CFG_CH6_SPEC
• sdma_sram::alt_chn_cfg_ch6::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch6::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch6::DST_INC_R
• sdma_sram::alt_chn_cfg_ch6::DST_INC_W
• sdma_sram::alt_chn_cfg_ch6::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch6::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch6::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch6::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch6::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch6::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch6::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch6::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch6::R
• sdma_sram::alt_chn_cfg_ch6::R_POWER_R
• sdma_sram::alt_chn_cfg_ch6::R_POWER_W
• sdma_sram::alt_chn_cfg_ch6::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch6::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch6::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch6::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch6::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch6::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch6::W
• sdma_sram::alt_chn_cfg_ch7::ALT_CHN_CFG_CH7_SPEC
• sdma_sram::alt_chn_cfg_ch7::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch7::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch7::DST_INC_R
• sdma_sram::alt_chn_cfg_ch7::DST_INC_W
• sdma_sram::alt_chn_cfg_ch7::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch7::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch7::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch7::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch7::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch7::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch7::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch7::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch7::R
• sdma_sram::alt_chn_cfg_ch7::R_POWER_R
• sdma_sram::alt_chn_cfg_ch7::R_POWER_W
• sdma_sram::alt_chn_cfg_ch7::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch7::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch7::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch7::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch7::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch7::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch7::W
• sdma_sram::alt_chn_cfg_ch8::ALT_CHN_CFG_CH8_SPEC
• sdma_sram::alt_chn_cfg_ch8::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch8::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch8::DST_INC_R
• sdma_sram::alt_chn_cfg_ch8::DST_INC_W
• sdma_sram::alt_chn_cfg_ch8::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch8::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch8::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch8::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch8::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch8::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch8::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch8::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch8::R
• sdma_sram::alt_chn_cfg_ch8::R_POWER_R
• sdma_sram::alt_chn_cfg_ch8::R_POWER_W
• sdma_sram::alt_chn_cfg_ch8::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch8::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch8::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch8::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch8::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch8::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch8::W
• sdma_sram::alt_chn_cfg_ch9::ALT_CHN_CFG_CH9_SPEC
• sdma_sram::alt_chn_cfg_ch9::CYCLE_CTRL_R
• sdma_sram::alt_chn_cfg_ch9::CYCLE_CTRL_W
• sdma_sram::alt_chn_cfg_ch9::DST_INC_R
• sdma_sram::alt_chn_cfg_ch9::DST_INC_W
• sdma_sram::alt_chn_cfg_ch9::DST_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch9::DST_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch9::DST_SIZE_R
• sdma_sram::alt_chn_cfg_ch9::DST_SIZE_W
• sdma_sram::alt_chn_cfg_ch9::NEXT_USEBURST_R
• sdma_sram::alt_chn_cfg_ch9::NEXT_USEBURST_W
• sdma_sram::alt_chn_cfg_ch9::N_MINUS_1_R
• sdma_sram::alt_chn_cfg_ch9::N_MINUS_1_W
• sdma_sram::alt_chn_cfg_ch9::R
• sdma_sram::alt_chn_cfg_ch9::R_POWER_R
• sdma_sram::alt_chn_cfg_ch9::R_POWER_W
• sdma_sram::alt_chn_cfg_ch9::SRC_INC_R
• sdma_sram::alt_chn_cfg_ch9::SRC_INC_W
• sdma_sram::alt_chn_cfg_ch9::SRC_PROT_CTRL_R
• sdma_sram::alt_chn_cfg_ch9::SRC_PROT_CTRL_W
• sdma_sram::alt_chn_cfg_ch9::SRC_SIZE_R
• sdma_sram::alt_chn_cfg_ch9::SRC_SIZE_W
• sdma_sram::alt_chn_cfg_ch9::W
• sdma_sram::alt_dst_data_end_ptr_ch0::ALT_DST_DATA_END_PTR_CH0_R
• sdma_sram::alt_dst_data_end_ptr_ch0::ALT_DST_DATA_END_PTR_CH0_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch0::ALT_DST_DATA_END_PTR_CH0_W
• sdma_sram::alt_dst_data_end_ptr_ch0::R
• sdma_sram::alt_dst_data_end_ptr_ch0::W
• sdma_sram::alt_dst_data_end_ptr_ch10::ALT_DST_DATA_END_PTR_CH10_R
• sdma_sram::alt_dst_data_end_ptr_ch10::ALT_DST_DATA_END_PTR_CH10_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch10::ALT_DST_DATA_END_PTR_CH10_W
• sdma_sram::alt_dst_data_end_ptr_ch10::R
• sdma_sram::alt_dst_data_end_ptr_ch10::W
• sdma_sram::alt_dst_data_end_ptr_ch11::ALT_DST_DATA_END_PTR_CH11_R
• sdma_sram::alt_dst_data_end_ptr_ch11::ALT_DST_DATA_END_PTR_CH11_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch11::ALT_DST_DATA_END_PTR_CH11_W
• sdma_sram::alt_dst_data_end_ptr_ch11::R
• sdma_sram::alt_dst_data_end_ptr_ch11::W
• sdma_sram::alt_dst_data_end_ptr_ch12::ALT_DST_DATA_END_PTR_CH12_R
• sdma_sram::alt_dst_data_end_ptr_ch12::ALT_DST_DATA_END_PTR_CH12_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch12::ALT_DST_DATA_END_PTR_CH12_W
• sdma_sram::alt_dst_data_end_ptr_ch12::R
• sdma_sram::alt_dst_data_end_ptr_ch12::W
• sdma_sram::alt_dst_data_end_ptr_ch13::ALT_DST_DATA_END_PTR_CH13_R
• sdma_sram::alt_dst_data_end_ptr_ch13::ALT_DST_DATA_END_PTR_CH13_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch13::ALT_DST_DATA_END_PTR_CH13_W
• sdma_sram::alt_dst_data_end_ptr_ch13::R
• sdma_sram::alt_dst_data_end_ptr_ch13::W
• sdma_sram::alt_dst_data_end_ptr_ch14::ALT_DST_DATA_END_PTR_CH14_R
• sdma_sram::alt_dst_data_end_ptr_ch14::ALT_DST_DATA_END_PTR_CH14_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch14::ALT_DST_DATA_END_PTR_CH14_W
• sdma_sram::alt_dst_data_end_ptr_ch14::R
• sdma_sram::alt_dst_data_end_ptr_ch14::W
• sdma_sram::alt_dst_data_end_ptr_ch15::ALT_DST_DATA_END_PTR_CH15_R
• sdma_sram::alt_dst_data_end_ptr_ch15::ALT_DST_DATA_END_PTR_CH15_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch15::ALT_DST_DATA_END_PTR_CH15_W
• sdma_sram::alt_dst_data_end_ptr_ch15::R
• sdma_sram::alt_dst_data_end_ptr_ch15::W
• sdma_sram::alt_dst_data_end_ptr_ch1::ALT_DST_DATA_END_PTR_CH1_R
• sdma_sram::alt_dst_data_end_ptr_ch1::ALT_DST_DATA_END_PTR_CH1_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch1::ALT_DST_DATA_END_PTR_CH1_W
• sdma_sram::alt_dst_data_end_ptr_ch1::R
• sdma_sram::alt_dst_data_end_ptr_ch1::W
• sdma_sram::alt_dst_data_end_ptr_ch2::ALT_DST_DATA_END_PTR_CH2_R
• sdma_sram::alt_dst_data_end_ptr_ch2::ALT_DST_DATA_END_PTR_CH2_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch2::ALT_DST_DATA_END_PTR_CH2_W
• sdma_sram::alt_dst_data_end_ptr_ch2::R
• sdma_sram::alt_dst_data_end_ptr_ch2::W
• sdma_sram::alt_dst_data_end_ptr_ch3::ALT_DST_DATA_END_PTR_CH3_R
• sdma_sram::alt_dst_data_end_ptr_ch3::ALT_DST_DATA_END_PTR_CH3_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch3::ALT_DST_DATA_END_PTR_CH3_W
• sdma_sram::alt_dst_data_end_ptr_ch3::R
• sdma_sram::alt_dst_data_end_ptr_ch3::W
• sdma_sram::alt_dst_data_end_ptr_ch4::ALT_DST_DATA_END_PTR_CH4_R
• sdma_sram::alt_dst_data_end_ptr_ch4::ALT_DST_DATA_END_PTR_CH4_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch4::ALT_DST_DATA_END_PTR_CH4_W
• sdma_sram::alt_dst_data_end_ptr_ch4::R
• sdma_sram::alt_dst_data_end_ptr_ch4::W
• sdma_sram::alt_dst_data_end_ptr_ch5::ALT_DST_DATA_END_PTR_CH5_R
• sdma_sram::alt_dst_data_end_ptr_ch5::ALT_DST_DATA_END_PTR_CH5_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch5::ALT_DST_DATA_END_PTR_CH5_W
• sdma_sram::alt_dst_data_end_ptr_ch5::R
• sdma_sram::alt_dst_data_end_ptr_ch5::W
• sdma_sram::alt_dst_data_end_ptr_ch6::ALT_DST_DATA_END_PTR_CH6_R
• sdma_sram::alt_dst_data_end_ptr_ch6::ALT_DST_DATA_END_PTR_CH6_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch6::ALT_DST_DATA_END_PTR_CH6_W
• sdma_sram::alt_dst_data_end_ptr_ch6::R
• sdma_sram::alt_dst_data_end_ptr_ch6::W
• sdma_sram::alt_dst_data_end_ptr_ch7::ALT_DST_DATA_END_PTR_CH7_R
• sdma_sram::alt_dst_data_end_ptr_ch7::ALT_DST_DATA_END_PTR_CH7_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch7::ALT_DST_DATA_END_PTR_CH7_W
• sdma_sram::alt_dst_data_end_ptr_ch7::R
• sdma_sram::alt_dst_data_end_ptr_ch7::W
• sdma_sram::alt_dst_data_end_ptr_ch8::ALT_DST_DATA_END_PTR_CH8_R
• sdma_sram::alt_dst_data_end_ptr_ch8::ALT_DST_DATA_END_PTR_CH8_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch8::ALT_DST_DATA_END_PTR_CH8_W
• sdma_sram::alt_dst_data_end_ptr_ch8::R
• sdma_sram::alt_dst_data_end_ptr_ch8::W
• sdma_sram::alt_dst_data_end_ptr_ch9::ALT_DST_DATA_END_PTR_CH9_R
• sdma_sram::alt_dst_data_end_ptr_ch9::ALT_DST_DATA_END_PTR_CH9_SPEC
• sdma_sram::alt_dst_data_end_ptr_ch9::ALT_DST_DATA_END_PTR_CH9_W
• sdma_sram::alt_dst_data_end_ptr_ch9::R
• sdma_sram::alt_dst_data_end_ptr_ch9::W
• sdma_sram::alt_src_data_end_ptr_ch0::ALT_SRC_DATA_END_PTR_CH0_R
• sdma_sram::alt_src_data_end_ptr_ch0::ALT_SRC_DATA_END_PTR_CH0_SPEC
• sdma_sram::alt_src_data_end_ptr_ch0::ALT_SRC_DATA_END_PTR_CH0_W
• sdma_sram::alt_src_data_end_ptr_ch0::R
• sdma_sram::alt_src_data_end_ptr_ch0::W
• sdma_sram::alt_src_data_end_ptr_ch10::ALT_SRC_DATA_END_PTR_CH10_R
• sdma_sram::alt_src_data_end_ptr_ch10::ALT_SRC_DATA_END_PTR_CH10_SPEC
• sdma_sram::alt_src_data_end_ptr_ch10::ALT_SRC_DATA_END_PTR_CH10_W
• sdma_sram::alt_src_data_end_ptr_ch10::R
• sdma_sram::alt_src_data_end_ptr_ch10::W
• sdma_sram::alt_src_data_end_ptr_ch11::ALT_SRC_DATA_END_PTR_CH11_R
• sdma_sram::alt_src_data_end_ptr_ch11::ALT_SRC_DATA_END_PTR_CH11_SPEC
• sdma_sram::alt_src_data_end_ptr_ch11::ALT_SRC_DATA_END_PTR_CH11_W
• sdma_sram::alt_src_data_end_ptr_ch11::R
• sdma_sram::alt_src_data_end_ptr_ch11::W
• sdma_sram::alt_src_data_end_ptr_ch12::ALT_SRC_DATA_END_PTR_CH12_R
• sdma_sram::alt_src_data_end_ptr_ch12::ALT_SRC_DATA_END_PTR_CH12_SPEC
• sdma_sram::alt_src_data_end_ptr_ch12::ALT_SRC_DATA_END_PTR_CH12_W
• sdma_sram::alt_src_data_end_ptr_ch12::R
• sdma_sram::alt_src_data_end_ptr_ch12::W
• sdma_sram::alt_src_data_end_ptr_ch13::ALT_SRC_DATA_END_PTR_CH13_R
• sdma_sram::alt_src_data_end_ptr_ch13::ALT_SRC_DATA_END_PTR_CH13_SPEC
• sdma_sram::alt_src_data_end_ptr_ch13::ALT_SRC_DATA_END_PTR_CH13_W
• sdma_sram::alt_src_data_end_ptr_ch13::R
• sdma_sram::alt_src_data_end_ptr_ch13::W
• sdma_sram::alt_src_data_end_ptr_ch14::ALT_SRC_DATA_END_PTR_CH14_R
• sdma_sram::alt_src_data_end_ptr_ch14::ALT_SRC_DATA_END_PTR_CH14_SPEC
• sdma_sram::alt_src_data_end_ptr_ch14::ALT_SRC_DATA_END_PTR_CH14_W
• sdma_sram::alt_src_data_end_ptr_ch14::R
• sdma_sram::alt_src_data_end_ptr_ch14::W
• sdma_sram::alt_src_data_end_ptr_ch15::ALT_SRC_DATA_END_PTR_CH15_R
• sdma_sram::alt_src_data_end_ptr_ch15::ALT_SRC_DATA_END_PTR_CH15_SPEC
• sdma_sram::alt_src_data_end_ptr_ch15::ALT_SRC_DATA_END_PTR_CH15_W
• sdma_sram::alt_src_data_end_ptr_ch15::R
• sdma_sram::alt_src_data_end_ptr_ch15::W
• sdma_sram::alt_src_data_end_ptr_ch1::ALT_SRC_DATA_END_PTR_CH1_R
• sdma_sram::alt_src_data_end_ptr_ch1::ALT_SRC_DATA_END_PTR_CH1_SPEC
• sdma_sram::alt_src_data_end_ptr_ch1::ALT_SRC_DATA_END_PTR_CH1_W
• sdma_sram::alt_src_data_end_ptr_ch1::R
• sdma_sram::alt_src_data_end_ptr_ch1::W
• sdma_sram::alt_src_data_end_ptr_ch2::ALT_SRC_DATA_END_PTR_CH0_R
• sdma_sram::alt_src_data_end_ptr_ch2::ALT_SRC_DATA_END_PTR_CH0_W
• sdma_sram::alt_src_data_end_ptr_ch2::ALT_SRC_DATA_END_PTR_CH2_SPEC
• sdma_sram::alt_src_data_end_ptr_ch2::R
• sdma_sram::alt_src_data_end_ptr_ch2::W
• sdma_sram::alt_src_data_end_ptr_ch3::ALT_SRC_DATA_END_PTR_CH3_R
• sdma_sram::alt_src_data_end_ptr_ch3::ALT_SRC_DATA_END_PTR_CH3_SPEC
• sdma_sram::alt_src_data_end_ptr_ch3::ALT_SRC_DATA_END_PTR_CH3_W
• sdma_sram::alt_src_data_end_ptr_ch3::R
• sdma_sram::alt_src_data_end_ptr_ch3::W
• sdma_sram::alt_src_data_end_ptr_ch4::ALT_SRC_DATA_END_PTR_CH4_R
• sdma_sram::alt_src_data_end_ptr_ch4::ALT_SRC_DATA_END_PTR_CH4_SPEC
• sdma_sram::alt_src_data_end_ptr_ch4::ALT_SRC_DATA_END_PTR_CH4_W
• sdma_sram::alt_src_data_end_ptr_ch4::R
• sdma_sram::alt_src_data_end_ptr_ch4::W
• sdma_sram::alt_src_data_end_ptr_ch5::ALT_SRC_DATA_END_PTR_CH5_R
• sdma_sram::alt_src_data_end_ptr_ch5::ALT_SRC_DATA_END_PTR_CH5_SPEC
• sdma_sram::alt_src_data_end_ptr_ch5::ALT_SRC_DATA_END_PTR_CH5_W
• sdma_sram::alt_src_data_end_ptr_ch5::R
• sdma_sram::alt_src_data_end_ptr_ch5::W
• sdma_sram::alt_src_data_end_ptr_ch6::ALT_SRC_DATA_END_PTR_CH6_R
• sdma_sram::alt_src_data_end_ptr_ch6::ALT_SRC_DATA_END_PTR_CH6_SPEC
• sdma_sram::alt_src_data_end_ptr_ch6::ALT_SRC_DATA_END_PTR_CH6_W
• sdma_sram::alt_src_data_end_ptr_ch6::R
• sdma_sram::alt_src_data_end_ptr_ch6::W
• sdma_sram::alt_src_data_end_ptr_ch7::ALT_SRC_DATA_END_PTR_CH7_R
• sdma_sram::alt_src_data_end_ptr_ch7::ALT_SRC_DATA_END_PTR_CH7_SPEC
• sdma_sram::alt_src_data_end_ptr_ch7::ALT_SRC_DATA_END_PTR_CH7_W
• sdma_sram::alt_src_data_end_ptr_ch7::R
• sdma_sram::alt_src_data_end_ptr_ch7::W
• sdma_sram::alt_src_data_end_ptr_ch8::ALT_SRC_DATA_END_PTR_CH8_R
• sdma_sram::alt_src_data_end_ptr_ch8::ALT_SRC_DATA_END_PTR_CH8_SPEC
• sdma_sram::alt_src_data_end_ptr_ch8::ALT_SRC_DATA_END_PTR_CH8_W
• sdma_sram::alt_src_data_end_ptr_ch8::R
• sdma_sram::alt_src_data_end_ptr_ch8::W
• sdma_sram::alt_src_data_end_ptr_ch9::ALT_SRC_DATA_END_PTR_CH9_R
• sdma_sram::alt_src_data_end_ptr_ch9::ALT_SRC_DATA_END_PTR_CH9_SPEC
• sdma_sram::alt_src_data_end_ptr_ch9::ALT_SRC_DATA_END_PTR_CH9_W
• sdma_sram::alt_src_data_end_ptr_ch9::R
• sdma_sram::alt_src_data_end_ptr_ch9::W
• sdma_sram::ch_cfg_ch0::CH_CFG_CH0_SPEC
• sdma_sram::ch_cfg_ch0::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch0::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch0::DST_INC_R
• sdma_sram::ch_cfg_ch0::DST_INC_W
• sdma_sram::ch_cfg_ch0::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch0::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch0::DST_SIZE_R
• sdma_sram::ch_cfg_ch0::DST_SIZE_W
• sdma_sram::ch_cfg_ch0::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch0::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch0::N_MINUS_1_R
• sdma_sram::ch_cfg_ch0::N_MINUS_1_W
• sdma_sram::ch_cfg_ch0::R
• sdma_sram::ch_cfg_ch0::R_POWER_R
• sdma_sram::ch_cfg_ch0::R_POWER_W
• sdma_sram::ch_cfg_ch0::SRC_INC_R
• sdma_sram::ch_cfg_ch0::SRC_INC_W
• sdma_sram::ch_cfg_ch0::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch0::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch0::SRC_SIZE_R
• sdma_sram::ch_cfg_ch0::SRC_SIZE_W
• sdma_sram::ch_cfg_ch0::W
• sdma_sram::ch_cfg_ch10::CH_CFG_CH10_SPEC
• sdma_sram::ch_cfg_ch10::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch10::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch10::DST_INC_R
• sdma_sram::ch_cfg_ch10::DST_INC_W
• sdma_sram::ch_cfg_ch10::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch10::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch10::DST_SIZE_R
• sdma_sram::ch_cfg_ch10::DST_SIZE_W
• sdma_sram::ch_cfg_ch10::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch10::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch10::N_MINUS_1_R
• sdma_sram::ch_cfg_ch10::N_MINUS_1_W
• sdma_sram::ch_cfg_ch10::R
• sdma_sram::ch_cfg_ch10::R_POWER_R
• sdma_sram::ch_cfg_ch10::R_POWER_W
• sdma_sram::ch_cfg_ch10::SRC_INC_R
• sdma_sram::ch_cfg_ch10::SRC_INC_W
• sdma_sram::ch_cfg_ch10::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch10::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch10::SRC_SIZE_R
• sdma_sram::ch_cfg_ch10::SRC_SIZE_W
• sdma_sram::ch_cfg_ch10::W
• sdma_sram::ch_cfg_ch11::CH_CFG_CH11_SPEC
• sdma_sram::ch_cfg_ch11::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch11::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch11::DST_INC_R
• sdma_sram::ch_cfg_ch11::DST_INC_W
• sdma_sram::ch_cfg_ch11::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch11::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch11::DST_SIZE_R
• sdma_sram::ch_cfg_ch11::DST_SIZE_W
• sdma_sram::ch_cfg_ch11::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch11::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch11::N_MINUS_1_R
• sdma_sram::ch_cfg_ch11::N_MINUS_1_W
• sdma_sram::ch_cfg_ch11::R
• sdma_sram::ch_cfg_ch11::R_POWER_R
• sdma_sram::ch_cfg_ch11::R_POWER_W
• sdma_sram::ch_cfg_ch11::SRC_INC_R
• sdma_sram::ch_cfg_ch11::SRC_INC_W
• sdma_sram::ch_cfg_ch11::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch11::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch11::SRC_SIZE_R
• sdma_sram::ch_cfg_ch11::SRC_SIZE_W
• sdma_sram::ch_cfg_ch11::W
• sdma_sram::ch_cfg_ch12::CH_CFG_CH12_SPEC
• sdma_sram::ch_cfg_ch12::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch12::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch12::DST_INC_R
• sdma_sram::ch_cfg_ch12::DST_INC_W
• sdma_sram::ch_cfg_ch12::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch12::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch12::DST_SIZE_R
• sdma_sram::ch_cfg_ch12::DST_SIZE_W
• sdma_sram::ch_cfg_ch12::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch12::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch12::N_MINUS_1_R
• sdma_sram::ch_cfg_ch12::N_MINUS_1_W
• sdma_sram::ch_cfg_ch12::R
• sdma_sram::ch_cfg_ch12::R_POWER_R
• sdma_sram::ch_cfg_ch12::R_POWER_W
• sdma_sram::ch_cfg_ch12::SRC_INC_R
• sdma_sram::ch_cfg_ch12::SRC_INC_W
• sdma_sram::ch_cfg_ch12::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch12::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch12::SRC_SIZE_R
• sdma_sram::ch_cfg_ch12::SRC_SIZE_W
• sdma_sram::ch_cfg_ch12::W
• sdma_sram::ch_cfg_ch13::CH_CFG_CH13_SPEC
• sdma_sram::ch_cfg_ch13::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch13::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch13::DST_INC_R
• sdma_sram::ch_cfg_ch13::DST_INC_W
• sdma_sram::ch_cfg_ch13::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch13::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch13::DST_SIZE_R
• sdma_sram::ch_cfg_ch13::DST_SIZE_W
• sdma_sram::ch_cfg_ch13::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch13::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch13::N_MINUS_1_R
• sdma_sram::ch_cfg_ch13::N_MINUS_1_W
• sdma_sram::ch_cfg_ch13::R
• sdma_sram::ch_cfg_ch13::R_POWER_R
• sdma_sram::ch_cfg_ch13::R_POWER_W
• sdma_sram::ch_cfg_ch13::SRC_INC_R
• sdma_sram::ch_cfg_ch13::SRC_INC_W
• sdma_sram::ch_cfg_ch13::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch13::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch13::SRC_SIZE_R
• sdma_sram::ch_cfg_ch13::SRC_SIZE_W
• sdma_sram::ch_cfg_ch13::W
• sdma_sram::ch_cfg_ch14::CH_CFG_CH14_SPEC
• sdma_sram::ch_cfg_ch14::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch14::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch14::DST_INC_R
• sdma_sram::ch_cfg_ch14::DST_INC_W
• sdma_sram::ch_cfg_ch14::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch14::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch14::DST_SIZE_R
• sdma_sram::ch_cfg_ch14::DST_SIZE_W
• sdma_sram::ch_cfg_ch14::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch14::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch14::N_MINUS_1_R
• sdma_sram::ch_cfg_ch14::N_MINUS_1_W
• sdma_sram::ch_cfg_ch14::R
• sdma_sram::ch_cfg_ch14::R_POWER_R
• sdma_sram::ch_cfg_ch14::R_POWER_W
• sdma_sram::ch_cfg_ch14::SRC_INC_R
• sdma_sram::ch_cfg_ch14::SRC_INC_W
• sdma_sram::ch_cfg_ch14::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch14::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch14::SRC_SIZE_R
• sdma_sram::ch_cfg_ch14::SRC_SIZE_W
• sdma_sram::ch_cfg_ch14::W
• sdma_sram::ch_cfg_ch15::CH_CFG_CH15_SPEC
• sdma_sram::ch_cfg_ch15::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch15::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch15::DST_INC_R
• sdma_sram::ch_cfg_ch15::DST_INC_W
• sdma_sram::ch_cfg_ch15::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch15::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch15::DST_SIZE_R
• sdma_sram::ch_cfg_ch15::DST_SIZE_W
• sdma_sram::ch_cfg_ch15::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch15::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch15::N_MINUS_1_R
• sdma_sram::ch_cfg_ch15::N_MINUS_1_W
• sdma_sram::ch_cfg_ch15::R
• sdma_sram::ch_cfg_ch15::R_POWER_R
• sdma_sram::ch_cfg_ch15::R_POWER_W
• sdma_sram::ch_cfg_ch15::SRC_INC_R
• sdma_sram::ch_cfg_ch15::SRC_INC_W
• sdma_sram::ch_cfg_ch15::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch15::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch15::SRC_SIZE_R
• sdma_sram::ch_cfg_ch15::SRC_SIZE_W
• sdma_sram::ch_cfg_ch15::W
• sdma_sram::ch_cfg_ch1::CH_CFG_CH1_SPEC
• sdma_sram::ch_cfg_ch1::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch1::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch1::DST_INC_R
• sdma_sram::ch_cfg_ch1::DST_INC_W
• sdma_sram::ch_cfg_ch1::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch1::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch1::DST_SIZE_R
• sdma_sram::ch_cfg_ch1::DST_SIZE_W
• sdma_sram::ch_cfg_ch1::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch1::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch1::N_MINUS_1_R
• sdma_sram::ch_cfg_ch1::N_MINUS_1_W
• sdma_sram::ch_cfg_ch1::R
• sdma_sram::ch_cfg_ch1::R_POWER_R
• sdma_sram::ch_cfg_ch1::R_POWER_W
• sdma_sram::ch_cfg_ch1::SRC_INC_R
• sdma_sram::ch_cfg_ch1::SRC_INC_W
• sdma_sram::ch_cfg_ch1::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch1::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch1::SRC_SIZE_R
• sdma_sram::ch_cfg_ch1::SRC_SIZE_W
• sdma_sram::ch_cfg_ch1::W
• sdma_sram::ch_cfg_ch2::CH_CFG_CH2_SPEC
• sdma_sram::ch_cfg_ch2::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch2::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch2::DST_INC_R
• sdma_sram::ch_cfg_ch2::DST_INC_W
• sdma_sram::ch_cfg_ch2::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch2::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch2::DST_SIZE_R
• sdma_sram::ch_cfg_ch2::DST_SIZE_W
• sdma_sram::ch_cfg_ch2::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch2::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch2::N_MINUS_1_R
• sdma_sram::ch_cfg_ch2::N_MINUS_1_W
• sdma_sram::ch_cfg_ch2::R
• sdma_sram::ch_cfg_ch2::R_POWER_R
• sdma_sram::ch_cfg_ch2::R_POWER_W
• sdma_sram::ch_cfg_ch2::SRC_INC_R
• sdma_sram::ch_cfg_ch2::SRC_INC_W
• sdma_sram::ch_cfg_ch2::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch2::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch2::SRC_SIZE_R
• sdma_sram::ch_cfg_ch2::SRC_SIZE_W
• sdma_sram::ch_cfg_ch2::W
• sdma_sram::ch_cfg_ch3::CH_CFG_CH3_SPEC
• sdma_sram::ch_cfg_ch3::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch3::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch3::DST_INC_R
• sdma_sram::ch_cfg_ch3::DST_INC_W
• sdma_sram::ch_cfg_ch3::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch3::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch3::DST_SIZE_R
• sdma_sram::ch_cfg_ch3::DST_SIZE_W
• sdma_sram::ch_cfg_ch3::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch3::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch3::N_MINUS_1_R
• sdma_sram::ch_cfg_ch3::N_MINUS_1_W
• sdma_sram::ch_cfg_ch3::R
• sdma_sram::ch_cfg_ch3::R_POWER_R
• sdma_sram::ch_cfg_ch3::R_POWER_W
• sdma_sram::ch_cfg_ch3::SRC_INC_R
• sdma_sram::ch_cfg_ch3::SRC_INC_W
• sdma_sram::ch_cfg_ch3::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch3::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch3::SRC_SIZE_R
• sdma_sram::ch_cfg_ch3::SRC_SIZE_W
• sdma_sram::ch_cfg_ch3::W
• sdma_sram::ch_cfg_ch4::CH_CFG_CH4_SPEC
• sdma_sram::ch_cfg_ch4::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch4::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch4::DST_INC_R
• sdma_sram::ch_cfg_ch4::DST_INC_W
• sdma_sram::ch_cfg_ch4::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch4::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch4::DST_SIZE_R
• sdma_sram::ch_cfg_ch4::DST_SIZE_W
• sdma_sram::ch_cfg_ch4::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch4::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch4::N_MINUS_1_R
• sdma_sram::ch_cfg_ch4::N_MINUS_1_W
• sdma_sram::ch_cfg_ch4::R
• sdma_sram::ch_cfg_ch4::R_POWER_R
• sdma_sram::ch_cfg_ch4::R_POWER_W
• sdma_sram::ch_cfg_ch4::SRC_INC_R
• sdma_sram::ch_cfg_ch4::SRC_INC_W
• sdma_sram::ch_cfg_ch4::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch4::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch4::SRC_SIZE_R
• sdma_sram::ch_cfg_ch4::SRC_SIZE_W
• sdma_sram::ch_cfg_ch4::W
• sdma_sram::ch_cfg_ch5::CH_CFG_CH5_SPEC
• sdma_sram::ch_cfg_ch5::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch5::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch5::DST_INC_R
• sdma_sram::ch_cfg_ch5::DST_INC_W
• sdma_sram::ch_cfg_ch5::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch5::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch5::DST_SIZE_R
• sdma_sram::ch_cfg_ch5::DST_SIZE_W
• sdma_sram::ch_cfg_ch5::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch5::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch5::N_MINUS_1_R
• sdma_sram::ch_cfg_ch5::N_MINUS_1_W
• sdma_sram::ch_cfg_ch5::R
• sdma_sram::ch_cfg_ch5::R_POWER_R
• sdma_sram::ch_cfg_ch5::R_POWER_W
• sdma_sram::ch_cfg_ch5::SRC_INC_R
• sdma_sram::ch_cfg_ch5::SRC_INC_W
• sdma_sram::ch_cfg_ch5::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch5::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch5::SRC_SIZE_R
• sdma_sram::ch_cfg_ch5::SRC_SIZE_W
• sdma_sram::ch_cfg_ch5::W
• sdma_sram::ch_cfg_ch6::CH_CFG_CH6_SPEC
• sdma_sram::ch_cfg_ch6::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch6::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch6::DST_INC_R
• sdma_sram::ch_cfg_ch6::DST_INC_W
• sdma_sram::ch_cfg_ch6::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch6::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch6::DST_SIZE_R
• sdma_sram::ch_cfg_ch6::DST_SIZE_W
• sdma_sram::ch_cfg_ch6::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch6::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch6::N_MINUS_1_R
• sdma_sram::ch_cfg_ch6::N_MINUS_1_W
• sdma_sram::ch_cfg_ch6::R
• sdma_sram::ch_cfg_ch6::R_POWER_R
• sdma_sram::ch_cfg_ch6::R_POWER_W
• sdma_sram::ch_cfg_ch6::SRC_INC_R
• sdma_sram::ch_cfg_ch6::SRC_INC_W
• sdma_sram::ch_cfg_ch6::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch6::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch6::SRC_SIZE_R
• sdma_sram::ch_cfg_ch6::SRC_SIZE_W
• sdma_sram::ch_cfg_ch6::W
• sdma_sram::ch_cfg_ch7::CH_CFG_CH7_SPEC
• sdma_sram::ch_cfg_ch7::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch7::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch7::DST_INC_R
• sdma_sram::ch_cfg_ch7::DST_INC_W
• sdma_sram::ch_cfg_ch7::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch7::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch7::DST_SIZE_R
• sdma_sram::ch_cfg_ch7::DST_SIZE_W
• sdma_sram::ch_cfg_ch7::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch7::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch7::N_MINUS_1_R
• sdma_sram::ch_cfg_ch7::N_MINUS_1_W
• sdma_sram::ch_cfg_ch7::R
• sdma_sram::ch_cfg_ch7::R_POWER_R
• sdma_sram::ch_cfg_ch7::R_POWER_W
• sdma_sram::ch_cfg_ch7::SRC_INC_R
• sdma_sram::ch_cfg_ch7::SRC_INC_W
• sdma_sram::ch_cfg_ch7::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch7::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch7::SRC_SIZE_R
• sdma_sram::ch_cfg_ch7::SRC_SIZE_W
• sdma_sram::ch_cfg_ch7::W
• sdma_sram::ch_cfg_ch8::CH_CFG_CH8_SPEC
• sdma_sram::ch_cfg_ch8::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch8::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch8::DST_INC_R
• sdma_sram::ch_cfg_ch8::DST_INC_W
• sdma_sram::ch_cfg_ch8::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch8::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch8::DST_SIZE_R
• sdma_sram::ch_cfg_ch8::DST_SIZE_W
• sdma_sram::ch_cfg_ch8::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch8::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch8::N_MINUS_1_R
• sdma_sram::ch_cfg_ch8::N_MINUS_1_W
• sdma_sram::ch_cfg_ch8::R
• sdma_sram::ch_cfg_ch8::R_POWER_R
• sdma_sram::ch_cfg_ch8::R_POWER_W
• sdma_sram::ch_cfg_ch8::SRC_INC_R
• sdma_sram::ch_cfg_ch8::SRC_INC_W
• sdma_sram::ch_cfg_ch8::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch8::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch8::SRC_SIZE_R
• sdma_sram::ch_cfg_ch8::SRC_SIZE_W
• sdma_sram::ch_cfg_ch8::W
• sdma_sram::ch_cfg_ch9::CH_CFG_CH9_SPEC
• sdma_sram::ch_cfg_ch9::CYCLE_CTRL_R
• sdma_sram::ch_cfg_ch9::CYCLE_CTRL_W
• sdma_sram::ch_cfg_ch9::DST_INC_R
• sdma_sram::ch_cfg_ch9::DST_INC_W
• sdma_sram::ch_cfg_ch9::DST_PROT_CTRL_R
• sdma_sram::ch_cfg_ch9::DST_PROT_CTRL_W
• sdma_sram::ch_cfg_ch9::DST_SIZE_R
• sdma_sram::ch_cfg_ch9::DST_SIZE_W
• sdma_sram::ch_cfg_ch9::NEXT_USEBURST_R
• sdma_sram::ch_cfg_ch9::NEXT_USEBURST_W
• sdma_sram::ch_cfg_ch9::N_MINUS_1_R
• sdma_sram::ch_cfg_ch9::N_MINUS_1_W
• sdma_sram::ch_cfg_ch9::R
• sdma_sram::ch_cfg_ch9::R_POWER_R
• sdma_sram::ch_cfg_ch9::R_POWER_W
• sdma_sram::ch_cfg_ch9::SRC_INC_R
• sdma_sram::ch_cfg_ch9::SRC_INC_W
• sdma_sram::ch_cfg_ch9::SRC_PROT_CTRL_R
• sdma_sram::ch_cfg_ch9::SRC_PROT_CTRL_W
• sdma_sram::ch_cfg_ch9::SRC_SIZE_R
• sdma_sram::ch_cfg_ch9::SRC_SIZE_W
• sdma_sram::ch_cfg_ch9::W
• sdma_sram::dst_data_end_ptr_ch0::DST_DATA_END_PTR_CH0_R
• sdma_sram::dst_data_end_ptr_ch0::DST_DATA_END_PTR_CH0_SPEC
• sdma_sram::dst_data_end_ptr_ch0::DST_DATA_END_PTR_CH0_W
• sdma_sram::dst_data_end_ptr_ch0::R
• sdma_sram::dst_data_end_ptr_ch0::W
• sdma_sram::dst_data_end_ptr_ch10::DST_DATA_END_PTR_CH10_R
• sdma_sram::dst_data_end_ptr_ch10::DST_DATA_END_PTR_CH10_SPEC
• sdma_sram::dst_data_end_ptr_ch10::DST_DATA_END_PTR_CH10_W
• sdma_sram::dst_data_end_ptr_ch10::R
• sdma_sram::dst_data_end_ptr_ch10::W
• sdma_sram::dst_data_end_ptr_ch11::DST_DATA_END_PTR_CH11_R
• sdma_sram::dst_data_end_ptr_ch11::DST_DATA_END_PTR_CH11_SPEC
• sdma_sram::dst_data_end_ptr_ch11::DST_DATA_END_PTR_CH11_W
• sdma_sram::dst_data_end_ptr_ch11::R
• sdma_sram::dst_data_end_ptr_ch11::W
• sdma_sram::dst_data_end_ptr_ch12::DST_DATA_END_PTR_CH12_R
• sdma_sram::dst_data_end_ptr_ch12::DST_DATA_END_PTR_CH12_SPEC
• sdma_sram::dst_data_end_ptr_ch12::DST_DATA_END_PTR_CH12_W
• sdma_sram::dst_data_end_ptr_ch12::R
• sdma_sram::dst_data_end_ptr_ch12::W
• sdma_sram::dst_data_end_ptr_ch13::DST_DATA_END_PTR_CH13_R
• sdma_sram::dst_data_end_ptr_ch13::DST_DATA_END_PTR_CH13_SPEC
• sdma_sram::dst_data_end_ptr_ch13::DST_DATA_END_PTR_CH13_W
• sdma_sram::dst_data_end_ptr_ch13::R
• sdma_sram::dst_data_end_ptr_ch13::W
• sdma_sram::dst_data_end_ptr_ch14::DST_DATA_END_PTR_CH14_R
• sdma_sram::dst_data_end_ptr_ch14::DST_DATA_END_PTR_CH14_SPEC
• sdma_sram::dst_data_end_ptr_ch14::DST_DATA_END_PTR_CH14_W
• sdma_sram::dst_data_end_ptr_ch14::R
• sdma_sram::dst_data_end_ptr_ch14::W
• sdma_sram::dst_data_end_ptr_ch15::DST_DATA_END_PTR_CH15_R
• sdma_sram::dst_data_end_ptr_ch15::DST_DATA_END_PTR_CH15_SPEC
• sdma_sram::dst_data_end_ptr_ch15::DST_DATA_END_PTR_CH15_W
• sdma_sram::dst_data_end_ptr_ch15::R
• sdma_sram::dst_data_end_ptr_ch15::W
• sdma_sram::dst_data_end_ptr_ch1::DST_DATA_END_PTR_CH1_R
• sdma_sram::dst_data_end_ptr_ch1::DST_DATA_END_PTR_CH1_SPEC
• sdma_sram::dst_data_end_ptr_ch1::DST_DATA_END_PTR_CH1_W
• sdma_sram::dst_data_end_ptr_ch1::R
• sdma_sram::dst_data_end_ptr_ch1::W
• sdma_sram::dst_data_end_ptr_ch2::DST_DATA_END_PTR_CH2_R
• sdma_sram::dst_data_end_ptr_ch2::DST_DATA_END_PTR_CH2_SPEC
• sdma_sram::dst_data_end_ptr_ch2::DST_DATA_END_PTR_CH2_W
• sdma_sram::dst_data_end_ptr_ch2::R
• sdma_sram::dst_data_end_ptr_ch2::W
• sdma_sram::dst_data_end_ptr_ch3::DST_DATA_END_PTR_CH3_R
• sdma_sram::dst_data_end_ptr_ch3::DST_DATA_END_PTR_CH3_SPEC
• sdma_sram::dst_data_end_ptr_ch3::DST_DATA_END_PTR_CH3_W
• sdma_sram::dst_data_end_ptr_ch3::R
• sdma_sram::dst_data_end_ptr_ch3::W
• sdma_sram::dst_data_end_ptr_ch4::DST_DATA_END_PTR_CH4_R
• sdma_sram::dst_data_end_ptr_ch4::DST_DATA_END_PTR_CH4_SPEC
• sdma_sram::dst_data_end_ptr_ch4::DST_DATA_END_PTR_CH4_W
• sdma_sram::dst_data_end_ptr_ch4::R
• sdma_sram::dst_data_end_ptr_ch4::W
• sdma_sram::dst_data_end_ptr_ch5::DST_DATA_END_PTR_CH5_R
• sdma_sram::dst_data_end_ptr_ch5::DST_DATA_END_PTR_CH5_SPEC
• sdma_sram::dst_data_end_ptr_ch5::DST_DATA_END_PTR_CH5_W
• sdma_sram::dst_data_end_ptr_ch5::R
• sdma_sram::dst_data_end_ptr_ch5::W
• sdma_sram::dst_data_end_ptr_ch6::DST_DATA_END_PTR_CH6_R
• sdma_sram::dst_data_end_ptr_ch6::DST_DATA_END_PTR_CH6_SPEC
• sdma_sram::dst_data_end_ptr_ch6::DST_DATA_END_PTR_CH6_W
• sdma_sram::dst_data_end_ptr_ch6::R
• sdma_sram::dst_data_end_ptr_ch6::W
• sdma_sram::dst_data_end_ptr_ch7::DST_DATA_END_PTR_CH7_R
• sdma_sram::dst_data_end_ptr_ch7::DST_DATA_END_PTR_CH7_SPEC
• sdma_sram::dst_data_end_ptr_ch7::DST_DATA_END_PTR_CH7_W
• sdma_sram::dst_data_end_ptr_ch7::R
• sdma_sram::dst_data_end_ptr_ch7::W
• sdma_sram::dst_data_end_ptr_ch8::DST_DATA_END_PTR_CH8_R
• sdma_sram::dst_data_end_ptr_ch8::DST_DATA_END_PTR_CH8_SPEC
• sdma_sram::dst_data_end_ptr_ch8::DST_DATA_END_PTR_CH8_W
• sdma_sram::dst_data_end_ptr_ch8::R
• sdma_sram::dst_data_end_ptr_ch8::W
• sdma_sram::dst_data_end_ptr_ch9::DST_DATA_END_PTR_CH9_R
• sdma_sram::dst_data_end_ptr_ch9::DST_DATA_END_PTR_CH9_SPEC
• sdma_sram::dst_data_end_ptr_ch9::DST_DATA_END_PTR_CH9_W
• sdma_sram::dst_data_end_ptr_ch9::R
• sdma_sram::dst_data_end_ptr_ch9::W
• sdma_sram::src_data_end_ptr_ch0::R
• sdma_sram::src_data_end_ptr_ch0::SRC_DATA_END_PTR_CH0_R
• sdma_sram::src_data_end_ptr_ch0::SRC_DATA_END_PTR_CH0_SPEC
• sdma_sram::src_data_end_ptr_ch0::SRC_DATA_END_PTR_CH0_W
• sdma_sram::src_data_end_ptr_ch0::W
• sdma_sram::src_data_end_ptr_ch10::R
• sdma_sram::src_data_end_ptr_ch10::SRC_DATA_END_PTR_CH10_R
• sdma_sram::src_data_end_ptr_ch10::SRC_DATA_END_PTR_CH10_SPEC
• sdma_sram::src_data_end_ptr_ch10::SRC_DATA_END_PTR_CH10_W
• sdma_sram::src_data_end_ptr_ch10::W
• sdma_sram::src_data_end_ptr_ch11::R
• sdma_sram::src_data_end_ptr_ch11::SRC_DATA_END_PTR_CH11_R
• sdma_sram::src_data_end_ptr_ch11::SRC_DATA_END_PTR_CH11_SPEC
• sdma_sram::src_data_end_ptr_ch11::SRC_DATA_END_PTR_CH11_W
• sdma_sram::src_data_end_ptr_ch11::W
• sdma_sram::src_data_end_ptr_ch12::R
• sdma_sram::src_data_end_ptr_ch12::SRC_DATA_END_PTR_CH12_R
• sdma_sram::src_data_end_ptr_ch12::SRC_DATA_END_PTR_CH12_SPEC
• sdma_sram::src_data_end_ptr_ch12::SRC_DATA_END_PTR_CH12_W
• sdma_sram::src_data_end_ptr_ch12::W
• sdma_sram::src_data_end_ptr_ch13::R
• sdma_sram::src_data_end_ptr_ch13::SRC_DATA_END_PTR_CH13_R
• sdma_sram::src_data_end_ptr_ch13::SRC_DATA_END_PTR_CH13_SPEC
• sdma_sram::src_data_end_ptr_ch13::SRC_DATA_END_PTR_CH13_W
• sdma_sram::src_data_end_ptr_ch13::W
• sdma_sram::src_data_end_ptr_ch14::R
• sdma_sram::src_data_end_ptr_ch14::SRC_DATA_END_PTR_CH14_R
• sdma_sram::src_data_end_ptr_ch14::SRC_DATA_END_PTR_CH14_SPEC
• sdma_sram::src_data_end_ptr_ch14::SRC_DATA_END_PTR_CH14_W
• sdma_sram::src_data_end_ptr_ch14::W
• sdma_sram::src_data_end_ptr_ch15::R
• sdma_sram::src_data_end_ptr_ch15::SRC_DATA_END_PTR_CH15_R
• sdma_sram::src_data_end_ptr_ch15::SRC_DATA_END_PTR_CH15_SPEC
• sdma_sram::src_data_end_ptr_ch15::SRC_DATA_END_PTR_CH15_W
• sdma_sram::src_data_end_ptr_ch15::W
• sdma_sram::src_data_end_ptr_ch1::R
• sdma_sram::src_data_end_ptr_ch1::SRC_DATA_END_PTR_CH1_R
• sdma_sram::src_data_end_ptr_ch1::SRC_DATA_END_PTR_CH1_SPEC
• sdma_sram::src_data_end_ptr_ch1::SRC_DATA_END_PTR_CH1_W
• sdma_sram::src_data_end_ptr_ch1::W
• sdma_sram::src_data_end_ptr_ch2::R
• sdma_sram::src_data_end_ptr_ch2::SRC_DATA_END_PTR_CH0_R
• sdma_sram::src_data_end_ptr_ch2::SRC_DATA_END_PTR_CH0_W
• sdma_sram::src_data_end_ptr_ch2::SRC_DATA_END_PTR_CH2_SPEC
• sdma_sram::src_data_end_ptr_ch2::W
• sdma_sram::src_data_end_ptr_ch3::R
• sdma_sram::src_data_end_ptr_ch3::SRC_DATA_END_PTR_CH3_R
• sdma_sram::src_data_end_ptr_ch3::SRC_DATA_END_PTR_CH3_SPEC
• sdma_sram::src_data_end_ptr_ch3::SRC_DATA_END_PTR_CH3_W
• sdma_sram::src_data_end_ptr_ch3::W
• sdma_sram::src_data_end_ptr_ch4::R
• sdma_sram::src_data_end_ptr_ch4::SRC_DATA_END_PTR_CH4_R
• sdma_sram::src_data_end_ptr_ch4::SRC_DATA_END_PTR_CH4_SPEC
• sdma_sram::src_data_end_ptr_ch4::SRC_DATA_END_PTR_CH4_W
• sdma_sram::src_data_end_ptr_ch4::W
• sdma_sram::src_data_end_ptr_ch5::R
• sdma_sram::src_data_end_ptr_ch5::SRC_DATA_END_PTR_CH5_R
• sdma_sram::src_data_end_ptr_ch5::SRC_DATA_END_PTR_CH5_SPEC
• sdma_sram::src_data_end_ptr_ch5::SRC_DATA_END_PTR_CH5_W
• sdma_sram::src_data_end_ptr_ch5::W
• sdma_sram::src_data_end_ptr_ch6::R
• sdma_sram::src_data_end_ptr_ch6::SRC_DATA_END_PTR_CH6_R
• sdma_sram::src_data_end_ptr_ch6::SRC_DATA_END_PTR_CH6_SPEC
• sdma_sram::src_data_end_ptr_ch6::SRC_DATA_END_PTR_CH6_W
• sdma_sram::src_data_end_ptr_ch6::W
• sdma_sram::src_data_end_ptr_ch7::R
• sdma_sram::src_data_end_ptr_ch7::SRC_DATA_END_PTR_CH7_R
• sdma_sram::src_data_end_ptr_ch7::SRC_DATA_END_PTR_CH7_SPEC
• sdma_sram::src_data_end_ptr_ch7::SRC_DATA_END_PTR_CH7_W
• sdma_sram::src_data_end_ptr_ch7::W
• sdma_sram::src_data_end_ptr_ch8::R
• sdma_sram::src_data_end_ptr_ch8::SRC_DATA_END_PTR_CH8_R
• sdma_sram::src_data_end_ptr_ch8::SRC_DATA_END_PTR_CH8_SPEC
• sdma_sram::src_data_end_ptr_ch8::SRC_DATA_END_PTR_CH8_W
• sdma_sram::src_data_end_ptr_ch8::W
• sdma_sram::src_data_end_ptr_ch9::R
• sdma_sram::src_data_end_ptr_ch9::SRC_DATA_END_PTR_CH9_R
• sdma_sram::src_data_end_ptr_ch9::SRC_DATA_END_PTR_CH9_SPEC
• sdma_sram::src_data_end_ptr_ch9::SRC_DATA_END_PTR_CH9_W
• sdma_sram::src_data_end_ptr_ch9::W
• spi::RegisterBlock
• spi::baudr::BAUDR_SPEC
• spi::baudr::R
• spi::baudr::SCKDV_0_R
• spi::baudr::SCKDV_15_1_R
• spi::baudr::SCKDV_15_1_W
• spi::baudr::W
• spi::ctrlr0::CFS_R
• spi::ctrlr0::CFS_W
• spi::ctrlr0::CTRLR0_SPEC
• spi::ctrlr0::DFS_R
• spi::ctrlr0::DFS_W
• spi::ctrlr0::FRF_R
• spi::ctrlr0::FRF_W
• spi::ctrlr0::R
• spi::ctrlr0::SCPH_R
• spi::ctrlr0::SCPH_W
• spi::ctrlr0::SCPOL_R
• spi::ctrlr0::SCPOL_W
• spi::ctrlr0::SLV_OE_R
• spi::ctrlr0::SLV_OE_W
• spi::ctrlr0::SRL_R
• spi::ctrlr0::SRL_W
• spi::ctrlr0::TMOD_R
• spi::ctrlr0::TMOD_W
• spi::ctrlr0::W
• spi::ctrlr1::CTRLR1_SPEC
• spi::ctrlr1::NDF_R
• spi::ctrlr1::NDF_W
• spi::ctrlr1::R
• spi::ctrlr1::W
• spi::dr0::DR0_SPEC
• spi::dr0::DR_R
• spi::dr0::DR_W
• spi::dr0::R
• spi::dr0::W
• spi::icr::ICR_SPEC
• spi::icr::R
• spi::icr::TXOICR_R
• spi::idr::IDCODE_R
• spi::idr::IDR_SPEC
• spi::idr::R
• spi::imr::IMR_SPEC
• spi::imr::MSTIM_W
• spi::imr::R
• spi::imr::RXFIM_W
• spi::imr::RXFOIM_W
• spi::imr::RXUIM_W
• spi::imr::TXEIM_R
• spi::imr::TXEIM_W
• spi::imr::TXOIM_W
• spi::imr::W
• spi::isr::ISR_SPEC
• spi::isr::MSTIS_R
• spi::isr::MSTIS_W
• spi::isr::R
• spi::isr::RXFIS_R
• spi::isr::RXFIS_W
• spi::isr::RXOIS_R
• spi::isr::RXOIS_W
• spi::isr::RXUIS_R
• spi::isr::RXUIS_W
• spi::isr::TXEIS_R
• spi::isr::TXEIS_W
• spi::isr::TXOIS_R
• spi::isr::TXOIS_W
• spi::isr::W
• spi::msticr::MSTICR_SPEC
• spi::msticr::R
• spi::msticr::TXOICR_R
• spi::risr::MSTIS_R
• spi::risr::MSTIS_W
• spi::risr::R
• spi::risr::RISR_SPEC
• spi::risr::RXFIS_R
• spi::risr::RXFIS_W
• spi::risr::RXOIS_R
• spi::risr::RXOIS_W
• spi::risr::RXUIS_R
• spi::risr::RXUIS_W
• spi::risr::TXEIS_R
• spi::risr::TXEIS_W
• spi::risr::TXOIS_R
• spi::risr::TXOIS_W
• spi::risr::W
• spi::rxflr::R
• spi::rxflr::RXFLR_SPEC
• spi::rxflr::RXTFL_R
• spi::rxftlr::R
• spi::rxftlr::RFT_R
• spi::rxftlr::RFT_W
• spi::rxftlr::RXFTLR_SPEC
• spi::rxftlr::W
• spi::rxoicr::R
• spi::rxoicr::RXOICR_SPEC
• spi::rxoicr::TXOICR_R
• spi::rxuicr::R
• spi::rxuicr::RXUICR_SPEC
• spi::rxuicr::TXOICR_R
• spi::ser::R
• spi::ser::SER_SPEC
• spi::ser::SER_SS1_R
• spi::ser::SER_SS1_W
• spi::ser::SER_SS2_R
• spi::ser::SER_SS2_W
• spi::ser::SER_SS3_R
• spi::ser::SER_SS3_W
• spi::ser::W
• spi::sr::BUSY_R
• spi::sr::DCOL_R
• spi::sr::R
• spi::sr::RFF_R
• spi::sr::RFNE_R
• spi::sr::SR_SPEC
• spi::sr::TFE_R
• spi::sr::TFNF_R
• spi::sr::TXE_R
• spi::ssi_comp_version::R
• spi::ssi_comp_version::SSI_COMP_VERSION_R
• spi::ssi_comp_version::SSI_COMP_VERSION_SPEC
• spi::ssi_comp_version::SSI_COMP_VERSION_W
• spi::ssi_comp_version::W
• spi::ssienr::R
• spi::ssienr::SSIENR_SPEC
• spi::ssienr::SSI_EN_R
• spi::ssienr::SSI_EN_W
• spi::ssienr::W
• spi::txflr::R
• spi::txflr::TXFLR_SPEC
• spi::txflr::TXTFL_R
• spi::txftlr::R
• spi::txftlr::TFT_R
• spi::txftlr::TFT_W
• spi::txftlr::TXFTLR_SPEC
• spi::txftlr::W
• spi::txoicr::R
• spi::txoicr::TXOICR_R
• spi::txoicr::TXOICR_SPEC
• spi_tlc::RegisterBlock
• spi_tlc::ahbaccessctl::AHBACCESSCTL_SPEC
• spi_tlc::ahbaccessctl::AHBREADREQMODE_R
• spi_tlc::ahbaccessctl::AHBREADREQMODE_W
• spi_tlc::ahbaccessctl::R
• spi_tlc::ahbaccessctl::SCRATCH0_R
• spi_tlc::ahbaccessctl::SCRATCH0_W
• spi_tlc::ahbaccessctl::W
• spi_tlc::ahbstatus::AHBREADDATAVALID_R
• spi_tlc::ahbstatus::AHBREQFIFOFULL_R
• spi_tlc::ahbstatus::AHBREQFIFOHALFEMPTY_R
• spi_tlc::ahbstatus::AHBREQFIFOSIZE_R
• spi_tlc::ahbstatus::AHBSTATUS_SPEC
• spi_tlc::ahbstatus::NOPENDINGAHBREQ_R
• spi_tlc::ahbstatus::R
• spi_tlc::cm_fifo_0_data::CM_FIFO_0_DATA_SPEC
• spi_tlc::cm_fifo_0_data::DATA_R
• spi_tlc::cm_fifo_0_data::R
• spi_tlc::cm_fifo_1_data::CM_FIFO_1_DATA_SPEC
• spi_tlc::cm_fifo_1_data::DATA_R
• spi_tlc::cm_fifo_1_data::R
• spi_tlc::cm_fifo_2_data::CM_FIFO_2_DATA_SPEC
• spi_tlc::cm_fifo_2_data::DATA_R
• spi_tlc::cm_fifo_2_data::R
• spi_tlc::cm_fifo_3_data::CM_FIFO_3_DATA_SPEC
• spi_tlc::cm_fifo_3_data::DATA_R
• spi_tlc::cm_fifo_3_data::R
• spi_tlc::deviceidbyte::DEVICEIDBYTE_R
• spi_tlc::deviceidbyte::DEVICEIDBYTE_SPEC
• spi_tlc::deviceidbyte::R
• spi_tlc::dmaaddr0::DMAADDR0_R
• spi_tlc::dmaaddr0::DMAADDR0_SPEC
• spi_tlc::dmaaddr0::DMAADDR0_W
• spi_tlc::dmaaddr0::R
• spi_tlc::dmaaddr0::W
• spi_tlc::dmaaddr1::DMAADDR1_R
• spi_tlc::dmaaddr1::DMAADDR1_SPEC
• spi_tlc::dmaaddr1::DMAADDR1_W
• spi_tlc::dmaaddr1::R
• spi_tlc::dmaaddr1::W
• spi_tlc::dmaaddr2::DMAADDR2_R
• spi_tlc::dmaaddr2::DMAADDR2_SPEC
• spi_tlc::dmaaddr2::DMAADDR2_W
• spi_tlc::dmaaddr2::R
• spi_tlc::dmaaddr2::W
• spi_tlc::dmaaddr3::DMAADDR3_R
• spi_tlc::dmaaddr3::DMAADDR3_SPEC
• spi_tlc::dmaaddr3::DMAADDR3_W
• spi_tlc::dmaaddr3::R
• spi_tlc::dmaaddr3::W
• spi_tlc::dmaburstsize0::DMABURSTSIZE0_R
• spi_tlc::dmaburstsize0::DMABURSTSIZE0_SPEC
• spi_tlc::dmaburstsize0::DMABURSTSIZE0_W
• spi_tlc::dmaburstsize0::R
• spi_tlc::dmaburstsize0::W
• spi_tlc::dmaburstsize1::DMABURSTSIZE1_R
• spi_tlc::dmaburstsize1::DMABURSTSIZE1_SPEC
• spi_tlc::dmaburstsize1::DMABURSTSIZE1_W
• spi_tlc::dmaburstsize1::R
• spi_tlc::dmaburstsize1::W
• spi_tlc::dmadebugctl0::DMADEBUGCTL0_SPEC
• spi_tlc::dmadebugctl0::DMAFIFOCLEAR_R
• spi_tlc::dmadebugctl0::DMAFIFOCLEAR_W
• spi_tlc::dmadebugctl0::R
• spi_tlc::dmadebugctl0::W
• spi_tlc::dmadebugctl1::DMACLEAR_R
• spi_tlc::dmadebugctl1::DMACLEAR_W
• spi_tlc::dmadebugctl1::DMADEBUGCTL1_SPEC
• spi_tlc::dmadebugctl1::R
• spi_tlc::dmadebugctl1::W
• spi_tlc::dmarddata::DMARDDATA_R
• spi_tlc::dmarddata::DMARDDATA_SPEC
• spi_tlc::dmarddata::R
• spi_tlc::dmastatus::DMAFIFO_EMPTY_R
• spi_tlc::dmastatus::DMAFIFO_UNDERFLOW_R
• spi_tlc::dmastatus::DMASTATUS_SPEC
• spi_tlc::dmastatus::R
• spi_tlc::mem_addr_byte0::MEMADDRBYTE0_R
• spi_tlc::mem_addr_byte0::MEMADDRBYTE0_SPEC
• spi_tlc::mem_addr_byte0::MEMADDRBYTE0_W
• spi_tlc::mem_addr_byte0::R
• spi_tlc::mem_addr_byte0::W
• spi_tlc::mem_addr_byte1::MEMADDRBYTE1_R
• spi_tlc::mem_addr_byte1::MEMADDRBYTE1_SPEC
• spi_tlc::mem_addr_byte1::MEMADDRBYTE1_W
• spi_tlc::mem_addr_byte1::R
• spi_tlc::mem_addr_byte1::W
• spi_tlc::mem_addr_byte2::MEMADDRBYTE2_R
• spi_tlc::mem_addr_byte2::MEMADDRBYTE2_SPEC
• spi_tlc::mem_addr_byte2::MEMADDRBYTE2_W
• spi_tlc::mem_addr_byte2::R
• spi_tlc::mem_addr_byte2::W
• spi_tlc::mem_addr_byte3::MEMADDRBYTE3_R
• spi_tlc::mem_addr_byte3::MEMADDRBYTE3_SPEC
• spi_tlc::mem_addr_byte3::MEMADDRBYTE3_W
• spi_tlc::mem_addr_byte3::R
• spi_tlc::mem_addr_byte3::W
• spi_tlc::mem_data_byte0::MEMDATABYTE0_R
• spi_tlc::mem_data_byte0::MEMDATABYTE0_SPEC
• spi_tlc::mem_data_byte0::MEMDATABYTE0_W
• spi_tlc::mem_data_byte0::R
• spi_tlc::mem_data_byte0::W
• spi_tlc::mem_data_byte1::MEMDATABYTE1_R
• spi_tlc::mem_data_byte1::MEMDATABYTE1_SPEC
• spi_tlc::mem_data_byte1::MEMDATABYTE1_W
• spi_tlc::mem_data_byte1::R
• spi_tlc::mem_data_byte1::W
• spi_tlc::mem_data_byte2::MEMDATABYTE2_R
• spi_tlc::mem_data_byte2::MEMDATABYTE2_SPEC
• spi_tlc::mem_data_byte2::MEMDATABYTE2_W
• spi_tlc::mem_data_byte2::R
• spi_tlc::mem_data_byte2::W
• spi_tlc::mem_data_byte3::MEMDATABYTE3_R
• spi_tlc::mem_data_byte3::MEMDATABYTE3_SPEC
• spi_tlc::mem_data_byte3::MEMDATABYTE3_W
• spi_tlc::mem_data_byte3::R
• spi_tlc::mem_data_byte3::W
• spi_tlc::reserved_dummy::DUMMY_W
• spi_tlc::reserved_dummy::RESERVED_DUMMY_SPEC
• spi_tlc::reserved_dummy::W
• spi_tlc::scratchbyte::R
• spi_tlc::scratchbyte::SCRATCHBYTE_R
• spi_tlc::scratchbyte::SCRATCHBYTE_SPEC
• spi_tlc::scratchbyte::SCRATCHBYTE_W
• spi_tlc::scratchbyte::W
• spi_tlc::tamarstatus::M4POWERSTATUS_R
• spi_tlc::tamarstatus::M4REBOOTREQ_R
• spi_tlc::tamarstatus::M4RESETSTATUS_R
• spi_tlc::tamarstatus::PORINICOND_R
• spi_tlc::tamarstatus::R
• spi_tlc::tamarstatus::TAMARSTATUS_SPEC
• spt::RegisterBlock
• spt::error_cmp_1s_0::ERROR_CMP_1S_0_R
• spt::error_cmp_1s_0::ERROR_CMP_1S_0_SPEC
• spt::error_cmp_1s_0::ERROR_CMP_1S_0_W
• spt::error_cmp_1s_0::R
• spt::error_cmp_1s_0::W
• spt::error_cmp_1s_1::ERROR_CMP_1S_1_R
• spt::error_cmp_1s_1::ERROR_CMP_1S_1_SPEC
• spt::error_cmp_1s_1::ERROR_CMP_1S_1_W
• spt::error_cmp_1s_1::R
• spt::error_cmp_1s_1::W
• spt::error_cmp_1s_2::ERROR_CMP_1S_2_R
• spt::error_cmp_1s_2::ERROR_CMP_1S_2_SPEC
• spt::error_cmp_1s_2::ERROR_CMP_1S_2_W
• spt::error_cmp_1s_2::R
• spt::error_cmp_1s_2::W
• spt::error_cmp_1s_3::ERROR_CMP_1S_3_R
• spt::error_cmp_1s_3::ERROR_CMP_1S_3_SPEC
• spt::error_cmp_1s_3::ERROR_CMP_1S_3_W
• spt::error_cmp_1s_3::R
• spt::error_cmp_1s_3::W
• spt::error_cmp_40m::ERROR_CMP_40M_R
• spt::error_cmp_40m::ERROR_CMP_40M_SPEC
• spt::error_cmp_40m::ERROR_CMP_40M_W
• spt::error_cmp_40m::R
• spt::error_cmp_40m::W
• spt::error_cmp_rtc_0::ERROR_CMP_RTC_0_SPEC
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_16_R
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_16_W
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_2_R
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_2_W
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_4_R
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_4_W
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_8_R
• spt::error_cmp_rtc_0::ERROT_CMP_RTC_0_8_W
• spt::error_cmp_rtc_0::R
• spt::error_cmp_rtc_0::W
• spt::error_cmp_rtc_1::ERROR_CMP_RTC_1_SPEC
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_128_R
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_128_W
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_256_R
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_256_W
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_32_R
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_32_W
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_64_R
• spt::error_cmp_rtc_1::ERROT_CMP_RTC_0_64_W
• spt::error_cmp_rtc_1::R
• spt::error_cmp_rtc_1::W
• spt::error_cmp_rtc_2::ERROR_CMP_RTC_2_SPEC
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_1024_R
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_1024_W
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_4096_R
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_4096_W
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_512_R
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_0_512_W
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_2_2048_R
• spt::error_cmp_rtc_2::ERROT_CMP_RTC_2_2048_W
• spt::error_cmp_rtc_2::R
• spt::error_cmp_rtc_2::W
• spt::error_cmp_rtc_3::ERROR_CMP_RTC_3_SPEC
• spt::error_cmp_rtc_3::ERROT_CMP_RTC_0_16384_R
• spt::error_cmp_rtc_3::ERROT_CMP_RTC_0_16384_W
• spt::error_cmp_rtc_3::ERROT_CMP_RTC_2_8192_R
• spt::error_cmp_rtc_3::ERROT_CMP_RTC_2_8192_W
• spt::error_cmp_rtc_3::R
• spt::error_cmp_rtc_3::W
• spt::event_cnt_value::EVENT_CNT_VALUE_R
• spt::event_cnt_value::EVENT_CNT_VALUE_SPEC
• spt::event_cnt_value::R
• spt::ms_cnt_value::MS_CNT_VALUE_R
• spt::ms_cnt_value::MS_CNT_VALUE_SPEC
• spt::ms_cnt_value::R
• spt::sleep_mode::R
• spt::sleep_mode::SLEEP_MODE_R
• spt::sleep_mode::SLEEP_MODE_SPEC
• spt::sleep_mode::SLEEP_MODE_W
• spt::sleep_mode::W
• spt::spare_bits::R
• spt::spare_bits::SPARE_BITS_R
• spt::spare_bits::SPARE_BITS_SPEC
• spt::spare_bits::SPARE_BITS_W
• spt::spare_bits::W
• spt::spt_cfg::CLK_SRC_SEL_R
• spt::spt_cfg::CLK_SRC_SEL_W
• spt::spt_cfg::FFE_TO_PERIOD_R
• spt::spt_cfg::FFE_TO_PERIOD_W
• spt::spt_cfg::INT_MASK_N_0_R
• spt::spt_cfg::INT_MASK_N_0_W
• spt::spt_cfg::INT_MASK_N_1_W
• spt::spt_cfg::INT_MASK_N_2_W
• spt::spt_cfg::INT_MASK_N_3_W
• spt::spt_cfg::INT_MASK_N_4_W
• spt::spt_cfg::INT_MASK_N_5_W
• spt::spt_cfg::INT_MASK_N_6_W
• spt::spt_cfg::INT_MASK_N_7_W
• spt::spt_cfg::PMU_TO_PERIO_R
• spt::spt_cfg::PMU_TO_PERIO_W
• spt::spt_cfg::R
• spt::spt_cfg::SPT_CFG_SPEC
• spt::spt_cfg::SPT_EN_R
• spt::spt_cfg::SPT_EN_W
• spt::spt_cfg::W
• spt::timer_value::R
• spt::timer_value::TIMER_VALUE_R
• spt::timer_value::TIMER_VALUE_SPEC
• spt::update_tmr_val::R
• spt::update_tmr_val::UPDATE_TIMER_VALUE_R
• spt::update_tmr_val::UPDATE_TIMER_VALUE_W
• spt::update_tmr_val::UPDATE_TMR_VAL_SPEC
• spt::update_tmr_val::W
• timer::RegisterBlock
• timer::cid0::CID0_SPEC
• timer::cid0::PID_R
• timer::cid0::R
• timer::cid1::CID1_SPEC
• timer::cid1::PID_R
• timer::cid1::R
• timer::cid2::CID2_SPEC
• timer::cid2::PID_R
• timer::cid2::R
• timer::cid3::CID3_SPEC
• timer::cid3::PID_R
• timer::cid3::R
• timer::ctrl::CTRL_SPEC
• timer::ctrl::ENABLE_R
• timer::ctrl::ENABLE_W
• timer::ctrl::R
• timer::ctrl::SEL_EXINT_AS_CLOCK_R
• timer::ctrl::SEL_EXINT_AS_CLOCK_W
• timer::ctrl::SEL_EXTINT_AS_ENABLE_R
• timer::ctrl::SEL_EXTINT_AS_ENABLE_W
• timer::ctrl::TIMER_INT_ENABLE_R
• timer::ctrl::TIMER_INT_ENABLE_W
• timer::ctrl::W
• timer::intstatus_intclear::INTSTATUS_INTCLEAR_R
• timer::intstatus_intclear::INTSTATUS_INTCLEAR_SPEC
• timer::intstatus_intclear::INTSTATUS_INTCLEAR_W
• timer::intstatus_intclear::R
• timer::intstatus_intclear::W
• timer::pid0::PID0_SPEC
• timer::pid0::PID_R
• timer::pid0::R
• timer::pid1::PID1_SPEC
• timer::pid1::PID_R
• timer::pid1::R
• timer::pid2::PID2_SPEC
• timer::pid2::PID_R
• timer::pid2::R
• timer::pid3::PID3_SPEC
• timer::pid3::PID_R
• timer::pid3::R
• timer::pid4::PID4_SPEC
• timer::pid4::PID_R
• timer::pid4::R
• timer::pid5::PID5_SPEC
• timer::pid5::PID_R
• timer::pid5::R
• timer::pid6::PID6_SPEC
• timer::pid6::PID_R
• timer::pid6::R
• timer::pid7::PID7_SPEC
• timer::pid7::PID_R
• timer::pid7::R
• timer::reload::R
• timer::reload::RELOAD_R
• timer::reload::RELOAD_SPEC
• timer::reload::RELOAD_W
• timer::reload::W
• timer::value::R
• timer::value::VALUE_R
• timer::value::VALUE_SPEC
• timer::value::VALUE_W
• timer::value::W
• uart::RegisterBlock
• uart::uart_cr::CTSEN_R
• uart::uart_cr::CTSEN_W
• uart::uart_cr::DTR_R
• uart::uart_cr::DTR_W
• uart::uart_cr::LBE_R
• uart::uart_cr::LBE_W
• uart::uart_cr::OUT1_R
• uart::uart_cr::OUT1_W
• uart::uart_cr::OUT2_R
• uart::uart_cr::OUT2_W
• uart::uart_cr::R
• uart::uart_cr::RTSEN_R
• uart::uart_cr::RTSEN_W
• uart::uart_cr::RTS_R
• uart::uart_cr::RTS_W
• uart::uart_cr::RXE_R
• uart::uart_cr::RXE_W
• uart::uart_cr::SIREN_R
• uart::uart_cr::SIREN_W
• uart::uart_cr::SIRLP_R
• uart::uart_cr::SIRLP_W
• uart::uart_cr::TXE_R
• uart::uart_cr::TXE_W
• uart::uart_cr::UARTEN_R
• uart::uart_cr::UARTEN_W
• uart::uart_cr::UART_CR_SPEC
• uart::uart_cr::W
• uart::uart_dr::BE_R
• uart::uart_dr::BE_W
• uart::uart_dr::DATA_R
• uart::uart_dr::DATA_W
• uart::uart_dr::FE_R
• uart::uart_dr::FE_W
• uart::uart_dr::OE_R
• uart::uart_dr::OE_W
• uart::uart_dr::PE_R
• uart::uart_dr::PE_W
• uart::uart_dr::R
• uart::uart_dr::UART_DR_SPEC
• uart::uart_dr::W
• uart::uart_fbrd::R
• uart::uart_fbrd::UART_FBRD_R
• uart::uart_fbrd::UART_FBRD_SPEC
• uart::uart_fbrd::UART_FBRD_W
• uart::uart_fbrd::W
• uart::uart_ibrd::R
• uart::uart_ibrd::UART_IBRD_R
• uart::uart_ibrd::UART_IBRD_SPEC
• uart::uart_ibrd::UART_IBRD_W
• uart::uart_ibrd::W
• uart::uart_icr::BEIC_W
• uart::uart_icr::CTSMIC_W
• uart::uart_icr::DCDMIC_W
• uart::uart_icr::DSRMIC_W
• uart::uart_icr::FEIC_W
• uart::uart_icr::OEIC_W
• uart::uart_icr::PEIC_W
• uart::uart_icr::RIMIC_W
• uart::uart_icr::RTIC_W
• uart::uart_icr::RXIC_W
• uart::uart_icr::TXIC_W
• uart::uart_icr::UART_ICR_SPEC
• uart::uart_icr::W
• uart::uart_ifls::R
• uart::uart_ifls::RXIFLSEL_W
• uart::uart_ifls::TXIFLSEL_R
• uart::uart_ifls::TXIFLSEL_W
• uart::uart_ifls::UART_IFLS_SPEC
• uart::uart_ifls::W
• uart::uart_ilpr::R
• uart::uart_ilpr::UART_ILPR_R
• uart::uart_ilpr::UART_ILPR_SPEC
• uart::uart_ilpr::UART_ILPR_W
• uart::uart_ilpr::W
• uart::uart_imsc::BEIM_R
• uart::uart_imsc::BEIM_W
• uart::uart_imsc::CTSMIM_R
• uart::uart_imsc::CTSMIM_W
• uart::uart_imsc::DCDMIM_R
• uart::uart_imsc::DCDMIM_W
• uart::uart_imsc::DSRMIM_R
• uart::uart_imsc::DSRMIM_W
• uart::uart_imsc::FEIM_R
• uart::uart_imsc::FEIM_W
• uart::uart_imsc::OEIM_R
• uart::uart_imsc::OEIM_W
• uart::uart_imsc::PEIM_R
• uart::uart_imsc::PEIM_W
• uart::uart_imsc::R
• uart::uart_imsc::RMIMIM_R
• uart::uart_imsc::RMIMIM_W
• uart::uart_imsc::RTIM_R
• uart::uart_imsc::RTIM_W
• uart::uart_imsc::RXIM_R
• uart::uart_imsc::RXIM_W
• uart::uart_imsc::TXMIM_R
• uart::uart_imsc::TXMIM_W
• uart::uart_imsc::UART_IMSC_SPEC
• uart::uart_imsc::W
• uart::uart_itip::NUARTCTS_R
• uart::uart_itip::NUARTDCD_R
• uart::uart_itip::NUARTDSR_R
• uart::uart_itip::NUARTRI_R
• uart::uart_itip::R
• uart::uart_itip::SIRIN_R
• uart::uart_itip::UARTRXDMACLR_R
• uart::uart_itip::UARTRXDMACLR_W
• uart::uart_itip::UARTRXD_R
• uart::uart_itip::UARTTXDMACLR_R
• uart::uart_itip::UARTTXDMACLR_W
• uart::uart_itip::UART_ITIP_SPEC
• uart::uart_itip::W
• uart::uart_itop::R
• uart::uart_itop::UART_ITOP_R
• uart::uart_itop::UART_ITOP_SPEC
• uart::uart_itop::UART_ITOP_W
• uart::uart_itop::W
• uart::uart_lcr_h::BRK_R
• uart::uart_lcr_h::BRK_W
• uart::uart_lcr_h::EPS_R
• uart::uart_lcr_h::EPS_W
• uart::uart_lcr_h::FEN_R
• uart::uart_lcr_h::FEN_W
• uart::uart_lcr_h::PEN_R
• uart::uart_lcr_h::PEN_W
• uart::uart_lcr_h::R
• uart::uart_lcr_h::SPS_R
• uart::uart_lcr_h::SPS_W
• uart::uart_lcr_h::STP2_R
• uart::uart_lcr_h::STP2_W
• uart::uart_lcr_h::UART_LCR_H_SPEC
• uart::uart_lcr_h::W
• uart::uart_lcr_h::WLEN_R
• uart::uart_lcr_h::WLEN_W
• uart::uart_mis::BEMIS_R
• uart::uart_mis::CTSMMIS_R
• uart::uart_mis::DCDMMIS_R
• uart::uart_mis::DSRMMIS_R
• uart::uart_mis::FEMIS_R
• uart::uart_mis::OEMIS_R
• uart::uart_mis::PEMIS_R
• uart::uart_mis::R
• uart::uart_mis::RIMMIS_R
• uart::uart_mis::RTMIS_R
• uart::uart_mis::RXMIS_R
• uart::uart_mis::TXMIS_R
• uart::uart_mis::UART_MIS_SPEC
• uart::uart_pcell_id0::R
• uart::uart_pcell_id0::UART_PCELLID0_R
• uart::uart_pcell_id0::UART_PCELLID0_SPEC
• uart::uart_pcell_id1::R
• uart::uart_pcell_id1::UART_PCELLID1_R
• uart::uart_pcell_id1::UART_PCELLID1_SPEC
• uart::uart_pcell_id2::R
• uart::uart_pcell_id2::UART_PCELLID2_R
• uart::uart_pcell_id2::UART_PCELLID2_SPEC
• uart::uart_pcell_id4::R
• uart::uart_pcell_id4::UART_PCELLID4_R
• uart::uart_pcell_id4::UART_PCELLID4_SPEC
• uart::uart_periph_id0::R
• uart::uart_periph_id0::UART_PERIPHID0_R
• uart::uart_periph_id0::UART_PERIPHID0_SPEC
• uart::uart_periph_id1::R
• uart::uart_periph_id1::UART_PERIPHID1_R
• uart::uart_periph_id1::UART_PERIPHID1_SPEC
• uart::uart_periph_id2::R
• uart::uart_periph_id2::UART_PERIPHID2_R
• uart::uart_periph_id2::UART_PERIPHID2_SPEC
• uart::uart_periph_id3::R
• uart::uart_periph_id3::UART_PERIPHID3_R
• uart::uart_periph_id3::UART_PERIPHID3_SPEC
• uart::uart_ris::BEIS_R
• uart::uart_ris::CTSRMIS_R
• uart::uart_ris::DCDRMIS_R
• uart::uart_ris::DSRRMIS_R
• uart::uart_ris::FEIS_R
• uart::uart_ris::OERMIS_R
• uart::uart_ris::PEIS_R
• uart::uart_ris::R
• uart::uart_ris::RIRMIS_R
• uart::uart_ris::RTRIS_R
• uart::uart_ris::RXRMIS_R
• uart::uart_ris::TXRMIS_R
• uart::uart_ris::UART_RIS_SPEC
• uart::uart_rsr::BE_R
• uart::uart_rsr::BE_W
• uart::uart_rsr::FE_R
• uart::uart_rsr::FE_W
• uart::uart_rsr::OE_R
• uart::uart_rsr::OE_W
• uart::uart_rsr::PE_R
• uart::uart_rsr::PE_W
• uart::uart_rsr::R
• uart::uart_rsr::UART_RSR_SPEC
• uart::uart_rsr::W
• uart::uart_tcr::ITEN_W
• uart::uart_tcr::SIRTEST_W
• uart::uart_tcr::TESTFINFO_W
• uart::uart_tcr::UART_TCR_SPEC
• uart::uart_tcr::W
• uart::uart_tdr::R
• uart::uart_tdr::UART_TDR_R
• uart::uart_tdr::UART_TDR_SPEC
• uart::uart_tdr::UART_TDR_W
• uart::uart_tdr::W
• uart::uart_tfr::BUSY_R
• uart::uart_tfr::CTS_R
• uart::uart_tfr::DCD_R
• uart::uart_tfr::DSR_R
• uart::uart_tfr::R
• uart::uart_tfr::RI_R
• uart::uart_tfr::RXFE_R
• uart::uart_tfr::RXFF_R
• uart::uart_tfr::TXFE_R
• uart::uart_tfr::TXFF_R
• uart::uart_tfr::UART_TFR_SPEC
• wdt::RegisterBlock
• wdt::wdogcontrol::INTEN_R
• wdt::wdogcontrol::INTEN_W
• wdt::wdogcontrol::R
• wdt::wdogcontrol::RESEN_R
• wdt::wdogcontrol::RESEN_W
• wdt::wdogcontrol::W
• wdt::wdogcontrol::WDOGCONTROL_SPEC
• wdt::wdogintclr::W
• wdt::wdogintclr::WDOGINTCLR_SPEC
• wdt::wdogintclr::WDOGINTCLR_W
• wdt::wdogitcr::R
• wdt::wdogitcr::W
• wdt::wdogitcr::WDOGITCR_R
• wdt::wdogitcr::WDOGITCR_SPEC
• wdt::wdogitcr::WDOGITCR_W
• wdt::wdogitop::W
• wdt::wdogitop::WDOGITOP_SPEC
• wdt::wdogitop::WDOGITOP_W
• wdt::wdogload::R
• wdt::wdogload::W
• wdt::wdogload::WDGLOAD_R
• wdt::wdogload::WDGLOAD_W
• wdt::wdogload::WDOGLOAD_SPEC
• wdt::wdoglock::R
• wdt::wdoglock::W
• wdt::wdoglock::WDOGLOCK_R
• wdt::wdoglock::WDOGLOCK_SPEC
• wdt::wdoglock::WDOGLOCK_W
• wdt::wdogmis::R
• wdt::wdogmis::WDOGMIS_R
• wdt::wdogmis::WDOGMIS_SPEC
• wdt::wdogpcellid0::R
• wdt::wdogpcellid0::WDOGPCELLID0_R
• wdt::wdogpcellid0::WDOGPCELLID0_SPEC
• wdt::wdogpcellid1::R
• wdt::wdogpcellid1::WDOGPCELLID1_R
• wdt::wdogpcellid1::WDOGPCELLID1_SPEC
• wdt::wdogpcellid2::R
• wdt::wdogpcellid2::WDOGPCELLID2_R
• wdt::wdogpcellid2::WDOGPCELLID2_SPEC
• wdt::wdogpcellid3::R
• wdt::wdogpcellid3::WDOGPCELLID3_R
• wdt::wdogpcellid3::WDOGPCELLID3_SPEC
• wdt::wdogperiphid0::R
• wdt::wdogperiphid0::WDOGPERIPHID0_R
• wdt::wdogperiphid0::WDOGPERIPHID0_SPEC
• wdt::wdogperiphid1::R
• wdt::wdogperiphid1::WDOGPERIPHID1_R
• wdt::wdogperiphid1::WDOGPERIPHID1_SPEC
• wdt::wdogperiphid2::R
• wdt::wdogperiphid2::WDOGPERIPHID2_R
• wdt::wdogperiphid2::WDOGPERIPHID2_SPEC
• wdt::wdogperiphid3::R
• wdt::wdogperiphid3::WDOGPERIPHID3_R
• wdt::wdogperiphid3::WDOGPERIPHID3_SPEC
• wdt::wdogperiphid4::R
• wdt::wdogperiphid4::WDOGPERIPHID4_R
• wdt::wdogperiphid4::WDOGPERIPHID4_SPEC
• wdt::wdogperiphid5::R
• wdt::wdogperiphid5::WDOGPERIPHID5_R
• wdt::wdogperiphid5::WDOGPERIPHID5_SPEC
• wdt::wdogperiphid6::R
• wdt::wdogperiphid6::WDOGPERIPHID6_R
• wdt::wdogperiphid6::WDOGPERIPHID6_SPEC
• wdt::wdogperiphid7::R
• wdt::wdogperiphid7::WDOGPERIPHID7_R
• wdt::wdogperiphid7::WDOGPERIPHID7_SPEC
• wdt::wdogris::R
• wdt::wdogris::W
• wdt::wdogris::WDOGRIS_R
• wdt::wdogris::WDOGRIS_SPEC
• wdt::wdogris::WDOGRIS_W
• wdt::wdogvalue::R
• wdt::wdogvalue::WDGVALUE_R
• wdt::wdogvalue::WDOGVALUE_SPEC

Enums

• Interrupt
• adc::adc_control::BAT_A
• adc::adc_control::SEL_A
• adc::adc_control::SOC_A
• adc::adc_status::EOC_A
• aip::ldo_30_ctrl_0::DISPG_A
• aip::ldo_30_ctrl_0::DIS_A
• aip::ldo_30_ctrl_0::DI_A
• aip::ldo_30_ctrl_0::IMAX_A
• aip::ldo_50_ctrl_0::DISPG_A
• aip::ldo_50_ctrl_0::DIS_A
• aip::ldo_50_ctrl_0::DI_A
• aip::ldo_50_ctrl_0::IMAX_A
• aip::osc_ctrl_0::EN_A
• aip::osc_ctrl_0::FREF16K_SEL_A
• aip::ring_osc::RING_OSC_EN_A
• aud::pdm_core_config::DIV_MODE_A
• aud::voice_config::DMIC_SEL_A
• aud::voice_config::LPSD_MUX_A
• aud::voice_config::LPSD_NO_A
• aud::voice_config::LPSD_SEL_A
• aud::voice_config::LPSD_VOICE_DETECTED_MASK_A
• aud::voice_config::MODE_SEL_A
• aud::voice_config::MONO_CHN_SEL_A
• aud::voice_config::PDM_MIC_SWITCH_TO_AP_A
• aud::voice_config::PDM_VOICE_SCENARIO_A
• cru::audio_misc_sw_reset::AD0_SW_RESET_A
• cru::c01_clk_div::C01_CLK_DIV_CG_A
• cru::c01_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c02_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c08_x1_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c08_x4_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c09_clk_div::C01_CLK_DIV_CG_A
• cru::c09_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_0_GATING_CONTROL_A
• cru::c11_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c16_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c19_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c21_clk_gate::PATH_0_GATING_CONTROL_A
• cru::c30_c31_clk_gate::C30_PATH_0_GATING_CONTROL_A
• cru::c31_clk_div::C01_CLK_DIV_CG_A
• cru::clk_ctrl_a_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_a_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_b_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_b_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_c_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_d_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_e_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_f_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_f_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_g_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_h_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_h_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_i_0::ENABLE_CLOCK_DIVIDER_A
• cru::clk_ctrl_i_1::CLOCK_SOURCE_SELECTION_A
• cru::clk_ctrl_pmu::ENABLE_CLOCK_DIVIDER_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_A_CG_A
• cru::clk_switch_for_b::CLOCK_SOURCE_SELECTION_A
• cru::clk_switch_for_c::CLOCK_SOURCE_SELECTION_A
• cru::clk_switch_for_d::CLOCK_SOURCE_SELECTION_A
• cru::clk_switch_for_g::CLOCK_SOURCE_SELECTION_A
• cru::clk_switch_for_h::CLOCK_SOURCE_SELECTION_A
• cru::clk_switch_for_j::CLOCK_SOURCE_SELECTION_A
• cru::cru_debug::CRU_DEBUG_SELECT_A
• cru::cru_general::SPICLK_ALWAYS_ON_A
• cru::cs_clk_gate::PATH_0_GATING_CONTROL_A
• cru::fb_misc_sw_rst_ctl::AHBWB_SW_RESET_A
• cru::fb_sw_reset::FB_C02_DOMAIN_SW_RESET_A
• cru::ffe_sw_reset::FFE_0_X1_SW_RESET_A
• cru::ffe_sw_reset::FFE_0_X4_SW_RESET_A
• cru::pf_sw_reset::PF_FIFO_0_SW_RESET_A
• dma::dma_intr_mask::DMA_HERROR_MASK_A
• ext_regs_ffe::addr::SLAVE_SEL_A
• ext_regs_ffe::csr::I2C0_MUX_SEL_A
• ext_regs_ffe::csr::MUX_WB_SM_AW
• ext_regs_ffe::csr::WB_MS_WEN_A
• ext_regs_ffe::ffe_csr::I2C2_SEL_A
• ext_regs_ffe::ffe_debug_sel::FFE_TOP_DEBUG_SEL_A
• ext_regs_ffe::interrupt_en::SM_MULT_WR_INTR_EN_A
• extm4regs::config1::BRCHSTAT_A
• extm4regs::config2::BIGEND_A
• i2s_slave::i2s_comp_param_1::APB_DATA_WIDTH_A
• i2s_slave::i2s_comp_param_1::I2S_FIFO_DEPTH_GLOBAL_A
• i2s_slave::i2s_comp_param_1::I2S_MODE_EN_A
• i2s_slave::i2s_comp_param_1::I2S_TX_CHANNELS_A
• i2s_slave::i2s_comp_param_1::I2S_TX_WORDSIZE_0_A
• i2s_slave::i2s_stereo_en::I2S_STEREO_EN_A
• i2s_slave::ier::IEN_A
• i2s_slave::imr0::RXFOM_A
• i2s_slave::isr0::TXFE_A
• i2s_slave::isr0::TXFO_A
• i2s_slave::iter::TXEN_A
• i2s_slave::tcr0::WLEN_A
• i2s_slave::ter0::TXCHEN0_A
• intr_ctrl::fb_intr_en_ap::FB_0_INTR_EN_AP_A
• intr_ctrl::fb_intr_en_m4::FB_0_INTR_EN_M4_A
• intr_ctrl::fb_intr_pol::FB_0_INTR_POL_A
• intr_ctrl::fb_intr_type::FB_0_INTR_TYPE_A
• intr_ctrl::ffe_intr_en_ap::FFE0_0_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_m4::FFE0_0_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_ap::GPIO_0_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_0_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_0_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_m4::GPIO_1_INTR_EN_M4_A
• intr_ctrl::gpio_intr_pol::GPIO_0_INTR_POL_A
• intr_ctrl::gpio_intr_type::GPIO_O_INTR_TYPE_A
• intr_ctrl::other_intr_en_ap::M4_SRAM_INTR_EN_AP_A
• intr_ctrl::other_intr_en_m4::M4_SRAM_INTR_EN_M4_A
• intr_ctrl::software_intr_en_m4::SW_INTR_2_EN_M4_A
• iomux::fbio_sel_1::SEL_A
• iomux::fbio_sel_2::SEL_A
• iomux::i2s_data_select::SEL_A
• iomux::io_reg_sel::IO_SEL_0_A
• iomux::io_reg_sel::IO_SEL_1_A
• iomux::io_reg_sel::IO_SEL_2_A
• iomux::io_reg_sel::IO_SEL_3_A
• iomux::io_reg_sel::IO_SEL_4_A
• iomux::io_reg_sel::IO_SEL_5_A
• iomux::io_reg_sel::IO_SEL_6_A
• iomux::io_reg_sel::IO_SEL_7_A
• iomux::ir_da_sirin_sel::SEL_A
• iomux::pad__ctrl::CTRL_SEL_A
• iomux::pad__ctrl::E_A
• iomux::pad__ctrl::FUNC_SEL_A
• iomux::pad__ctrl::OEN_A
• iomux::pad__ctrl::P_A
• iomux::pad__ctrl::REN_A
• iomux::pad__ctrl::SMT_A
• iomux::pad__ctrl::SR_A
• iomux::pad__ctrl_ffe::CTRL_SEL_A
• iomux::pad__ctrl_ffe::E_A
• iomux::pad__ctrl_ffe::FUNC_SEL_A
• iomux::pad__ctrl_ffe::OEN_A
• iomux::pad__ctrl_ffe::P_A
• iomux::pad__ctrl_ffe::REN_A
• iomux::pad__ctrl_ffe::SMT_A
• iomux::pad__ctrl_ffe::SR_A
• iomux::pdm_data_sele::SEL_A
• iomux::s_intr_0_sel_reg::SEL_A
• iomux::s_intr_1_sel_reg::SEL_A
• iomux::s_intr_2_sel::SEL_A
• iomux::s_intr_3_sel::SEL_A
• iomux::s_intr_4_sel::SEL_A
• iomux::s_intr_5_sel::SEL_A
• iomux::s_intr_6_sel::SEL_A
• iomux::s_intr_7_sel::SEL_A
• iomux::scl0_sel_reg::SEL_A
• iomux::scl1_sel_reg::SEL_A
• iomux::scl2_sel_reg::SEL_A
• iomux::sda0_sel_reg::SEL_A
• iomux::sda1_sel_reg::SEL_A
• iomux::sda2_sel_reg::SEL_A
• iomux::spi_sensor_miso_sel::SEL_A
• iomux::spi_sensor_mosi_sel::SEL_A
• iomux::sw_clk_sel::SEL_A
• iomux::sw_io_sel::SEL_A
• iomux::uart_rxd_sel::SEL_A
• misc::a0_dbg_mon_sel::A0_DEBUG_MON_SEL_A
• misc::a0_pmu_dbg_mon_sel::A0_PMU_DEBUG_MON_SEL_A
• misc::lock_key_ctrl::LOCK_KEY_EN_A
• misc::subsys_dbg_mon_sel::SUBSYS_DEBUG_MON_SEL_A
• pkfb::pkfb_fifo_coll_intr_en::PF0_COLL_INTR_EN_A
• pkfb::pkfb_fifoctrl::PF0_EN_A
• pkfb::pkfb_fifoctrl::PF0_FFE_SEL_A
• pkfb::pkfb_fifoctrl::PF0_POP_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF0_POP_MUX_A
• pkfb::pkfb_fifoctrl::PF0_PUSH_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF0_PUSH_MUX_A
• pkfb::pkfb_fifostatus::PF0_SRAM_SLEEP_A
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_OV_A
• pkfb::pkfb_pf0popctl::PF0_POP_SLEEP_TYPE_A
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_OV_A
• pkfb::pkfb_pf0pushctl::PF0_PUSH_SLEEP_TYPE_A
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_OV_A
• pkfb::pkfb_pf1popctl::PF1_POP_SLEEP_TYPE_A
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_OV_A
• pkfb::pkfb_pf1pushctl::PF1_PUSH_SLEEP_TYPE_A
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_OV_A
• pkfb::pkfb_pf2popctl::PF2_POP_SLEEP_TYPE_A
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_OV_A
• pkfb::pkfb_pf2pushctl::PF2_PUSH_SLEEP_TYPE_A
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_OV_A
• pkfb::pkfb_pf8kpopctl::PF8K_POP_SLEEP_TYPE_A
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_OV_A
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_SLEEP_TYPE_A
• pmu::a1_pwr_mode_cfg::A1_POWER_MODE_CFG_A
• pmu::a1_wu_src_mask_n::A1_WU_EVENT_MASK_M_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_0_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_0_A
• pmu::audio_sram_sw_wu::AUDIO_AD0_WU_A
• pmu::audio_sw_pd::AUDIO_AD0_PD_A
• pmu::audio_wu_src_mask_n::AD0_WU_EVENT_MASK_N_A
• pmu::chip_sta_1::CLOCK_BYPASS_CFG_A
• pmu::chip_sta_1::CODE_SOURCE_CFG_A
• pmu::chip_sta_1::DEBUG_PORT_CFG_A
• pmu::chip_sta_1::FFE0_BUSY_A
• pmu::chip_sta_1::SWD_MODE_CFG_A
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_0_A
• pmu::fb_pwr_mode_cfg::FB_POWER_MODE_CFG_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_0_INT_A
• pmu::ffe_fb_pf_sw_pd::FFE_SOFTWARE_PD_A
• pmu::ffe_fb_pf_sw_wu::FFE_SOFTWARE_WU_A
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_0_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM0_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM0_A
• pmu::ffe_pd_src_mask_n::FFE_PD_EVENT_MASK_A
• pmu::ffe_pwr_mode_cfg::FFE_POWER_MODE_CFG_A
• pmu::ffe_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_0_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_0_A
• pmu::m4_pwr_mode_cfg::M4_POWER_MODE_CFG_A
• pmu::m4_sram_sw_pd::M4S0_SOFTWARE_PD_A
• pmu::m4_sram_sw_wu::M4S0_SOFTWARE_WU_A
• pmu::m4s0_pd_src_mask_n::M4S0_PD_EVENT_MASK_A
• pmu::m4s0_pwr_mode_cfg::M4S0_POWER_MODE_CFG_A
• pmu::m4sram_ssw_lpmf::M4SRAM_LPMF_A
• pmu::m4sram_ssw_lpmh_mask_n::M4SRAM_LPMH_MASK_N_A
• pmu::misc_por_0::M4_RST_RELEASE_A
• pmu::misc_por_1::CFG_FPD_ON_A
• pmu::misc_por_1::SYS_RST_AS_INT_A
• pmu::misc_por_1::SYS_RST_AS_INT_PW_A
• pmu::misc_por_1::SYS_RST_PULSE_EXT_A
• pmu::misc_por_2::AP_REBOOT_ENABLE_N_A
• pmu::misc_por_2::SPI_REBOOT_ENABLE_N_A
• pmu::misc_sw_pd::SDMA_SOFTWARE_PD_A
• pmu::misc_sw_wu::SDMA_SOFTWARE_WU_A
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_0_A
• pmu::pf_pwr_mode_cfg::PF_POWER_MODE_CFG_A
• pmu::pmu_stm_priority::PMU_STM_PRIORITY_A
• pmu::pwr_dwn_sch::AUDIO_PD_A
• pmu::pwr_dwn_sch::AUDIO_WU_A
• pmu::pwr_dwn_sch::FFEFB_PD_A
• pmu::pwr_dwn_sch::FFEFB_WU_A
• pmu::pwr_dwn_sch::M4M4S0_PD_A
• pmu::pwr_dwn_sch::M4M4S0_WU_A
• pmu::pwr_dwn_sch::SRAM_PD_A
• pmu::pwr_dwn_sch::SRAM_WU_A
• pmu::sdma_mem_ctrl_0::SDMA_SRAM_DS_A
• pmu::sdma_mem_ctrl_1::SDMA_SRAM_SD_A
• pmu::sdma_pd_src_mask_n::SDMA_PD_EVENT_A
• pmu::sdma_power_mode_cfg::SDMA_POWER_MODE_CFG_A
• sdma::dma_status::STATE_A
• spi::ctrlr0::CFS_A
• spi::ctrlr0::DFS_A
• spi::ctrlr0::SCPH_A
• spi::ctrlr0::SCPOL_A
• spi::ctrlr0::SRL_A
• spi::ctrlr0::TMOD_A
• spi::imr::TXEIM_A
• spi_tlc::tamarstatus::M4POWERSTATUS_A
• spi_tlc::tamarstatus::M4REBOOTREQ_A
• spi_tlc::tamarstatus::M4RESETSTATUS_A
• spt::spt_cfg::CLK_SRC_SEL_A
• spt::spt_cfg::INT_MASK_N_0_A
• spt::spt_cfg::SPT_EN_A
• uart::uart_cr::SIREN_A
• uart::uart_cr::UARTEN_A
• uart::uart_ifls::TXIFLSEL_A
• uart::uart_lcr_h::EPS_A
• uart::uart_lcr_h::FEN_A
• uart::uart_lcr_h::PEN_A
• uart::uart_lcr_h::SPS_A
• uart::uart_lcr_h::WLEN_A
• wdt::wdogitop::WDOGITOP_AW
• wdt::wdoglock::WDOGLOCK_A

Traits

• generic::Readable
• generic::RegisterSpec
• generic::Resettable
• generic::Writable

Type Aliases

• a1_regs::CFG_CTRL
• adc::ADC_CONTROL
• adc::ADC_OUT
• adc::ADC_STATUS
• aip::APC_CTRL_0
• aip::APC_CTRL_1
• aip::APC_CTRL_2
• aip::APC_CTRL_3
• aip::APC_CTRL_4
• aip::APC_CTRL_5
• aip::APC_CTRL_6
• aip::APC_CTRL_7
• aip::APC_STA_0
• aip::APC_STA_1
• aip::LDO_30_CTRL_0
• aip::LDO_30_CTRL_1
• aip::LDO_50_CTRL_0
• aip::LDO_50_CTRL_1
• aip::OSC_CTRL_0
• aip::OSC_CTRL_1
• aip::OSC_CTRL_2
• aip::OSC_CTRL_3
• aip::OSC_CTRL_4
• aip::OSC_CTRL_5
• aip::OSC_CTRL_6
• aip::OSC_CTRL_7
• aip::OSC_STA_0
• aip::OSC_STA_1
• aip::RING_OSC
• aip::RTC_CTRL_1
• aip::RTC_CTRL_2
• aip::RTC_CTRL_3
• aip::RTC_CTRL_4
• aip::RTC_CTRL_5
• aip::RTC_CTRL_6
• aip::RTC_CTRL_7
• aip::RTC_STA_0
• aip::RTC_STA_1
• aud::DBG_MUX_CFG
• aud::FIFO_SRAM_CFG
• aud::I2S_CONFIG
• aud::LPSD_CONFIG
• aud::PDMA_SRAM_CFG
• aud::PDM_CORE_CONFIG
• aud::VOICE_CONFIG
• aud::VOICE_DMAC_DST_ADDR0
• aud::VOICE_DMAC_DST_ADDR1
• aud::VOICE_DMAC_FIFO
• aud::VOICE_DMAC_LEN
• aud::VOICE_DMA_CONFIG
• aud::VOICE_STATUS
• aud::voice_config::AP_PDM_CLK_IB_MASK_A
• aud::voice_config::AP_PDM_CLK_IB_MASK_R
• aud::voice_config::AP_PDM_CLK_OFF_MASK_A
• aud::voice_config::AP_PDM_CLK_OFF_MASK_R
• aud::voice_config::DMAC_BLK_DONE_MASK_A
• aud::voice_config::DMAC_BLK_DONE_MASK_R
• aud::voice_config::DMAC_BUF_DONE_MASK_A
• aud::voice_config::DMAC_BUF_DONE_MASK_R
• aud::voice_config::DMIC_VOICE_DETECTED_MASK_A
• aud::voice_config::DMIC_VOICE_DETECTED_MASK_R
• cfg_ctl::CFG_CTL
• cfg_ctl::CFG_DATA
• cfg_ctl::MAX_BL_CNT
• cfg_ctl::MAX_WL_CNT
• cfg_ctl::RAMFIFO0
• cfg_ctl::RAMFIFO1
• cfg_ctl::RAMFIFO2
• cfg_ctl::RAMFIFO3
• cru::A1_SW_RESET
• cru::AUDIO_MISC_SW_RESET
• cru::C01_CLK_DIV
• cru::C01_CLK_GATE
• cru::C02_CLK_GATE
• cru::C08_X1_CLK_GATE
• cru::C08_X4_CLK_GATE
• cru::C09_CLK_DIV
• cru::C09_CLK_GATE
• cru::C10_FCLK_GATE
• cru::C11_CLK_GATE
• cru::C12_CLK_GATE_RESERVED
• cru::C16_CLK_GATE
• cru::C19_CLK_GATE
• cru::C21_CLK_GATE
• cru::C30_C31_CLK_GATE
• cru::C31_CLK_DIV
• cru::CLK_CTRL_A_0
• cru::CLK_CTRL_A_1
• cru::CLK_CTRL_B_0
• cru::CLK_CTRL_B_1
• cru::CLK_CTRL_C_0
• cru::CLK_CTRL_D_0
• cru::CLK_CTRL_E_0
• cru::CLK_CTRL_E_1
• cru::CLK_CTRL_F_0
• cru::CLK_CTRL_F_1
• cru::CLK_CTRL_G_0
• cru::CLK_CTRL_H_0
• cru::CLK_CTRL_H_1
• cru::CLK_CTRL_I_0
• cru::CLK_CTRL_I_1
• cru::CLK_CTRL_PMU
• cru::CLK_DIVIDER_CLK_GATING
• cru::CLK_RESERVED_0
• cru::CLK_SWITCH_FOR_B
• cru::CLK_SWITCH_FOR_C
• cru::CLK_SWITCH_FOR_D
• cru::CLK_SWITCH_FOR_G
• cru::CLK_SWITCH_FOR_H
• cru::CLK_SWITCH_FOR_J
• cru::CRU_DEBUG
• cru::CRU_GENERAL
• cru::CS_CLK_GATE
• cru::CU_CLK_GATE_RESERVED
• cru::FB_MISC_SW_RST_CTL
• cru::FB_SW_RESET
• cru::FFE_SW_RESET
• cru::PF_SW_RESET
• cru::audio_misc_sw_reset::AD1_SW_RESET_A
• cru::audio_misc_sw_reset::AD1_SW_RESET_R
• cru::audio_misc_sw_reset::AD2_SW_RESET_A
• cru::audio_misc_sw_reset::AD2_SW_RESET_R
• cru::audio_misc_sw_reset::AD3_SW_RESET_A
• cru::audio_misc_sw_reset::AD3_SW_RESET_R
• cru::audio_misc_sw_reset::AD4_SW_RESET_A
• cru::audio_misc_sw_reset::AD4_SW_RESET_R
• cru::audio_misc_sw_reset::AD5_SW_RESET_A
• cru::audio_misc_sw_reset::AD5_SW_RESET_R
• cru::audio_misc_sw_reset::DMA_SW_RESET_A
• cru::audio_misc_sw_reset::DMA_SW_RESET_R
• cru::audio_misc_sw_reset::I2S_SW_RESET_A
• cru::audio_misc_sw_reset::I2S_SW_RESET_R
• cru::c01_clk_gate::PATH_1_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_1_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_2_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_2_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_3_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_3_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_4_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_4_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_5_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_5_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_6_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_6_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_7_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_7_GATING_CONTROL_R
• cru::c01_clk_gate::PATH_9_GATING_CONTROL_A
• cru::c01_clk_gate::PATH_9_GATING_CONTROL_R
• cru::c02_clk_gate::PATH_1_GATING_CONTROL_A
• cru::c02_clk_gate::PATH_1_GATING_CONTROL_R
• cru::c02_clk_gate::PATH_2_GATING_CONTROL_A
• cru::c02_clk_gate::PATH_2_GATING_CONTROL_R
• cru::c08_x1_clk_gate::PATH_2_GATING_CONTROL_A
• cru::c08_x1_clk_gate::PATH_2_GATING_CONTROL_R
• cru::c08_x1_clk_gate::PATH_3_GATING_CONTROL_A
• cru::c08_x1_clk_gate::PATH_3_GATING_CONTROL_R
• cru::c09_clk_gate::PATH_1_GATING_CONTROL_A
• cru::c09_clk_gate::PATH_1_GATING_CONTROL_R
• cru::c09_clk_gate::PATH_2_GATING_CONTROL_A
• cru::c09_clk_gate::PATH_2_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_1_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_1_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_2_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_2_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_3_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_3_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_4_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_4_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_5_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_5_GATING_CONTROL_R
• cru::c10_fclk_gate::PATH_6_GATING_CONTROL_A
• cru::c10_fclk_gate::PATH_6_GATING_CONTROL_R
• cru::c30_c31_clk_gate::C30_PATH_1_GATING_CONTROL_A
• cru::c30_c31_clk_gate::C30_PATH_1_GATING_CONTROL_R
• cru::c30_c31_clk_gate::C30_PATH_2_GATING_CONTROL_A
• cru::c30_c31_clk_gate::C30_PATH_2_GATING_CONTROL_R
• cru::c30_c31_clk_gate::C31_PATH_0_GATING_CONTROL_A
• cru::c30_c31_clk_gate::C31_PATH_0_GATING_CONTROL_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_B_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_B_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_C_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_C_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_D_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_D_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_F_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_F_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_G_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_G_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_H_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_H_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_I_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_I_CG_R
• cru::clk_divider_clk_gating::CLK_DIVIDER_J_CG_A
• cru::clk_divider_clk_gating::CLK_DIVIDER_J_CG_R
• cru::fb_misc_sw_rst_ctl::PFAFIFO1_SW_RESET_A
• cru::fb_misc_sw_rst_ctl::PFAFIFO1_SW_RESET_R
• cru::fb_sw_reset::FB_C09_DOMAIN_SW_RESET_A
• cru::fb_sw_reset::FB_C09_DOMAIN_SW_RESET_R
• cru::fb_sw_reset::FB_C16_DOMAIN_SW_RESET_A
• cru::fb_sw_reset::FB_C16_DOMAIN_SW_RESET_R
• cru::fb_sw_reset::FB_C21_DOMAIN_SW_RESET_A
• cru::fb_sw_reset::FB_C21_DOMAIN_SW_RESET_R
• cru::pf_sw_reset::PF_ASYNC_FIFO_0_SW_RESET_A
• cru::pf_sw_reset::PF_ASYNC_FIFO_0_SW_RESET_R
• cru::pf_sw_reset::PF_FIFO_1_SW_RESET_A
• cru::pf_sw_reset::PF_FIFO_1_SW_RESET_R
• cru::pf_sw_reset::PF_FIFO_2_SW_RESET_A
• cru::pf_sw_reset::PF_FIFO_2_SW_RESET_R
• cru::pf_sw_reset::PF_FIFO_8K_SW_RESET_A
• cru::pf_sw_reset::PF_FIFO_8K_SW_RESET_R
• cru::pf_sw_reset::PF_PERIPHERAL_SW_RESET_A
• cru::pf_sw_reset::PF_PERIPHERAL_SW_RESET_R
• dma::CFG_FLASH_HEADER
• dma::CFG_MACHINE_ST_DELAY
• dma::DMA_CTRL
• dma::DMA_DEST_ADDR
• dma::DMA_INTR
• dma::DMA_INTR_MASK
• dma::DMA_XFER_CNT
• dma::dma_intr_mask::AHB_BRIDGE_FIFO_OVERFLOW_MASK_A
• dma::dma_intr_mask::AHB_BRIDGE_FIFO_OVERFLOW_MASK_R
• dma::dma_intr_mask::RX_DATA_AVAILABLE_MASK_A
• dma::dma_intr_mask::RX_DATA_AVAILABLE_MASK_R
• ext_regs_ffe::ADDR
• ext_regs_ffe::CMD
• ext_regs_ffe::CSR
• ext_regs_ffe::FFE0_BP_XPC_0
• ext_regs_ffe::FFE0_BP_XPC_1
• ext_regs_ffe::FFE0_BP_XPC_2
• ext_regs_ffe::FFE0_BP_XPC_3
• ext_regs_ffe::FFE0_BREAK_POINT_CFG
• ext_regs_ffe::FFE0_BREAK_POINT_CONT
• ext_regs_ffe::FFE0_BREAK_POINT_STAT
• ext_regs_ffe::FFE_CSR
• ext_regs_ffe::FFE_DBG_COMBINED
• ext_regs_ffe::FFE_DEBUG_SEL
• ext_regs_ffe::INTERRUPT
• ext_regs_ffe::INTERRUPT_EN
• ext_regs_ffe::MAILBOX_TO_FFE0
• ext_regs_ffe::RDATA
• ext_regs_ffe::SM0_DEBUG_SEL
• ext_regs_ffe::SM0_RUNTIME_ADDR_CTRL
• ext_regs_ffe::SM0_RUNTIME_ADDR_CUR
• ext_regs_ffe::SM1_DEBUG_SEL
• ext_regs_ffe::SM1_RUNTIME_ADDR_CTRL
• ext_regs_ffe::SM1_RUNTIME_ADDR_CUR
• ext_regs_ffe::SM_RUNTIME_ADDR
• ext_regs_ffe::SRAM_TEST_REG1
• ext_regs_ffe::SRAM_TEST_REG2
• ext_regs_ffe::STATUS
• ext_regs_ffe::WDATA
• ext_regs_ffe::csr::I2C1_MUX_SEL_A
• ext_regs_ffe::csr::I2C1_MUX_SEL_R
• ext_regs_ffe::csr::SPI0_MUX_SEL_A
• ext_regs_ffe::csr::SPI0_MUX_SEL_R
• ext_regs_ffe::interrupt_en::AHBM_BUS_ERROR_INTR_EN_A
• ext_regs_ffe::interrupt_en::AHBM_BUS_ERROR_INTR_EN_R
• ext_regs_ffe::interrupt_en::CM_2K_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::CM_2K_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::CM_8K_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::CM_8K_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::DM0_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::DM0_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::DM1_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::DM1_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::DM2_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::DM2_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::DM3_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::DM3_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::FFE0_BP_MATCH_INTR_EN_A
• ext_regs_ffe::interrupt_en::FFE0_BP_MATCH_INTR_EN_R
• ext_regs_ffe::interrupt_en::FFE0_OVERRUN_EN_A
• ext_regs_ffe::interrupt_en::FFE0_OVERRUN_EN_R
• ext_regs_ffe::interrupt_en::FFE0_SM0_OVERRUN_EN_A
• ext_regs_ffe::interrupt_en::FFE0_SM0_OVERRUN_EN_R
• ext_regs_ffe::interrupt_en::FFE0_SM1_OVERRUN_EN_A
• ext_regs_ffe::interrupt_en::FFE0_SM1_OVERRUN_EN_R
• ext_regs_ffe::interrupt_en::FFE1_OVERRUN_EN_A
• ext_regs_ffe::interrupt_en::FFE1_OVERRUN_EN_R
• ext_regs_ffe::interrupt_en::I2C_MS_0_ERROR_EN_A
• ext_regs_ffe::interrupt_en::I2C_MS_0_ERROR_EN_R
• ext_regs_ffe::interrupt_en::I2C_MS_1_ERROR_EN_A
• ext_regs_ffe::interrupt_en::I2C_MS_1_ERROR_EN_R
• ext_regs_ffe::interrupt_en::PKFB_OVF_EN_A
• ext_regs_ffe::interrupt_en::PKFB_OVF_EN_R
• ext_regs_ffe::interrupt_en::SM0_BP_MATCH_INTR_EN_A
• ext_regs_ffe::interrupt_en::SM0_BP_MATCH_INTR_EN_R
• ext_regs_ffe::interrupt_en::SM0_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::SM0_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::SM1_BP_MATCH_INTR_EN_A
• ext_regs_ffe::interrupt_en::SM1_BP_MATCH_INTR_EN_R
• ext_regs_ffe::interrupt_en::SM1_LP_INTR_EN_A
• ext_regs_ffe::interrupt_en::SM1_LP_INTR_EN_R
• ext_regs_ffe::interrupt_en::SPI_MS_INTR_EN_A
• ext_regs_ffe::interrupt_en::SPI_MS_INTR_EN_R
• extm4regs::A1_POWER_STAT
• extm4regs::CONFIG1
• extm4regs::CONFIG2
• extm4regs::CONFIG_FP1
• extm4regs::CONFIG_FP2
• extm4regs::CONFIG_MEM1
• extm4regs::CONFIG_MEM2
• extm4regs::CONFIG_MEM3
• extm4regs::FB_RAMFIFO
• extm4regs::M4_MEM_INT
• extm4regs::M4_MEM_INTR_EN
• extm4regs::SYSTICK_REG
• extm4regs::TO_INTR
• extm4regs::TO_INTR_EN
• i2s_slave::I2S_COMP_PARAM_1
• i2s_slave::I2S_COMP_TYPE
• i2s_slave::I2S_COMP_VERSION
• i2s_slave::I2S_STEREO_EN
• i2s_slave::IER
• i2s_slave::IMR0
• i2s_slave::ISR0
• i2s_slave::ITER
• i2s_slave::LTHR0
• i2s_slave::RTHR0
• i2s_slave::RTXDMA
• i2s_slave::TCR0
• i2s_slave::TER0
• i2s_slave::TFCR0
• i2s_slave::TFF0
• i2s_slave::TOR0
• i2s_slave::TXDMA
• i2s_slave::TXFFR
• i2s_slave::imr0::TXFOM_A
• i2s_slave::imr0::TXFOM_R
• intr_ctrl::FB_INTR
• intr_ctrl::FB_INTR_EN_AP
• intr_ctrl::FB_INTR_EN_M4
• intr_ctrl::FB_INTR_POL
• intr_ctrl::FB_INTR_RAW
• intr_ctrl::FB_INTR_TYPE
• intr_ctrl::FFE_INTR
• intr_ctrl::FFE_INTR_EN_AP
• intr_ctrl::FFE_INTR_EN_M4
• intr_ctrl::GPIO_INTR
• intr_ctrl::GPIO_INTR_EN_AP
• intr_ctrl::GPIO_INTR_EN_FFE0
• intr_ctrl::GPIO_INTR_EN_FFE1
• intr_ctrl::GPIO_INTR_EN_M4
• intr_ctrl::GPIO_INTR_POL
• intr_ctrl::GPIO_INTR_RAW
• intr_ctrl::GPIO_INTR_TYPE
• intr_ctrl::M4_MEM_AON_INTR
• intr_ctrl::M4_MEM_AON_INTR_EN
• intr_ctrl::OTHER_INTR
• intr_ctrl::OTHER_INTR_EN_AP
• intr_ctrl::OTHER_INTR_EN_M4
• intr_ctrl::SOFTWARE_INTR_1
• intr_ctrl::SOFTWARE_INTR_1_EN_AP
• intr_ctrl::SOFTWARE_INTR_2
• intr_ctrl::SOFTWARE_INTR_2_EN_AP
• intr_ctrl::SOFTWARE_INTR_EN_M4
• intr_ctrl::fb_intr_en_ap::FB_1_INTR_EN_AP_A
• intr_ctrl::fb_intr_en_ap::FB_1_INTR_EN_AP_R
• intr_ctrl::fb_intr_en_ap::FB_2_INTR_EN_AP_A
• intr_ctrl::fb_intr_en_ap::FB_2_INTR_EN_AP_R
• intr_ctrl::fb_intr_en_ap::FB_3_INTR_EN_AP_A
• intr_ctrl::fb_intr_en_ap::FB_3_INTR_EN_AP_R
• intr_ctrl::fb_intr_en_m4::FB_1_INTR_EN_M4_A
• intr_ctrl::fb_intr_en_m4::FB_1_INTR_EN_M4_R
• intr_ctrl::fb_intr_en_m4::FB_2_INTR_EN_M4_A
• intr_ctrl::fb_intr_en_m4::FB_2_INTR_EN_M4_R
• intr_ctrl::fb_intr_en_m4::FB_3_INTR_EN_M4_A
• intr_ctrl::fb_intr_en_m4::FB_3_INTR_EN_M4_R
• intr_ctrl::fb_intr_pol::FB_1_INTR_POL_A
• intr_ctrl::fb_intr_pol::FB_1_INTR_POL_R
• intr_ctrl::fb_intr_pol::FB_2_INTR_POL_A
• intr_ctrl::fb_intr_pol::FB_2_INTR_POL_R
• intr_ctrl::fb_intr_pol::FB_3_INTR_POL_A
• intr_ctrl::fb_intr_pol::FB_3_INTR_POL_R
• intr_ctrl::fb_intr_type::FB_1_INTR_TYPE_A
• intr_ctrl::fb_intr_type::FB_1_INTR_TYPE_R
• intr_ctrl::fb_intr_type::FB_2_INTR_TYPE_A
• intr_ctrl::fb_intr_type::FB_2_INTR_TYPE_R
• intr_ctrl::fb_intr_type::FB_3_INTR_TYPE_A
• intr_ctrl::fb_intr_type::FB_3_INTR_TYPE_R
• intr_ctrl::ffe_intr_en_ap::FFE0_1_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_1_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_2_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_2_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_3_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_3_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_4_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_4_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_5_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_5_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_6_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_6_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_ap::FFE0_7_INTR_EN_AP_A
• intr_ctrl::ffe_intr_en_ap::FFE0_7_INTR_EN_AP_R
• intr_ctrl::ffe_intr_en_m4::FFE0_1_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_1_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_2_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_2_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_3_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_3_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_4_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_4_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_5_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_5_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_6_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_6_INTR_EN_M4_R
• intr_ctrl::ffe_intr_en_m4::FFE0_7_INTR_EN_M4_A
• intr_ctrl::ffe_intr_en_m4::FFE0_7_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_ap::GPIO_1_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_1_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_2_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_2_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_3_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_3_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_4_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_4_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_5_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_5_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_6_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_6_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ap::GPIO_7_INTR_EN_AP_A
• intr_ctrl::gpio_intr_en_ap::GPIO_7_INTR_EN_AP_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_1_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_1_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_2_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_2_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_3_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_3_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_4_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_4_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_5_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_5_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_6_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_6_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe0::GPIO_7_INTR_EN_FFE0_A
• intr_ctrl::gpio_intr_en_ffe0::GPIO_7_INTR_EN_FFE0_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_1_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_1_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_2_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_2_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_3_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_3_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_4_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_4_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_5_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_5_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_6_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_6_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_ffe1::GPIO_7_INTR_EN_FFE1_A
• intr_ctrl::gpio_intr_en_ffe1::GPIO_7_INTR_EN_FFE1_R
• intr_ctrl::gpio_intr_en_m4::GPIO_2_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_2_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_3_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_3_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_4_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_4_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_5_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_5_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_6_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_6_INTR_EN_M4_R
• intr_ctrl::gpio_intr_en_m4::GPIO_7_INTR_EN_M4_A
• intr_ctrl::gpio_intr_en_m4::GPIO_7_INTR_EN_M4_R
• intr_ctrl::gpio_intr_pol::GPIO_1_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_1_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_2_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_2_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_3_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_3_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_4_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_4_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_5_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_5_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_6_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_6_INTR_POL_R
• intr_ctrl::gpio_intr_pol::GPIO_7_INTR_POL_A
• intr_ctrl::gpio_intr_pol::GPIO_7_INTR_POL_R
• intr_ctrl::gpio_intr_type::GPIO_1_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_1_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_2_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_2_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_3_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_3_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_4_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_4_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_5_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_5_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_6_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_6_INTR_TYPE_R
• intr_ctrl::gpio_intr_type::GPIO_7_INTR_TYPE_A
• intr_ctrl::gpio_intr_type::GPIO_7_INTR_TYPE_R
• intr_ctrl::other_intr_en_ap::ADC_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::ADC_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::APBOOT_EN_AP_A
• intr_ctrl::other_intr_en_ap::APBOOT_EN_AP_R
• intr_ctrl::other_intr_en_ap::CFG_DMA_DONE_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::CFG_DMA_DONE_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::DMIC_VOICE_DET_EN_AP_A
• intr_ctrl::other_intr_en_ap::DMIC_VOICE_DET_EN_AP_R
• intr_ctrl::other_intr_en_ap::FFE0_INTR_OTHERS_EN_AP_A
• intr_ctrl::other_intr_en_ap::FFE0_INTR_OTHERS_EN_AP_R
• intr_ctrl::other_intr_en_ap::FPU_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::FPU_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::LDO30_PG_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::LDO30_PG_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::LDO50_PG_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::LDO50_PG_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::LPSD_VOICE_DET_EN_AP_A
• intr_ctrl::other_intr_en_ap::LPSD_VOICE_DET_EN_AP_R
• intr_ctrl::other_intr_en_ap::PKFB_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::PKFB_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::PMU_TMR_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::PMU_TMR_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::RST_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::RST_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::RTC_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::RTC_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::SPI_MS_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::SPI_MS_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::SRAM_128KB_TIMEOUT_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::SRAM_128KB_TIMEOUT_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::TIMEOUT_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::TIMEOUT_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::TIMER_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::TIMER_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::UART_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::UART_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::WDOG_INTR_EN_AP_A
• intr_ctrl::other_intr_en_ap::WDOG_INTR_EN_AP_R
• intr_ctrl::other_intr_en_ap::WDOG_RST_EN_AP_A
• intr_ctrl::other_intr_en_ap::WDOG_RST_EN_AP_R
• intr_ctrl::other_intr_en_m4::ADC_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::ADC_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::APBOOT_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::APBOOT_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::CFG_DMA_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::CFG_DMA_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::DMIC_VOICE_DET_EN_M4_A
• intr_ctrl::other_intr_en_m4::DMIC_VOICE_DET_EN_M4_R
• intr_ctrl::other_intr_en_m4::FFE0_INTR_OTHERS_EN_M4_A
• intr_ctrl::other_intr_en_m4::FFE0_INTR_OTHERS_EN_M4_R
• intr_ctrl::other_intr_en_m4::FPU_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::FPU_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::LDO30_PG_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::LDO30_PG_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::LDO50_PG_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::LDO50_PG_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::LPSD_VOICE_DET_EN_M4_A
• intr_ctrl::other_intr_en_m4::LPSD_VOICE_DET_EN_M4_R
• intr_ctrl::other_intr_en_m4::PKFB_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::PKFB_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::PMU_TMR_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::PMU_TMR_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::RST_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::RST_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::RTC_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::RTC_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::SPI_MS_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::SPI_MS_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::TIMEOUT_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::TIMEOUT_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::TIMER_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::TIMER_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::UART_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::UART_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::WDOG_INTR_EN_M4_A
• intr_ctrl::other_intr_en_m4::WDOG_INTR_EN_M4_R
• intr_ctrl::other_intr_en_m4::WDOG_RST_EN_M4_A
• intr_ctrl::other_intr_en_m4::WDOG_RST_EN_M4_R
• iomux::FBIO_SEL_1
• iomux::FBIO_SEL_2
• iomux::I2S_CLKIN_SEL
• iomux::I2S_DATA_SELECT
• iomux::I2S_WD_CLKIN_SEL
• iomux::IO_REG_SEL
• iomux::IRDA_SIRIN_SEL
• iomux::NUARTCTS_SEL
• iomux::PAD__CTRL
• iomux::PAD__CTRL_FFE
• iomux::PDM_CLKIN_SEL
• iomux::PDM_DATA_SELE
• iomux::PDM_STAT_IN_SEL
• iomux::SCL0_SEL_REG
• iomux::SCL1_SEL_REG
• iomux::SCL2_SEL_REG
• iomux::SDA0_SEL_REG
• iomux::SDA1_SEL_REG
• iomux::SDA2_SEL_REG
• iomux::SPIS_CLK_SEL
• iomux::SPIS_MISO_SEL
• iomux::SPIS_MOSI_SEL
• iomux::SPIS_SSN_SEL
• iomux::SPI_SENSOR_MISO_SEL
• iomux::SPI_SENSOR_MOSI_SEL
• iomux::SW_CLK_SEL
• iomux::SW_IO_SEL
• iomux::S_INTR_0_SEL_REG
• iomux::S_INTR_1_SEL_REG
• iomux::S_INTR_2_SEL
• iomux::S_INTR_3_SEL
• iomux::S_INTR_4_SEL
• iomux::S_INTR_5_SEL
• iomux::S_INTR_6_SEL
• iomux::S_INTR_7_SEL
• iomux::UART_RXD_SEL
• misc::A0_DBG_MON_SEL
• misc::A0_PMU_DBG_MON_SEL
• misc::CONFIG_MEM128_AON
• misc::DBG_MON
• misc::FB_DEVICE_ID
• misc::IO_INPUT
• misc::IO_OUTPUT
• misc::LOCK_KEY_CTRL
• misc::PAD_SEL18
• misc::SUBSYS_DBG_MON_SEL
• misc::SW_MB_1
• misc::SW_MB_2
• pkfb::PKFB_FIFOCTRL
• pkfb::PKFB_FIFOSRAMCTRL0
• pkfb::PKFB_FIFOSRAMCTRL1
• pkfb::PKFB_FIFOSTATUS
• pkfb::PKFB_FIFO_COLL_INTR
• pkfb::PKFB_FIFO_COLL_INTR_EN
• pkfb::PKFB_PF0CNT
• pkfb::PKFB_PF0DATA
• pkfb::PKFB_PF0POPCTL
• pkfb::PKFB_PF0PUSHCTL
• pkfb::PKFB_PF1CNT
• pkfb::PKFB_PF1DATA
• pkfb::PKFB_PF1POPCTL
• pkfb::PKFB_PF1PUSHCTL
• pkfb::PKFB_PF2CNT
• pkfb::PKFB_PF2DATA
• pkfb::PKFB_PF2POPCTL
• pkfb::PKFB_PF2PUSHCTL
• pkfb::PKFB_PF8KCNT
• pkfb::PKFB_PF8KDATA
• pkfb::PKFB_PF8KPOPCTL
• pkfb::PKFB_PF8KPUSHCTL
• pkfb::pkfb_fifo_coll_intr_en::PF1_COLL_INTR_EN_A
• pkfb::pkfb_fifo_coll_intr_en::PF1_COLL_INTR_EN_R
• pkfb::pkfb_fifo_coll_intr_en::PF2_COLL_INTR_EN_A
• pkfb::pkfb_fifo_coll_intr_en::PF2_COLL_INTR_EN_R
• pkfb::pkfb_fifo_coll_intr_en::PF8K_COLL_INTR_EN_A
• pkfb::pkfb_fifo_coll_intr_en::PF8K_COLL_INTR_EN_R
• pkfb::pkfb_fifoctrl::PF1_EN_A
• pkfb::pkfb_fifoctrl::PF1_EN_R
• pkfb::pkfb_fifoctrl::PF1_FFE_SEL_A
• pkfb::pkfb_fifoctrl::PF1_FFE_SEL_R
• pkfb::pkfb_fifoctrl::PF1_POP_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF1_POP_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF1_POP_MUX_A
• pkfb::pkfb_fifoctrl::PF1_POP_MUX_R
• pkfb::pkfb_fifoctrl::PF1_PUSH_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF1_PUSH_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF1_PUSH_MUX_A
• pkfb::pkfb_fifoctrl::PF1_PUSH_MUX_R
• pkfb::pkfb_fifoctrl::PF2_EN_A
• pkfb::pkfb_fifoctrl::PF2_EN_R
• pkfb::pkfb_fifoctrl::PF2_FFE_SEL_A
• pkfb::pkfb_fifoctrl::PF2_FFE_SEL_R
• pkfb::pkfb_fifoctrl::PF2_POP_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF2_POP_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF2_POP_MUX_A
• pkfb::pkfb_fifoctrl::PF2_POP_MUX_R
• pkfb::pkfb_fifoctrl::PF2_PUSH_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF2_PUSH_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF2_PUSH_MUX_A
• pkfb::pkfb_fifoctrl::PF2_PUSH_MUX_R
• pkfb::pkfb_fifoctrl::PF8K_EN_A
• pkfb::pkfb_fifoctrl::PF8K_EN_R
• pkfb::pkfb_fifoctrl::PF8K_FFE_SEL_A
• pkfb::pkfb_fifoctrl::PF8K_FFE_SEL_R
• pkfb::pkfb_fifoctrl::PF8K_POP_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF8K_POP_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF8K_POP_MUX_A
• pkfb::pkfb_fifoctrl::PF8K_POP_MUX_R
• pkfb::pkfb_fifoctrl::PF8K_PUSH_INT_MUX_A
• pkfb::pkfb_fifoctrl::PF8K_PUSH_INT_MUX_R
• pkfb::pkfb_fifoctrl::PF8K_PUSH_MUX_A
• pkfb::pkfb_fifoctrl::PF8K_PUSH_MUX_R
• pkfb::pkfb_fifostatus::PF1_SRAM_SLEEP_A
• pkfb::pkfb_fifostatus::PF1_SRAM_SLEEP_R
• pkfb::pkfb_fifostatus::PF2_SRAM_SLEEP_A
• pkfb::pkfb_fifostatus::PF2_SRAM_SLEEP_R
• pkfb::pkfb_fifostatus::PF8K_SRAM_SLEEP_A
• pkfb::pkfb_fifostatus::PF8K_SRAM_SLEEP_R
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_THRESH_A
• pkfb::pkfb_pf0popctl::PF0_POP_INT_EN_THRESH_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_THRESH_A
• pkfb::pkfb_pf0pushctl::PF0_PUSH_INT_EN_THRESH_R
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_THRESH_A
• pkfb::pkfb_pf1popctl::PF1_POP_INT_EN_THRESH_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_THRESH_A
• pkfb::pkfb_pf1pushctl::PF1_PUSH_INT_EN_THRESH_R
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_THRESH_A
• pkfb::pkfb_pf2popctl::PF2_POP_INT_EN_THRESH_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_THRESH_A
• pkfb::pkfb_pf2pushctl::PF2_PUSH_INT_EN_THRESH_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_THRESH_A
• pkfb::pkfb_pf8kpopctl::PF8K_POP_INT_EN_THRESH_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_SRAM_SLEEP_A
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_SRAM_SLEEP_R
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_THRESH_A
• pkfb::pkfb_pf8kpushctl::PF8K_PUSH_INT_EN_THRESH_R
• pmu::A1_PD_SRC_MASK_N
• pmu::A1_PWR_MODE_CFG
• pmu::A1_STATUS
• pmu::A1_WU_SRC_MASK_N
• pmu::APREBOOTSTATUS
• pmu::AUDIO_MEM_CFG
• pmu::AUDIO_MEM_CTRL_0
• pmu::AUDIO_MEM_CTRL_1
• pmu::AUDIO_SRAM_SW_WU
• pmu::AUDIO_STATUS
• pmu::AUDIO_SW_PD
• pmu::AUDIO_WU_SRC_MASK_N
• pmu::CHIP_STA_0
• pmu::CHIP_STA_1
• pmu::EXT_WAKING_UP_SRC
• pmu::FBVLPMINWIDTH
• pmu::FB_ISOLATION
• pmu::FB_PD_SRC_MASK_N
• pmu::FB_PWR_MODE_CFG
• pmu::FB_STATUS
• pmu::FB_WU_SRC_MASK_N
• pmu::FFE_FB_PF_SW_PD
• pmu::FFE_FB_PF_SW_WU
• pmu::FFE_MEM_CFG
• pmu::FFE_MEM_CTRL_0
• pmu::FFE_MEM_CTRL_1
• pmu::FFE_PD_SRC_MASK_N
• pmu::FFE_PWR_MODE_CFG
• pmu::FFE_STATUS
• pmu::FFE_WU_SRC_MASK_N
• pmu::GEN_PURPOSE_0
• pmu::GEN_PURPOSE_1
• pmu::M4S0_PD_SRC_MASK_N
• pmu::M4S0_PWR_MODE_CFG
• pmu::M4S0_SRAM_STATUS
• pmu::M4S0_WU_SRC_MASK_N
• pmu::M4SRAM_SSW_LPMF
• pmu::M4SRAM_SSW_LPMH_MASK_N
• pmu::M4_MEM_CFG
• pmu::M4_MEM_CTRL_0
• pmu::M4_MEM_CTRL_1
• pmu::M4_MEM_CTRL_PWR_0
• pmu::M4_MEM_CTRL_PWR_1
• pmu::M4_MEM_CTRL_PWR_2
• pmu::M4_PD_SRC_MASKK_N
• pmu::M4_PWR_MODE_CFG
• pmu::M4_SRAM_STATUS
• pmu::M4_SRAM_SW_PD
• pmu::M4_SRAM_SW_WU
• pmu::M4_STATUS
• pmu::M4_WU
• pmu::MEM_PWR_DWN_CTRL
• pmu::MISC_POR_0
• pmu::MISC_POR_1
• pmu::MISC_POR_2
• pmu::MISC_POR_3
• pmu::MISC_STATUS
• pmu::MISC_SW_PD
• pmu::MISC_SW_WU
• pmu::PDWU_TIMER_CFG
• pmu::PF_MEM_CFG
• pmu::PF_MEM_CTRL_0
• pmu::PF_MEM_CTRL_1
• pmu::PF_PD_SRC_MASK_N
• pmu::PF_PWR_MODE_CFG
• pmu::PF_STATUS
• pmu::PF_WU_SRC_MASK_N
• pmu::PMU_STM_PRIORITY
• pmu::PMU_TIMER_CFG_0
• pmu::PMU_TIMER_CFG_1
• pmu::PWR_DWN_SCH
• pmu::PWR_OFF_OSC
• pmu::RST_CTRL_0
• pmu::RST_CTRL_1
• pmu::SDMA_MEM_CTRL_0
• pmu::SDMA_MEM_CTRL_1
• pmu::SDMA_PD_SRC_MASK_N
• pmu::SDMA_POWER_MODE_CFG
• pmu::SDMA_STATUS
• pmu::SDMA_WU_SRC_MASK_N
• pmu::WIC_CTRL
• pmu::WIC_STATUS
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_1_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_1_R
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_2_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_LC_DS_2_R
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_0_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_0_R
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_1_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_1_R
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_2_A
• pmu::audio_mem_ctrl_0::AUDIO_SRAM_RC_DS_2_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_1_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_1_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_2_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_LC_SD_2_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_0_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_0_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_1_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_1_R
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_2_A
• pmu::audio_mem_ctrl_1::AUDIO_SRAM_RC_SD_2_R
• pmu::audio_sram_sw_wu::AUDIO_AD1_WU_A
• pmu::audio_sram_sw_wu::AUDIO_AD1_WU_R
• pmu::audio_sram_sw_wu::AUDIO_AD2_WU_A
• pmu::audio_sram_sw_wu::AUDIO_AD2_WU_R
• pmu::audio_sram_sw_wu::AUDIO_AD3_WU_A
• pmu::audio_sram_sw_wu::AUDIO_AD3_WU_R
• pmu::audio_sram_sw_wu::AUDIO_AD4_WU_A
• pmu::audio_sram_sw_wu::AUDIO_AD4_WU_R
• pmu::audio_sram_sw_wu::AUDIO_AD5_WU_A
• pmu::audio_sram_sw_wu::AUDIO_AD5_WU_R
• pmu::audio_sw_pd::AUDIO_AD1_PD_A
• pmu::audio_sw_pd::AUDIO_AD1_PD_R
• pmu::audio_sw_pd::AUDIO_AD2_PD_A
• pmu::audio_sw_pd::AUDIO_AD2_PD_R
• pmu::audio_sw_pd::AUDIO_AD3_PD_A
• pmu::audio_sw_pd::AUDIO_AD3_PD_R
• pmu::audio_sw_pd::AUDIO_AD4_PD_A
• pmu::audio_sw_pd::AUDIO_AD4_PD_R
• pmu::audio_sw_pd::AUDIO_AD5_PD_A
• pmu::audio_sw_pd::AUDIO_AD5_PD_R
• pmu::audio_wu_src_mask_n::AD1_WU_EVENT_MASK_N_A
• pmu::audio_wu_src_mask_n::AD1_WU_EVENT_MASK_N_R
• pmu::audio_wu_src_mask_n::AD2_WU_EVENT_MASK_N_A
• pmu::audio_wu_src_mask_n::AD2_WU_EVENT_MASK_N_R
• pmu::audio_wu_src_mask_n::AD3_WU_EVENT_MASK_N_A
• pmu::audio_wu_src_mask_n::AD3_WU_EVENT_MASK_N_R
• pmu::audio_wu_src_mask_n::AD4_WU_EVENT_MASK_N_A
• pmu::audio_wu_src_mask_n::AD4_WU_EVENT_MASK_N_R
• pmu::audio_wu_src_mask_n::AD5_WU_EVENT_MASK_N_A
• pmu::audio_wu_src_mask_n::AD5_WU_EVENT_MASK_N_R
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_1_A
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_1_R
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_2_A
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_2_R
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_3_A
• pmu::fb_pd_src_mask_n::INTERFACE_SIGNAL_3_R
• pmu::fb_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_A
• pmu::fb_wu_src_mask_n::KICKOFF_TIMER_TIME_OUT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_1_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_1_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_2_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_2_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_3_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_3_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_4_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_4_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_5_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_5_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_6_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_6_INT_R
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_7_INT_A
• pmu::fb_wu_src_mask_n::SENSOR_GPIO_7_INT_R
• pmu::ffe_fb_pf_sw_pd::FB_SOFTWARE_PD_A
• pmu::ffe_fb_pf_sw_pd::FB_SOFTWARE_PD_R
• pmu::ffe_fb_pf_sw_pd::PF_SOFTWARE_PD_A
• pmu::ffe_fb_pf_sw_pd::PF_SOFTWARE_PD_R
• pmu::ffe_fb_pf_sw_wu::FB_SOFTWARE_WU_A
• pmu::ffe_fb_pf_sw_wu::FB_SOFTWARE_WU_R
• pmu::ffe_fb_pf_sw_wu::PF_SOFTWARE_WU_A
• pmu::ffe_fb_pf_sw_wu::PF_SOFTWARE_WU_R
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_1_A
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_1_R
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_2_A
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_2_R
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_3_A
• pmu::ffe_mem_cfg::CFG_FFE_SRAM_LS_3_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM1_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_CM1_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM0_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM0_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM1_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM1_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM2_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM2_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM3_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_DM3_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM0_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM0_R
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM1_A
• pmu::ffe_mem_ctrl_0::CTRL_FFE_SRAM_DS_SM1_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM1_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_CM1_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM0_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM0_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM1_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM1_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM2_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM2_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM3_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_DM3_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM0_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM0_R
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM1_A
• pmu::ffe_mem_ctrl_1::CTRL_FFE_SRAM_SD_SM1_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_0_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_0_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_1_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_1_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_2_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_2_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_3_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_3_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_4_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_4_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_5_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_5_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_6_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_6_INT_R
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_7_INT_A
• pmu::ffe_wu_src_mask_n::SENSOR_GPIO_7_INT_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_10_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_10_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_11_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_11_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_12_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_12_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_13_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_13_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_14_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_14_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_15_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_15_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_1_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_1_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_2_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_2_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_3_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_3_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_4_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_4_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_5_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_5_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_6_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_6_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_7_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_7_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_8_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_8_R
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_9_A
• pmu::m4_mem_ctrl_0::CTRL_M4_SRAM_DS_9_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_10_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_10_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_11_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_11_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_12_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_12_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_13_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_13_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_14_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_14_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_15_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_15_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_1_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_1_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_2_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_2_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_3_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_3_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_4_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_4_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_5_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_5_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_6_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_6_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_7_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_7_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_8_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_8_R
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_9_A
• pmu::m4_mem_ctrl_1::CTRL_M4_SRAM_SD_9_R
• pmu::m4_sram_sw_pd::M4S10_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S10_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S11_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S11_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S12_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S12_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S13_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S13_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S14_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S14_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S15_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S15_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S1_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S1_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S2_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S2_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S3_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S3_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S4_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S4_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S5_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S5_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S6_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S6_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S7_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S7_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S8_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S8_SOFTWARE_PD_R
• pmu::m4_sram_sw_pd::M4S9_SOFTWARE_PD_A
• pmu::m4_sram_sw_pd::M4S9_SOFTWARE_PD_R
• pmu::m4_sram_sw_wu::M4S10_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S10_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S11_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S11_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S12_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S12_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S13_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S13_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S14_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S14_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S15_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S15_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S1_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S1_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S2_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S2_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S3_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S3_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S4_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S4_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S5_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S5_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S6_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S6_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S7_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S7_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S8_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S8_SOFTWARE_WU_R
• pmu::m4_sram_sw_wu::M4S9_SOFTWARE_WU_A
• pmu::m4_sram_sw_wu::M4S9_SOFTWARE_WU_R
• pmu::misc_sw_pd::A1_SOFTWARE_PD_A
• pmu::misc_sw_pd::A1_SOFTWARE_PD_R
• pmu::misc_sw_pd::I2S_SOFTWARE_PD_A
• pmu::misc_sw_pd::I2S_SOFTWARE_PD_R
• pmu::misc_sw_wu::A1_SOFTWARE_WU_A
• pmu::misc_sw_wu::A1_SOFTWARE_WU_R
• pmu::misc_sw_wu::I2S_SOFTWARE_WU_A
• pmu::misc_sw_wu::I2S_SOFTWARE_WU_R
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_8K_A
• pmu::pf_mem_ctrl_1::CTRL_PF_SRAM_SD_8K_R
• sdma::ALT_CTRL_BASE_PTR
• sdma::CHNL_ENABLE_CLR
• sdma::CHNL_ENABLE_SET
• sdma::CHNL_PRIORITY_CLEAR
• sdma::CHNL_PRIORITY_SET
• sdma::CHNL_PRI_ALT_CLR
• sdma::CHNL_PRI_ALT_SET
• sdma::CHNL_REQ_MASK_CLR
• sdma::CHNL_REQ_MASK_SET
• sdma::CHNL_SW_REQ
• sdma::CHNL_USEBURST_SET
• sdma::CHNL_USE_BURST_SET
• sdma::CTRL_BASE_PTR
• sdma::DMA_CFG
• sdma::DMA_STATUS
• sdma::DMA_WAITONREQ_STATUS
• sdma::ERR_CLR
• sdma::PCELL_ID_0
• sdma::PCELL_ID_1
• sdma::PCELL_ID_2
• sdma::PCELL_ID_3
• sdma::PERIPH_ID_0
• sdma::PERIPH_ID_1
• sdma::PERIPH_ID_2
• sdma::PERIPH_ID_3
• sdma::PERIPH_ID_4
• sdma_bridge::DMA_ACTIVE_REG
• sdma_bridge::DMA_REQ
• sdma_bridge::DMA_WAITONREQ_REG
• sdma_bridge::SDMA_PWRD_CNT
• sdma_bridge::SDMA_SRAM_CTL
• sdma_sram::ALT_CHN_CFG_CH0
• sdma_sram::ALT_CHN_CFG_CH1
• sdma_sram::ALT_CHN_CFG_CH10
• sdma_sram::ALT_CHN_CFG_CH11
• sdma_sram::ALT_CHN_CFG_CH12
• sdma_sram::ALT_CHN_CFG_CH13
• sdma_sram::ALT_CHN_CFG_CH14
• sdma_sram::ALT_CHN_CFG_CH15
• sdma_sram::ALT_CHN_CFG_CH2
• sdma_sram::ALT_CHN_CFG_CH3
• sdma_sram::ALT_CHN_CFG_CH4
• sdma_sram::ALT_CHN_CFG_CH5
• sdma_sram::ALT_CHN_CFG_CH6
• sdma_sram::ALT_CHN_CFG_CH7
• sdma_sram::ALT_CHN_CFG_CH8
• sdma_sram::ALT_CHN_CFG_CH9
• sdma_sram::ALT_DST_DATA_END_PTR_CH0
• sdma_sram::ALT_DST_DATA_END_PTR_CH1
• sdma_sram::ALT_DST_DATA_END_PTR_CH10
• sdma_sram::ALT_DST_DATA_END_PTR_CH11
• sdma_sram::ALT_DST_DATA_END_PTR_CH12
• sdma_sram::ALT_DST_DATA_END_PTR_CH13
• sdma_sram::ALT_DST_DATA_END_PTR_CH14
• sdma_sram::ALT_DST_DATA_END_PTR_CH15
• sdma_sram::ALT_DST_DATA_END_PTR_CH2
• sdma_sram::ALT_DST_DATA_END_PTR_CH3
• sdma_sram::ALT_DST_DATA_END_PTR_CH4
• sdma_sram::ALT_DST_DATA_END_PTR_CH5
• sdma_sram::ALT_DST_DATA_END_PTR_CH6
• sdma_sram::ALT_DST_DATA_END_PTR_CH7
• sdma_sram::ALT_DST_DATA_END_PTR_CH8
• sdma_sram::ALT_DST_DATA_END_PTR_CH9
• sdma_sram::ALT_SRC_DATA_END_PTR_CH0
• sdma_sram::ALT_SRC_DATA_END_PTR_CH1
• sdma_sram::ALT_SRC_DATA_END_PTR_CH10
• sdma_sram::ALT_SRC_DATA_END_PTR_CH11
• sdma_sram::ALT_SRC_DATA_END_PTR_CH12
• sdma_sram::ALT_SRC_DATA_END_PTR_CH13
• sdma_sram::ALT_SRC_DATA_END_PTR_CH14
• sdma_sram::ALT_SRC_DATA_END_PTR_CH15
• sdma_sram::ALT_SRC_DATA_END_PTR_CH2
• sdma_sram::ALT_SRC_DATA_END_PTR_CH3
• sdma_sram::ALT_SRC_DATA_END_PTR_CH4
• sdma_sram::ALT_SRC_DATA_END_PTR_CH5
• sdma_sram::ALT_SRC_DATA_END_PTR_CH6
• sdma_sram::ALT_SRC_DATA_END_PTR_CH7
• sdma_sram::ALT_SRC_DATA_END_PTR_CH8
• sdma_sram::ALT_SRC_DATA_END_PTR_CH9
• sdma_sram::CH_CFG_CH0
• sdma_sram::CH_CFG_CH1
• sdma_sram::CH_CFG_CH10
• sdma_sram::CH_CFG_CH11
• sdma_sram::CH_CFG_CH12
• sdma_sram::CH_CFG_CH13
• sdma_sram::CH_CFG_CH14
• sdma_sram::CH_CFG_CH15
• sdma_sram::CH_CFG_CH2
• sdma_sram::CH_CFG_CH3
• sdma_sram::CH_CFG_CH4
• sdma_sram::CH_CFG_CH5
• sdma_sram::CH_CFG_CH6
• sdma_sram::CH_CFG_CH7
• sdma_sram::CH_CFG_CH8
• sdma_sram::CH_CFG_CH9
• sdma_sram::DST_DATA_END_PTR_CH0
• sdma_sram::DST_DATA_END_PTR_CH1
• sdma_sram::DST_DATA_END_PTR_CH10
• sdma_sram::DST_DATA_END_PTR_CH11
• sdma_sram::DST_DATA_END_PTR_CH12
• sdma_sram::DST_DATA_END_PTR_CH13
• sdma_sram::DST_DATA_END_PTR_CH14
• sdma_sram::DST_DATA_END_PTR_CH15
• sdma_sram::DST_DATA_END_PTR_CH2
• sdma_sram::DST_DATA_END_PTR_CH3
• sdma_sram::DST_DATA_END_PTR_CH4
• sdma_sram::DST_DATA_END_PTR_CH5
• sdma_sram::DST_DATA_END_PTR_CH6
• sdma_sram::DST_DATA_END_PTR_CH7
• sdma_sram::DST_DATA_END_PTR_CH8
• sdma_sram::DST_DATA_END_PTR_CH9
• sdma_sram::SRC_DATA_END_PTR_CH0
• sdma_sram::SRC_DATA_END_PTR_CH1
• sdma_sram::SRC_DATA_END_PTR_CH10
• sdma_sram::SRC_DATA_END_PTR_CH11
• sdma_sram::SRC_DATA_END_PTR_CH12
• sdma_sram::SRC_DATA_END_PTR_CH13
• sdma_sram::SRC_DATA_END_PTR_CH14
• sdma_sram::SRC_DATA_END_PTR_CH15
• sdma_sram::SRC_DATA_END_PTR_CH2
• sdma_sram::SRC_DATA_END_PTR_CH3
• sdma_sram::SRC_DATA_END_PTR_CH4
• sdma_sram::SRC_DATA_END_PTR_CH5
• sdma_sram::SRC_DATA_END_PTR_CH6
• sdma_sram::SRC_DATA_END_PTR_CH7
• sdma_sram::SRC_DATA_END_PTR_CH8
• sdma_sram::SRC_DATA_END_PTR_CH9
• spi::BAUDR
• spi::CTRLR0
• spi::CTRLR1
• spi::DR0
• spi::ICR
• spi::IDR
• spi::IMR
• spi::ISR
• spi::MSTICR
• spi::RISR
• spi::RXFLR
• spi::RXFTLR
• spi::RXOICR
• spi::RXUICR
• spi::SER
• spi::SR
• spi::SSIENR
• spi::SSI_COMP_VERSION
• spi::TXFLR
• spi::TXFTLR
• spi::TXOICR
• spi::ctrlr0::DFS_32_A
• spi::ctrlr0::DFS_32_R
• spi::imr::MSTIM_A
• spi::imr::MSTIM_R
• spi::imr::RXFIM_A
• spi::imr::RXFIM_R
• spi::imr::RXFOIM_A
• spi::imr::RXFOIM_R
• spi::imr::RXUIM_A
• spi::imr::RXUIM_R
• spi::imr::TXOIM_A
• spi::imr::TXOIM_R
• spi_tlc::AHBACCESSCTL
• spi_tlc::AHBSTATUS
• spi_tlc::CM_FIFO_0_DATA
• spi_tlc::CM_FIFO_1_DATA
• spi_tlc::CM_FIFO_2_DATA
• spi_tlc::CM_FIFO_3_DATA
• spi_tlc::DEVICEIDBYTE
• spi_tlc::DMAADDR0
• spi_tlc::DMAADDR1
• spi_tlc::DMAADDR2
• spi_tlc::DMAADDR3
• spi_tlc::DMABURSTSIZE0
• spi_tlc::DMABURSTSIZE1
• spi_tlc::DMADEBUGCTL0
• spi_tlc::DMADEBUGCTL1
• spi_tlc::DMARDDATA
• spi_tlc::DMASTATUS
• spi_tlc::MEMADDRBYTE0
• spi_tlc::MEMADDRBYTE1
• spi_tlc::MEMADDRBYTE2
• spi_tlc::MEMADDRBYTE3
• spi_tlc::MEMDATABYTE0
• spi_tlc::MEMDATABYTE1
• spi_tlc::MEMDATABYTE2
• spi_tlc::MEMDATABYTE3
• spi_tlc::RESERVED_DUMMY
• spi_tlc::SCRATCHBYTE
• spi_tlc::TAMARSTATUS
• spt::ERROR_CMP_1S_0
• spt::ERROR_CMP_1S_1
• spt::ERROR_CMP_1S_2
• spt::ERROR_CMP_1S_3
• spt::ERROR_CMP_40M
• spt::ERROR_CMP_RTC_0
• spt::ERROR_CMP_RTC_1
• spt::ERROR_CMP_RTC_2
• spt::ERROR_CMP_RTC_3
• spt::EVENT_CNT_VALUE
• spt::MS_CNT_VALUE
• spt::SLEEP_MODE
• spt::SPARE_BITS
• spt::SPT_CFG
• spt::TIMER_VALUE
• spt::UPDATE_TMR_VAL
• spt::spt_cfg::INT_MASK_N_1_A
• spt::spt_cfg::INT_MASK_N_1_R
• spt::spt_cfg::INT_MASK_N_2_A
• spt::spt_cfg::INT_MASK_N_2_R
• spt::spt_cfg::INT_MASK_N_3_A
• spt::spt_cfg::INT_MASK_N_3_R
• spt::spt_cfg::INT_MASK_N_4_A
• spt::spt_cfg::INT_MASK_N_4_R
• spt::spt_cfg::INT_MASK_N_5_A
• spt::spt_cfg::INT_MASK_N_5_R
• spt::spt_cfg::INT_MASK_N_6_A
• spt::spt_cfg::INT_MASK_N_6_R
• spt::spt_cfg::INT_MASK_N_7_A
• spt::spt_cfg::INT_MASK_N_7_R
• timer::CID0
• timer::CID1
• timer::CID2
• timer::CID3
• timer::CTRL
• timer::INTSTATUS_INTCLEAR
• timer::PID0
• timer::PID1
• timer::PID2
• timer::PID3
• timer::PID4
• timer::PID5
• timer::PID6
• timer::PID7
• timer::RELOAD
• timer::VALUE
• uart::UART_CR
• uart::UART_DR
• uart::UART_FBRD
• uart::UART_IBRD
• uart::UART_ICR
• uart::UART_IFLS
• uart::UART_ILPR
• uart::UART_IMSC
• uart::UART_ITIP
• uart::UART_ITOP
• uart::UART_LCR_H
• uart::UART_MIS
• uart::UART_PCELLID0
• uart::UART_PCELLID1
• uart::UART_PCELLID2
• uart::UART_PCELLID4
• uart::UART_PERIPHID0
• uart::UART_PERIPHID1
• uart::UART_PERIPHID2
• uart::UART_PERIPHID3
• uart::UART_RIS
• uart::UART_RSR
• uart::UART_TCR
• uart::UART_TDR
• uart::UART_TFR
• uart::uart_ifls::RXIFLSEL_A
• uart::uart_ifls::RXIFLSEL_R
• wdt::WDOGCONTROL
• wdt::WDOGINTCLR
• wdt::WDOGITCR
• wdt::WDOGITOP
• wdt::WDOGLOAD
• wdt::WDOGLOCK
• wdt::WDOGMIS
• wdt::WDOGPCELLID0
• wdt::WDOGPCELLID1
• wdt::WDOGPCELLID2
• wdt::WDOGPCELLID3
• wdt::WDOGPERIPHID0
• wdt::WDOGPERIPHID1
• wdt::WDOGPERIPHID2
• wdt::WDOGPERIPHID3
• wdt::WDOGPERIPHID4
• wdt::WDOGPERIPHID5
• wdt::WDOGPERIPHID6
• wdt::WDOGPERIPHID7
• wdt::WDOGRIS
• wdt::WDOGVALUE

Constants

• NVIC_PRIO_BITS