embassy_net_wiznet/chip/
w5500.rs

1use embedded_hal_async::spi::{Operation, SpiDevice};
2
3#[repr(u8)]
4pub enum RegisterBlock {
5    Common = 0x00,
6    Socket0 = 0x01,
7    TxBuf = 0x02,
8    RxBuf = 0x03,
9}
10
11/// Wiznet W5500 chip.
12pub enum W5500 {}
13
14impl super::Chip for W5500 {}
15impl super::SealedChip for W5500 {
16    type Address = (RegisterBlock, u16);
17
18    const CHIP_VERSION: u8 = 0x04;
19
20    const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
21    const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x09);
22    const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x18);
23    const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x2E);
24    const COMMON_VERSION: Self::Address = (RegisterBlock::Common, 0x39);
25
26    const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x00);
27    const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x01);
28    const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1E);
29    const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1F);
30    const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x20);
31    const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x24);
32    const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x26);
33    const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
34    const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
35    const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
36
37    const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 7);
38
39    const BUF_SIZE: u16 = 0x4000;
40    const AUTO_WRAP: bool = true;
41
42    fn rx_addr(addr: u16) -> Self::Address {
43        (RegisterBlock::RxBuf, addr)
44    }
45
46    fn tx_addr(addr: u16) -> Self::Address {
47        (RegisterBlock::TxBuf, addr)
48    }
49
50    async fn bus_read<SPI: SpiDevice>(
51        spi: &mut SPI,
52        address: Self::Address,
53        data: &mut [u8],
54    ) -> Result<(), SPI::Error> {
55        let address_phase = address.1.to_be_bytes();
56        let control_phase = [(address.0 as u8) << 3];
57        let operations = &mut [
58            Operation::Write(&address_phase),
59            Operation::Write(&control_phase),
60            Operation::TransferInPlace(data),
61        ];
62        spi.transaction(operations).await
63    }
64
65    async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
66        let address_phase = address.1.to_be_bytes();
67        let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
68        let data_phase = data;
69        let operations = &mut [
70            Operation::Write(&address_phase[..]),
71            Operation::Write(&control_phase),
72            Operation::Write(&data_phase),
73        ];
74        spi.transaction(operations).await
75    }
76}
embassy_net_wiznet/chip/w5500.rs

embassy_net_wiznet/chip/
w5500.rs
