Enum efr32xg12p::prs::ch9_ctrl::EDSELW [] [src]

pub enum EDSELW {
    OFF,
    POSEDGE,
    NEGEDGE,
    BOTHEDGES,
}

Values that can be written to the field EDSEL

Variants

Signal is left as it is

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal